2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
37 struct pipe_resource
*dst
,
39 unsigned dstx
, unsigned dsty
, unsigned dstz
,
40 struct pipe_resource
*src
,
42 const struct pipe_box
*src_box
)
44 struct pipe_blit_info blit
;
46 memset(&blit
, 0, sizeof(blit
));
47 blit
.src
.resource
= src
;
48 blit
.src
.format
= src
->format
;
49 blit
.src
.level
= src_level
;
50 blit
.src
.box
= *src_box
;
51 blit
.dst
.resource
= dst
;
52 blit
.dst
.format
= dst
->format
;
53 blit
.dst
.level
= dst_level
;
54 blit
.dst
.box
.x
= dstx
;
55 blit
.dst
.box
.y
= dsty
;
56 blit
.dst
.box
.z
= dstz
;
57 blit
.dst
.box
.width
= src_box
->width
;
58 blit
.dst
.box
.height
= src_box
->height
;
59 blit
.dst
.box
.depth
= src_box
->depth
;
60 blit
.mask
= util_format_get_mask(src
->format
) &
61 util_format_get_mask(dst
->format
);
62 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
65 pipe
->blit(pipe
, &blit
);
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
72 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
73 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
74 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
75 struct pipe_resource
*src
= transfer
->resource
;
77 if (src
->nr_samples
> 1) {
78 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
79 src
, transfer
->level
, &transfer
->box
);
83 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
90 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
91 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
92 struct pipe_resource
*dst
= transfer
->resource
;
93 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
96 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
98 if (dst
->nr_samples
> 1) {
99 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
100 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
105 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
106 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
110 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
111 const struct pipe_box
*box
)
113 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
115 return rtex
->surface
.level
[level
].offset
+
116 box
->z
* rtex
->surface
.level
[level
].slice_size
+
117 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
118 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
121 static int r600_init_surface(struct r600_common_screen
*rscreen
,
122 struct radeon_surf
*surface
,
123 const struct pipe_resource
*ptex
,
125 bool is_flushed_depth
)
127 const struct util_format_description
*desc
=
128 util_format_description(ptex
->format
);
129 bool is_depth
, is_stencil
;
131 is_depth
= util_format_has_depth(desc
);
132 is_stencil
= util_format_has_stencil(desc
);
134 surface
->npix_x
= ptex
->width0
;
135 surface
->npix_y
= ptex
->height0
;
136 surface
->npix_z
= ptex
->depth0
;
137 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
138 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
140 surface
->array_size
= 1;
141 surface
->last_level
= ptex
->last_level
;
143 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
144 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
145 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
147 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
148 /* align byte per element on dword */
149 if (surface
->bpe
== 3) {
154 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
155 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
157 switch (ptex
->target
) {
158 case PIPE_TEXTURE_1D
:
159 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
161 case PIPE_TEXTURE_RECT
:
162 case PIPE_TEXTURE_2D
:
163 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
165 case PIPE_TEXTURE_3D
:
166 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
168 case PIPE_TEXTURE_1D_ARRAY
:
169 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
170 surface
->array_size
= ptex
->array_size
;
172 case PIPE_TEXTURE_2D_ARRAY
:
173 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
174 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
175 surface
->array_size
= ptex
->array_size
;
177 case PIPE_TEXTURE_CUBE
:
178 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
184 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
185 surface
->flags
|= RADEON_SURF_SCANOUT
;
188 if (!is_flushed_depth
&& is_depth
) {
189 surface
->flags
|= RADEON_SURF_ZBUFFER
;
192 surface
->flags
|= RADEON_SURF_SBUFFER
|
193 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
196 if (rscreen
->chip_class
>= SI
) {
197 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
202 static int r600_setup_surface(struct pipe_screen
*screen
,
203 struct r600_texture
*rtex
,
204 unsigned pitch_in_bytes_override
,
207 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
211 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
216 rtex
->size
= rtex
->surface
.bo_size
;
218 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
219 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
222 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
223 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
224 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
228 for (i
= 0; i
< Elements(rtex
->surface
.level
); ++i
)
229 rtex
->surface
.level
[i
].offset
+= offset
;
234 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
235 struct radeon_bo_metadata
*metadata
)
237 struct radeon_surf
*surface
= &rtex
->surface
;
239 memset(metadata
, 0, sizeof(*metadata
));
240 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
241 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
242 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
243 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
244 metadata
->pipe_config
= surface
->pipe_config
;
245 metadata
->bankw
= surface
->bankw
;
246 metadata
->bankh
= surface
->bankh
;
247 metadata
->tile_split
= surface
->tile_split
;
248 metadata
->stencil_tile_split
= surface
->stencil_tile_split
;
249 metadata
->mtilea
= surface
->mtilea
;
250 metadata
->num_banks
= surface
->num_banks
;
251 metadata
->stride
= surface
->level
[0].pitch_bytes
;
252 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
255 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
257 p_atomic_inc(&rscreen
->dirty_fb_counter
);
260 static void r600_eliminate_fast_color_clear(struct r600_common_screen
*rscreen
,
261 struct r600_texture
*rtex
)
263 struct pipe_context
*ctx
= rscreen
->aux_context
;
265 pipe_mutex_lock(rscreen
->aux_context_lock
);
266 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
267 ctx
->flush(ctx
, NULL
, 0);
268 pipe_mutex_unlock(rscreen
->aux_context_lock
);
271 static void r600_texture_disable_cmask(struct r600_common_screen
*rscreen
,
272 struct r600_texture
*rtex
)
274 if (!rtex
->cmask
.size
)
277 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
280 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
281 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
283 if (rscreen
->chip_class
>= SI
)
284 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
286 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
288 if (rtex
->cmask_buffer
!= &rtex
->resource
)
289 pipe_resource_reference((struct pipe_resource
**)&rtex
->cmask_buffer
, NULL
);
291 /* Notify all contexts about the change. */
292 r600_dirty_all_framebuffer_states(rscreen
);
293 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
296 void r600_texture_disable_dcc(struct r600_common_screen
*rscreen
,
297 struct r600_texture
*rtex
)
299 struct r600_common_context
*rctx
=
300 (struct r600_common_context
*)rscreen
->aux_context
;
302 if (!rtex
->dcc_offset
)
305 /* Decompress DCC. */
306 pipe_mutex_lock(rscreen
->aux_context_lock
);
307 rctx
->decompress_dcc(&rctx
->b
, rtex
);
308 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
309 pipe_mutex_unlock(rscreen
->aux_context_lock
);
312 rtex
->dcc_offset
= 0;
313 rtex
->cb_color_info
&= ~VI_S_028C70_DCC_ENABLE(1);
315 /* Notify all contexts about the change. */
316 r600_dirty_all_framebuffer_states(rscreen
);
319 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
320 struct pipe_resource
*resource
,
321 struct winsys_handle
*whandle
,
324 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
325 struct r600_resource
*res
= (struct r600_resource
*)resource
;
326 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
327 struct radeon_bo_metadata metadata
;
328 bool update_metadata
= false;
330 /* This is not supported now, but it might be required for OpenCL
331 * interop in the future.
333 if (resource
->target
!= PIPE_BUFFER
&&
334 (resource
->nr_samples
> 1 || rtex
->is_depth
))
337 if (resource
->target
!= PIPE_BUFFER
) {
338 /* Since shader image stores don't support DCC on VI,
339 * disable it for external clients that want write
342 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
343 r600_texture_disable_dcc(rscreen
, rtex
);
344 update_metadata
= true;
347 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
349 /* Eliminate fast clear (both CMASK and DCC) */
350 r600_eliminate_fast_color_clear(rscreen
, rtex
);
352 /* Disable CMASK if flush_resource isn't going
355 r600_texture_disable_cmask(rscreen
, rtex
);
356 update_metadata
= true;
360 if (!res
->is_shared
|| update_metadata
) {
361 r600_texture_init_metadata(rtex
, &metadata
);
362 if (rscreen
->query_opaque_metadata
)
363 rscreen
->query_opaque_metadata(rscreen
, rtex
,
366 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
370 if (res
->is_shared
) {
371 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
374 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
375 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
376 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
378 res
->is_shared
= true;
379 res
->external_usage
= usage
;
382 return rscreen
->ws
->buffer_get_handle(res
->buf
,
383 rtex
->surface
.level
[0].pitch_bytes
,
384 rtex
->surface
.level
[0].offset
,
385 rtex
->surface
.level
[0].slice_size
,
389 static void r600_texture_destroy(struct pipe_screen
*screen
,
390 struct pipe_resource
*ptex
)
392 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
393 struct r600_resource
*resource
= &rtex
->resource
;
395 if (rtex
->flushed_depth_texture
)
396 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
398 pipe_resource_reference((struct pipe_resource
**)&rtex
->htile_buffer
, NULL
);
399 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
400 pipe_resource_reference((struct pipe_resource
**)&rtex
->cmask_buffer
, NULL
);
402 pb_reference(&resource
->buf
, NULL
);
406 static const struct u_resource_vtbl r600_texture_vtbl
;
408 /* The number of samples can be specified independently of the texture. */
409 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
410 struct r600_texture
*rtex
,
412 struct r600_fmask_info
*out
)
414 /* FMASK is allocated like an ordinary texture. */
415 struct radeon_surf fmask
= rtex
->surface
;
417 memset(out
, 0, sizeof(*out
));
419 fmask
.bo_alignment
= 0;
422 fmask
.flags
|= RADEON_SURF_FMASK
;
424 /* Force 2D tiling if it wasn't set. This may occur when creating
425 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
426 * destination buffer must have an FMASK too. */
427 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
428 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
430 if (rscreen
->chip_class
>= SI
) {
431 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
434 switch (nr_samples
) {
438 if (rscreen
->chip_class
<= CAYMAN
) {
446 R600_ERR("Invalid sample count for FMASK allocation.\n");
450 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
451 * This can be fixed by writing a separate FMASK allocator specifically
452 * for R600-R700 asics. */
453 if (rscreen
->chip_class
<= R700
) {
457 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
458 R600_ERR("Got error in surface_init while allocating FMASK.\n");
462 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
464 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
465 if (out
->slice_tile_max
)
466 out
->slice_tile_max
-= 1;
468 out
->tile_mode_index
= fmask
.tiling_index
[0];
469 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
470 out
->bank_height
= fmask
.bankh
;
471 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
472 out
->size
= fmask
.bo_size
;
475 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
476 struct r600_texture
*rtex
)
478 r600_texture_get_fmask_info(rscreen
, rtex
,
479 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
481 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
482 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
485 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
486 struct r600_texture
*rtex
,
487 struct r600_cmask_info
*out
)
489 unsigned cmask_tile_width
= 8;
490 unsigned cmask_tile_height
= 8;
491 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
492 unsigned element_bits
= 4;
493 unsigned cmask_cache_bits
= 1024;
494 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
495 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
497 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
498 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
499 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
500 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
501 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
503 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
504 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
506 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
507 unsigned slice_bytes
=
508 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
510 assert(macro_tile_width
% 128 == 0);
511 assert(macro_tile_height
% 128 == 0);
513 out
->pitch
= pitch_elements
;
514 out
->height
= height
;
515 out
->xalign
= macro_tile_width
;
516 out
->yalign
= macro_tile_height
;
517 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
518 out
->alignment
= MAX2(256, base_align
);
519 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
520 align(slice_bytes
, base_align
);
523 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
524 struct r600_texture
*rtex
,
525 struct r600_cmask_info
*out
)
527 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
528 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
529 unsigned cl_width
, cl_height
;
544 case 16: /* Hawaii */
553 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
555 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
556 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
557 unsigned slice_elements
= (width
* height
) / (8*8);
559 /* Each element of CMASK is a nibble. */
560 unsigned slice_bytes
= slice_elements
/ 2;
563 out
->height
= height
;
564 out
->xalign
= cl_width
* 8;
565 out
->yalign
= cl_height
* 8;
566 out
->slice_tile_max
= (width
* height
) / (128*128);
567 if (out
->slice_tile_max
)
568 out
->slice_tile_max
-= 1;
570 out
->alignment
= MAX2(256, base_align
);
571 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
572 align(slice_bytes
, base_align
);
575 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
576 struct r600_texture
*rtex
)
578 if (rscreen
->chip_class
>= SI
) {
579 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
581 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
584 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
585 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
587 if (rscreen
->chip_class
>= SI
)
588 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
590 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
593 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
594 struct r600_texture
*rtex
)
596 if (rtex
->cmask_buffer
)
599 assert(rtex
->cmask
.size
== 0);
601 if (rscreen
->chip_class
>= SI
) {
602 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
604 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
607 rtex
->cmask_buffer
= (struct r600_resource
*)
608 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
609 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
610 if (rtex
->cmask_buffer
== NULL
) {
611 rtex
->cmask
.size
= 0;
615 /* update colorbuffer state bits */
616 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
618 if (rscreen
->chip_class
>= SI
)
619 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
621 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
623 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
626 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
627 struct r600_texture
*rtex
)
629 unsigned cl_width
, cl_height
, width
, height
;
630 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
631 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
633 if (rscreen
->chip_class
<= EVERGREEN
&&
634 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
637 /* HW bug on R6xx. */
638 if (rscreen
->chip_class
== R600
&&
639 (rtex
->surface
.level
[0].npix_x
> 7680 ||
640 rtex
->surface
.level
[0].npix_y
> 7680))
643 /* HTILE is broken with 1D tiling on old kernels and CIK. */
644 if (rscreen
->chip_class
>= CIK
&&
645 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
646 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
649 /* Overalign HTILE on P2 configs to work around GPU hangs in
650 * piglit/depthstencil-render-miplevels 585.
652 * This has been confirmed to help Kabini & Stoney, where the hangs
653 * are always reproducible. I think I have seen the test hang
654 * on Carrizo too, though it was very rare there.
656 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
685 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
686 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
688 slice_elements
= (width
* height
) / (8 * 8);
689 slice_bytes
= slice_elements
* 4;
691 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
692 base_align
= num_pipes
* pipe_interleave_bytes
;
694 rtex
->htile
.pitch
= width
;
695 rtex
->htile
.height
= height
;
696 rtex
->htile
.xalign
= cl_width
* 8;
697 rtex
->htile
.yalign
= cl_height
* 8;
699 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
700 align(slice_bytes
, base_align
);
703 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
704 struct r600_texture
*rtex
)
706 unsigned htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
711 rtex
->htile_buffer
= (struct r600_resource
*)
712 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
713 PIPE_USAGE_DEFAULT
, htile_size
);
714 if (rtex
->htile_buffer
== NULL
) {
715 /* this is not a fatal error as we can still keep rendering
716 * without htile buffer */
717 R600_ERR("Failed to create buffer object for htile buffer.\n");
719 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0,
720 htile_size
, 0, true);
724 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
728 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
729 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
730 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
731 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
732 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
733 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
734 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
735 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
736 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
738 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
739 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
740 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
741 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
742 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
743 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
745 if (rtex
->fmask
.size
)
746 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
747 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
748 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
749 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
750 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
752 if (rtex
->cmask
.size
)
753 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
754 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
755 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
756 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
757 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
759 if (rtex
->htile_buffer
)
760 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
761 "xalign=%u, yalign=%u\n",
762 rtex
->htile_buffer
->b
.b
.width0
,
763 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
764 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
);
766 if (rtex
->dcc_offset
) {
767 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
768 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
769 rtex
->surface
.dcc_alignment
);
770 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
771 fprintf(f
, " DCCLevel[%i]: offset=%"PRIu64
"\n",
772 i
, rtex
->surface
.level
[i
].dcc_offset
);
775 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
776 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
777 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
778 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
779 i
, rtex
->surface
.level
[i
].offset
,
780 rtex
->surface
.level
[i
].slice_size
,
781 u_minify(rtex
->resource
.b
.b
.width0
, i
),
782 u_minify(rtex
->resource
.b
.b
.height0
, i
),
783 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
784 rtex
->surface
.level
[i
].nblk_x
,
785 rtex
->surface
.level
[i
].nblk_y
,
786 rtex
->surface
.level
[i
].nblk_z
,
787 rtex
->surface
.level
[i
].pitch_bytes
,
788 rtex
->surface
.level
[i
].mode
);
790 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
791 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
792 fprintf(f
, " StencilLayout: tilesplit=%u\n",
793 rtex
->surface
.stencil_tile_split
);
794 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
795 "slice_size=%"PRIu64
", npix_x=%u, "
796 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
797 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
798 i
, rtex
->surface
.stencil_level
[i
].offset
,
799 rtex
->surface
.stencil_level
[i
].slice_size
,
800 u_minify(rtex
->resource
.b
.b
.width0
, i
),
801 u_minify(rtex
->resource
.b
.b
.height0
, i
),
802 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
803 rtex
->surface
.stencil_level
[i
].nblk_x
,
804 rtex
->surface
.stencil_level
[i
].nblk_y
,
805 rtex
->surface
.stencil_level
[i
].nblk_z
,
806 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
807 rtex
->surface
.stencil_level
[i
].mode
);
812 /* Common processing for r600_texture_create and r600_texture_from_handle */
813 static struct r600_texture
*
814 r600_texture_create_object(struct pipe_screen
*screen
,
815 const struct pipe_resource
*base
,
816 unsigned pitch_in_bytes_override
,
818 struct pb_buffer
*buf
,
819 struct radeon_surf
*surface
)
821 struct r600_texture
*rtex
;
822 struct r600_resource
*resource
;
823 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
825 rtex
= CALLOC_STRUCT(r600_texture
);
829 resource
= &rtex
->resource
;
830 resource
->b
.b
= *base
;
831 resource
->b
.vtbl
= &r600_texture_vtbl
;
832 pipe_reference_init(&resource
->b
.b
.reference
, 1);
833 resource
->b
.b
.screen
= screen
;
835 /* don't include stencil-only formats which we don't support for rendering */
836 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
838 rtex
->surface
= *surface
;
839 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
, offset
)) {
844 /* Tiled depth textures utilize the non-displayable tile order.
845 * This must be done after r600_setup_surface.
846 * Applies to R600-Cayman. */
847 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
849 if (rtex
->is_depth
) {
850 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
851 R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
852 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
)) {
854 r600_texture_allocate_htile(rscreen
, rtex
);
857 if (base
->nr_samples
> 1) {
859 r600_texture_allocate_fmask(rscreen
, rtex
);
860 r600_texture_allocate_cmask(rscreen
, rtex
);
861 rtex
->cmask_buffer
= &rtex
->resource
;
863 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
869 if (!buf
&& rtex
->surface
.dcc_size
&&
870 !(rscreen
->debug_flags
& DBG_NO_DCC
)) {
871 /* Reserve space for the DCC buffer. */
872 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
873 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
874 rtex
->cb_color_info
|= VI_S_028C70_DCC_ENABLE(1);
878 /* Now create the backing buffer. */
880 if (!r600_init_resource(rscreen
, resource
, rtex
->size
,
881 rtex
->surface
.bo_alignment
, TRUE
)) {
887 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
888 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
891 if (rtex
->cmask
.size
) {
892 /* Initialize the cmask to 0xCC (= compressed state). */
893 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
894 rtex
->cmask
.offset
, rtex
->cmask
.size
,
897 if (rtex
->dcc_offset
) {
898 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
900 rtex
->surface
.dcc_size
,
904 /* Initialize the CMASK base register value. */
905 rtex
->cmask
.base_address_reg
=
906 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
908 if (rscreen
->debug_flags
& DBG_VM
) {
909 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
910 rtex
->resource
.gpu_address
,
911 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
912 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
913 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
916 if (rscreen
->debug_flags
& DBG_TEX
) {
918 r600_print_texture_info(rtex
, stdout
);
924 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
925 const struct pipe_resource
*templ
)
927 const struct util_format_description
*desc
= util_format_description(templ
->format
);
928 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
930 /* MSAA resources must be 2D tiled. */
931 if (templ
->nr_samples
> 1)
932 return RADEON_SURF_MODE_2D
;
934 /* Transfer resources should be linear. */
935 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
936 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
938 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
939 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
940 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
941 (templ
->target
== PIPE_TEXTURE_2D
||
942 templ
->target
== PIPE_TEXTURE_3D
))
945 /* Handle common candidates for the linear mode.
946 * Compressed textures and DB surfaces must always be tiled.
948 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
949 (!util_format_is_depth_or_stencil(templ
->format
) ||
950 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
951 if (rscreen
->debug_flags
& DBG_NO_TILING
)
952 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
954 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
955 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
956 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
958 /* Cursors are linear on SI.
959 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
960 if (rscreen
->chip_class
>= SI
&&
961 (templ
->bind
& PIPE_BIND_CURSOR
))
962 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
964 if (templ
->bind
& PIPE_BIND_LINEAR
)
965 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
967 /* Textures with a very small height are recommended to be linear. */
968 if (templ
->target
== PIPE_TEXTURE_1D
||
969 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
971 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
973 /* Textures likely to be mapped often. */
974 if (templ
->usage
== PIPE_USAGE_STAGING
||
975 templ
->usage
== PIPE_USAGE_STREAM
)
976 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
979 /* Make small textures 1D tiled. */
980 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
981 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
982 return RADEON_SURF_MODE_1D
;
984 /* The allocator will switch to 1D if needed. */
985 return RADEON_SURF_MODE_2D
;
988 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
989 const struct pipe_resource
*templ
)
991 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
992 struct radeon_surf surface
= {0};
995 r
= r600_init_surface(rscreen
, &surface
, templ
,
996 r600_choose_tiling(rscreen
, templ
),
997 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1001 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
1005 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, 0,
1009 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1010 const struct pipe_resource
*templ
,
1011 struct winsys_handle
*whandle
,
1014 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1015 struct pb_buffer
*buf
= NULL
;
1016 unsigned stride
= 0, offset
= 0;
1017 unsigned array_mode
;
1018 struct radeon_surf surface
;
1020 struct radeon_bo_metadata metadata
= {};
1021 struct r600_texture
*rtex
;
1023 /* Support only 2D textures without mipmaps */
1024 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1025 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1028 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1032 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1034 surface
.bankw
= metadata
.bankw
;
1035 surface
.bankh
= metadata
.bankh
;
1036 surface
.tile_split
= metadata
.tile_split
;
1037 surface
.stencil_tile_split
= metadata
.stencil_tile_split
;
1038 surface
.mtilea
= metadata
.mtilea
;
1040 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1041 array_mode
= RADEON_SURF_MODE_2D
;
1042 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1043 array_mode
= RADEON_SURF_MODE_1D
;
1045 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1047 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
1052 if (metadata
.scanout
)
1053 surface
.flags
|= RADEON_SURF_SCANOUT
;
1055 rtex
= r600_texture_create_object(screen
, templ
, stride
,
1056 offset
, buf
, &surface
);
1060 rtex
->resource
.is_shared
= true;
1061 rtex
->resource
.external_usage
= usage
;
1062 return &rtex
->resource
.b
.b
;
1065 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1066 struct pipe_resource
*texture
,
1067 struct r600_texture
**staging
)
1069 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1070 struct pipe_resource resource
;
1071 struct r600_texture
**flushed_depth_texture
= staging
?
1072 staging
: &rtex
->flushed_depth_texture
;
1074 if (!staging
&& rtex
->flushed_depth_texture
)
1075 return true; /* it's ready */
1077 resource
.target
= texture
->target
;
1078 resource
.format
= texture
->format
;
1079 resource
.width0
= texture
->width0
;
1080 resource
.height0
= texture
->height0
;
1081 resource
.depth0
= texture
->depth0
;
1082 resource
.array_size
= texture
->array_size
;
1083 resource
.last_level
= texture
->last_level
;
1084 resource
.nr_samples
= texture
->nr_samples
;
1085 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1086 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1087 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1090 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1092 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1093 if (*flushed_depth_texture
== NULL
) {
1094 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1098 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
1099 (*flushed_depth_texture
)->non_disp_tiling
= false;
1104 * Initialize the pipe_resource descriptor to be of the same size as the box,
1105 * which is supposed to hold a subregion of the texture "orig" at the given
1108 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1109 struct pipe_resource
*orig
,
1110 const struct pipe_box
*box
,
1111 unsigned level
, unsigned flags
)
1113 memset(res
, 0, sizeof(*res
));
1114 res
->format
= orig
->format
;
1115 res
->width0
= box
->width
;
1116 res
->height0
= box
->height
;
1118 res
->array_size
= 1;
1119 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1122 /* We must set the correct texture target and dimensions for a 3D box. */
1123 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0)
1124 res
->target
= orig
->target
;
1126 res
->target
= PIPE_TEXTURE_2D
;
1128 switch (res
->target
) {
1129 case PIPE_TEXTURE_1D_ARRAY
:
1130 case PIPE_TEXTURE_2D_ARRAY
:
1131 case PIPE_TEXTURE_CUBE_ARRAY
:
1132 res
->array_size
= box
->depth
;
1134 case PIPE_TEXTURE_3D
:
1135 res
->depth0
= box
->depth
;
1141 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1142 struct pipe_resource
*texture
,
1145 const struct pipe_box
*box
,
1146 struct pipe_transfer
**ptransfer
)
1148 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1149 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1150 struct r600_transfer
*trans
;
1151 boolean use_staging_texture
= FALSE
;
1152 struct r600_resource
*buf
;
1153 unsigned offset
= 0;
1156 /* We cannot map a tiled texture directly because the data is
1157 * in a different order, therefore we do detiling using a blit.
1159 * Also, use a temporary in GTT memory for read transfers, as
1160 * the CPU is much happier reading out of cached system memory
1161 * than uncached VRAM.
1163 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
) {
1164 use_staging_texture
= TRUE
;
1165 } else if ((usage
& PIPE_TRANSFER_READ
) && !(usage
& PIPE_TRANSFER_MAP_DIRECTLY
) &&
1166 (rtex
->resource
.domains
== RADEON_DOMAIN_VRAM
)) {
1167 /* Untiled buffers in VRAM, which is slow for CPU reads */
1168 use_staging_texture
= TRUE
;
1169 } else if (!(usage
& PIPE_TRANSFER_READ
) &&
1170 (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
, RADEON_USAGE_READWRITE
) ||
1171 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0, RADEON_USAGE_READWRITE
))) {
1172 /* Use a staging texture for uploads if the underlying BO is busy. */
1173 use_staging_texture
= TRUE
;
1176 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
1177 use_staging_texture
= FALSE
;
1180 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
1184 trans
= CALLOC_STRUCT(r600_transfer
);
1187 trans
->transfer
.resource
= texture
;
1188 trans
->transfer
.level
= level
;
1189 trans
->transfer
.usage
= usage
;
1190 trans
->transfer
.box
= *box
;
1192 if (rtex
->is_depth
) {
1193 struct r600_texture
*staging_depth
;
1195 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1196 /* MSAA depth buffers need to be converted to single sample buffers.
1198 * Mapping MSAA depth buffers can occur if ReadPixels is called
1199 * with a multisample GLX visual.
1201 * First downsample the depth buffer to a temporary texture,
1202 * then decompress the temporary one to staging.
1204 * Only the region being mapped is transfered.
1206 struct pipe_resource resource
;
1208 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1210 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1211 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1216 if (usage
& PIPE_TRANSFER_READ
) {
1217 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1219 R600_ERR("failed to create a temporary depth texture\n");
1224 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1225 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1226 0, 0, 0, box
->depth
, 0, 0);
1227 pipe_resource_reference(&temp
, NULL
);
1231 /* XXX: only readback the rectangle which is being mapped? */
1232 /* XXX: when discard is true, no need to read back from depth texture */
1233 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1234 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1239 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1241 box
->z
, box
->z
+ box
->depth
- 1,
1244 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1247 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1248 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1249 trans
->staging
= (struct r600_resource
*)staging_depth
;
1250 } else if (use_staging_texture
) {
1251 struct pipe_resource resource
;
1252 struct r600_texture
*staging
;
1254 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1255 R600_RESOURCE_FLAG_TRANSFER
);
1256 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1257 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1259 /* Create the temporary texture. */
1260 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1262 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1266 trans
->staging
= &staging
->resource
;
1267 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1268 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1269 if (usage
& PIPE_TRANSFER_READ
) {
1270 r600_copy_to_staging_texture(ctx
, trans
);
1273 /* the resource is mapped directly */
1274 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1275 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1276 offset
= r600_texture_get_offset(rtex
, level
, box
);
1279 if (trans
->staging
) {
1280 buf
= trans
->staging
;
1281 if (!rtex
->is_depth
&& !(usage
& PIPE_TRANSFER_READ
))
1282 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1284 buf
= &rtex
->resource
;
1287 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1288 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
1293 *ptransfer
= &trans
->transfer
;
1294 return map
+ offset
;
1297 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1298 struct pipe_transfer
* transfer
)
1300 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1301 struct pipe_resource
*texture
= transfer
->resource
;
1302 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1304 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1305 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1306 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1307 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1308 &rtransfer
->staging
->b
.b
, transfer
->level
,
1311 r600_copy_from_staging_texture(ctx
, rtransfer
);
1315 if (rtransfer
->staging
)
1316 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
1321 static const struct u_resource_vtbl r600_texture_vtbl
=
1323 NULL
, /* get_handle */
1324 r600_texture_destroy
, /* resource_destroy */
1325 r600_texture_transfer_map
, /* transfer_map */
1326 u_default_transfer_flush_region
, /* transfer_flush_region */
1327 r600_texture_transfer_unmap
, /* transfer_unmap */
1328 NULL
/* transfer_inline_write */
1331 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1332 struct pipe_resource
*texture
,
1333 const struct pipe_surface
*templ
,
1334 unsigned width
, unsigned height
)
1336 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1341 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1342 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1344 pipe_reference_init(&surface
->base
.reference
, 1);
1345 pipe_resource_reference(&surface
->base
.texture
, texture
);
1346 surface
->base
.context
= pipe
;
1347 surface
->base
.format
= templ
->format
;
1348 surface
->base
.width
= width
;
1349 surface
->base
.height
= height
;
1350 surface
->base
.u
= templ
->u
;
1351 return &surface
->base
;
1354 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1355 struct pipe_resource
*tex
,
1356 const struct pipe_surface
*templ
)
1358 unsigned level
= templ
->u
.tex
.level
;
1359 unsigned width
= u_minify(tex
->width0
, level
);
1360 unsigned height
= u_minify(tex
->height0
, level
);
1362 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1363 const struct util_format_description
*tex_desc
1364 = util_format_description(tex
->format
);
1365 const struct util_format_description
*templ_desc
1366 = util_format_description(templ
->format
);
1368 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1370 /* Adjust size of surface if and only if the block width or
1371 * height is changed. */
1372 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1373 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1374 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1375 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1377 width
= nblks_x
* templ_desc
->block
.width
;
1378 height
= nblks_y
* templ_desc
->block
.height
;
1382 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1385 static void r600_surface_destroy(struct pipe_context
*pipe
,
1386 struct pipe_surface
*surface
)
1388 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1389 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
1390 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
1391 pipe_resource_reference(&surface
->texture
, NULL
);
1395 unsigned r600_translate_colorswap(enum pipe_format format
)
1397 const struct util_format_description
*desc
= util_format_description(format
);
1399 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1401 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1402 return V_0280A0_SWAP_STD
;
1404 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1407 switch (desc
->nr_channels
) {
1409 if (HAS_SWIZZLE(0,X
))
1410 return V_0280A0_SWAP_STD
; /* X___ */
1411 else if (HAS_SWIZZLE(3,X
))
1412 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1415 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1416 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1417 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1418 return V_0280A0_SWAP_STD
; /* XY__ */
1419 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1420 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1421 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1422 return V_0280A0_SWAP_STD_REV
; /* YX__ */
1423 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1424 return V_0280A0_SWAP_ALT
; /* X__Y */
1425 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1426 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1429 if (HAS_SWIZZLE(0,X
))
1430 return V_0280A0_SWAP_STD
; /* XYZ */
1431 else if (HAS_SWIZZLE(0,Z
))
1432 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1435 /* check the middle channels, the 1st and 4th channel can be NONE */
1436 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
))
1437 return V_0280A0_SWAP_STD
; /* XYZW */
1438 else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
))
1439 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1440 else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
))
1441 return V_0280A0_SWAP_ALT
; /* ZYXW */
1442 else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
))
1443 return V_0280A0_SWAP_ALT_REV
; /* YZWX */
1449 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
1450 enum pipe_format surface_format
,
1451 const union pipe_color_union
*color
)
1453 union util_color uc
;
1455 memset(&uc
, 0, sizeof(uc
));
1457 if (util_format_is_pure_uint(surface_format
)) {
1458 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
1459 } else if (util_format_is_pure_sint(surface_format
)) {
1460 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
1462 util_pack_color(color
->f
, surface_format
, &uc
);
1465 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
1468 static void vi_get_fast_clear_parameters(enum pipe_format surface_format
,
1469 const union pipe_color_union
*color
,
1470 uint32_t* reset_value
,
1471 bool* clear_words_needed
)
1473 bool values
[4] = {};
1475 bool main_value
= false;
1476 bool extra_value
= false;
1478 const struct util_format_description
*desc
= util_format_description(surface_format
);
1480 *clear_words_needed
= true;
1481 *reset_value
= 0x20202020U
;
1483 /* If we want to clear without needing a fast clear eliminate step, we
1484 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1485 * have two sets of flags, one for the last or first channel(extra) and
1486 * one for the other channels(main).
1489 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
1490 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
1491 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
1493 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
1494 if(r600_translate_colorswap(surface_format
) <= 1)
1495 extra_channel
= desc
->nr_channels
- 1;
1501 for (i
= 0; i
< 4; ++i
) {
1502 int index
= desc
->swizzle
[i
] - UTIL_FORMAT_SWIZZLE_X
;
1504 if (desc
->swizzle
[i
] < UTIL_FORMAT_SWIZZLE_X
||
1505 desc
->swizzle
[i
] > UTIL_FORMAT_SWIZZLE_W
)
1508 if (util_format_is_pure_sint(surface_format
)) {
1509 values
[i
] = color
->i
[i
] != 0;
1510 if (color
->i
[i
] != 0 && color
->i
[i
] != INT32_MAX
)
1512 } else if (util_format_is_pure_uint(surface_format
)) {
1513 values
[i
] = color
->ui
[i
] != 0U;
1514 if (color
->ui
[i
] != 0U && color
->ui
[i
] != UINT32_MAX
)
1517 values
[i
] = color
->f
[i
] != 0.0F
;
1518 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
1522 if (index
== extra_channel
)
1523 extra_value
= values
[i
];
1525 main_value
= values
[i
];
1528 for (int i
= 0; i
< 4; ++i
)
1529 if (values
[i
] != main_value
&&
1530 desc
->swizzle
[i
] - UTIL_FORMAT_SWIZZLE_X
!= extra_channel
&&
1531 desc
->swizzle
[i
] >= UTIL_FORMAT_SWIZZLE_X
&&
1532 desc
->swizzle
[i
] <= UTIL_FORMAT_SWIZZLE_W
)
1535 *clear_words_needed
= false;
1537 *reset_value
|= 0x80808080U
;
1540 *reset_value
|= 0x40404040U
;
1543 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
1544 struct pipe_framebuffer_state
*fb
,
1545 struct r600_atom
*fb_state
,
1546 unsigned *buffers
, unsigned *dirty_cbufs
,
1547 const union pipe_color_union
*color
)
1551 /* This function is broken in BE, so just disable this path for now */
1552 #ifdef PIPE_ARCH_BIG_ENDIAN
1556 if (rctx
->render_cond
)
1559 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1560 struct r600_texture
*tex
;
1561 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
1566 /* if this colorbuffer is not being cleared */
1567 if (!(*buffers
& clear_bit
))
1570 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
1572 /* 128-bit formats are unusupported */
1573 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
1577 /* the clear is allowed if all layers are bound */
1578 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
1579 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
1583 /* cannot clear mipmapped textures */
1584 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
1588 /* only supported on tiled surfaces */
1589 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
1593 /* shared textures can't use fast clear without an explicit flush,
1594 * because there is no way to communicate the clear color among
1597 if (tex
->resource
.is_shared
&&
1598 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
1601 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1602 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
1603 rctx
->chip_class
>= CIK
&&
1604 rctx
->screen
->info
.drm_major
== 2 &&
1605 rctx
->screen
->info
.drm_minor
< 38) {
1609 if (tex
->dcc_offset
) {
1610 uint32_t reset_value
;
1611 bool clear_words_needed
;
1613 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
1616 vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
, color
, &reset_value
, &clear_words_needed
);
1618 rctx
->clear_buffer(&rctx
->b
, &tex
->resource
.b
.b
,
1619 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1622 if (clear_words_needed
)
1623 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
1625 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1626 if (rctx
->family
== CHIP_STONEY
)
1629 /* ensure CMASK is enabled */
1630 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
1631 if (tex
->cmask
.size
== 0) {
1635 /* Do the fast clear. */
1636 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
1637 tex
->cmask
.offset
, tex
->cmask
.size
, 0, true);
1639 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
1642 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
1645 *dirty_cbufs
|= 1 << i
;
1646 rctx
->set_atom_dirty(rctx
, fb_state
, true);
1647 *buffers
&= ~clear_bit
;
1651 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
1653 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
1654 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
1657 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
1659 rctx
->b
.create_surface
= r600_create_surface
;
1660 rctx
->b
.surface_destroy
= r600_surface_destroy
;