2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& src_level
< rsrc
->surface
.num_dcc_levels
) ||
76 (rdst
->dcc_offset
&& dst_level
< rdst
->surface
.num_dcc_levels
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
184 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
185 (box
->y
/ rtex
->surface
.blk_h
*
186 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
187 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
190 static int r600_init_surface(struct r600_common_screen
*rscreen
,
191 struct radeon_surf
*surface
,
192 const struct pipe_resource
*ptex
,
193 enum radeon_surf_mode array_mode
,
194 unsigned pitch_in_bytes_override
,
198 bool is_flushed_depth
,
199 bool tc_compatible_htile
)
201 const struct util_format_description
*desc
=
202 util_format_description(ptex
->format
);
203 bool is_depth
, is_stencil
;
205 unsigned i
, bpe
, flags
= 0;
207 is_depth
= util_format_has_depth(desc
);
208 is_stencil
= util_format_has_stencil(desc
);
210 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
211 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
212 bpe
= 4; /* stencil is allocated separately on evergreen */
214 bpe
= util_format_get_blocksize(ptex
->format
);
215 /* align byte per element on dword */
221 if (!is_flushed_depth
&& is_depth
) {
222 flags
|= RADEON_SURF_ZBUFFER
;
224 if (tc_compatible_htile
&&
225 (rscreen
->chip_class
>= GFX9
||
226 array_mode
== RADEON_SURF_MODE_2D
)) {
227 /* TC-compatible HTILE only supports Z32_FLOAT.
228 * GFX9 also supports Z16_UNORM.
229 * On VI, promote Z16 to Z32. DB->CB copies will convert
230 * the format for transfers.
232 if (rscreen
->chip_class
== VI
)
235 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
239 flags
|= RADEON_SURF_SBUFFER
;
242 if (rscreen
->chip_class
>= VI
&&
243 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
244 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
245 flags
|= RADEON_SURF_DISABLE_DCC
;
247 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
248 /* This should catch bugs in gallium users setting incorrect flags. */
249 assert(ptex
->nr_samples
<= 1 &&
250 ptex
->array_size
== 1 &&
252 ptex
->last_level
== 0 &&
253 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
255 flags
|= RADEON_SURF_SCANOUT
;
259 flags
|= RADEON_SURF_IMPORTED
;
260 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
261 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
263 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
264 array_mode
, surface
);
269 if (pitch_in_bytes_override
&&
270 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
271 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
274 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
275 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
* surface
->u
.legacy
.level
[0].nblk_y
;
279 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
280 surface
->u
.legacy
.level
[i
].offset
+= offset
;
285 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
286 struct r600_texture
*rtex
,
287 struct radeon_bo_metadata
*metadata
)
289 struct radeon_surf
*surface
= &rtex
->surface
;
291 memset(metadata
, 0, sizeof(*metadata
));
293 if (rscreen
->chip_class
>= GFX9
) {
295 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
296 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
297 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
298 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
299 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
300 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
301 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
302 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
303 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
304 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
305 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
306 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
310 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
311 struct r600_texture
*rtex
)
313 struct r600_common_screen
*rscreen
= rctx
->screen
;
314 struct pipe_context
*ctx
= &rctx
->b
;
316 if (ctx
== rscreen
->aux_context
)
317 mtx_lock(&rscreen
->aux_context_lock
);
319 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
320 ctx
->flush(ctx
, NULL
, 0);
322 if (ctx
== rscreen
->aux_context
)
323 mtx_unlock(&rscreen
->aux_context_lock
);
326 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
327 struct r600_texture
*rtex
)
329 if (!rtex
->cmask
.size
)
332 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
335 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
336 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
337 rtex
->dirty_level_mask
= 0;
339 if (rscreen
->chip_class
>= SI
)
340 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
342 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
344 if (rtex
->cmask_buffer
!= &rtex
->resource
)
345 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
347 /* Notify all contexts about the change. */
348 p_atomic_inc(&rscreen
->dirty_tex_counter
);
349 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
352 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
354 /* We can't disable DCC if it can be written by another process. */
355 return rtex
->dcc_offset
&&
356 (!rtex
->resource
.is_shared
||
357 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
360 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
361 struct r600_texture
*rtex
)
363 if (!r600_can_disable_dcc(rtex
))
366 assert(rtex
->dcc_separate_buffer
== NULL
);
369 rtex
->dcc_offset
= 0;
371 /* Notify all contexts about the change. */
372 p_atomic_inc(&rscreen
->dirty_tex_counter
);
377 * Disable DCC for the texture. (first decompress, then discard metadata).
379 * There is unresolved multi-context synchronization issue between
380 * screen::aux_context and the current context. If applications do this with
381 * multiple contexts, it's already undefined behavior for them and we don't
382 * have to worry about that. The scenario is:
384 * If context 1 disables DCC and context 2 has queued commands that write
385 * to the texture via CB with DCC enabled, and the order of operations is
387 * context 2 queues draw calls rendering to the texture, but doesn't flush
388 * context 1 disables DCC and flushes
389 * context 1 & 2 reset descriptors and FB state
390 * context 2 flushes (new compressed tiles written by the draw calls)
391 * context 1 & 2 read garbage, because DCC is disabled, yet there are
394 * \param rctx the current context if you have one, or rscreen->aux_context
397 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
398 struct r600_texture
*rtex
)
400 struct r600_common_screen
*rscreen
= rctx
->screen
;
402 if (!r600_can_disable_dcc(rtex
))
405 if (&rctx
->b
== rscreen
->aux_context
)
406 mtx_lock(&rscreen
->aux_context_lock
);
408 /* Decompress DCC. */
409 rctx
->decompress_dcc(&rctx
->b
, rtex
);
410 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
412 if (&rctx
->b
== rscreen
->aux_context
)
413 mtx_unlock(&rscreen
->aux_context_lock
);
415 return r600_texture_discard_dcc(rscreen
, rtex
);
418 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
419 struct r600_texture
*rtex
,
420 bool invalidate_storage
)
422 struct pipe_screen
*screen
= rctx
->b
.screen
;
423 struct r600_texture
*new_tex
;
424 struct pipe_resource templ
= rtex
->resource
.b
.b
;
427 templ
.bind
|= PIPE_BIND_LINEAR
;
429 /* r600g doesn't react to dirty_tex_descriptor_counter */
430 if (rctx
->chip_class
< SI
)
433 if (rtex
->resource
.is_shared
||
434 rtex
->surface
.is_linear
)
437 /* This fails with MSAA, depth, and compressed textures. */
438 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
439 RADEON_SURF_MODE_LINEAR_ALIGNED
)
442 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
446 /* Copy the pixels to the new texture. */
447 if (!invalidate_storage
) {
448 for (i
= 0; i
<= templ
.last_level
; i
++) {
452 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
453 util_max_layer(&templ
, i
) + 1, &box
);
455 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
456 &rtex
->resource
.b
.b
, i
, &box
);
460 r600_texture_discard_cmask(rctx
->screen
, rtex
);
461 r600_texture_discard_dcc(rctx
->screen
, rtex
);
463 /* Replace the structure fields of rtex. */
464 rtex
->resource
.b
.b
.bind
= templ
.bind
;
465 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
466 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
467 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
468 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
469 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
470 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
471 rtex
->resource
.domains
= new_tex
->resource
.domains
;
472 rtex
->resource
.flags
= new_tex
->resource
.flags
;
473 rtex
->size
= new_tex
->size
;
474 rtex
->surface
= new_tex
->surface
;
475 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
476 rtex
->cb_color_info
= new_tex
->cb_color_info
;
477 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
479 assert(!rtex
->htile_buffer
);
480 assert(!rtex
->cmask
.size
);
481 assert(!rtex
->fmask
.size
);
482 assert(!rtex
->dcc_offset
);
483 assert(!rtex
->is_depth
);
485 r600_texture_reference(&new_tex
, NULL
);
487 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
490 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
491 struct pipe_context
*ctx
,
492 struct pipe_resource
*resource
,
493 struct winsys_handle
*whandle
,
496 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
497 struct r600_common_context
*rctx
= (struct r600_common_context
*)
498 (ctx
? ctx
: rscreen
->aux_context
);
499 struct r600_resource
*res
= (struct r600_resource
*)resource
;
500 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
501 struct radeon_bo_metadata metadata
;
502 bool update_metadata
= false;
503 unsigned stride
, offset
, slice_size
;
505 /* This is not supported now, but it might be required for OpenCL
506 * interop in the future.
508 if (resource
->target
!= PIPE_BUFFER
&&
509 (resource
->nr_samples
> 1 || rtex
->is_depth
))
512 if (resource
->target
!= PIPE_BUFFER
) {
513 /* Since shader image stores don't support DCC on VI,
514 * disable it for external clients that want write
517 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
518 if (r600_texture_disable_dcc(rctx
, rtex
))
519 update_metadata
= true;
522 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
523 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
524 /* Eliminate fast clear (both CMASK and DCC) */
525 r600_eliminate_fast_color_clear(rctx
, rtex
);
527 /* Disable CMASK if flush_resource isn't going
530 if (rtex
->cmask
.size
)
531 r600_texture_discard_cmask(rscreen
, rtex
);
535 if (!res
->is_shared
|| update_metadata
) {
536 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
537 if (rscreen
->query_opaque_metadata
)
538 rscreen
->query_opaque_metadata(rscreen
, rtex
,
541 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
545 if (res
->is_shared
) {
546 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
549 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
550 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
551 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
553 res
->is_shared
= true;
554 res
->external_usage
= usage
;
557 if (rscreen
->chip_class
>= GFX9
) {
559 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
561 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
563 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
564 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
566 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
568 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
569 slice_size
, whandle
);
572 static void r600_texture_destroy(struct pipe_screen
*screen
,
573 struct pipe_resource
*ptex
)
575 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
576 struct r600_resource
*resource
= &rtex
->resource
;
578 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
580 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
581 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
582 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
584 pb_reference(&resource
->buf
, NULL
);
585 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
586 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
590 static const struct u_resource_vtbl r600_texture_vtbl
;
592 /* The number of samples can be specified independently of the texture. */
593 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
594 struct r600_texture
*rtex
,
596 struct r600_fmask_info
*out
)
598 /* FMASK is allocated like an ordinary texture. */
599 struct pipe_resource templ
= rtex
->resource
.b
.b
;
600 struct radeon_surf fmask
= {};
603 memset(out
, 0, sizeof(*out
));
605 if (rscreen
->chip_class
>= GFX9
) {
606 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
607 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
611 templ
.nr_samples
= 1;
612 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
614 if (rscreen
->chip_class
<= CAYMAN
) {
615 /* Use the same parameters and tile mode. */
616 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
617 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
618 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
619 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
622 fmask
.u
.legacy
.bankh
= 4;
625 switch (nr_samples
) {
634 R600_ERR("Invalid sample count for FMASK allocation.\n");
638 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
639 * This can be fixed by writing a separate FMASK allocator specifically
640 * for R600-R700 asics. */
641 if (rscreen
->chip_class
<= R700
) {
645 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
646 RADEON_SURF_MODE_2D
, &fmask
)) {
647 R600_ERR("Got error in surface_init while allocating FMASK.\n");
651 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
653 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
654 if (out
->slice_tile_max
)
655 out
->slice_tile_max
-= 1;
657 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
658 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
659 out
->bank_height
= fmask
.u
.legacy
.bankh
;
660 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
661 out
->size
= fmask
.surf_size
;
664 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
665 struct r600_texture
*rtex
)
667 r600_texture_get_fmask_info(rscreen
, rtex
,
668 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
670 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
671 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
674 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
675 struct r600_texture
*rtex
,
676 struct r600_cmask_info
*out
)
678 unsigned cmask_tile_width
= 8;
679 unsigned cmask_tile_height
= 8;
680 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
681 unsigned element_bits
= 4;
682 unsigned cmask_cache_bits
= 1024;
683 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
684 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
686 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
687 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
688 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
689 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
690 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
692 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
693 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
695 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
696 unsigned slice_bytes
=
697 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
699 assert(macro_tile_width
% 128 == 0);
700 assert(macro_tile_height
% 128 == 0);
702 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
703 out
->alignment
= MAX2(256, base_align
);
704 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
705 align(slice_bytes
, base_align
);
708 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
709 struct r600_texture
*rtex
,
710 struct r600_cmask_info
*out
)
712 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
713 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
714 unsigned cl_width
, cl_height
;
716 if (rscreen
->chip_class
>= GFX9
) {
717 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
718 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
735 case 16: /* Hawaii */
744 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
746 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
747 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
748 unsigned slice_elements
= (width
* height
) / (8*8);
750 /* Each element of CMASK is a nibble. */
751 unsigned slice_bytes
= slice_elements
/ 2;
753 out
->slice_tile_max
= (width
* height
) / (128*128);
754 if (out
->slice_tile_max
)
755 out
->slice_tile_max
-= 1;
757 out
->alignment
= MAX2(256, base_align
);
758 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
759 align(slice_bytes
, base_align
);
762 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
763 struct r600_texture
*rtex
)
765 if (rscreen
->chip_class
>= SI
) {
766 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
768 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
771 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
772 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
774 if (rscreen
->chip_class
>= SI
)
775 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
777 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
780 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
781 struct r600_texture
*rtex
)
783 if (rtex
->cmask_buffer
)
786 assert(rtex
->cmask
.size
== 0);
788 if (rscreen
->chip_class
>= SI
) {
789 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
791 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
794 rtex
->cmask_buffer
= (struct r600_resource
*)
795 r600_aligned_buffer_create(&rscreen
->b
,
796 R600_RESOURCE_FLAG_UNMAPPABLE
,
799 rtex
->cmask
.alignment
);
800 if (rtex
->cmask_buffer
== NULL
) {
801 rtex
->cmask
.size
= 0;
805 /* update colorbuffer state bits */
806 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
808 if (rscreen
->chip_class
>= SI
)
809 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
811 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
813 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
816 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
817 struct r600_texture
*rtex
)
819 unsigned cl_width
, cl_height
, width
, height
;
820 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
821 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
823 assert(rscreen
->chip_class
<= VI
);
825 rtex
->surface
.htile_size
= 0;
827 if (rscreen
->chip_class
<= EVERGREEN
&&
828 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
831 /* HW bug on R6xx. */
832 if (rscreen
->chip_class
== R600
&&
833 (rtex
->resource
.b
.b
.width0
> 7680 ||
834 rtex
->resource
.b
.b
.height0
> 7680))
837 /* HTILE is broken with 1D tiling on old kernels and CIK. */
838 if (rscreen
->chip_class
>= CIK
&&
839 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
840 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
843 /* Overalign HTILE on P2 configs to work around GPU hangs in
844 * piglit/depthstencil-render-miplevels 585.
846 * This has been confirmed to help Kabini & Stoney, where the hangs
847 * are always reproducible. I think I have seen the test hang
848 * on Carrizo too, though it was very rare there.
850 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
879 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
880 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
882 slice_elements
= (width
* height
) / (8 * 8);
883 slice_bytes
= slice_elements
* 4;
885 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
886 base_align
= num_pipes
* pipe_interleave_bytes
;
888 rtex
->surface
.htile_alignment
= base_align
;
889 rtex
->surface
.htile_size
=
890 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
891 align(slice_bytes
, base_align
);
894 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
895 struct r600_texture
*rtex
)
897 uint32_t clear_value
;
899 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
) {
900 clear_value
= 0x0000030F;
902 r600_texture_get_htile_size(rscreen
, rtex
);
906 if (!rtex
->surface
.htile_size
)
909 rtex
->htile_buffer
= (struct r600_resource
*)
910 r600_aligned_buffer_create(&rscreen
->b
,
911 R600_RESOURCE_FLAG_UNMAPPABLE
,
913 rtex
->surface
.htile_size
,
914 rtex
->surface
.htile_alignment
);
915 if (rtex
->htile_buffer
== NULL
) {
916 /* this is not a fatal error as we can still keep rendering
917 * without htile buffer */
918 R600_ERR("Failed to create buffer object for htile buffer.\n");
920 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
921 0, rtex
->surface
.htile_size
,
926 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
927 struct r600_texture
*rtex
, FILE *f
)
931 /* Common parameters. */
932 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
933 "blk_h=%u, array_size=%u, last_level=%u, "
934 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
935 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
936 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
938 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
939 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
940 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
942 if (rscreen
->chip_class
>= GFX9
) {
943 fprintf(f
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
944 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
945 rtex
->surface
.surf_size
,
946 rtex
->surface
.u
.gfx9
.surf_slice_size
,
947 rtex
->surface
.surf_alignment
,
948 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
949 rtex
->surface
.u
.gfx9
.surf
.epitch
,
950 rtex
->surface
.u
.gfx9
.surf_pitch
);
952 if (rtex
->fmask
.size
) {
953 fprintf(f
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
954 "alignment=%u, swmode=%u, epitch=%u\n",
956 rtex
->surface
.u
.gfx9
.fmask_size
,
957 rtex
->surface
.u
.gfx9
.fmask_alignment
,
958 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
959 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
962 if (rtex
->cmask
.size
) {
963 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
964 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
966 rtex
->surface
.u
.gfx9
.cmask_size
,
967 rtex
->surface
.u
.gfx9
.cmask_alignment
,
968 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
969 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
972 if (rtex
->htile_buffer
) {
973 fprintf(f
, " HTile: size=%u, alignment=%u, "
974 "rb_aligned=%u, pipe_aligned=%u\n",
975 rtex
->htile_buffer
->b
.b
.width0
,
976 rtex
->htile_buffer
->buf
->alignment
,
977 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
978 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
981 if (rtex
->dcc_offset
) {
982 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
983 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
984 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
985 rtex
->surface
.dcc_alignment
,
986 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
987 rtex
->surface
.num_dcc_levels
);
990 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
991 fprintf(f
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
992 rtex
->surface
.u
.gfx9
.stencil_offset
,
993 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
994 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
999 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1000 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1001 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1002 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1003 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1004 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1006 if (rtex
->fmask
.size
)
1007 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1008 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1009 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1010 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1011 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1013 if (rtex
->cmask
.size
)
1014 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1015 "slice_tile_max=%u\n",
1016 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1017 rtex
->cmask
.slice_tile_max
);
1019 if (rtex
->htile_buffer
)
1020 fprintf(f
, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
1021 rtex
->htile_buffer
->b
.b
.width0
,
1022 rtex
->htile_buffer
->buf
->alignment
,
1023 rtex
->tc_compatible_htile
);
1025 if (rtex
->dcc_offset
) {
1026 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1027 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1028 rtex
->surface
.dcc_alignment
);
1029 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1030 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1031 "fast_clear_size=%"PRIu64
"\n",
1032 i
, i
< rtex
->surface
.num_dcc_levels
,
1033 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1034 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1037 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1038 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1039 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1040 "mode=%u, tiling_index = %u\n",
1041 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1042 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1043 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1044 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1045 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1046 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1047 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1048 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1049 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1051 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1052 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1053 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1054 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1055 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1056 "slice_size=%"PRIu64
", npix_x=%u, "
1057 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1058 "mode=%u, tiling_index = %u\n",
1059 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1060 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1061 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1062 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1063 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1064 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1065 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1066 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1067 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1072 /* Common processing for r600_texture_create and r600_texture_from_handle */
1073 static struct r600_texture
*
1074 r600_texture_create_object(struct pipe_screen
*screen
,
1075 const struct pipe_resource
*base
,
1076 struct pb_buffer
*buf
,
1077 struct radeon_surf
*surface
)
1079 struct r600_texture
*rtex
;
1080 struct r600_resource
*resource
;
1081 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1083 rtex
= CALLOC_STRUCT(r600_texture
);
1087 resource
= &rtex
->resource
;
1088 resource
->b
.b
= *base
;
1089 resource
->b
.b
.next
= NULL
;
1090 resource
->b
.vtbl
= &r600_texture_vtbl
;
1091 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1092 resource
->b
.b
.screen
= screen
;
1094 /* don't include stencil-only formats which we don't support for rendering */
1095 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1097 rtex
->surface
= *surface
;
1098 rtex
->size
= rtex
->surface
.surf_size
;
1100 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1101 (rtex
->surface
.flags
&
1102 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1104 /* TC-compatible HTILE:
1105 * - VI only supports Z32_FLOAT.
1106 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1107 if (rtex
->tc_compatible_htile
) {
1108 if (rscreen
->chip_class
>= GFX9
&&
1109 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1110 rtex
->db_render_format
= base
->format
;
1112 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1114 rtex
->db_render_format
= base
->format
;
1117 /* Tiled depth textures utilize the non-displayable tile order.
1118 * This must be done after r600_setup_surface.
1119 * Applies to R600-Cayman. */
1120 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1121 /* Applies to GCN. */
1122 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1124 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1125 * between frames, so the only thing that can enable separate DCC
1126 * with DRI2 is multiple slow clears within a frame.
1128 rtex
->ps_draw_ratio
= 0;
1130 if (rtex
->is_depth
) {
1131 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1132 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1133 rscreen
->chip_class
>= EVERGREEN
) {
1134 if (rscreen
->chip_class
>= GFX9
) {
1135 rtex
->can_sample_z
= true;
1136 rtex
->can_sample_s
= true;
1138 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1139 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1142 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1143 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1144 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1145 rtex
->can_sample_z
= true;
1148 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1149 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1150 rtex
->db_compatible
= true;
1152 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1153 r600_texture_allocate_htile(rscreen
, rtex
);
1156 if (base
->nr_samples
> 1) {
1158 r600_texture_allocate_fmask(rscreen
, rtex
);
1159 r600_texture_allocate_cmask(rscreen
, rtex
);
1160 rtex
->cmask_buffer
= &rtex
->resource
;
1162 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1168 /* Shared textures must always set up DCC here.
1169 * If it's not present, it will be disabled by
1170 * apply_opaque_metadata later.
1172 if (rtex
->surface
.dcc_size
&&
1173 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1174 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1175 /* Reserve space for the DCC buffer. */
1176 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1177 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1181 /* Now create the backing buffer. */
1183 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1184 rtex
->surface
.surf_alignment
);
1186 resource
->flags
|= RADEON_FLAG_HANDLE
;
1188 if (!r600_alloc_resource(rscreen
, resource
)) {
1193 resource
->buf
= buf
;
1194 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1195 resource
->bo_size
= buf
->size
;
1196 resource
->bo_alignment
= buf
->alignment
;
1197 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1198 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1199 resource
->vram_usage
= buf
->size
;
1200 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1201 resource
->gart_usage
= buf
->size
;
1204 if (rtex
->cmask
.size
) {
1205 /* Initialize the cmask to 0xCC (= compressed state). */
1206 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1207 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1211 /* Initialize DCC only if the texture is not being imported. */
1212 if (!buf
&& rtex
->dcc_offset
) {
1213 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1215 rtex
->surface
.dcc_size
,
1219 /* Initialize the CMASK base register value. */
1220 rtex
->cmask
.base_address_reg
=
1221 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1223 if (rscreen
->debug_flags
& DBG_VM
) {
1224 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1225 rtex
->resource
.gpu_address
,
1226 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1227 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1228 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1231 if (rscreen
->debug_flags
& DBG_TEX
) {
1233 r600_print_texture_info(rscreen
, rtex
, stdout
);
1240 static enum radeon_surf_mode
1241 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1242 const struct pipe_resource
*templ
)
1244 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1245 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1247 /* MSAA resources must be 2D tiled. */
1248 if (templ
->nr_samples
> 1)
1249 return RADEON_SURF_MODE_2D
;
1251 /* Transfer resources should be linear. */
1252 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1253 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1255 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1256 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1257 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1258 (templ
->target
== PIPE_TEXTURE_2D
||
1259 templ
->target
== PIPE_TEXTURE_3D
))
1260 force_tiling
= true;
1262 /* Handle common candidates for the linear mode.
1263 * Compressed textures and DB surfaces must always be tiled.
1265 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1266 (!util_format_is_depth_or_stencil(templ
->format
) ||
1267 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1268 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1269 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1271 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1272 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1273 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1275 /* Cursors are linear on SI.
1276 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1277 if (rscreen
->chip_class
>= SI
&&
1278 (templ
->bind
& PIPE_BIND_CURSOR
))
1279 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1281 if (templ
->bind
& PIPE_BIND_LINEAR
)
1282 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1284 /* Textures with a very small height are recommended to be linear. */
1285 if (templ
->target
== PIPE_TEXTURE_1D
||
1286 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1287 /* Only very thin and long 2D textures should benefit from
1288 * linear_aligned. */
1289 (templ
->width0
> 8 && templ
->height0
<= 2))
1290 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1292 /* Textures likely to be mapped often. */
1293 if (templ
->usage
== PIPE_USAGE_STAGING
||
1294 templ
->usage
== PIPE_USAGE_STREAM
)
1295 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1298 /* Make small textures 1D tiled. */
1299 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1300 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1301 return RADEON_SURF_MODE_1D
;
1303 /* The allocator will switch to 1D if needed. */
1304 return RADEON_SURF_MODE_2D
;
1307 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1308 const struct pipe_resource
*templ
)
1310 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1311 struct radeon_surf surface
= {0};
1312 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1313 bool tc_compatible_htile
=
1314 rscreen
->chip_class
>= VI
&&
1315 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1316 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1317 !is_flushed_depth
&&
1318 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1319 util_format_is_depth_or_stencil(templ
->format
);
1323 r
= r600_init_surface(rscreen
, &surface
, templ
,
1324 r600_choose_tiling(rscreen
, templ
), 0, 0,
1325 false, false, is_flushed_depth
,
1326 tc_compatible_htile
);
1331 return (struct pipe_resource
*)
1332 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1335 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1336 const struct pipe_resource
*templ
,
1337 struct winsys_handle
*whandle
,
1340 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1341 struct pb_buffer
*buf
= NULL
;
1342 unsigned stride
= 0, offset
= 0;
1343 unsigned array_mode
;
1344 struct radeon_surf surface
;
1346 struct radeon_bo_metadata metadata
= {};
1347 struct r600_texture
*rtex
;
1349 /* Support only 2D textures without mipmaps */
1350 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1351 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1354 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1358 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1360 if (rscreen
->chip_class
>= GFX9
) {
1362 surface
.u
.legacy
.pipe_config
= metadata
.u
.legacy
.pipe_config
;
1363 surface
.u
.legacy
.bankw
= metadata
.u
.legacy
.bankw
;
1364 surface
.u
.legacy
.bankh
= metadata
.u
.legacy
.bankh
;
1365 surface
.u
.legacy
.tile_split
= metadata
.u
.legacy
.tile_split
;
1366 surface
.u
.legacy
.mtilea
= metadata
.u
.legacy
.mtilea
;
1367 surface
.u
.legacy
.num_banks
= metadata
.u
.legacy
.num_banks
;
1369 if (metadata
.u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1370 array_mode
= RADEON_SURF_MODE_2D
;
1371 else if (metadata
.u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1372 array_mode
= RADEON_SURF_MODE_1D
;
1374 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1377 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1378 offset
, true, metadata
.u
.legacy
.scanout
, false, false);
1383 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1387 rtex
->resource
.is_shared
= true;
1388 rtex
->resource
.external_usage
= usage
;
1390 if (rscreen
->apply_opaque_metadata
)
1391 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1393 return &rtex
->resource
.b
.b
;
1396 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1397 struct pipe_resource
*texture
,
1398 struct r600_texture
**staging
)
1400 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1401 struct pipe_resource resource
;
1402 struct r600_texture
**flushed_depth_texture
= staging
?
1403 staging
: &rtex
->flushed_depth_texture
;
1404 enum pipe_format pipe_format
= texture
->format
;
1407 if (rtex
->flushed_depth_texture
)
1408 return true; /* it's ready */
1410 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1411 switch (pipe_format
) {
1412 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1413 /* Save memory by not allocating the S plane. */
1414 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1416 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1417 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1418 /* Save memory bandwidth by not copying the
1419 * stencil part during flush.
1421 * This potentially increases memory bandwidth
1422 * if an application uses both Z and S texturing
1423 * simultaneously (a flushed Z24S8 texture
1424 * would be stored compactly), but how often
1425 * does that really happen?
1427 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1431 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1432 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1434 /* DB->CB copies to an 8bpp surface don't work. */
1435 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1439 memset(&resource
, 0, sizeof(resource
));
1440 resource
.target
= texture
->target
;
1441 resource
.format
= pipe_format
;
1442 resource
.width0
= texture
->width0
;
1443 resource
.height0
= texture
->height0
;
1444 resource
.depth0
= texture
->depth0
;
1445 resource
.array_size
= texture
->array_size
;
1446 resource
.last_level
= texture
->last_level
;
1447 resource
.nr_samples
= texture
->nr_samples
;
1448 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1449 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1450 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1453 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1455 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1456 if (*flushed_depth_texture
== NULL
) {
1457 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1461 (*flushed_depth_texture
)->non_disp_tiling
= false;
1466 * Initialize the pipe_resource descriptor to be of the same size as the box,
1467 * which is supposed to hold a subregion of the texture "orig" at the given
1470 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1471 struct pipe_resource
*orig
,
1472 const struct pipe_box
*box
,
1473 unsigned level
, unsigned flags
)
1475 memset(res
, 0, sizeof(*res
));
1476 res
->format
= orig
->format
;
1477 res
->width0
= box
->width
;
1478 res
->height0
= box
->height
;
1480 res
->array_size
= 1;
1481 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1484 /* We must set the correct texture target and dimensions for a 3D box. */
1485 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1486 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1487 res
->array_size
= box
->depth
;
1489 res
->target
= PIPE_TEXTURE_2D
;
1493 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1494 struct r600_texture
*rtex
,
1495 unsigned transfer_usage
,
1496 const struct pipe_box
*box
)
1498 /* r600g doesn't react to dirty_tex_descriptor_counter */
1499 return rscreen
->chip_class
>= SI
&&
1500 !rtex
->resource
.is_shared
&&
1501 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1502 rtex
->resource
.b
.b
.last_level
== 0 &&
1503 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1504 box
->x
, box
->y
, box
->z
,
1505 box
->width
, box
->height
,
1509 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1510 struct r600_texture
*rtex
)
1512 struct r600_common_screen
*rscreen
= rctx
->screen
;
1514 /* There is no point in discarding depth and tiled buffers. */
1515 assert(!rtex
->is_depth
);
1516 assert(rtex
->surface
.is_linear
);
1518 /* Reallocate the buffer in the same pipe_resource. */
1519 r600_alloc_resource(rscreen
, &rtex
->resource
);
1521 /* Initialize the CMASK base address (needed even without CMASK). */
1522 rtex
->cmask
.base_address_reg
=
1523 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1525 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1527 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1530 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1531 struct pipe_resource
*texture
,
1534 const struct pipe_box
*box
,
1535 struct pipe_transfer
**ptransfer
)
1537 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1538 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1539 struct r600_transfer
*trans
;
1540 struct r600_resource
*buf
;
1541 unsigned offset
= 0;
1543 bool use_staging_texture
= false;
1545 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1546 assert(box
->width
&& box
->height
&& box
->depth
);
1548 /* Depth textures use staging unconditionally. */
1549 if (!rtex
->is_depth
) {
1550 /* Degrade the tile mode if we get too many transfers on APUs.
1551 * On dGPUs, the staging texture is always faster.
1552 * Only count uploads that are at least 4x4 pixels large.
1554 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1556 box
->width
>= 4 && box
->height
>= 4 &&
1557 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1558 bool can_invalidate
=
1559 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1562 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1566 /* Tiled textures need to be converted into a linear texture for CPU
1567 * access. The staging texture is always linear and is placed in GART.
1569 * Reading from VRAM or GTT WC is slow, always use the staging
1570 * texture in this case.
1572 * Use the staging texture for uploads if the underlying BO
1575 if (!rtex
->surface
.is_linear
)
1576 use_staging_texture
= true;
1577 else if (usage
& PIPE_TRANSFER_READ
)
1578 use_staging_texture
=
1579 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1580 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1581 /* Write & linear only: */
1582 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1583 RADEON_USAGE_READWRITE
) ||
1584 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1585 RADEON_USAGE_READWRITE
)) {
1587 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1589 r600_texture_invalidate_storage(rctx
, rtex
);
1591 use_staging_texture
= true;
1595 trans
= CALLOC_STRUCT(r600_transfer
);
1598 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
1599 trans
->transfer
.level
= level
;
1600 trans
->transfer
.usage
= usage
;
1601 trans
->transfer
.box
= *box
;
1603 if (rtex
->is_depth
) {
1604 struct r600_texture
*staging_depth
;
1606 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1607 /* MSAA depth buffers need to be converted to single sample buffers.
1609 * Mapping MSAA depth buffers can occur if ReadPixels is called
1610 * with a multisample GLX visual.
1612 * First downsample the depth buffer to a temporary texture,
1613 * then decompress the temporary one to staging.
1615 * Only the region being mapped is transfered.
1617 struct pipe_resource resource
;
1619 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1621 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1622 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1627 if (usage
& PIPE_TRANSFER_READ
) {
1628 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1630 R600_ERR("failed to create a temporary depth texture\n");
1635 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1636 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1637 0, 0, 0, box
->depth
, 0, 0);
1638 pipe_resource_reference(&temp
, NULL
);
1642 /* XXX: only readback the rectangle which is being mapped? */
1643 /* XXX: when discard is true, no need to read back from depth texture */
1644 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1645 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1650 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1652 box
->z
, box
->z
+ box
->depth
- 1,
1655 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1658 trans
->transfer
.stride
= staging_depth
->surface
.u
.legacy
.level
[level
].nblk_x
*
1659 staging_depth
->surface
.bpe
;
1660 trans
->transfer
.layer_stride
= staging_depth
->surface
.u
.legacy
.level
[level
].slice_size
;
1661 trans
->staging
= (struct r600_resource
*)staging_depth
;
1662 buf
= trans
->staging
;
1663 } else if (use_staging_texture
) {
1664 struct pipe_resource resource
;
1665 struct r600_texture
*staging
;
1667 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1668 R600_RESOURCE_FLAG_TRANSFER
);
1669 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1670 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1672 /* Create the temporary texture. */
1673 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1675 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1679 trans
->staging
= &staging
->resource
;
1680 trans
->transfer
.stride
= staging
->surface
.u
.legacy
.level
[0].nblk_x
*
1681 staging
->surface
.bpe
;
1682 trans
->transfer
.layer_stride
= staging
->surface
.u
.legacy
.level
[0].slice_size
;
1684 if (usage
& PIPE_TRANSFER_READ
)
1685 r600_copy_to_staging_texture(ctx
, trans
);
1687 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1689 buf
= trans
->staging
;
1691 /* the resource is mapped directly */
1692 trans
->transfer
.stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
1694 trans
->transfer
.layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
1695 offset
= r600_texture_get_offset(rtex
, level
, box
);
1696 buf
= &rtex
->resource
;
1699 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1700 r600_resource_reference(&trans
->staging
, NULL
);
1705 *ptransfer
= &trans
->transfer
;
1706 return map
+ offset
;
1709 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1710 struct pipe_transfer
* transfer
)
1712 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1713 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1714 struct pipe_resource
*texture
= transfer
->resource
;
1715 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1717 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1718 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1719 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1720 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1721 &rtransfer
->staging
->b
.b
, transfer
->level
,
1724 r600_copy_from_staging_texture(ctx
, rtransfer
);
1728 if (rtransfer
->staging
) {
1729 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1730 r600_resource_reference(&rtransfer
->staging
, NULL
);
1733 /* Heuristic for {upload, draw, upload, draw, ..}:
1735 * Flush the gfx IB if we've allocated too much texture storage.
1737 * The idea is that we don't want to build IBs that use too much
1738 * memory and put pressure on the kernel memory manager and we also
1739 * want to make temporary and invalidated buffers go idle ASAP to
1740 * decrease the total memory usage or make them reusable. The memory
1741 * usage will be slightly higher than given here because of the buffer
1742 * cache in the winsys.
1744 * The result is that the kernel memory manager is never a bottleneck.
1746 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1747 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1748 rctx
->num_alloc_tex_transfer_bytes
= 0;
1751 pipe_resource_reference(&transfer
->resource
, NULL
);
1755 static const struct u_resource_vtbl r600_texture_vtbl
=
1757 NULL
, /* get_handle */
1758 r600_texture_destroy
, /* resource_destroy */
1759 r600_texture_transfer_map
, /* transfer_map */
1760 u_default_transfer_flush_region
, /* transfer_flush_region */
1761 r600_texture_transfer_unmap
, /* transfer_unmap */
1764 /* DCC channel type categories within which formats can be reinterpreted
1765 * while keeping the same DCC encoding. The swizzle must also match. */
1766 enum dcc_channel_type
{
1767 dcc_channel_float32
,
1770 dcc_channel_float16
,
1773 dcc_channel_uint_10_10_10_2
,
1776 dcc_channel_incompatible
,
1779 /* Return the type of DCC encoding. */
1780 static enum dcc_channel_type
1781 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1785 /* Find the first non-void channel. */
1786 for (i
= 0; i
< desc
->nr_channels
; i
++)
1787 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1789 if (i
== desc
->nr_channels
)
1790 return dcc_channel_incompatible
;
1792 switch (desc
->channel
[i
].size
) {
1794 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1795 return dcc_channel_float32
;
1796 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1797 return dcc_channel_uint32
;
1798 return dcc_channel_sint32
;
1800 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1801 return dcc_channel_float16
;
1802 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1803 return dcc_channel_uint16
;
1804 return dcc_channel_sint16
;
1806 return dcc_channel_uint_10_10_10_2
;
1808 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1809 return dcc_channel_uint8
;
1810 return dcc_channel_sint8
;
1812 return dcc_channel_incompatible
;
1816 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1817 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1818 enum pipe_format format2
)
1820 const struct util_format_description
*desc1
, *desc2
;
1821 enum dcc_channel_type type1
, type2
;
1824 if (format1
== format2
)
1827 desc1
= util_format_description(format1
);
1828 desc2
= util_format_description(format2
);
1830 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1833 /* Swizzles must be the same. */
1834 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1835 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1836 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1837 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1840 type1
= vi_get_dcc_channel_type(desc1
);
1841 type2
= vi_get_dcc_channel_type(desc2
);
1843 return type1
!= dcc_channel_incompatible
&&
1844 type2
!= dcc_channel_incompatible
&&
1848 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1849 struct pipe_resource
*tex
,
1851 enum pipe_format view_format
)
1853 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1855 if (rtex
->dcc_offset
&&
1856 level
< rtex
->surface
.num_dcc_levels
&&
1857 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1858 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1859 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1862 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1863 struct pipe_resource
*texture
,
1864 const struct pipe_surface
*templ
,
1865 unsigned width0
, unsigned height0
,
1866 unsigned width
, unsigned height
)
1868 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1869 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1874 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1875 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1877 pipe_reference_init(&surface
->base
.reference
, 1);
1878 pipe_resource_reference(&surface
->base
.texture
, texture
);
1879 surface
->base
.context
= pipe
;
1880 surface
->base
.format
= templ
->format
;
1881 surface
->base
.width
= width
;
1882 surface
->base
.height
= height
;
1883 surface
->base
.u
= templ
->u
;
1885 surface
->width0
= width0
;
1886 surface
->height0
= height0
;
1888 if (texture
->target
!= PIPE_BUFFER
)
1889 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1893 return &surface
->base
;
1896 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1897 struct pipe_resource
*tex
,
1898 const struct pipe_surface
*templ
)
1900 unsigned level
= templ
->u
.tex
.level
;
1901 unsigned width
= u_minify(tex
->width0
, level
);
1902 unsigned height
= u_minify(tex
->height0
, level
);
1904 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1905 const struct util_format_description
*tex_desc
1906 = util_format_description(tex
->format
);
1907 const struct util_format_description
*templ_desc
1908 = util_format_description(templ
->format
);
1910 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1912 /* Adjust size of surface if and only if the block width or
1913 * height is changed. */
1914 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1915 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1916 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1917 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1919 width
= nblks_x
* templ_desc
->block
.width
;
1920 height
= nblks_y
* templ_desc
->block
.height
;
1924 return r600_create_surface_custom(pipe
, tex
, templ
,
1925 tex
->width0
, tex
->height0
,
1929 static void r600_surface_destroy(struct pipe_context
*pipe
,
1930 struct pipe_surface
*surface
)
1932 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1933 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1934 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1935 pipe_resource_reference(&surface
->texture
, NULL
);
1939 static void r600_clear_texture(struct pipe_context
*pipe
,
1940 struct pipe_resource
*tex
,
1942 const struct pipe_box
*box
,
1945 struct pipe_screen
*screen
= pipe
->screen
;
1946 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1947 struct pipe_surface tmpl
= {{0}};
1948 struct pipe_surface
*sf
;
1949 const struct util_format_description
*desc
=
1950 util_format_description(tex
->format
);
1952 tmpl
.format
= tex
->format
;
1953 tmpl
.u
.tex
.first_layer
= box
->z
;
1954 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1955 tmpl
.u
.tex
.level
= level
;
1956 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1960 if (rtex
->is_depth
) {
1963 uint8_t stencil
= 0;
1965 /* Depth is always present. */
1966 clear
= PIPE_CLEAR_DEPTH
;
1967 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1969 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1970 clear
|= PIPE_CLEAR_STENCIL
;
1971 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1974 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1976 box
->width
, box
->height
, false);
1978 union pipe_color_union color
;
1980 /* pipe_color_union requires the full vec4 representation. */
1981 if (util_format_is_pure_uint(tex
->format
))
1982 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1983 else if (util_format_is_pure_sint(tex
->format
))
1984 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1986 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1988 if (screen
->is_format_supported(screen
, tex
->format
,
1990 PIPE_BIND_RENDER_TARGET
)) {
1991 pipe
->clear_render_target(pipe
, sf
, &color
,
1993 box
->width
, box
->height
, false);
1995 /* Software fallback - just for R9G9B9E5_FLOAT */
1996 util_clear_render_target(pipe
, sf
, &color
,
1998 box
->width
, box
->height
);
2001 pipe_surface_reference(&sf
, NULL
);
2004 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2006 const struct util_format_description
*desc
= util_format_description(format
);
2008 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2010 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2011 return V_0280A0_SWAP_STD
;
2013 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2016 switch (desc
->nr_channels
) {
2018 if (HAS_SWIZZLE(0,X
))
2019 return V_0280A0_SWAP_STD
; /* X___ */
2020 else if (HAS_SWIZZLE(3,X
))
2021 return V_0280A0_SWAP_ALT_REV
; /* ___X */
2024 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2025 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2026 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2027 return V_0280A0_SWAP_STD
; /* XY__ */
2028 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2029 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2030 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2032 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
2033 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2034 return V_0280A0_SWAP_ALT
; /* X__Y */
2035 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2036 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2039 if (HAS_SWIZZLE(0,X
))
2040 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2041 else if (HAS_SWIZZLE(0,Z
))
2042 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2045 /* check the middle channels, the 1st and 4th channel can be NONE */
2046 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2047 return V_0280A0_SWAP_STD
; /* XYZW */
2048 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2049 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2050 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2051 return V_0280A0_SWAP_ALT
; /* ZYXW */
2052 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2055 return V_0280A0_SWAP_ALT_REV
;
2057 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2064 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2066 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2071 if (rctx
->dcc_stats
[slot
].query_active
)
2072 vi_separate_dcc_stop_query(&rctx
->b
,
2073 rctx
->dcc_stats
[slot
].tex
);
2075 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2076 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2077 rctx
->b
.destroy_query(&rctx
->b
,
2078 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2079 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2082 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2086 * Return the per-context slot where DCC statistics queries for the texture live.
2088 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2089 struct r600_texture
*tex
)
2091 int i
, empty_slot
= -1;
2093 /* Remove zombie textures (textures kept alive by this array only). */
2094 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2095 if (rctx
->dcc_stats
[i
].tex
&&
2096 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2097 vi_dcc_clean_up_context_slot(rctx
, i
);
2099 /* Find the texture. */
2100 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2101 /* Return if found. */
2102 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2103 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2107 /* Record the first seen empty slot. */
2108 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2112 /* Not found. Remove the oldest member to make space in the array. */
2113 if (empty_slot
== -1) {
2114 int oldest_slot
= 0;
2116 /* Find the oldest slot. */
2117 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2118 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2119 rctx
->dcc_stats
[i
].last_use_timestamp
)
2122 /* Clean up the oldest slot. */
2123 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2124 empty_slot
= oldest_slot
;
2127 /* Add the texture to the new slot. */
2128 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2129 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2133 static struct pipe_query
*
2134 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2136 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2137 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2139 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2140 return (struct pipe_query
*)query
;
2144 * Called when binding a color buffer.
2146 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2147 struct r600_texture
*tex
)
2149 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2150 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2152 assert(!rctx
->dcc_stats
[i
].query_active
);
2154 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2155 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2157 /* begin or resume the query */
2158 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2159 rctx
->dcc_stats
[i
].query_active
= true;
2163 * Called when unbinding a color buffer.
2165 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2166 struct r600_texture
*tex
)
2168 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2169 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2171 assert(rctx
->dcc_stats
[i
].query_active
);
2172 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2174 /* pause or end the query */
2175 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2176 rctx
->dcc_stats
[i
].query_active
= false;
2179 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2181 /* The minimum number of fullscreen draws per frame that is required
2183 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2186 /* Called by fast clear. */
2187 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2188 struct r600_texture
*tex
)
2190 /* The intent is to use this with shared displayable back buffers,
2191 * but it's not strictly limited only to them.
2193 if (!tex
->resource
.is_shared
||
2194 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2195 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2196 tex
->resource
.b
.b
.last_level
> 0 ||
2197 !tex
->surface
.dcc_size
)
2200 if (tex
->dcc_offset
)
2201 return; /* already enabled */
2203 /* Enable the DCC stat gathering. */
2204 if (!tex
->dcc_gather_statistics
) {
2205 tex
->dcc_gather_statistics
= true;
2206 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2209 if (!vi_should_enable_separate_dcc(tex
))
2210 return; /* stats show that DCC decompression is too expensive */
2212 assert(tex
->surface
.num_dcc_levels
);
2213 assert(!tex
->dcc_separate_buffer
);
2215 r600_texture_discard_cmask(rctx
->screen
, tex
);
2217 /* Get a DCC buffer. */
2218 if (tex
->last_dcc_separate_buffer
) {
2219 assert(tex
->dcc_gather_statistics
);
2220 assert(!tex
->dcc_separate_buffer
);
2221 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2222 tex
->last_dcc_separate_buffer
= NULL
;
2224 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2225 r600_aligned_buffer_create(rctx
->b
.screen
,
2226 R600_RESOURCE_FLAG_UNMAPPABLE
,
2228 tex
->surface
.dcc_size
,
2229 tex
->surface
.dcc_alignment
);
2230 if (!tex
->dcc_separate_buffer
)
2234 /* dcc_offset is the absolute GPUVM address. */
2235 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2237 /* no need to flag anything since this is called by fast clear that
2238 * flags framebuffer state
2243 * Called by pipe_context::flush_resource, the place where DCC decompression
2246 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2247 struct r600_texture
*tex
)
2249 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2250 struct pipe_query
*tmp
;
2251 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2252 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2253 bool disable
= false;
2255 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2256 union pipe_query_result result
;
2258 /* Read the results. */
2259 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2261 r600_query_hw_reset_buffers(rctx
,
2262 (struct r600_query_hw
*)
2263 rctx
->dcc_stats
[i
].ps_stats
[2]);
2265 /* Compute the approximate number of fullscreen draws. */
2266 tex
->ps_draw_ratio
=
2267 result
.pipeline_statistics
.ps_invocations
/
2268 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2269 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2271 disable
= tex
->dcc_separate_buffer
&&
2272 !vi_should_enable_separate_dcc(tex
);
2275 tex
->num_slow_clears
= 0;
2277 /* stop the statistics query for ps_stats[0] */
2279 vi_separate_dcc_stop_query(ctx
, tex
);
2281 /* Move the queries in the queue by one. */
2282 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2283 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2284 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2285 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2287 /* create and start a new query as ps_stats[0] */
2289 vi_separate_dcc_start_query(ctx
, tex
);
2292 assert(!tex
->last_dcc_separate_buffer
);
2293 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2294 tex
->dcc_separate_buffer
= NULL
;
2295 tex
->dcc_offset
= 0;
2296 /* no need to flag anything since this is called after
2297 * decompression that re-sets framebuffer state
2302 /* FAST COLOR CLEAR */
2304 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2305 enum pipe_format surface_format
,
2306 const union pipe_color_union
*color
)
2308 union util_color uc
;
2310 memset(&uc
, 0, sizeof(uc
));
2312 if (rtex
->surface
.bpe
== 16) {
2313 /* DCC fast clear only:
2314 * CLEAR_WORD0 = R = G = B
2317 assert(color
->ui
[0] == color
->ui
[1] &&
2318 color
->ui
[0] == color
->ui
[2]);
2319 uc
.ui
[0] = color
->ui
[0];
2320 uc
.ui
[1] = color
->ui
[3];
2321 } else if (util_format_is_pure_uint(surface_format
)) {
2322 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2323 } else if (util_format_is_pure_sint(surface_format
)) {
2324 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2326 util_pack_color(color
->f
, surface_format
, &uc
);
2329 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2332 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2333 const union pipe_color_union
*color
,
2334 uint32_t* reset_value
,
2335 bool* clear_words_needed
)
2337 bool values
[4] = {};
2339 bool main_value
= false;
2340 bool extra_value
= false;
2342 const struct util_format_description
*desc
= util_format_description(surface_format
);
2344 if (desc
->block
.bits
== 128 &&
2345 (color
->ui
[0] != color
->ui
[1] ||
2346 color
->ui
[0] != color
->ui
[2]))
2349 *clear_words_needed
= true;
2350 *reset_value
= 0x20202020U
;
2352 /* If we want to clear without needing a fast clear eliminate step, we
2353 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2354 * have two sets of flags, one for the last or first channel(extra) and
2355 * one for the other channels(main).
2358 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2359 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2360 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2362 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2363 if(r600_translate_colorswap(surface_format
, false) <= 1)
2364 extra_channel
= desc
->nr_channels
- 1;
2370 for (i
= 0; i
< 4; ++i
) {
2371 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2373 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2374 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2377 if (desc
->channel
[i
].pure_integer
&&
2378 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2379 /* Use the maximum value for clamping the clear color. */
2380 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2382 values
[i
] = color
->i
[i
] != 0;
2383 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2385 } else if (desc
->channel
[i
].pure_integer
&&
2386 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2387 /* Use the maximum value for clamping the clear color. */
2388 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2390 values
[i
] = color
->ui
[i
] != 0U;
2391 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2394 values
[i
] = color
->f
[i
] != 0.0F
;
2395 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2399 if (index
== extra_channel
)
2400 extra_value
= values
[i
];
2402 main_value
= values
[i
];
2405 for (int i
= 0; i
< 4; ++i
)
2406 if (values
[i
] != main_value
&&
2407 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2408 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2409 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2412 *clear_words_needed
= false;
2414 *reset_value
|= 0x80808080U
;
2417 *reset_value
|= 0x40404040U
;
2421 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2422 struct r600_texture
*rtex
,
2423 unsigned level
, unsigned clear_value
)
2425 struct pipe_resource
*dcc_buffer
;
2426 uint64_t dcc_offset
, clear_size
;
2428 assert(rtex
->dcc_offset
&& level
< rtex
->surface
.num_dcc_levels
);
2430 if (rtex
->dcc_separate_buffer
) {
2431 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2434 dcc_buffer
= &rtex
->resource
.b
.b
;
2435 dcc_offset
= rtex
->dcc_offset
;
2438 if (rctx
->chip_class
>= GFX9
) {
2439 /* Mipmap level clears aren't implemented. */
2440 assert(rtex
->resource
.b
.b
.last_level
== 0);
2441 /* MSAA needs a different clear size. */
2442 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2443 clear_size
= rtex
->surface
.dcc_size
;
2445 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2446 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2449 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2450 clear_value
, R600_COHERENCY_CB_META
);
2453 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2454 * This allows hitting the MSAA resolve fast path, which requires that both
2455 * src and dst micro tile modes match.
2457 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2458 struct r600_texture
*rtex
)
2460 if (rtex
->resource
.is_shared
||
2461 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2462 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2465 assert(rscreen
->chip_class
>= GFX9
||
2466 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2467 assert(rtex
->resource
.b
.b
.last_level
== 0);
2469 if (rscreen
->chip_class
>= GFX9
) {
2470 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2471 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2473 /* If you do swizzle_mode % 4, you'll get:
2479 * Depth-sample order isn't allowed:
2481 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2483 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2484 case RADEON_MICRO_MODE_DISPLAY
:
2485 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2486 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2488 case RADEON_MICRO_MODE_THIN
:
2489 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2490 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2492 case RADEON_MICRO_MODE_ROTATED
:
2493 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2494 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2496 default: /* depth */
2497 assert(!"unexpected micro mode");
2500 } else if (rscreen
->chip_class
>= CIK
) {
2501 /* These magic numbers were copied from addrlib. It doesn't use
2502 * any definitions for them either. They are all 2D_TILED_THIN1
2503 * modes with different bpp and micro tile mode.
2505 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2506 case RADEON_MICRO_MODE_DISPLAY
:
2507 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2509 case RADEON_MICRO_MODE_THIN
:
2510 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2512 case RADEON_MICRO_MODE_ROTATED
:
2513 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2515 default: /* depth, thick */
2516 assert(!"unexpected micro mode");
2520 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2521 case RADEON_MICRO_MODE_DISPLAY
:
2522 switch (rtex
->surface
.bpe
) {
2524 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2527 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2530 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2534 case RADEON_MICRO_MODE_THIN
:
2535 switch (rtex
->surface
.bpe
) {
2537 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2540 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2543 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2545 default: /* 8, 16 */
2546 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2550 default: /* depth, thick */
2551 assert(!"unexpected micro mode");
2556 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2558 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2561 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2562 struct pipe_framebuffer_state
*fb
,
2563 struct r600_atom
*fb_state
,
2564 unsigned *buffers
, unsigned *dirty_cbufs
,
2565 const union pipe_color_union
*color
)
2569 /* This function is broken in BE, so just disable this path for now */
2570 #ifdef PIPE_ARCH_BIG_ENDIAN
2574 if (rctx
->render_cond
)
2577 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2578 struct r600_texture
*tex
;
2579 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2584 /* if this colorbuffer is not being cleared */
2585 if (!(*buffers
& clear_bit
))
2588 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2590 /* the clear is allowed if all layers are bound */
2591 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2592 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2596 /* cannot clear mipmapped textures */
2597 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2601 /* only supported on tiled surfaces */
2602 if (tex
->surface
.is_linear
) {
2606 /* shared textures can't use fast clear without an explicit flush,
2607 * because there is no way to communicate the clear color among
2610 if (tex
->resource
.is_shared
&&
2611 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2614 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2615 if (rctx
->chip_class
== CIK
&&
2616 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2617 rctx
->screen
->info
.drm_major
== 2 &&
2618 rctx
->screen
->info
.drm_minor
< 38) {
2622 /* Fast clear is the most appropriate place to enable DCC for
2623 * displayable surfaces.
2625 if (rctx
->chip_class
>= VI
&&
2626 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2627 vi_separate_dcc_try_enable(rctx
, tex
);
2629 /* RB+ isn't supported with a CMASK-based clear, so all
2630 * clears are considered to be hypothetically slow
2631 * clears, which is weighed when determining whether to
2632 * enable separate DCC.
2634 if (tex
->dcc_gather_statistics
&&
2635 rctx
->screen
->rbplus_allowed
)
2636 tex
->num_slow_clears
++;
2639 /* Try to clear DCC first, otherwise try CMASK. */
2640 if (tex
->dcc_offset
&& tex
->surface
.num_dcc_levels
) {
2641 uint32_t reset_value
;
2642 bool clear_words_needed
;
2644 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2647 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2648 color
, &reset_value
,
2649 &clear_words_needed
))
2652 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2654 if (clear_words_needed
)
2655 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2656 tex
->separate_dcc_dirty
= true;
2658 /* 128-bit formats are unusupported */
2659 if (tex
->surface
.bpe
> 8) {
2663 /* RB+ doesn't work with CMASK fast clear. */
2664 if (rctx
->screen
->rbplus_allowed
)
2667 /* ensure CMASK is enabled */
2668 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2669 if (tex
->cmask
.size
== 0) {
2673 /* Do the fast clear. */
2674 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2675 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2676 R600_COHERENCY_CB_META
);
2678 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2681 /* We can change the micro tile mode before a full clear. */
2682 if (rctx
->screen
->chip_class
>= SI
)
2683 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2685 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2688 *dirty_cbufs
|= 1 << i
;
2689 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2690 *buffers
&= ~clear_bit
;
2694 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2696 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2697 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2700 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2702 rctx
->b
.create_surface
= r600_create_surface
;
2703 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2704 rctx
->b
.clear_texture
= r600_clear_texture
;