2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "os/os_time.h"
38 #include "state_tracker/drm_driver.h"
40 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
41 struct r600_texture
*rtex
);
42 static enum radeon_surf_mode
43 r600_choose_tiling(struct r600_common_screen
*rscreen
,
44 const struct pipe_resource
*templ
);
47 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
48 struct r600_texture
*rdst
,
49 unsigned dst_level
, unsigned dstx
,
50 unsigned dsty
, unsigned dstz
,
51 struct r600_texture
*rsrc
,
53 const struct pipe_box
*src_box
)
58 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
61 /* MSAA: Blits don't exist in the real world. */
62 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
63 rdst
->resource
.b
.b
.nr_samples
> 1)
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
70 if (rsrc
->is_depth
|| rdst
->is_depth
)
74 * src: Use the 3D path. DCC decompression is expensive.
75 * dst: Use the 3D path to compress the pixels with DCC.
77 if (vi_dcc_enabled(rsrc
, src_level
) ||
78 vi_dcc_enabled(rdst
, dst_level
))
82 * src: Both texture and SDMA paths need decompression. Use SDMA.
83 * dst: If overwriting the whole texture, discard CMASK and use
84 * SDMA. Otherwise, use the 3D path.
86 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
87 /* The CMASK clear is only enabled for the first level. */
88 assert(dst_level
== 0);
89 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
90 dstx
, dsty
, dstz
, src_box
->width
,
91 src_box
->height
, src_box
->depth
))
94 r600_texture_discard_cmask(rctx
->screen
, rdst
);
97 /* All requirements are met. Prepare textures for SDMA. */
98 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
99 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
101 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
102 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
107 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
108 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
109 struct pipe_resource
*dst
,
111 unsigned dstx
, unsigned dsty
, unsigned dstz
,
112 struct pipe_resource
*src
,
114 const struct pipe_box
*src_box
)
116 struct pipe_blit_info blit
;
118 memset(&blit
, 0, sizeof(blit
));
119 blit
.src
.resource
= src
;
120 blit
.src
.format
= src
->format
;
121 blit
.src
.level
= src_level
;
122 blit
.src
.box
= *src_box
;
123 blit
.dst
.resource
= dst
;
124 blit
.dst
.format
= dst
->format
;
125 blit
.dst
.level
= dst_level
;
126 blit
.dst
.box
.x
= dstx
;
127 blit
.dst
.box
.y
= dsty
;
128 blit
.dst
.box
.z
= dstz
;
129 blit
.dst
.box
.width
= src_box
->width
;
130 blit
.dst
.box
.height
= src_box
->height
;
131 blit
.dst
.box
.depth
= src_box
->depth
;
132 blit
.mask
= util_format_get_mask(src
->format
) &
133 util_format_get_mask(dst
->format
);
134 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
137 pipe
->blit(pipe
, &blit
);
141 /* Copy from a full GPU texture to a transfer's staging one. */
142 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
144 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
145 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
146 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
147 struct pipe_resource
*src
= transfer
->resource
;
149 if (src
->nr_samples
> 1) {
150 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
151 src
, transfer
->level
, &transfer
->box
);
155 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
159 /* Copy from a transfer's staging texture to a full GPU one. */
160 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
162 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
163 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
164 struct pipe_resource
*dst
= transfer
->resource
;
165 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
166 struct pipe_box sbox
;
168 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
170 if (dst
->nr_samples
> 1) {
171 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
172 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
177 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
178 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
182 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
183 struct r600_texture
*rtex
, unsigned level
,
184 const struct pipe_box
*box
,
186 unsigned *layer_stride
)
188 if (rscreen
->chip_class
>= GFX9
) {
189 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
190 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
195 /* Each texture is an array of slices. Each slice is an array
196 * of mipmap levels. */
197 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
198 rtex
->surface
.u
.gfx9
.offset
[level
] +
199 (box
->y
/ rtex
->surface
.blk_h
*
200 rtex
->surface
.u
.gfx9
.surf_pitch
+
201 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
203 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
205 *layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
208 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
214 (box
->y
/ rtex
->surface
.blk_h
*
215 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
220 static int r600_init_surface(struct r600_common_screen
*rscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 enum radeon_surf_mode array_mode
,
224 unsigned pitch_in_bytes_override
,
228 bool is_flushed_depth
,
229 bool tc_compatible_htile
)
231 const struct util_format_description
*desc
=
232 util_format_description(ptex
->format
);
233 bool is_depth
, is_stencil
;
235 unsigned i
, bpe
, flags
= 0;
237 is_depth
= util_format_has_depth(desc
);
238 is_stencil
= util_format_has_stencil(desc
);
240 if (!is_flushed_depth
&&
241 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
242 bpe
= 4; /* stencil is allocated separately on evergreen */
244 bpe
= util_format_get_blocksize(ptex
->format
);
245 assert(util_is_power_of_two(bpe
));
248 if (!is_flushed_depth
&& is_depth
) {
249 flags
|= RADEON_SURF_ZBUFFER
;
251 if (tc_compatible_htile
&&
252 (rscreen
->chip_class
>= GFX9
||
253 array_mode
== RADEON_SURF_MODE_2D
)) {
254 /* TC-compatible HTILE only supports Z32_FLOAT.
255 * GFX9 also supports Z16_UNORM.
256 * On VI, promote Z16 to Z32. DB->CB copies will convert
257 * the format for transfers.
259 if (rscreen
->chip_class
== VI
)
262 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
266 flags
|= RADEON_SURF_SBUFFER
;
269 if (rscreen
->chip_class
>= VI
&&
270 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
271 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
272 flags
|= RADEON_SURF_DISABLE_DCC
;
274 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
275 /* This should catch bugs in gallium users setting incorrect flags. */
276 assert(ptex
->nr_samples
<= 1 &&
277 ptex
->array_size
== 1 &&
279 ptex
->last_level
== 0 &&
280 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
282 flags
|= RADEON_SURF_SCANOUT
;
285 if (ptex
->bind
& PIPE_BIND_SHARED
)
286 flags
|= RADEON_SURF_SHAREABLE
;
288 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
289 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
290 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
292 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
293 array_mode
, surface
);
298 if (rscreen
->chip_class
>= GFX9
) {
299 assert(!pitch_in_bytes_override
||
300 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
301 surface
->u
.gfx9
.surf_offset
= offset
;
303 if (pitch_in_bytes_override
&&
304 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
305 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
308 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
309 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
*
310 surface
->u
.legacy
.level
[0].nblk_y
;
314 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
315 surface
->u
.legacy
.level
[i
].offset
+= offset
;
321 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
322 struct r600_texture
*rtex
,
323 struct radeon_bo_metadata
*metadata
)
325 struct radeon_surf
*surface
= &rtex
->surface
;
327 memset(metadata
, 0, sizeof(*metadata
));
329 if (rscreen
->chip_class
>= GFX9
) {
330 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
332 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
333 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
334 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
335 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
336 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
337 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
338 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
339 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
340 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
341 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
342 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
343 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
347 static void r600_surface_import_metadata(struct r600_common_screen
*rscreen
,
348 struct radeon_surf
*surf
,
349 struct radeon_bo_metadata
*metadata
,
350 enum radeon_surf_mode
*array_mode
,
353 if (rscreen
->chip_class
>= GFX9
) {
354 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
355 *array_mode
= RADEON_SURF_MODE_2D
;
357 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
359 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
360 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
362 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
364 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
365 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
366 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
367 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
368 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
369 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
371 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
372 *array_mode
= RADEON_SURF_MODE_2D
;
373 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
374 *array_mode
= RADEON_SURF_MODE_1D
;
376 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
378 *is_scanout
= metadata
->u
.legacy
.scanout
;
382 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
383 struct r600_texture
*rtex
)
385 struct r600_common_screen
*rscreen
= rctx
->screen
;
386 struct pipe_context
*ctx
= &rctx
->b
;
388 if (ctx
== rscreen
->aux_context
)
389 mtx_lock(&rscreen
->aux_context_lock
);
391 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
392 ctx
->flush(ctx
, NULL
, 0);
394 if (ctx
== rscreen
->aux_context
)
395 mtx_unlock(&rscreen
->aux_context_lock
);
398 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
399 struct r600_texture
*rtex
)
401 if (!rtex
->cmask
.size
)
404 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
407 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
408 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
409 rtex
->dirty_level_mask
= 0;
411 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
413 if (rtex
->cmask_buffer
!= &rtex
->resource
)
414 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
416 /* Notify all contexts about the change. */
417 p_atomic_inc(&rscreen
->dirty_tex_counter
);
418 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
421 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
423 /* We can't disable DCC if it can be written by another process. */
424 return rtex
->dcc_offset
&&
425 (!rtex
->resource
.b
.is_shared
||
426 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
429 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
430 struct r600_texture
*rtex
)
432 if (!r600_can_disable_dcc(rtex
))
435 assert(rtex
->dcc_separate_buffer
== NULL
);
438 rtex
->dcc_offset
= 0;
440 /* Notify all contexts about the change. */
441 p_atomic_inc(&rscreen
->dirty_tex_counter
);
446 * Disable DCC for the texture. (first decompress, then discard metadata).
448 * There is unresolved multi-context synchronization issue between
449 * screen::aux_context and the current context. If applications do this with
450 * multiple contexts, it's already undefined behavior for them and we don't
451 * have to worry about that. The scenario is:
453 * If context 1 disables DCC and context 2 has queued commands that write
454 * to the texture via CB with DCC enabled, and the order of operations is
456 * context 2 queues draw calls rendering to the texture, but doesn't flush
457 * context 1 disables DCC and flushes
458 * context 1 & 2 reset descriptors and FB state
459 * context 2 flushes (new compressed tiles written by the draw calls)
460 * context 1 & 2 read garbage, because DCC is disabled, yet there are
463 * \param rctx the current context if you have one, or rscreen->aux_context
466 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
467 struct r600_texture
*rtex
)
469 struct r600_common_screen
*rscreen
= rctx
->screen
;
471 if (!r600_can_disable_dcc(rtex
))
474 if (&rctx
->b
== rscreen
->aux_context
)
475 mtx_lock(&rscreen
->aux_context_lock
);
477 /* Decompress DCC. */
478 rctx
->decompress_dcc(&rctx
->b
, rtex
);
479 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
481 if (&rctx
->b
== rscreen
->aux_context
)
482 mtx_unlock(&rscreen
->aux_context_lock
);
484 return r600_texture_discard_dcc(rscreen
, rtex
);
487 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
488 struct r600_texture
*rtex
,
489 unsigned new_bind_flag
,
490 bool invalidate_storage
)
492 struct pipe_screen
*screen
= rctx
->b
.screen
;
493 struct r600_texture
*new_tex
;
494 struct pipe_resource templ
= rtex
->resource
.b
.b
;
497 templ
.bind
|= new_bind_flag
;
499 /* r600g doesn't react to dirty_tex_descriptor_counter */
500 if (rctx
->chip_class
< SI
)
503 if (rtex
->resource
.b
.is_shared
)
506 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
507 if (rtex
->surface
.is_linear
)
510 /* This fails with MSAA, depth, and compressed textures. */
511 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
512 RADEON_SURF_MODE_LINEAR_ALIGNED
)
516 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
520 /* Copy the pixels to the new texture. */
521 if (!invalidate_storage
) {
522 for (i
= 0; i
<= templ
.last_level
; i
++) {
526 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
527 util_max_layer(&templ
, i
) + 1, &box
);
529 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
530 &rtex
->resource
.b
.b
, i
, &box
);
534 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
535 r600_texture_discard_cmask(rctx
->screen
, rtex
);
536 r600_texture_discard_dcc(rctx
->screen
, rtex
);
539 /* Replace the structure fields of rtex. */
540 rtex
->resource
.b
.b
.bind
= templ
.bind
;
541 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
542 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
543 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
544 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
545 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
546 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
547 rtex
->resource
.domains
= new_tex
->resource
.domains
;
548 rtex
->resource
.flags
= new_tex
->resource
.flags
;
549 rtex
->size
= new_tex
->size
;
550 rtex
->db_render_format
= new_tex
->db_render_format
;
551 rtex
->db_compatible
= new_tex
->db_compatible
;
552 rtex
->can_sample_z
= new_tex
->can_sample_z
;
553 rtex
->can_sample_s
= new_tex
->can_sample_s
;
554 rtex
->surface
= new_tex
->surface
;
555 rtex
->fmask
= new_tex
->fmask
;
556 rtex
->cmask
= new_tex
->cmask
;
557 rtex
->cb_color_info
= new_tex
->cb_color_info
;
558 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
559 rtex
->htile_offset
= new_tex
->htile_offset
;
560 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
561 rtex
->depth_cleared
= new_tex
->depth_cleared
;
562 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
563 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
564 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
565 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
567 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
568 assert(!rtex
->htile_offset
);
569 assert(!rtex
->cmask
.size
);
570 assert(!rtex
->fmask
.size
);
571 assert(!rtex
->dcc_offset
);
572 assert(!rtex
->is_depth
);
575 r600_texture_reference(&new_tex
, NULL
);
577 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
580 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
581 struct pipe_context
*ctx
,
582 struct pipe_resource
*resource
,
583 struct winsys_handle
*whandle
,
586 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
587 struct r600_common_context
*rctx
;
588 struct r600_resource
*res
= (struct r600_resource
*)resource
;
589 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
590 struct radeon_bo_metadata metadata
;
591 bool update_metadata
= false;
592 unsigned stride
, offset
, slice_size
;
594 ctx
= threaded_context_unwrap_sync(ctx
);
595 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
597 if (resource
->target
!= PIPE_BUFFER
) {
598 /* This is not supported now, but it might be required for OpenCL
599 * interop in the future.
601 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
604 /* Move a suballocated texture into a non-suballocated allocation. */
605 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
606 rtex
->surface
.tile_swizzle
||
607 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
608 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
609 assert(!res
->b
.is_shared
);
610 r600_reallocate_texture_inplace(rctx
, rtex
,
611 PIPE_BIND_SHARED
, false);
612 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
613 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
614 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
615 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
616 assert(rtex
->surface
.tile_swizzle
== 0);
619 /* Since shader image stores don't support DCC on VI,
620 * disable it for external clients that want write
623 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
624 if (si_texture_disable_dcc(rctx
, rtex
))
625 update_metadata
= true;
628 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
629 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
630 /* Eliminate fast clear (both CMASK and DCC) */
631 r600_eliminate_fast_color_clear(rctx
, rtex
);
633 /* Disable CMASK if flush_resource isn't going
636 if (rtex
->cmask
.size
)
637 r600_texture_discard_cmask(rscreen
, rtex
);
641 if (!res
->b
.is_shared
|| update_metadata
) {
642 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
643 if (rscreen
->query_opaque_metadata
)
644 rscreen
->query_opaque_metadata(rscreen
, rtex
,
647 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
650 if (rscreen
->chip_class
>= GFX9
) {
651 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
652 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
654 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
656 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
657 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
659 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
662 /* Move a suballocated buffer into a non-suballocated allocation. */
663 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
664 assert(!res
->b
.is_shared
);
666 /* Allocate a new buffer with PIPE_BIND_SHARED. */
667 struct pipe_resource templ
= res
->b
.b
;
668 templ
.bind
|= PIPE_BIND_SHARED
;
670 struct pipe_resource
*newb
=
671 screen
->resource_create(screen
, &templ
);
675 /* Copy the old buffer contents to the new one. */
677 u_box_1d(0, newb
->width0
, &box
);
678 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
680 /* Move the new buffer storage to the old pipe_resource. */
681 si_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
682 pipe_resource_reference(&newb
, NULL
);
684 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
685 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
694 if (res
->b
.is_shared
) {
695 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
698 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
699 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
700 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
702 res
->b
.is_shared
= true;
703 res
->external_usage
= usage
;
706 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
707 slice_size
, whandle
);
710 static void r600_texture_destroy(struct pipe_screen
*screen
,
711 struct pipe_resource
*ptex
)
713 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
714 struct r600_resource
*resource
= &rtex
->resource
;
716 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
718 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
719 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
721 pb_reference(&resource
->buf
, NULL
);
722 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
723 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
727 static const struct u_resource_vtbl r600_texture_vtbl
;
729 /* The number of samples can be specified independently of the texture. */
730 void si_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
731 struct r600_texture
*rtex
,
733 struct r600_fmask_info
*out
)
735 /* FMASK is allocated like an ordinary texture. */
736 struct pipe_resource templ
= rtex
->resource
.b
.b
;
737 struct radeon_surf fmask
= {};
740 memset(out
, 0, sizeof(*out
));
742 if (rscreen
->chip_class
>= GFX9
) {
743 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
744 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
748 templ
.nr_samples
= 1;
749 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
751 switch (nr_samples
) {
760 R600_ERR("Invalid sample count for FMASK allocation.\n");
764 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
765 RADEON_SURF_MODE_2D
, &fmask
)) {
766 R600_ERR("Got error in surface_init while allocating FMASK.\n");
770 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
772 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
773 if (out
->slice_tile_max
)
774 out
->slice_tile_max
-= 1;
776 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
777 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
778 out
->bank_height
= fmask
.u
.legacy
.bankh
;
779 out
->tile_swizzle
= fmask
.tile_swizzle
;
780 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
781 out
->size
= fmask
.surf_size
;
784 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
785 struct r600_texture
*rtex
)
787 si_texture_get_fmask_info(rscreen
, rtex
,
788 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
790 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
791 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
794 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
795 struct r600_texture
*rtex
,
796 struct r600_cmask_info
*out
)
798 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
799 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
800 unsigned cl_width
, cl_height
;
802 if (rscreen
->chip_class
>= GFX9
) {
803 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
804 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
821 case 16: /* Hawaii */
830 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
832 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
833 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
834 unsigned slice_elements
= (width
* height
) / (8*8);
836 /* Each element of CMASK is a nibble. */
837 unsigned slice_bytes
= slice_elements
/ 2;
839 out
->slice_tile_max
= (width
* height
) / (128*128);
840 if (out
->slice_tile_max
)
841 out
->slice_tile_max
-= 1;
843 out
->alignment
= MAX2(256, base_align
);
844 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
845 align(slice_bytes
, base_align
);
848 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
849 struct r600_texture
*rtex
)
851 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
853 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
854 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
856 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
859 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
860 struct r600_texture
*rtex
)
862 if (rtex
->cmask_buffer
)
865 assert(rtex
->cmask
.size
== 0);
867 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
869 rtex
->cmask_buffer
= (struct r600_resource
*)
870 si_aligned_buffer_create(&rscreen
->b
,
871 R600_RESOURCE_FLAG_UNMAPPABLE
,
874 rtex
->cmask
.alignment
);
875 if (rtex
->cmask_buffer
== NULL
) {
876 rtex
->cmask
.size
= 0;
880 /* update colorbuffer state bits */
881 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
883 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
885 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
888 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
889 struct r600_texture
*rtex
)
891 unsigned cl_width
, cl_height
, width
, height
;
892 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
893 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
895 assert(rscreen
->chip_class
<= VI
);
897 rtex
->surface
.htile_size
= 0;
899 /* HTILE is broken with 1D tiling on old kernels and CIK. */
900 if (rscreen
->chip_class
>= CIK
&&
901 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
902 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
905 /* Overalign HTILE on P2 configs to work around GPU hangs in
906 * piglit/depthstencil-render-miplevels 585.
908 * This has been confirmed to help Kabini & Stoney, where the hangs
909 * are always reproducible. I think I have seen the test hang
910 * on Carrizo too, though it was very rare there.
912 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
941 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
942 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
944 slice_elements
= (width
* height
) / (8 * 8);
945 slice_bytes
= slice_elements
* 4;
947 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
948 base_align
= num_pipes
* pipe_interleave_bytes
;
950 rtex
->surface
.htile_alignment
= base_align
;
951 rtex
->surface
.htile_size
=
952 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
953 align(slice_bytes
, base_align
);
956 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
957 struct r600_texture
*rtex
)
959 if (rscreen
->chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
960 r600_texture_get_htile_size(rscreen
, rtex
);
962 if (!rtex
->surface
.htile_size
)
965 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
966 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
969 void si_print_texture_info(struct r600_common_screen
*rscreen
,
970 struct r600_texture
*rtex
, struct u_log_context
*log
)
974 /* Common parameters. */
975 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
976 "blk_h=%u, array_size=%u, last_level=%u, "
977 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
978 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
979 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
981 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
982 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
983 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
985 if (rscreen
->chip_class
>= GFX9
) {
986 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
987 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
988 rtex
->surface
.surf_size
,
989 rtex
->surface
.u
.gfx9
.surf_slice_size
,
990 rtex
->surface
.surf_alignment
,
991 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
992 rtex
->surface
.u
.gfx9
.surf
.epitch
,
993 rtex
->surface
.u
.gfx9
.surf_pitch
);
995 if (rtex
->fmask
.size
) {
996 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
997 "alignment=%u, swmode=%u, epitch=%u\n",
999 rtex
->surface
.u
.gfx9
.fmask_size
,
1000 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1001 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1002 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1005 if (rtex
->cmask
.size
) {
1006 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1007 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1009 rtex
->surface
.u
.gfx9
.cmask_size
,
1010 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1011 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1012 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1015 if (rtex
->htile_offset
) {
1016 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1017 "rb_aligned=%u, pipe_aligned=%u\n",
1019 rtex
->surface
.htile_size
,
1020 rtex
->surface
.htile_alignment
,
1021 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1022 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1025 if (rtex
->dcc_offset
) {
1026 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
1027 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1028 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1029 rtex
->surface
.dcc_alignment
,
1030 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1031 rtex
->surface
.num_dcc_levels
);
1034 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1035 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1036 rtex
->surface
.u
.gfx9
.stencil_offset
,
1037 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1038 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1043 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1044 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1045 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1046 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1047 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1048 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1050 if (rtex
->fmask
.size
)
1051 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1052 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1053 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1054 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1055 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1057 if (rtex
->cmask
.size
)
1058 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1059 "slice_tile_max=%u\n",
1060 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1061 rtex
->cmask
.slice_tile_max
);
1063 if (rtex
->htile_offset
)
1064 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", "
1065 "alignment=%u, TC_compatible = %u\n",
1066 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1067 rtex
->surface
.htile_alignment
,
1068 rtex
->tc_compatible_htile
);
1070 if (rtex
->dcc_offset
) {
1071 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1072 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1073 rtex
->surface
.dcc_alignment
);
1074 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1075 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1076 "fast_clear_size=%"PRIu64
"\n",
1077 i
, i
< rtex
->surface
.num_dcc_levels
,
1078 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1079 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1082 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1083 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1084 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1085 "mode=%u, tiling_index = %u\n",
1086 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1087 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1088 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1089 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1090 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1091 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1092 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1093 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1094 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1096 if (rtex
->surface
.has_stencil
) {
1097 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1098 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1099 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1100 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1101 "slice_size=%"PRIu64
", npix_x=%u, "
1102 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1103 "mode=%u, tiling_index = %u\n",
1104 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1105 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1106 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1107 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1108 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1109 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1110 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1111 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1112 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1117 /* Common processing for r600_texture_create and r600_texture_from_handle */
1118 static struct r600_texture
*
1119 r600_texture_create_object(struct pipe_screen
*screen
,
1120 const struct pipe_resource
*base
,
1121 struct pb_buffer
*buf
,
1122 struct radeon_surf
*surface
)
1124 struct r600_texture
*rtex
;
1125 struct r600_resource
*resource
;
1126 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1128 rtex
= CALLOC_STRUCT(r600_texture
);
1132 resource
= &rtex
->resource
;
1133 resource
->b
.b
= *base
;
1134 resource
->b
.b
.next
= NULL
;
1135 resource
->b
.vtbl
= &r600_texture_vtbl
;
1136 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1137 resource
->b
.b
.screen
= screen
;
1139 /* don't include stencil-only formats which we don't support for rendering */
1140 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1142 rtex
->surface
= *surface
;
1143 rtex
->size
= rtex
->surface
.surf_size
;
1145 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1146 (rtex
->surface
.flags
&
1147 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1149 /* TC-compatible HTILE:
1150 * - VI only supports Z32_FLOAT.
1151 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1152 if (rtex
->tc_compatible_htile
) {
1153 if (rscreen
->chip_class
>= GFX9
&&
1154 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1155 rtex
->db_render_format
= base
->format
;
1157 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1158 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1159 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1162 rtex
->db_render_format
= base
->format
;
1165 /* Tiled depth textures utilize the non-displayable tile order.
1166 * This must be done after r600_setup_surface.
1167 * Applies to R600-Cayman. */
1168 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1169 /* Applies to GCN. */
1170 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1172 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1173 * between frames, so the only thing that can enable separate DCC
1174 * with DRI2 is multiple slow clears within a frame.
1176 rtex
->ps_draw_ratio
= 0;
1178 if (rtex
->is_depth
) {
1179 if (rscreen
->chip_class
>= GFX9
) {
1180 rtex
->can_sample_z
= true;
1181 rtex
->can_sample_s
= true;
1183 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1184 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1187 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1188 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1189 rtex
->db_compatible
= true;
1191 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1192 r600_texture_allocate_htile(rscreen
, rtex
);
1195 if (base
->nr_samples
> 1) {
1197 r600_texture_allocate_fmask(rscreen
, rtex
);
1198 r600_texture_allocate_cmask(rscreen
, rtex
);
1199 rtex
->cmask_buffer
= &rtex
->resource
;
1201 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1207 /* Shared textures must always set up DCC here.
1208 * If it's not present, it will be disabled by
1209 * apply_opaque_metadata later.
1211 if (rtex
->surface
.dcc_size
&&
1212 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1213 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1214 /* Reserve space for the DCC buffer. */
1215 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1216 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1220 /* Now create the backing buffer. */
1222 si_init_resource_fields(rscreen
, resource
, rtex
->size
,
1223 rtex
->surface
.surf_alignment
);
1225 if (!si_alloc_resource(rscreen
, resource
)) {
1230 resource
->buf
= buf
;
1231 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1232 resource
->bo_size
= buf
->size
;
1233 resource
->bo_alignment
= buf
->alignment
;
1234 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1235 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1236 resource
->vram_usage
= buf
->size
;
1237 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1238 resource
->gart_usage
= buf
->size
;
1241 if (rtex
->cmask
.size
) {
1242 /* Initialize the cmask to 0xCC (= compressed state). */
1243 si_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1244 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1247 if (rtex
->htile_offset
) {
1248 uint32_t clear_value
= 0;
1250 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1251 clear_value
= 0x0000030F;
1253 si_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1255 rtex
->surface
.htile_size
,
1259 /* Initialize DCC only if the texture is not being imported. */
1260 if (!buf
&& rtex
->dcc_offset
) {
1261 si_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1263 rtex
->surface
.dcc_size
,
1267 /* Initialize the CMASK base register value. */
1268 rtex
->cmask
.base_address_reg
=
1269 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1271 if (rscreen
->debug_flags
& DBG_VM
) {
1272 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1273 rtex
->resource
.gpu_address
,
1274 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1275 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1276 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1279 if (rscreen
->debug_flags
& DBG_TEX
) {
1281 struct u_log_context log
;
1282 u_log_context_init(&log
);
1283 si_print_texture_info(rscreen
, rtex
, &log
);
1284 u_log_new_page_print(&log
, stdout
);
1286 u_log_context_destroy(&log
);
1292 static enum radeon_surf_mode
1293 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1294 const struct pipe_resource
*templ
)
1296 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1297 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1298 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1299 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1301 /* MSAA resources must be 2D tiled. */
1302 if (templ
->nr_samples
> 1)
1303 return RADEON_SURF_MODE_2D
;
1305 /* Transfer resources should be linear. */
1306 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1307 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1309 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1310 * which requires 2D tiling.
1312 if (rscreen
->chip_class
== VI
&&
1314 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1315 return RADEON_SURF_MODE_2D
;
1317 /* Handle common candidates for the linear mode.
1318 * Compressed textures and DB surfaces must always be tiled.
1320 if (!force_tiling
&&
1321 !is_depth_stencil
&&
1322 !util_format_is_compressed(templ
->format
)) {
1323 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1324 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1326 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1327 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1328 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1330 /* Cursors are linear on SI.
1331 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1332 if (templ
->bind
& PIPE_BIND_CURSOR
)
1333 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1335 if (templ
->bind
& PIPE_BIND_LINEAR
)
1336 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1338 /* Textures with a very small height are recommended to be linear. */
1339 if (templ
->target
== PIPE_TEXTURE_1D
||
1340 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1341 /* Only very thin and long 2D textures should benefit from
1342 * linear_aligned. */
1343 (templ
->width0
> 8 && templ
->height0
<= 2))
1344 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1346 /* Textures likely to be mapped often. */
1347 if (templ
->usage
== PIPE_USAGE_STAGING
||
1348 templ
->usage
== PIPE_USAGE_STREAM
)
1349 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1352 /* Make small textures 1D tiled. */
1353 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1354 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1355 return RADEON_SURF_MODE_1D
;
1357 /* The allocator will switch to 1D if needed. */
1358 return RADEON_SURF_MODE_2D
;
1361 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1362 const struct pipe_resource
*templ
)
1364 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1365 struct radeon_surf surface
= {0};
1366 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1367 bool tc_compatible_htile
=
1368 rscreen
->chip_class
>= VI
&&
1369 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1370 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1371 !is_flushed_depth
&&
1372 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1373 util_format_is_depth_or_stencil(templ
->format
);
1377 r
= r600_init_surface(rscreen
, &surface
, templ
,
1378 r600_choose_tiling(rscreen
, templ
), 0, 0,
1379 false, false, is_flushed_depth
,
1380 tc_compatible_htile
);
1385 return (struct pipe_resource
*)
1386 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1389 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1390 const struct pipe_resource
*templ
,
1391 struct winsys_handle
*whandle
,
1394 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1395 struct pb_buffer
*buf
= NULL
;
1396 unsigned stride
= 0, offset
= 0;
1397 enum radeon_surf_mode array_mode
;
1398 struct radeon_surf surface
= {};
1400 struct radeon_bo_metadata metadata
= {};
1401 struct r600_texture
*rtex
;
1404 /* Support only 2D textures without mipmaps */
1405 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1406 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1409 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1413 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1414 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
1415 &array_mode
, &is_scanout
);
1417 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1418 offset
, true, is_scanout
, false, false);
1423 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1427 rtex
->resource
.b
.is_shared
= true;
1428 rtex
->resource
.external_usage
= usage
;
1430 if (rscreen
->apply_opaque_metadata
)
1431 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1433 assert(rtex
->surface
.tile_swizzle
== 0);
1434 return &rtex
->resource
.b
.b
;
1437 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1438 struct pipe_resource
*texture
,
1439 struct r600_texture
**staging
)
1441 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1442 struct pipe_resource resource
;
1443 struct r600_texture
**flushed_depth_texture
= staging
?
1444 staging
: &rtex
->flushed_depth_texture
;
1445 enum pipe_format pipe_format
= texture
->format
;
1448 if (rtex
->flushed_depth_texture
)
1449 return true; /* it's ready */
1451 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1452 switch (pipe_format
) {
1453 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1454 /* Save memory by not allocating the S plane. */
1455 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1457 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1458 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1459 /* Save memory bandwidth by not copying the
1460 * stencil part during flush.
1462 * This potentially increases memory bandwidth
1463 * if an application uses both Z and S texturing
1464 * simultaneously (a flushed Z24S8 texture
1465 * would be stored compactly), but how often
1466 * does that really happen?
1468 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1472 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1473 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1475 /* DB->CB copies to an 8bpp surface don't work. */
1476 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1480 memset(&resource
, 0, sizeof(resource
));
1481 resource
.target
= texture
->target
;
1482 resource
.format
= pipe_format
;
1483 resource
.width0
= texture
->width0
;
1484 resource
.height0
= texture
->height0
;
1485 resource
.depth0
= texture
->depth0
;
1486 resource
.array_size
= texture
->array_size
;
1487 resource
.last_level
= texture
->last_level
;
1488 resource
.nr_samples
= texture
->nr_samples
;
1489 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1490 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1491 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1494 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1496 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1497 if (*flushed_depth_texture
== NULL
) {
1498 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1502 (*flushed_depth_texture
)->non_disp_tiling
= false;
1507 * Initialize the pipe_resource descriptor to be of the same size as the box,
1508 * which is supposed to hold a subregion of the texture "orig" at the given
1511 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1512 struct pipe_resource
*orig
,
1513 const struct pipe_box
*box
,
1514 unsigned level
, unsigned flags
)
1516 memset(res
, 0, sizeof(*res
));
1517 res
->format
= orig
->format
;
1518 res
->width0
= box
->width
;
1519 res
->height0
= box
->height
;
1521 res
->array_size
= 1;
1522 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1525 /* We must set the correct texture target and dimensions for a 3D box. */
1526 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1527 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1528 res
->array_size
= box
->depth
;
1530 res
->target
= PIPE_TEXTURE_2D
;
1534 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1535 struct r600_texture
*rtex
,
1536 unsigned transfer_usage
,
1537 const struct pipe_box
*box
)
1539 return !rtex
->resource
.b
.is_shared
&&
1540 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1541 rtex
->resource
.b
.b
.last_level
== 0 &&
1542 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1543 box
->x
, box
->y
, box
->z
,
1544 box
->width
, box
->height
,
1548 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1549 struct r600_texture
*rtex
)
1551 struct r600_common_screen
*rscreen
= rctx
->screen
;
1553 /* There is no point in discarding depth and tiled buffers. */
1554 assert(!rtex
->is_depth
);
1555 assert(rtex
->surface
.is_linear
);
1557 /* Reallocate the buffer in the same pipe_resource. */
1558 si_alloc_resource(rscreen
, &rtex
->resource
);
1560 /* Initialize the CMASK base address (needed even without CMASK). */
1561 rtex
->cmask
.base_address_reg
=
1562 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1564 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1566 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1569 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1570 struct pipe_resource
*texture
,
1573 const struct pipe_box
*box
,
1574 struct pipe_transfer
**ptransfer
)
1576 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1577 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1578 struct r600_transfer
*trans
;
1579 struct r600_resource
*buf
;
1580 unsigned offset
= 0;
1582 bool use_staging_texture
= false;
1584 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1585 assert(box
->width
&& box
->height
&& box
->depth
);
1587 /* Depth textures use staging unconditionally. */
1588 if (!rtex
->is_depth
) {
1589 /* Degrade the tile mode if we get too many transfers on APUs.
1590 * On dGPUs, the staging texture is always faster.
1591 * Only count uploads that are at least 4x4 pixels large.
1593 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1595 box
->width
>= 4 && box
->height
>= 4 &&
1596 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1597 bool can_invalidate
=
1598 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1601 r600_reallocate_texture_inplace(rctx
, rtex
,
1606 /* Tiled textures need to be converted into a linear texture for CPU
1607 * access. The staging texture is always linear and is placed in GART.
1609 * Reading from VRAM or GTT WC is slow, always use the staging
1610 * texture in this case.
1612 * Use the staging texture for uploads if the underlying BO
1615 if (!rtex
->surface
.is_linear
)
1616 use_staging_texture
= true;
1617 else if (usage
& PIPE_TRANSFER_READ
)
1618 use_staging_texture
=
1619 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1620 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1621 /* Write & linear only: */
1622 else if (si_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1623 RADEON_USAGE_READWRITE
) ||
1624 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1625 RADEON_USAGE_READWRITE
)) {
1627 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1629 r600_texture_invalidate_storage(rctx
, rtex
);
1631 use_staging_texture
= true;
1635 trans
= CALLOC_STRUCT(r600_transfer
);
1638 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1639 trans
->b
.b
.level
= level
;
1640 trans
->b
.b
.usage
= usage
;
1641 trans
->b
.b
.box
= *box
;
1643 if (rtex
->is_depth
) {
1644 struct r600_texture
*staging_depth
;
1646 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1647 /* MSAA depth buffers need to be converted to single sample buffers.
1649 * Mapping MSAA depth buffers can occur if ReadPixels is called
1650 * with a multisample GLX visual.
1652 * First downsample the depth buffer to a temporary texture,
1653 * then decompress the temporary one to staging.
1655 * Only the region being mapped is transfered.
1657 struct pipe_resource resource
;
1659 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1661 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1662 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1667 if (usage
& PIPE_TRANSFER_READ
) {
1668 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1670 R600_ERR("failed to create a temporary depth texture\n");
1675 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1676 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1677 0, 0, 0, box
->depth
, 0, 0);
1678 pipe_resource_reference(&temp
, NULL
);
1681 /* Just get the strides. */
1682 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1684 &trans
->b
.b
.layer_stride
);
1686 /* XXX: only readback the rectangle which is being mapped? */
1687 /* XXX: when discard is true, no need to read back from depth texture */
1688 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1689 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1694 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1696 box
->z
, box
->z
+ box
->depth
- 1,
1699 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1702 &trans
->b
.b
.layer_stride
);
1705 trans
->staging
= (struct r600_resource
*)staging_depth
;
1706 buf
= trans
->staging
;
1707 } else if (use_staging_texture
) {
1708 struct pipe_resource resource
;
1709 struct r600_texture
*staging
;
1711 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1712 R600_RESOURCE_FLAG_TRANSFER
);
1713 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1714 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1716 /* Create the temporary texture. */
1717 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1719 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1723 trans
->staging
= &staging
->resource
;
1725 /* Just get the strides. */
1726 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1728 &trans
->b
.b
.layer_stride
);
1730 if (usage
& PIPE_TRANSFER_READ
)
1731 r600_copy_to_staging_texture(ctx
, trans
);
1733 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1735 buf
= trans
->staging
;
1737 /* the resource is mapped directly */
1738 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1740 &trans
->b
.b
.layer_stride
);
1741 buf
= &rtex
->resource
;
1744 if (!(map
= si_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1745 r600_resource_reference(&trans
->staging
, NULL
);
1750 *ptransfer
= &trans
->b
.b
;
1751 return map
+ offset
;
1754 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1755 struct pipe_transfer
* transfer
)
1757 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1758 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1759 struct pipe_resource
*texture
= transfer
->resource
;
1760 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1762 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1763 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1764 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1765 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1766 &rtransfer
->staging
->b
.b
, transfer
->level
,
1769 r600_copy_from_staging_texture(ctx
, rtransfer
);
1773 if (rtransfer
->staging
) {
1774 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1775 r600_resource_reference(&rtransfer
->staging
, NULL
);
1778 /* Heuristic for {upload, draw, upload, draw, ..}:
1780 * Flush the gfx IB if we've allocated too much texture storage.
1782 * The idea is that we don't want to build IBs that use too much
1783 * memory and put pressure on the kernel memory manager and we also
1784 * want to make temporary and invalidated buffers go idle ASAP to
1785 * decrease the total memory usage or make them reusable. The memory
1786 * usage will be slightly higher than given here because of the buffer
1787 * cache in the winsys.
1789 * The result is that the kernel memory manager is never a bottleneck.
1791 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1792 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1793 rctx
->num_alloc_tex_transfer_bytes
= 0;
1796 pipe_resource_reference(&transfer
->resource
, NULL
);
1800 static const struct u_resource_vtbl r600_texture_vtbl
=
1802 NULL
, /* get_handle */
1803 r600_texture_destroy
, /* resource_destroy */
1804 r600_texture_transfer_map
, /* transfer_map */
1805 u_default_transfer_flush_region
, /* transfer_flush_region */
1806 r600_texture_transfer_unmap
, /* transfer_unmap */
1809 /* DCC channel type categories within which formats can be reinterpreted
1810 * while keeping the same DCC encoding. The swizzle must also match. */
1811 enum dcc_channel_type
{
1812 dcc_channel_float32
,
1815 dcc_channel_float16
,
1818 dcc_channel_uint_10_10_10_2
,
1821 dcc_channel_incompatible
,
1824 /* Return the type of DCC encoding. */
1825 static enum dcc_channel_type
1826 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1830 /* Find the first non-void channel. */
1831 for (i
= 0; i
< desc
->nr_channels
; i
++)
1832 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1834 if (i
== desc
->nr_channels
)
1835 return dcc_channel_incompatible
;
1837 switch (desc
->channel
[i
].size
) {
1839 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1840 return dcc_channel_float32
;
1841 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1842 return dcc_channel_uint32
;
1843 return dcc_channel_sint32
;
1845 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1846 return dcc_channel_float16
;
1847 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1848 return dcc_channel_uint16
;
1849 return dcc_channel_sint16
;
1851 return dcc_channel_uint_10_10_10_2
;
1853 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1854 return dcc_channel_uint8
;
1855 return dcc_channel_sint8
;
1857 return dcc_channel_incompatible
;
1861 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1862 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1863 enum pipe_format format2
)
1865 const struct util_format_description
*desc1
, *desc2
;
1866 enum dcc_channel_type type1
, type2
;
1869 if (format1
== format2
)
1872 desc1
= util_format_description(format1
);
1873 desc2
= util_format_description(format2
);
1875 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1878 /* Swizzles must be the same. */
1879 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1880 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1881 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1882 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1885 type1
= vi_get_dcc_channel_type(desc1
);
1886 type2
= vi_get_dcc_channel_type(desc2
);
1888 return type1
!= dcc_channel_incompatible
&&
1889 type2
!= dcc_channel_incompatible
&&
1893 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1895 enum pipe_format view_format
)
1897 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1899 return vi_dcc_enabled(rtex
, level
) &&
1900 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1903 /* This can't be merged with the above function, because
1904 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1905 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1906 struct pipe_resource
*tex
,
1908 enum pipe_format view_format
)
1910 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1912 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1913 if (!si_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1914 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1917 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1918 struct pipe_resource
*texture
,
1919 const struct pipe_surface
*templ
,
1920 unsigned width0
, unsigned height0
,
1921 unsigned width
, unsigned height
)
1923 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1928 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1929 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1931 pipe_reference_init(&surface
->base
.reference
, 1);
1932 pipe_resource_reference(&surface
->base
.texture
, texture
);
1933 surface
->base
.context
= pipe
;
1934 surface
->base
.format
= templ
->format
;
1935 surface
->base
.width
= width
;
1936 surface
->base
.height
= height
;
1937 surface
->base
.u
= templ
->u
;
1939 surface
->width0
= width0
;
1940 surface
->height0
= height0
;
1942 surface
->dcc_incompatible
=
1943 texture
->target
!= PIPE_BUFFER
&&
1944 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1946 return &surface
->base
;
1949 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1950 struct pipe_resource
*tex
,
1951 const struct pipe_surface
*templ
)
1953 unsigned level
= templ
->u
.tex
.level
;
1954 unsigned width
= u_minify(tex
->width0
, level
);
1955 unsigned height
= u_minify(tex
->height0
, level
);
1956 unsigned width0
= tex
->width0
;
1957 unsigned height0
= tex
->height0
;
1959 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1960 const struct util_format_description
*tex_desc
1961 = util_format_description(tex
->format
);
1962 const struct util_format_description
*templ_desc
1963 = util_format_description(templ
->format
);
1965 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1967 /* Adjust size of surface if and only if the block width or
1968 * height is changed. */
1969 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1970 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1971 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1972 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1974 width
= nblks_x
* templ_desc
->block
.width
;
1975 height
= nblks_y
* templ_desc
->block
.height
;
1977 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1978 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1982 return si_create_surface_custom(pipe
, tex
, templ
,
1987 static void r600_surface_destroy(struct pipe_context
*pipe
,
1988 struct pipe_surface
*surface
)
1990 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1991 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1992 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1993 pipe_resource_reference(&surface
->texture
, NULL
);
1997 static void r600_clear_texture(struct pipe_context
*pipe
,
1998 struct pipe_resource
*tex
,
2000 const struct pipe_box
*box
,
2003 struct pipe_screen
*screen
= pipe
->screen
;
2004 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
2005 struct pipe_surface tmpl
= {{0}};
2006 struct pipe_surface
*sf
;
2007 const struct util_format_description
*desc
=
2008 util_format_description(tex
->format
);
2010 tmpl
.format
= tex
->format
;
2011 tmpl
.u
.tex
.first_layer
= box
->z
;
2012 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
2013 tmpl
.u
.tex
.level
= level
;
2014 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
2018 if (rtex
->is_depth
) {
2021 uint8_t stencil
= 0;
2023 /* Depth is always present. */
2024 clear
= PIPE_CLEAR_DEPTH
;
2025 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
2027 if (rtex
->surface
.has_stencil
) {
2028 clear
|= PIPE_CLEAR_STENCIL
;
2029 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
2032 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
2034 box
->width
, box
->height
, false);
2036 union pipe_color_union color
;
2038 /* pipe_color_union requires the full vec4 representation. */
2039 if (util_format_is_pure_uint(tex
->format
))
2040 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2041 else if (util_format_is_pure_sint(tex
->format
))
2042 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2044 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2046 if (screen
->is_format_supported(screen
, tex
->format
,
2048 PIPE_BIND_RENDER_TARGET
)) {
2049 pipe
->clear_render_target(pipe
, sf
, &color
,
2051 box
->width
, box
->height
, false);
2053 /* Software fallback - just for R9G9B9E5_FLOAT */
2054 util_clear_render_target(pipe
, sf
, &color
,
2056 box
->width
, box
->height
);
2059 pipe_surface_reference(&sf
, NULL
);
2062 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2064 const struct util_format_description
*desc
= util_format_description(format
);
2066 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2068 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2069 return V_0280A0_SWAP_STD
;
2071 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2074 switch (desc
->nr_channels
) {
2076 if (HAS_SWIZZLE(0,X
))
2077 return V_0280A0_SWAP_STD
; /* X___ */
2078 else if (HAS_SWIZZLE(3,X
))
2079 return V_0280A0_SWAP_ALT_REV
; /* ___X */
2082 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2083 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2084 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2085 return V_0280A0_SWAP_STD
; /* XY__ */
2086 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2087 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2088 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2090 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
2091 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2092 return V_0280A0_SWAP_ALT
; /* X__Y */
2093 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2094 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2097 if (HAS_SWIZZLE(0,X
))
2098 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2099 else if (HAS_SWIZZLE(0,Z
))
2100 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2103 /* check the middle channels, the 1st and 4th channel can be NONE */
2104 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2105 return V_0280A0_SWAP_STD
; /* XYZW */
2106 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2107 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2108 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2109 return V_0280A0_SWAP_ALT
; /* ZYXW */
2110 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2113 return V_0280A0_SWAP_ALT_REV
;
2115 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2122 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2124 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2129 if (rctx
->dcc_stats
[slot
].query_active
)
2130 vi_separate_dcc_stop_query(&rctx
->b
,
2131 rctx
->dcc_stats
[slot
].tex
);
2133 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2134 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2135 rctx
->b
.destroy_query(&rctx
->b
,
2136 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2137 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2140 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2144 * Return the per-context slot where DCC statistics queries for the texture live.
2146 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2147 struct r600_texture
*tex
)
2149 int i
, empty_slot
= -1;
2151 /* Remove zombie textures (textures kept alive by this array only). */
2152 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2153 if (rctx
->dcc_stats
[i
].tex
&&
2154 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2155 vi_dcc_clean_up_context_slot(rctx
, i
);
2157 /* Find the texture. */
2158 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2159 /* Return if found. */
2160 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2161 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2165 /* Record the first seen empty slot. */
2166 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2170 /* Not found. Remove the oldest member to make space in the array. */
2171 if (empty_slot
== -1) {
2172 int oldest_slot
= 0;
2174 /* Find the oldest slot. */
2175 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2176 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2177 rctx
->dcc_stats
[i
].last_use_timestamp
)
2180 /* Clean up the oldest slot. */
2181 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2182 empty_slot
= oldest_slot
;
2185 /* Add the texture to the new slot. */
2186 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2187 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2191 static struct pipe_query
*
2192 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2194 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2195 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2197 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2198 return (struct pipe_query
*)query
;
2202 * Called when binding a color buffer.
2204 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2205 struct r600_texture
*tex
)
2207 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2208 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2210 assert(!rctx
->dcc_stats
[i
].query_active
);
2212 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2213 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2215 /* begin or resume the query */
2216 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2217 rctx
->dcc_stats
[i
].query_active
= true;
2221 * Called when unbinding a color buffer.
2223 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2224 struct r600_texture
*tex
)
2226 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2227 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2229 assert(rctx
->dcc_stats
[i
].query_active
);
2230 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2232 /* pause or end the query */
2233 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2234 rctx
->dcc_stats
[i
].query_active
= false;
2237 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2239 /* The minimum number of fullscreen draws per frame that is required
2241 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2244 /* Called by fast clear. */
2245 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2246 struct r600_texture
*tex
)
2248 /* The intent is to use this with shared displayable back buffers,
2249 * but it's not strictly limited only to them.
2251 if (!tex
->resource
.b
.is_shared
||
2252 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2253 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2254 tex
->resource
.b
.b
.last_level
> 0 ||
2255 !tex
->surface
.dcc_size
)
2258 if (tex
->dcc_offset
)
2259 return; /* already enabled */
2261 /* Enable the DCC stat gathering. */
2262 if (!tex
->dcc_gather_statistics
) {
2263 tex
->dcc_gather_statistics
= true;
2264 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2267 if (!vi_should_enable_separate_dcc(tex
))
2268 return; /* stats show that DCC decompression is too expensive */
2270 assert(tex
->surface
.num_dcc_levels
);
2271 assert(!tex
->dcc_separate_buffer
);
2273 r600_texture_discard_cmask(rctx
->screen
, tex
);
2275 /* Get a DCC buffer. */
2276 if (tex
->last_dcc_separate_buffer
) {
2277 assert(tex
->dcc_gather_statistics
);
2278 assert(!tex
->dcc_separate_buffer
);
2279 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2280 tex
->last_dcc_separate_buffer
= NULL
;
2282 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2283 si_aligned_buffer_create(rctx
->b
.screen
,
2284 R600_RESOURCE_FLAG_UNMAPPABLE
,
2286 tex
->surface
.dcc_size
,
2287 tex
->surface
.dcc_alignment
);
2288 if (!tex
->dcc_separate_buffer
)
2292 /* dcc_offset is the absolute GPUVM address. */
2293 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2295 /* no need to flag anything since this is called by fast clear that
2296 * flags framebuffer state
2301 * Called by pipe_context::flush_resource, the place where DCC decompression
2304 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2305 struct r600_texture
*tex
)
2307 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2308 struct pipe_query
*tmp
;
2309 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2310 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2311 bool disable
= false;
2313 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2314 union pipe_query_result result
;
2316 /* Read the results. */
2317 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2319 si_query_hw_reset_buffers(rctx
,
2320 (struct r600_query_hw
*)
2321 rctx
->dcc_stats
[i
].ps_stats
[2]);
2323 /* Compute the approximate number of fullscreen draws. */
2324 tex
->ps_draw_ratio
=
2325 result
.pipeline_statistics
.ps_invocations
/
2326 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2327 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2329 disable
= tex
->dcc_separate_buffer
&&
2330 !vi_should_enable_separate_dcc(tex
);
2333 tex
->num_slow_clears
= 0;
2335 /* stop the statistics query for ps_stats[0] */
2337 vi_separate_dcc_stop_query(ctx
, tex
);
2339 /* Move the queries in the queue by one. */
2340 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2341 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2342 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2343 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2345 /* create and start a new query as ps_stats[0] */
2347 vi_separate_dcc_start_query(ctx
, tex
);
2350 assert(!tex
->last_dcc_separate_buffer
);
2351 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2352 tex
->dcc_separate_buffer
= NULL
;
2353 tex
->dcc_offset
= 0;
2354 /* no need to flag anything since this is called after
2355 * decompression that re-sets framebuffer state
2360 /* FAST COLOR CLEAR */
2362 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2363 enum pipe_format surface_format
,
2364 const union pipe_color_union
*color
)
2366 union util_color uc
;
2368 memset(&uc
, 0, sizeof(uc
));
2370 if (rtex
->surface
.bpe
== 16) {
2371 /* DCC fast clear only:
2372 * CLEAR_WORD0 = R = G = B
2375 assert(color
->ui
[0] == color
->ui
[1] &&
2376 color
->ui
[0] == color
->ui
[2]);
2377 uc
.ui
[0] = color
->ui
[0];
2378 uc
.ui
[1] = color
->ui
[3];
2379 } else if (util_format_is_pure_uint(surface_format
)) {
2380 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2381 } else if (util_format_is_pure_sint(surface_format
)) {
2382 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2384 util_pack_color(color
->f
, surface_format
, &uc
);
2387 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2390 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2391 const union pipe_color_union
*color
,
2392 uint32_t* reset_value
,
2393 bool* clear_words_needed
)
2395 bool values
[4] = {};
2397 bool main_value
= false;
2398 bool extra_value
= false;
2401 /* This is needed to get the correct DCC clear value for luminance formats.
2402 * 1) Get the linear format (because the next step can't handle L8_SRGB).
2403 * 2) Convert luminance to red. (the real hw format for luminance)
2405 surface_format
= util_format_linear(surface_format
);
2406 surface_format
= util_format_luminance_to_red(surface_format
);
2408 const struct util_format_description
*desc
= util_format_description(surface_format
);
2410 if (desc
->block
.bits
== 128 &&
2411 (color
->ui
[0] != color
->ui
[1] ||
2412 color
->ui
[0] != color
->ui
[2]))
2415 *clear_words_needed
= true;
2416 *reset_value
= 0x20202020U
;
2418 /* If we want to clear without needing a fast clear eliminate step, we
2419 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2420 * have two sets of flags, one for the last or first channel(extra) and
2421 * one for the other channels(main).
2424 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2425 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2426 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
||
2427 util_format_is_alpha(surface_format
)) {
2429 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2430 if(si_translate_colorswap(surface_format
, false) <= 1)
2431 extra_channel
= desc
->nr_channels
- 1;
2437 for (i
= 0; i
< 4; ++i
) {
2438 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2440 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2441 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2444 if (desc
->channel
[i
].pure_integer
&&
2445 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2446 /* Use the maximum value for clamping the clear color. */
2447 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2449 values
[i
] = color
->i
[i
] != 0;
2450 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2452 } else if (desc
->channel
[i
].pure_integer
&&
2453 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2454 /* Use the maximum value for clamping the clear color. */
2455 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2457 values
[i
] = color
->ui
[i
] != 0U;
2458 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2461 values
[i
] = color
->f
[i
] != 0.0F
;
2462 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2466 if (index
== extra_channel
)
2467 extra_value
= values
[i
];
2469 main_value
= values
[i
];
2472 for (int i
= 0; i
< 4; ++i
)
2473 if (values
[i
] != main_value
&&
2474 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2475 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2476 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2479 *clear_words_needed
= false;
2481 *reset_value
|= 0x80808080U
;
2484 *reset_value
|= 0x40404040U
;
2488 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2489 struct r600_texture
*rtex
,
2490 unsigned level
, unsigned clear_value
)
2492 struct pipe_resource
*dcc_buffer
;
2493 uint64_t dcc_offset
, clear_size
;
2495 assert(vi_dcc_enabled(rtex
, level
));
2497 if (rtex
->dcc_separate_buffer
) {
2498 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2501 dcc_buffer
= &rtex
->resource
.b
.b
;
2502 dcc_offset
= rtex
->dcc_offset
;
2505 if (rctx
->chip_class
>= GFX9
) {
2506 /* Mipmap level clears aren't implemented. */
2507 assert(rtex
->resource
.b
.b
.last_level
== 0);
2508 /* MSAA needs a different clear size. */
2509 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2510 clear_size
= rtex
->surface
.dcc_size
;
2512 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2513 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2516 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2517 clear_value
, R600_COHERENCY_CB_META
);
2520 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2521 * This allows hitting the MSAA resolve fast path, which requires that both
2522 * src and dst micro tile modes match.
2524 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2525 struct r600_texture
*rtex
)
2527 if (rtex
->resource
.b
.is_shared
||
2528 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2529 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2532 assert(rscreen
->chip_class
>= GFX9
||
2533 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2534 assert(rtex
->resource
.b
.b
.last_level
== 0);
2536 if (rscreen
->chip_class
>= GFX9
) {
2537 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2538 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2540 /* If you do swizzle_mode % 4, you'll get:
2546 * Depth-sample order isn't allowed:
2548 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2550 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2551 case RADEON_MICRO_MODE_DISPLAY
:
2552 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2553 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2555 case RADEON_MICRO_MODE_THIN
:
2556 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2557 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2559 case RADEON_MICRO_MODE_ROTATED
:
2560 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2561 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2563 default: /* depth */
2564 assert(!"unexpected micro mode");
2567 } else if (rscreen
->chip_class
>= CIK
) {
2568 /* These magic numbers were copied from addrlib. It doesn't use
2569 * any definitions for them either. They are all 2D_TILED_THIN1
2570 * modes with different bpp and micro tile mode.
2572 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2573 case RADEON_MICRO_MODE_DISPLAY
:
2574 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2576 case RADEON_MICRO_MODE_THIN
:
2577 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2579 case RADEON_MICRO_MODE_ROTATED
:
2580 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2582 default: /* depth, thick */
2583 assert(!"unexpected micro mode");
2587 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2588 case RADEON_MICRO_MODE_DISPLAY
:
2589 switch (rtex
->surface
.bpe
) {
2591 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2594 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2597 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2601 case RADEON_MICRO_MODE_THIN
:
2602 switch (rtex
->surface
.bpe
) {
2604 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2607 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2610 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2612 default: /* 8, 16 */
2613 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2617 default: /* depth, thick */
2618 assert(!"unexpected micro mode");
2623 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2625 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2628 void si_do_fast_color_clear(struct r600_common_context
*rctx
,
2629 struct pipe_framebuffer_state
*fb
,
2630 struct r600_atom
*fb_state
,
2631 unsigned *buffers
, ubyte
*dirty_cbufs
,
2632 const union pipe_color_union
*color
)
2636 /* This function is broken in BE, so just disable this path for now */
2637 #ifdef PIPE_ARCH_BIG_ENDIAN
2641 if (rctx
->render_cond
)
2644 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2645 struct r600_texture
*tex
;
2646 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2651 /* if this colorbuffer is not being cleared */
2652 if (!(*buffers
& clear_bit
))
2655 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2657 /* the clear is allowed if all layers are bound */
2658 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2659 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2663 /* cannot clear mipmapped textures */
2664 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2668 /* only supported on tiled surfaces */
2669 if (tex
->surface
.is_linear
) {
2673 /* shared textures can't use fast clear without an explicit flush,
2674 * because there is no way to communicate the clear color among
2677 if (tex
->resource
.b
.is_shared
&&
2678 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2681 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2682 if (rctx
->chip_class
== CIK
&&
2683 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2684 rctx
->screen
->info
.drm_major
== 2 &&
2685 rctx
->screen
->info
.drm_minor
< 38) {
2689 /* Fast clear is the most appropriate place to enable DCC for
2690 * displayable surfaces.
2692 if (rctx
->chip_class
>= VI
&&
2693 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2694 vi_separate_dcc_try_enable(rctx
, tex
);
2696 /* RB+ isn't supported with a CMASK clear only on Stoney,
2697 * so all clears are considered to be hypothetically slow
2698 * clears, which is weighed when determining whether to
2699 * enable separate DCC.
2701 if (tex
->dcc_gather_statistics
&&
2702 rctx
->family
== CHIP_STONEY
)
2703 tex
->num_slow_clears
++;
2706 /* Try to clear DCC first, otherwise try CMASK. */
2707 if (vi_dcc_enabled(tex
, 0)) {
2708 uint32_t reset_value
;
2709 bool clear_words_needed
;
2711 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2714 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2715 color
, &reset_value
,
2716 &clear_words_needed
))
2719 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2721 unsigned level_bit
= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2722 if (clear_words_needed
) {
2723 bool need_compressed_update
= !tex
->dirty_level_mask
;
2725 tex
->dirty_level_mask
|= level_bit
;
2727 if (need_compressed_update
)
2728 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2730 tex
->separate_dcc_dirty
= true;
2732 /* 128-bit formats are unusupported */
2733 if (tex
->surface
.bpe
> 8) {
2737 /* RB+ doesn't work with CMASK fast clear on Stoney. */
2738 if (rctx
->family
== CHIP_STONEY
)
2741 /* ensure CMASK is enabled */
2742 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2743 if (tex
->cmask
.size
== 0) {
2747 /* Do the fast clear. */
2748 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2749 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2750 R600_COHERENCY_CB_META
);
2752 bool need_compressed_update
= !tex
->dirty_level_mask
;
2754 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2756 if (need_compressed_update
)
2757 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2760 /* We can change the micro tile mode before a full clear. */
2761 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2763 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2766 *dirty_cbufs
|= 1 << i
;
2767 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2768 *buffers
&= ~clear_bit
;
2772 static struct pipe_memory_object
*
2773 r600_memobj_from_handle(struct pipe_screen
*screen
,
2774 struct winsys_handle
*whandle
,
2777 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2778 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2779 struct pb_buffer
*buf
= NULL
;
2780 uint32_t stride
, offset
;
2785 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
,
2792 memobj
->b
.dedicated
= dedicated
;
2794 memobj
->stride
= stride
;
2795 memobj
->offset
= offset
;
2797 return (struct pipe_memory_object
*)memobj
;
2802 r600_memobj_destroy(struct pipe_screen
*screen
,
2803 struct pipe_memory_object
*_memobj
)
2805 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2807 pb_reference(&memobj
->buf
, NULL
);
2811 static struct pipe_resource
*
2812 r600_texture_from_memobj(struct pipe_screen
*screen
,
2813 const struct pipe_resource
*templ
,
2814 struct pipe_memory_object
*_memobj
,
2818 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2819 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2820 struct r600_texture
*rtex
;
2821 struct radeon_surf surface
= {};
2822 struct radeon_bo_metadata metadata
= {};
2823 enum radeon_surf_mode array_mode
;
2825 struct pb_buffer
*buf
= NULL
;
2827 if (memobj
->b
.dedicated
) {
2828 rscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2829 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
2830 &array_mode
, &is_scanout
);
2833 * The bo metadata is unset for un-dedicated images. So we fall
2834 * back to linear. See answer to question 5 of the
2835 * VK_KHX_external_memory spec for some details.
2837 * It is possible that this case isn't going to work if the
2838 * surface pitch isn't correctly aligned by default.
2840 * In order to support it correctly we require multi-image
2841 * metadata to be syncrhonized between radv and radeonsi. The
2842 * semantics of associating multiple image metadata to a memory
2843 * object on the vulkan export side are not concretely defined
2846 * All the use cases we are aware of at the moment for memory
2847 * objects use dedicated allocations. So lets keep the initial
2848 * implementation simple.
2850 * A possible alternative is to attempt to reconstruct the
2851 * tiling information when the TexParameter TEXTURE_TILING_EXT
2854 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2859 r
= r600_init_surface(rscreen
, &surface
, templ
,
2860 array_mode
, memobj
->stride
,
2861 offset
, true, is_scanout
,
2866 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2870 /* r600_texture_create_object doesn't increment refcount of
2871 * memobj->buf, so increment it here.
2873 pb_reference(&buf
, memobj
->buf
);
2875 rtex
->resource
.b
.is_shared
= true;
2876 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2878 if (rscreen
->apply_opaque_metadata
)
2879 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
2881 return &rtex
->resource
.b
.b
;
2884 void si_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2886 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2887 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2888 rscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2889 rscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2890 rscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2893 void si_init_context_texture_functions(struct r600_common_context
*rctx
)
2895 rctx
->b
.create_surface
= r600_create_surface
;
2896 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2897 rctx
->b
.clear_texture
= r600_clear_texture
;