2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if (vi_dcc_enabled(rsrc
, src_level
) ||
76 vi_dcc_enabled(rdst
, dst_level
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
181 struct r600_texture
*rtex
, unsigned level
,
182 const struct pipe_box
*box
,
184 unsigned *layer_stride
)
186 if (rscreen
->chip_class
>= GFX9
) {
187 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
188 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
193 /* Each texture is an array of slices. Each slice is an array
194 * of mipmap levels. */
195 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
196 rtex
->surface
.u
.gfx9
.offset
[level
] +
197 (box
->y
/ rtex
->surface
.blk_h
*
198 rtex
->surface
.u
.gfx9
.surf_pitch
+
199 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
201 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
203 *layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
206 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
208 /* Each texture is an array of mipmap levels. Each level is
209 * an array of slices. */
210 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
211 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
212 (box
->y
/ rtex
->surface
.blk_h
*
213 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
214 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
218 static int r600_init_surface(struct r600_common_screen
*rscreen
,
219 struct radeon_surf
*surface
,
220 const struct pipe_resource
*ptex
,
221 enum radeon_surf_mode array_mode
,
222 unsigned pitch_in_bytes_override
,
226 bool is_flushed_depth
,
227 bool tc_compatible_htile
)
229 const struct util_format_description
*desc
=
230 util_format_description(ptex
->format
);
231 bool is_depth
, is_stencil
;
233 unsigned i
, bpe
, flags
= 0;
235 is_depth
= util_format_has_depth(desc
);
236 is_stencil
= util_format_has_stencil(desc
);
238 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
239 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
240 bpe
= 4; /* stencil is allocated separately on evergreen */
242 bpe
= util_format_get_blocksize(ptex
->format
);
243 assert(util_is_power_of_two(bpe
));
246 if (!is_flushed_depth
&& is_depth
) {
247 flags
|= RADEON_SURF_ZBUFFER
;
249 if (tc_compatible_htile
&&
250 (rscreen
->chip_class
>= GFX9
||
251 array_mode
== RADEON_SURF_MODE_2D
)) {
252 /* TC-compatible HTILE only supports Z32_FLOAT.
253 * GFX9 also supports Z16_UNORM.
254 * On VI, promote Z16 to Z32. DB->CB copies will convert
255 * the format for transfers.
257 if (rscreen
->chip_class
== VI
)
260 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
264 flags
|= RADEON_SURF_SBUFFER
;
267 if (rscreen
->chip_class
>= VI
&&
268 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
269 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
270 flags
|= RADEON_SURF_DISABLE_DCC
;
272 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
273 /* This should catch bugs in gallium users setting incorrect flags. */
274 assert(ptex
->nr_samples
<= 1 &&
275 ptex
->array_size
== 1 &&
277 ptex
->last_level
== 0 &&
278 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
280 flags
|= RADEON_SURF_SCANOUT
;
283 if (ptex
->bind
& PIPE_BIND_SHARED
)
284 flags
|= RADEON_SURF_SHAREABLE
;
286 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
287 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
288 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
290 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
291 array_mode
, surface
);
296 if (rscreen
->chip_class
>= GFX9
) {
297 assert(!pitch_in_bytes_override
||
298 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
299 surface
->u
.gfx9
.surf_offset
= offset
;
301 if (pitch_in_bytes_override
&&
302 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
303 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
306 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
307 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
*
308 surface
->u
.legacy
.level
[0].nblk_y
;
312 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
313 surface
->u
.legacy
.level
[i
].offset
+= offset
;
319 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
320 struct r600_texture
*rtex
,
321 struct radeon_bo_metadata
*metadata
)
323 struct radeon_surf
*surface
= &rtex
->surface
;
325 memset(metadata
, 0, sizeof(*metadata
));
327 if (rscreen
->chip_class
>= GFX9
) {
328 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
330 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
331 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
332 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
333 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
334 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
335 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
336 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
337 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
338 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
339 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
340 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
341 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
345 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
346 struct r600_texture
*rtex
)
348 struct r600_common_screen
*rscreen
= rctx
->screen
;
349 struct pipe_context
*ctx
= &rctx
->b
;
351 if (ctx
== rscreen
->aux_context
)
352 mtx_lock(&rscreen
->aux_context_lock
);
354 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
355 ctx
->flush(ctx
, NULL
, 0);
357 if (ctx
== rscreen
->aux_context
)
358 mtx_unlock(&rscreen
->aux_context_lock
);
361 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
362 struct r600_texture
*rtex
)
364 if (!rtex
->cmask
.size
)
367 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
370 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
371 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
372 rtex
->dirty_level_mask
= 0;
374 if (rscreen
->chip_class
>= SI
)
375 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
377 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
379 if (rtex
->cmask_buffer
!= &rtex
->resource
)
380 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
382 /* Notify all contexts about the change. */
383 p_atomic_inc(&rscreen
->dirty_tex_counter
);
384 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
387 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
389 /* We can't disable DCC if it can be written by another process. */
390 return rtex
->dcc_offset
&&
391 (!rtex
->resource
.b
.is_shared
||
392 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
395 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
396 struct r600_texture
*rtex
)
398 if (!r600_can_disable_dcc(rtex
))
401 assert(rtex
->dcc_separate_buffer
== NULL
);
404 rtex
->dcc_offset
= 0;
406 /* Notify all contexts about the change. */
407 p_atomic_inc(&rscreen
->dirty_tex_counter
);
412 * Disable DCC for the texture. (first decompress, then discard metadata).
414 * There is unresolved multi-context synchronization issue between
415 * screen::aux_context and the current context. If applications do this with
416 * multiple contexts, it's already undefined behavior for them and we don't
417 * have to worry about that. The scenario is:
419 * If context 1 disables DCC and context 2 has queued commands that write
420 * to the texture via CB with DCC enabled, and the order of operations is
422 * context 2 queues draw calls rendering to the texture, but doesn't flush
423 * context 1 disables DCC and flushes
424 * context 1 & 2 reset descriptors and FB state
425 * context 2 flushes (new compressed tiles written by the draw calls)
426 * context 1 & 2 read garbage, because DCC is disabled, yet there are
429 * \param rctx the current context if you have one, or rscreen->aux_context
432 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
433 struct r600_texture
*rtex
)
435 struct r600_common_screen
*rscreen
= rctx
->screen
;
437 if (!r600_can_disable_dcc(rtex
))
440 if (&rctx
->b
== rscreen
->aux_context
)
441 mtx_lock(&rscreen
->aux_context_lock
);
443 /* Decompress DCC. */
444 rctx
->decompress_dcc(&rctx
->b
, rtex
);
445 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
447 if (&rctx
->b
== rscreen
->aux_context
)
448 mtx_unlock(&rscreen
->aux_context_lock
);
450 return r600_texture_discard_dcc(rscreen
, rtex
);
453 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
454 struct r600_texture
*rtex
,
455 unsigned new_bind_flag
,
456 bool invalidate_storage
)
458 struct pipe_screen
*screen
= rctx
->b
.screen
;
459 struct r600_texture
*new_tex
;
460 struct pipe_resource templ
= rtex
->resource
.b
.b
;
463 templ
.bind
|= new_bind_flag
;
465 /* r600g doesn't react to dirty_tex_descriptor_counter */
466 if (rctx
->chip_class
< SI
)
469 if (rtex
->resource
.b
.is_shared
)
472 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
473 if (rtex
->surface
.is_linear
)
476 /* This fails with MSAA, depth, and compressed textures. */
477 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
478 RADEON_SURF_MODE_LINEAR_ALIGNED
)
482 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
486 /* Copy the pixels to the new texture. */
487 if (!invalidate_storage
) {
488 for (i
= 0; i
<= templ
.last_level
; i
++) {
492 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
493 util_max_layer(&templ
, i
) + 1, &box
);
495 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
496 &rtex
->resource
.b
.b
, i
, &box
);
500 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
501 r600_texture_discard_cmask(rctx
->screen
, rtex
);
502 r600_texture_discard_dcc(rctx
->screen
, rtex
);
505 /* Replace the structure fields of rtex. */
506 rtex
->resource
.b
.b
.bind
= templ
.bind
;
507 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
508 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
509 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
510 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
511 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
512 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
513 rtex
->resource
.domains
= new_tex
->resource
.domains
;
514 rtex
->resource
.flags
= new_tex
->resource
.flags
;
515 rtex
->size
= new_tex
->size
;
516 rtex
->db_render_format
= new_tex
->db_render_format
;
517 rtex
->db_compatible
= new_tex
->db_compatible
;
518 rtex
->can_sample_z
= new_tex
->can_sample_z
;
519 rtex
->can_sample_s
= new_tex
->can_sample_s
;
520 rtex
->surface
= new_tex
->surface
;
521 rtex
->fmask
= new_tex
->fmask
;
522 rtex
->cmask
= new_tex
->cmask
;
523 rtex
->cb_color_info
= new_tex
->cb_color_info
;
524 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
525 rtex
->htile_offset
= new_tex
->htile_offset
;
526 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
527 rtex
->depth_cleared
= new_tex
->depth_cleared
;
528 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
529 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
530 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
531 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
533 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
534 assert(!rtex
->htile_offset
);
535 assert(!rtex
->cmask
.size
);
536 assert(!rtex
->fmask
.size
);
537 assert(!rtex
->dcc_offset
);
538 assert(!rtex
->is_depth
);
541 r600_texture_reference(&new_tex
, NULL
);
543 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
546 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
547 struct pipe_context
*ctx
,
548 struct pipe_resource
*resource
,
549 struct winsys_handle
*whandle
,
552 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
553 struct r600_common_context
*rctx
;
554 struct r600_resource
*res
= (struct r600_resource
*)resource
;
555 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
556 struct radeon_bo_metadata metadata
;
557 bool update_metadata
= false;
558 unsigned stride
, offset
, slice_size
;
560 ctx
= threaded_context_unwrap_sync(ctx
);
561 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
563 if (resource
->target
!= PIPE_BUFFER
) {
564 /* This is not supported now, but it might be required for OpenCL
565 * interop in the future.
567 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
570 /* Move a suballocated texture into a non-suballocated allocation. */
571 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
572 assert(!res
->b
.is_shared
);
573 r600_reallocate_texture_inplace(rctx
, rtex
,
574 PIPE_BIND_SHARED
, false);
575 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
576 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
577 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
580 /* Since shader image stores don't support DCC on VI,
581 * disable it for external clients that want write
584 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
585 if (r600_texture_disable_dcc(rctx
, rtex
))
586 update_metadata
= true;
589 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
590 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
591 /* Eliminate fast clear (both CMASK and DCC) */
592 r600_eliminate_fast_color_clear(rctx
, rtex
);
594 /* Disable CMASK if flush_resource isn't going
597 if (rtex
->cmask
.size
)
598 r600_texture_discard_cmask(rscreen
, rtex
);
602 if (!res
->b
.is_shared
|| update_metadata
) {
603 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
604 if (rscreen
->query_opaque_metadata
)
605 rscreen
->query_opaque_metadata(rscreen
, rtex
,
608 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
611 if (rscreen
->chip_class
>= GFX9
) {
612 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
613 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
615 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
617 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
618 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
620 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
623 /* Move a suballocated buffer into a non-suballocated allocation. */
624 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
625 assert(!res
->b
.is_shared
);
627 /* Allocate a new buffer with PIPE_BIND_SHARED. */
628 struct pipe_resource templ
= res
->b
.b
;
629 templ
.bind
|= PIPE_BIND_SHARED
;
631 struct pipe_resource
*newb
=
632 screen
->resource_create(screen
, &templ
);
636 /* Copy the old buffer contents to the new one. */
638 u_box_1d(0, newb
->width0
, &box
);
639 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
641 /* Move the new buffer storage to the old pipe_resource. */
642 r600_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
643 pipe_resource_reference(&newb
, NULL
);
645 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
646 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
655 if (res
->b
.is_shared
) {
656 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
659 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
660 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
661 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
663 res
->b
.is_shared
= true;
664 res
->external_usage
= usage
;
667 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
668 slice_size
, whandle
);
671 static void r600_texture_destroy(struct pipe_screen
*screen
,
672 struct pipe_resource
*ptex
)
674 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
675 struct r600_resource
*resource
= &rtex
->resource
;
677 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
679 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
680 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
682 pb_reference(&resource
->buf
, NULL
);
683 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
684 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
688 static const struct u_resource_vtbl r600_texture_vtbl
;
690 /* The number of samples can be specified independently of the texture. */
691 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
692 struct r600_texture
*rtex
,
694 struct r600_fmask_info
*out
)
696 /* FMASK is allocated like an ordinary texture. */
697 struct pipe_resource templ
= rtex
->resource
.b
.b
;
698 struct radeon_surf fmask
= {};
701 memset(out
, 0, sizeof(*out
));
703 if (rscreen
->chip_class
>= GFX9
) {
704 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
705 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
709 templ
.nr_samples
= 1;
710 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
712 if (rscreen
->chip_class
<= CAYMAN
) {
713 /* Use the same parameters and tile mode. */
714 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
715 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
716 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
717 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
720 fmask
.u
.legacy
.bankh
= 4;
723 switch (nr_samples
) {
732 R600_ERR("Invalid sample count for FMASK allocation.\n");
736 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
737 * This can be fixed by writing a separate FMASK allocator specifically
738 * for R600-R700 asics. */
739 if (rscreen
->chip_class
<= R700
) {
743 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
744 RADEON_SURF_MODE_2D
, &fmask
)) {
745 R600_ERR("Got error in surface_init while allocating FMASK.\n");
749 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
751 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
752 if (out
->slice_tile_max
)
753 out
->slice_tile_max
-= 1;
755 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
756 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
757 out
->bank_height
= fmask
.u
.legacy
.bankh
;
758 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
759 out
->size
= fmask
.surf_size
;
762 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
763 struct r600_texture
*rtex
)
765 r600_texture_get_fmask_info(rscreen
, rtex
,
766 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
768 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
769 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
772 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
773 struct r600_texture
*rtex
,
774 struct r600_cmask_info
*out
)
776 unsigned cmask_tile_width
= 8;
777 unsigned cmask_tile_height
= 8;
778 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
779 unsigned element_bits
= 4;
780 unsigned cmask_cache_bits
= 1024;
781 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
782 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
784 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
785 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
786 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
787 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
788 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
790 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
791 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
793 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
794 unsigned slice_bytes
=
795 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
797 assert(macro_tile_width
% 128 == 0);
798 assert(macro_tile_height
% 128 == 0);
800 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
801 out
->alignment
= MAX2(256, base_align
);
802 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
803 align(slice_bytes
, base_align
);
806 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
807 struct r600_texture
*rtex
,
808 struct r600_cmask_info
*out
)
810 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
811 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
812 unsigned cl_width
, cl_height
;
814 if (rscreen
->chip_class
>= GFX9
) {
815 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
816 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
833 case 16: /* Hawaii */
842 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
844 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
845 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
846 unsigned slice_elements
= (width
* height
) / (8*8);
848 /* Each element of CMASK is a nibble. */
849 unsigned slice_bytes
= slice_elements
/ 2;
851 out
->slice_tile_max
= (width
* height
) / (128*128);
852 if (out
->slice_tile_max
)
853 out
->slice_tile_max
-= 1;
855 out
->alignment
= MAX2(256, base_align
);
856 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
857 align(slice_bytes
, base_align
);
860 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
861 struct r600_texture
*rtex
)
863 if (rscreen
->chip_class
>= SI
) {
864 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
866 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
869 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
870 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
872 if (rscreen
->chip_class
>= SI
)
873 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
875 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
878 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
879 struct r600_texture
*rtex
)
881 if (rtex
->cmask_buffer
)
884 assert(rtex
->cmask
.size
== 0);
886 if (rscreen
->chip_class
>= SI
) {
887 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
889 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
892 rtex
->cmask_buffer
= (struct r600_resource
*)
893 r600_aligned_buffer_create(&rscreen
->b
,
894 R600_RESOURCE_FLAG_UNMAPPABLE
,
897 rtex
->cmask
.alignment
);
898 if (rtex
->cmask_buffer
== NULL
) {
899 rtex
->cmask
.size
= 0;
903 /* update colorbuffer state bits */
904 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
906 if (rscreen
->chip_class
>= SI
)
907 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
909 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
911 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
914 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
915 struct r600_texture
*rtex
)
917 unsigned cl_width
, cl_height
, width
, height
;
918 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
919 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
921 assert(rscreen
->chip_class
<= VI
);
923 rtex
->surface
.htile_size
= 0;
925 if (rscreen
->chip_class
<= EVERGREEN
&&
926 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
929 /* HW bug on R6xx. */
930 if (rscreen
->chip_class
== R600
&&
931 (rtex
->resource
.b
.b
.width0
> 7680 ||
932 rtex
->resource
.b
.b
.height0
> 7680))
935 /* HTILE is broken with 1D tiling on old kernels and CIK. */
936 if (rscreen
->chip_class
>= CIK
&&
937 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
938 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
941 /* Overalign HTILE on P2 configs to work around GPU hangs in
942 * piglit/depthstencil-render-miplevels 585.
944 * This has been confirmed to help Kabini & Stoney, where the hangs
945 * are always reproducible. I think I have seen the test hang
946 * on Carrizo too, though it was very rare there.
948 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
977 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
978 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
980 slice_elements
= (width
* height
) / (8 * 8);
981 slice_bytes
= slice_elements
* 4;
983 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
984 base_align
= num_pipes
* pipe_interleave_bytes
;
986 rtex
->surface
.htile_alignment
= base_align
;
987 rtex
->surface
.htile_size
=
988 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
989 align(slice_bytes
, base_align
);
992 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
993 struct r600_texture
*rtex
)
995 if (rscreen
->chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
996 r600_texture_get_htile_size(rscreen
, rtex
);
998 if (!rtex
->surface
.htile_size
)
1001 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
1002 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
1005 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
1006 struct r600_texture
*rtex
, FILE *f
)
1010 /* Common parameters. */
1011 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1012 "blk_h=%u, array_size=%u, last_level=%u, "
1013 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1014 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
1015 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1016 rtex
->surface
.blk_h
,
1017 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
1018 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
1019 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
1021 if (rscreen
->chip_class
>= GFX9
) {
1022 fprintf(f
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1023 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1024 rtex
->surface
.surf_size
,
1025 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1026 rtex
->surface
.surf_alignment
,
1027 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1028 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1029 rtex
->surface
.u
.gfx9
.surf_pitch
);
1031 if (rtex
->fmask
.size
) {
1032 fprintf(f
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1033 "alignment=%u, swmode=%u, epitch=%u\n",
1035 rtex
->surface
.u
.gfx9
.fmask_size
,
1036 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1037 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1038 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1041 if (rtex
->cmask
.size
) {
1042 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1043 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1045 rtex
->surface
.u
.gfx9
.cmask_size
,
1046 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1047 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1048 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1051 if (rtex
->htile_offset
) {
1052 fprintf(f
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1053 "rb_aligned=%u, pipe_aligned=%u\n",
1055 rtex
->surface
.htile_size
,
1056 rtex
->surface
.htile_alignment
,
1057 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1058 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1061 if (rtex
->dcc_offset
) {
1062 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
1063 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1064 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1065 rtex
->surface
.dcc_alignment
,
1066 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1067 rtex
->surface
.num_dcc_levels
);
1070 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1071 fprintf(f
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1072 rtex
->surface
.u
.gfx9
.stencil_offset
,
1073 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1074 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1079 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1080 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1081 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1082 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1083 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1084 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1086 if (rtex
->fmask
.size
)
1087 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1088 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1089 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1090 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1091 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1093 if (rtex
->cmask
.size
)
1094 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1095 "slice_tile_max=%u\n",
1096 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1097 rtex
->cmask
.slice_tile_max
);
1099 if (rtex
->htile_offset
)
1100 fprintf(f
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", "
1101 "alignment=%u, TC_compatible = %u\n",
1102 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1103 rtex
->surface
.htile_alignment
,
1104 rtex
->tc_compatible_htile
);
1106 if (rtex
->dcc_offset
) {
1107 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1108 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1109 rtex
->surface
.dcc_alignment
);
1110 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1111 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1112 "fast_clear_size=%"PRIu64
"\n",
1113 i
, i
< rtex
->surface
.num_dcc_levels
,
1114 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1115 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1118 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1119 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1120 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1121 "mode=%u, tiling_index = %u\n",
1122 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1123 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1124 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1125 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1126 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1127 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1128 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1129 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1130 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1132 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1133 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1134 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1135 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1136 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1137 "slice_size=%"PRIu64
", npix_x=%u, "
1138 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1139 "mode=%u, tiling_index = %u\n",
1140 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1141 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1142 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1143 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1144 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1145 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1146 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1147 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1148 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1153 /* Common processing for r600_texture_create and r600_texture_from_handle */
1154 static struct r600_texture
*
1155 r600_texture_create_object(struct pipe_screen
*screen
,
1156 const struct pipe_resource
*base
,
1157 struct pb_buffer
*buf
,
1158 struct radeon_surf
*surface
)
1160 struct r600_texture
*rtex
;
1161 struct r600_resource
*resource
;
1162 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1164 rtex
= CALLOC_STRUCT(r600_texture
);
1168 resource
= &rtex
->resource
;
1169 resource
->b
.b
= *base
;
1170 resource
->b
.b
.next
= NULL
;
1171 resource
->b
.vtbl
= &r600_texture_vtbl
;
1172 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1173 resource
->b
.b
.screen
= screen
;
1175 /* don't include stencil-only formats which we don't support for rendering */
1176 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1178 rtex
->surface
= *surface
;
1179 rtex
->size
= rtex
->surface
.surf_size
;
1181 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1182 (rtex
->surface
.flags
&
1183 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1185 /* TC-compatible HTILE:
1186 * - VI only supports Z32_FLOAT.
1187 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1188 if (rtex
->tc_compatible_htile
) {
1189 if (rscreen
->chip_class
>= GFX9
&&
1190 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1191 rtex
->db_render_format
= base
->format
;
1193 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1195 rtex
->db_render_format
= base
->format
;
1198 /* Tiled depth textures utilize the non-displayable tile order.
1199 * This must be done after r600_setup_surface.
1200 * Applies to R600-Cayman. */
1201 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1202 /* Applies to GCN. */
1203 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1205 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1206 * between frames, so the only thing that can enable separate DCC
1207 * with DRI2 is multiple slow clears within a frame.
1209 rtex
->ps_draw_ratio
= 0;
1211 if (rtex
->is_depth
) {
1212 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1213 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1214 rscreen
->chip_class
>= EVERGREEN
) {
1215 if (rscreen
->chip_class
>= GFX9
) {
1216 rtex
->can_sample_z
= true;
1217 rtex
->can_sample_s
= true;
1219 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1220 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1223 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1224 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1225 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1226 rtex
->can_sample_z
= true;
1229 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1230 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1231 rtex
->db_compatible
= true;
1233 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1234 r600_texture_allocate_htile(rscreen
, rtex
);
1237 if (base
->nr_samples
> 1) {
1239 r600_texture_allocate_fmask(rscreen
, rtex
);
1240 r600_texture_allocate_cmask(rscreen
, rtex
);
1241 rtex
->cmask_buffer
= &rtex
->resource
;
1243 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1249 /* Shared textures must always set up DCC here.
1250 * If it's not present, it will be disabled by
1251 * apply_opaque_metadata later.
1253 if (rtex
->surface
.dcc_size
&&
1254 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1255 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1256 /* Reserve space for the DCC buffer. */
1257 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1258 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1262 /* Now create the backing buffer. */
1264 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1265 rtex
->surface
.surf_alignment
);
1267 /* Displayable surfaces are not suballocated. */
1268 if (resource
->b
.b
.bind
& PIPE_BIND_SCANOUT
)
1269 resource
->flags
|= RADEON_FLAG_NO_SUBALLOC
;
1271 if (!r600_alloc_resource(rscreen
, resource
)) {
1276 resource
->buf
= buf
;
1277 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1278 resource
->bo_size
= buf
->size
;
1279 resource
->bo_alignment
= buf
->alignment
;
1280 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1281 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1282 resource
->vram_usage
= buf
->size
;
1283 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1284 resource
->gart_usage
= buf
->size
;
1287 if (rtex
->cmask
.size
) {
1288 /* Initialize the cmask to 0xCC (= compressed state). */
1289 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1290 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1293 if (rtex
->htile_offset
) {
1294 uint32_t clear_value
= 0;
1296 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1297 clear_value
= 0x0000030F;
1299 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1301 rtex
->surface
.htile_size
,
1305 /* Initialize DCC only if the texture is not being imported. */
1306 if (!buf
&& rtex
->dcc_offset
) {
1307 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1309 rtex
->surface
.dcc_size
,
1313 /* Initialize the CMASK base register value. */
1314 rtex
->cmask
.base_address_reg
=
1315 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1317 if (rscreen
->debug_flags
& DBG_VM
) {
1318 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1319 rtex
->resource
.gpu_address
,
1320 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1321 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1322 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1325 if (rscreen
->debug_flags
& DBG_TEX
) {
1327 r600_print_texture_info(rscreen
, rtex
, stdout
);
1334 static enum radeon_surf_mode
1335 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1336 const struct pipe_resource
*templ
)
1338 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1339 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1340 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1341 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1343 /* MSAA resources must be 2D tiled. */
1344 if (templ
->nr_samples
> 1)
1345 return RADEON_SURF_MODE_2D
;
1347 /* Transfer resources should be linear. */
1348 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1349 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1351 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1352 * which requires 2D tiling.
1354 if (rscreen
->chip_class
== VI
&&
1356 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1357 return RADEON_SURF_MODE_2D
;
1359 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1360 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1361 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1362 (templ
->target
== PIPE_TEXTURE_2D
||
1363 templ
->target
== PIPE_TEXTURE_3D
))
1364 force_tiling
= true;
1366 /* Handle common candidates for the linear mode.
1367 * Compressed textures and DB surfaces must always be tiled.
1369 if (!force_tiling
&&
1370 !is_depth_stencil
&&
1371 !util_format_is_compressed(templ
->format
)) {
1372 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1373 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1375 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1376 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1377 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1379 /* Cursors are linear on SI.
1380 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1381 if (rscreen
->chip_class
>= SI
&&
1382 (templ
->bind
& PIPE_BIND_CURSOR
))
1383 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1385 if (templ
->bind
& PIPE_BIND_LINEAR
)
1386 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1388 /* Textures with a very small height are recommended to be linear. */
1389 if (templ
->target
== PIPE_TEXTURE_1D
||
1390 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1391 /* Only very thin and long 2D textures should benefit from
1392 * linear_aligned. */
1393 (templ
->width0
> 8 && templ
->height0
<= 2))
1394 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1396 /* Textures likely to be mapped often. */
1397 if (templ
->usage
== PIPE_USAGE_STAGING
||
1398 templ
->usage
== PIPE_USAGE_STREAM
)
1399 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1402 /* Make small textures 1D tiled. */
1403 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1404 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1405 return RADEON_SURF_MODE_1D
;
1407 /* The allocator will switch to 1D if needed. */
1408 return RADEON_SURF_MODE_2D
;
1411 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1412 const struct pipe_resource
*templ
)
1414 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1415 struct radeon_surf surface
= {0};
1416 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1417 bool tc_compatible_htile
=
1418 rscreen
->chip_class
>= VI
&&
1419 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1420 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1421 !is_flushed_depth
&&
1422 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1423 util_format_is_depth_or_stencil(templ
->format
);
1427 r
= r600_init_surface(rscreen
, &surface
, templ
,
1428 r600_choose_tiling(rscreen
, templ
), 0, 0,
1429 false, false, is_flushed_depth
,
1430 tc_compatible_htile
);
1435 return (struct pipe_resource
*)
1436 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1439 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1440 const struct pipe_resource
*templ
,
1441 struct winsys_handle
*whandle
,
1444 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1445 struct pb_buffer
*buf
= NULL
;
1446 unsigned stride
= 0, offset
= 0;
1447 unsigned array_mode
;
1448 struct radeon_surf surface
;
1450 struct radeon_bo_metadata metadata
= {};
1451 struct r600_texture
*rtex
;
1454 /* Support only 2D textures without mipmaps */
1455 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1456 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1459 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1463 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1465 if (rscreen
->chip_class
>= GFX9
) {
1466 if (metadata
.u
.gfx9
.swizzle_mode
> 0)
1467 array_mode
= RADEON_SURF_MODE_2D
;
1469 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1471 is_scanout
= metadata
.u
.gfx9
.swizzle_mode
== 0 ||
1472 metadata
.u
.gfx9
.swizzle_mode
% 4 == 2;
1474 surface
.u
.legacy
.pipe_config
= metadata
.u
.legacy
.pipe_config
;
1475 surface
.u
.legacy
.bankw
= metadata
.u
.legacy
.bankw
;
1476 surface
.u
.legacy
.bankh
= metadata
.u
.legacy
.bankh
;
1477 surface
.u
.legacy
.tile_split
= metadata
.u
.legacy
.tile_split
;
1478 surface
.u
.legacy
.mtilea
= metadata
.u
.legacy
.mtilea
;
1479 surface
.u
.legacy
.num_banks
= metadata
.u
.legacy
.num_banks
;
1481 if (metadata
.u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1482 array_mode
= RADEON_SURF_MODE_2D
;
1483 else if (metadata
.u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1484 array_mode
= RADEON_SURF_MODE_1D
;
1486 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1488 is_scanout
= metadata
.u
.legacy
.scanout
;
1491 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1492 offset
, true, is_scanout
, false, false);
1497 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1501 rtex
->resource
.b
.is_shared
= true;
1502 rtex
->resource
.external_usage
= usage
;
1504 if (rscreen
->apply_opaque_metadata
)
1505 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1507 /* Validate that addrlib arrived at the same surface parameters. */
1508 if (rscreen
->chip_class
>= GFX9
) {
1509 assert(metadata
.u
.gfx9
.swizzle_mode
== surface
.u
.gfx9
.surf
.swizzle_mode
);
1512 return &rtex
->resource
.b
.b
;
1515 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1516 struct pipe_resource
*texture
,
1517 struct r600_texture
**staging
)
1519 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1520 struct pipe_resource resource
;
1521 struct r600_texture
**flushed_depth_texture
= staging
?
1522 staging
: &rtex
->flushed_depth_texture
;
1523 enum pipe_format pipe_format
= texture
->format
;
1526 if (rtex
->flushed_depth_texture
)
1527 return true; /* it's ready */
1529 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1530 switch (pipe_format
) {
1531 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1532 /* Save memory by not allocating the S plane. */
1533 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1535 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1536 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1537 /* Save memory bandwidth by not copying the
1538 * stencil part during flush.
1540 * This potentially increases memory bandwidth
1541 * if an application uses both Z and S texturing
1542 * simultaneously (a flushed Z24S8 texture
1543 * would be stored compactly), but how often
1544 * does that really happen?
1546 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1550 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1551 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1553 /* DB->CB copies to an 8bpp surface don't work. */
1554 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1558 memset(&resource
, 0, sizeof(resource
));
1559 resource
.target
= texture
->target
;
1560 resource
.format
= pipe_format
;
1561 resource
.width0
= texture
->width0
;
1562 resource
.height0
= texture
->height0
;
1563 resource
.depth0
= texture
->depth0
;
1564 resource
.array_size
= texture
->array_size
;
1565 resource
.last_level
= texture
->last_level
;
1566 resource
.nr_samples
= texture
->nr_samples
;
1567 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1568 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1569 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1572 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1574 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1575 if (*flushed_depth_texture
== NULL
) {
1576 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1580 (*flushed_depth_texture
)->non_disp_tiling
= false;
1585 * Initialize the pipe_resource descriptor to be of the same size as the box,
1586 * which is supposed to hold a subregion of the texture "orig" at the given
1589 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1590 struct pipe_resource
*orig
,
1591 const struct pipe_box
*box
,
1592 unsigned level
, unsigned flags
)
1594 memset(res
, 0, sizeof(*res
));
1595 res
->format
= orig
->format
;
1596 res
->width0
= box
->width
;
1597 res
->height0
= box
->height
;
1599 res
->array_size
= 1;
1600 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1603 /* We must set the correct texture target and dimensions for a 3D box. */
1604 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1605 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1606 res
->array_size
= box
->depth
;
1608 res
->target
= PIPE_TEXTURE_2D
;
1612 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1613 struct r600_texture
*rtex
,
1614 unsigned transfer_usage
,
1615 const struct pipe_box
*box
)
1617 /* r600g doesn't react to dirty_tex_descriptor_counter */
1618 return rscreen
->chip_class
>= SI
&&
1619 !rtex
->resource
.b
.is_shared
&&
1620 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1621 rtex
->resource
.b
.b
.last_level
== 0 &&
1622 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1623 box
->x
, box
->y
, box
->z
,
1624 box
->width
, box
->height
,
1628 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1629 struct r600_texture
*rtex
)
1631 struct r600_common_screen
*rscreen
= rctx
->screen
;
1633 /* There is no point in discarding depth and tiled buffers. */
1634 assert(!rtex
->is_depth
);
1635 assert(rtex
->surface
.is_linear
);
1637 /* Reallocate the buffer in the same pipe_resource. */
1638 r600_alloc_resource(rscreen
, &rtex
->resource
);
1640 /* Initialize the CMASK base address (needed even without CMASK). */
1641 rtex
->cmask
.base_address_reg
=
1642 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1644 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1646 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1649 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1650 struct pipe_resource
*texture
,
1653 const struct pipe_box
*box
,
1654 struct pipe_transfer
**ptransfer
)
1656 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1657 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1658 struct r600_transfer
*trans
;
1659 struct r600_resource
*buf
;
1660 unsigned offset
= 0;
1662 bool use_staging_texture
= false;
1664 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1665 assert(box
->width
&& box
->height
&& box
->depth
);
1667 /* Depth textures use staging unconditionally. */
1668 if (!rtex
->is_depth
) {
1669 /* Degrade the tile mode if we get too many transfers on APUs.
1670 * On dGPUs, the staging texture is always faster.
1671 * Only count uploads that are at least 4x4 pixels large.
1673 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1675 box
->width
>= 4 && box
->height
>= 4 &&
1676 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1677 bool can_invalidate
=
1678 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1681 r600_reallocate_texture_inplace(rctx
, rtex
,
1686 /* Tiled textures need to be converted into a linear texture for CPU
1687 * access. The staging texture is always linear and is placed in GART.
1689 * Reading from VRAM or GTT WC is slow, always use the staging
1690 * texture in this case.
1692 * Use the staging texture for uploads if the underlying BO
1695 if (!rtex
->surface
.is_linear
)
1696 use_staging_texture
= true;
1697 else if (usage
& PIPE_TRANSFER_READ
)
1698 use_staging_texture
=
1699 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1700 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1701 /* Write & linear only: */
1702 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1703 RADEON_USAGE_READWRITE
) ||
1704 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1705 RADEON_USAGE_READWRITE
)) {
1707 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1709 r600_texture_invalidate_storage(rctx
, rtex
);
1711 use_staging_texture
= true;
1715 trans
= CALLOC_STRUCT(r600_transfer
);
1718 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1719 trans
->b
.b
.level
= level
;
1720 trans
->b
.b
.usage
= usage
;
1721 trans
->b
.b
.box
= *box
;
1723 if (rtex
->is_depth
) {
1724 struct r600_texture
*staging_depth
;
1726 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1727 /* MSAA depth buffers need to be converted to single sample buffers.
1729 * Mapping MSAA depth buffers can occur if ReadPixels is called
1730 * with a multisample GLX visual.
1732 * First downsample the depth buffer to a temporary texture,
1733 * then decompress the temporary one to staging.
1735 * Only the region being mapped is transfered.
1737 struct pipe_resource resource
;
1739 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1741 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1742 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1747 if (usage
& PIPE_TRANSFER_READ
) {
1748 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1750 R600_ERR("failed to create a temporary depth texture\n");
1755 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1756 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1757 0, 0, 0, box
->depth
, 0, 0);
1758 pipe_resource_reference(&temp
, NULL
);
1761 /* Just get the strides. */
1762 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1764 &trans
->b
.b
.layer_stride
);
1766 /* XXX: only readback the rectangle which is being mapped? */
1767 /* XXX: when discard is true, no need to read back from depth texture */
1768 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1769 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1774 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1776 box
->z
, box
->z
+ box
->depth
- 1,
1779 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1782 &trans
->b
.b
.layer_stride
);
1785 trans
->staging
= (struct r600_resource
*)staging_depth
;
1786 buf
= trans
->staging
;
1787 } else if (use_staging_texture
) {
1788 struct pipe_resource resource
;
1789 struct r600_texture
*staging
;
1791 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1792 R600_RESOURCE_FLAG_TRANSFER
);
1793 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1794 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1796 /* Create the temporary texture. */
1797 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1799 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1803 trans
->staging
= &staging
->resource
;
1805 /* Just get the strides. */
1806 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1808 &trans
->b
.b
.layer_stride
);
1810 if (usage
& PIPE_TRANSFER_READ
)
1811 r600_copy_to_staging_texture(ctx
, trans
);
1813 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1815 buf
= trans
->staging
;
1817 /* the resource is mapped directly */
1818 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1820 &trans
->b
.b
.layer_stride
);
1821 buf
= &rtex
->resource
;
1824 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1825 r600_resource_reference(&trans
->staging
, NULL
);
1830 *ptransfer
= &trans
->b
.b
;
1831 return map
+ offset
;
1834 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1835 struct pipe_transfer
* transfer
)
1837 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1838 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1839 struct pipe_resource
*texture
= transfer
->resource
;
1840 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1842 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1843 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1844 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1845 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1846 &rtransfer
->staging
->b
.b
, transfer
->level
,
1849 r600_copy_from_staging_texture(ctx
, rtransfer
);
1853 if (rtransfer
->staging
) {
1854 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1855 r600_resource_reference(&rtransfer
->staging
, NULL
);
1858 /* Heuristic for {upload, draw, upload, draw, ..}:
1860 * Flush the gfx IB if we've allocated too much texture storage.
1862 * The idea is that we don't want to build IBs that use too much
1863 * memory and put pressure on the kernel memory manager and we also
1864 * want to make temporary and invalidated buffers go idle ASAP to
1865 * decrease the total memory usage or make them reusable. The memory
1866 * usage will be slightly higher than given here because of the buffer
1867 * cache in the winsys.
1869 * The result is that the kernel memory manager is never a bottleneck.
1871 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1872 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1873 rctx
->num_alloc_tex_transfer_bytes
= 0;
1876 pipe_resource_reference(&transfer
->resource
, NULL
);
1880 static const struct u_resource_vtbl r600_texture_vtbl
=
1882 NULL
, /* get_handle */
1883 r600_texture_destroy
, /* resource_destroy */
1884 r600_texture_transfer_map
, /* transfer_map */
1885 u_default_transfer_flush_region
, /* transfer_flush_region */
1886 r600_texture_transfer_unmap
, /* transfer_unmap */
1889 /* DCC channel type categories within which formats can be reinterpreted
1890 * while keeping the same DCC encoding. The swizzle must also match. */
1891 enum dcc_channel_type
{
1892 dcc_channel_float32
,
1895 dcc_channel_float16
,
1898 dcc_channel_uint_10_10_10_2
,
1901 dcc_channel_incompatible
,
1904 /* Return the type of DCC encoding. */
1905 static enum dcc_channel_type
1906 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1910 /* Find the first non-void channel. */
1911 for (i
= 0; i
< desc
->nr_channels
; i
++)
1912 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1914 if (i
== desc
->nr_channels
)
1915 return dcc_channel_incompatible
;
1917 switch (desc
->channel
[i
].size
) {
1919 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1920 return dcc_channel_float32
;
1921 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1922 return dcc_channel_uint32
;
1923 return dcc_channel_sint32
;
1925 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1926 return dcc_channel_float16
;
1927 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1928 return dcc_channel_uint16
;
1929 return dcc_channel_sint16
;
1931 return dcc_channel_uint_10_10_10_2
;
1933 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1934 return dcc_channel_uint8
;
1935 return dcc_channel_sint8
;
1937 return dcc_channel_incompatible
;
1941 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1942 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1943 enum pipe_format format2
)
1945 const struct util_format_description
*desc1
, *desc2
;
1946 enum dcc_channel_type type1
, type2
;
1949 if (format1
== format2
)
1952 desc1
= util_format_description(format1
);
1953 desc2
= util_format_description(format2
);
1955 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1958 /* Swizzles must be the same. */
1959 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1960 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1961 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1962 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1965 type1
= vi_get_dcc_channel_type(desc1
);
1966 type2
= vi_get_dcc_channel_type(desc2
);
1968 return type1
!= dcc_channel_incompatible
&&
1969 type2
!= dcc_channel_incompatible
&&
1973 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1975 enum pipe_format view_format
)
1977 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1979 return vi_dcc_enabled(rtex
, level
) &&
1980 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1983 /* This can't be merged with the above function, because
1984 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1985 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1986 struct pipe_resource
*tex
,
1988 enum pipe_format view_format
)
1990 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1992 if (vi_dcc_enabled(rtex
, level
) &&
1993 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1994 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1995 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1998 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1999 struct pipe_resource
*texture
,
2000 const struct pipe_surface
*templ
,
2001 unsigned width0
, unsigned height0
,
2002 unsigned width
, unsigned height
)
2004 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
2009 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2010 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2012 pipe_reference_init(&surface
->base
.reference
, 1);
2013 pipe_resource_reference(&surface
->base
.texture
, texture
);
2014 surface
->base
.context
= pipe
;
2015 surface
->base
.format
= templ
->format
;
2016 surface
->base
.width
= width
;
2017 surface
->base
.height
= height
;
2018 surface
->base
.u
= templ
->u
;
2020 surface
->width0
= width0
;
2021 surface
->height0
= height0
;
2023 surface
->dcc_incompatible
=
2024 texture
->target
!= PIPE_BUFFER
&&
2025 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2027 return &surface
->base
;
2030 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
2031 struct pipe_resource
*tex
,
2032 const struct pipe_surface
*templ
)
2034 unsigned level
= templ
->u
.tex
.level
;
2035 unsigned width
= u_minify(tex
->width0
, level
);
2036 unsigned height
= u_minify(tex
->height0
, level
);
2037 unsigned width0
= tex
->width0
;
2038 unsigned height0
= tex
->height0
;
2040 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2041 const struct util_format_description
*tex_desc
2042 = util_format_description(tex
->format
);
2043 const struct util_format_description
*templ_desc
2044 = util_format_description(templ
->format
);
2046 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2048 /* Adjust size of surface if and only if the block width or
2049 * height is changed. */
2050 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2051 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2052 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2053 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2055 width
= nblks_x
* templ_desc
->block
.width
;
2056 height
= nblks_y
* templ_desc
->block
.height
;
2058 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2059 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2063 return r600_create_surface_custom(pipe
, tex
, templ
,
2068 static void r600_surface_destroy(struct pipe_context
*pipe
,
2069 struct pipe_surface
*surface
)
2071 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
2072 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
2073 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
2074 pipe_resource_reference(&surface
->texture
, NULL
);
2078 static void r600_clear_texture(struct pipe_context
*pipe
,
2079 struct pipe_resource
*tex
,
2081 const struct pipe_box
*box
,
2084 struct pipe_screen
*screen
= pipe
->screen
;
2085 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
2086 struct pipe_surface tmpl
= {{0}};
2087 struct pipe_surface
*sf
;
2088 const struct util_format_description
*desc
=
2089 util_format_description(tex
->format
);
2091 tmpl
.format
= tex
->format
;
2092 tmpl
.u
.tex
.first_layer
= box
->z
;
2093 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
2094 tmpl
.u
.tex
.level
= level
;
2095 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
2099 if (rtex
->is_depth
) {
2102 uint8_t stencil
= 0;
2104 /* Depth is always present. */
2105 clear
= PIPE_CLEAR_DEPTH
;
2106 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
2108 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2109 clear
|= PIPE_CLEAR_STENCIL
;
2110 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
2113 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
2115 box
->width
, box
->height
, false);
2117 union pipe_color_union color
;
2119 /* pipe_color_union requires the full vec4 representation. */
2120 if (util_format_is_pure_uint(tex
->format
))
2121 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2122 else if (util_format_is_pure_sint(tex
->format
))
2123 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2125 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2127 if (screen
->is_format_supported(screen
, tex
->format
,
2129 PIPE_BIND_RENDER_TARGET
)) {
2130 pipe
->clear_render_target(pipe
, sf
, &color
,
2132 box
->width
, box
->height
, false);
2134 /* Software fallback - just for R9G9B9E5_FLOAT */
2135 util_clear_render_target(pipe
, sf
, &color
,
2137 box
->width
, box
->height
);
2140 pipe_surface_reference(&sf
, NULL
);
2143 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2145 const struct util_format_description
*desc
= util_format_description(format
);
2147 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2149 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2150 return V_0280A0_SWAP_STD
;
2152 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2155 switch (desc
->nr_channels
) {
2157 if (HAS_SWIZZLE(0,X
))
2158 return V_0280A0_SWAP_STD
; /* X___ */
2159 else if (HAS_SWIZZLE(3,X
))
2160 return V_0280A0_SWAP_ALT_REV
; /* ___X */
2163 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2164 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2165 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2166 return V_0280A0_SWAP_STD
; /* XY__ */
2167 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2168 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2169 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2171 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
2172 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2173 return V_0280A0_SWAP_ALT
; /* X__Y */
2174 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2175 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2178 if (HAS_SWIZZLE(0,X
))
2179 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2180 else if (HAS_SWIZZLE(0,Z
))
2181 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2184 /* check the middle channels, the 1st and 4th channel can be NONE */
2185 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2186 return V_0280A0_SWAP_STD
; /* XYZW */
2187 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2188 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2189 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2190 return V_0280A0_SWAP_ALT
; /* ZYXW */
2191 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2194 return V_0280A0_SWAP_ALT_REV
;
2196 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2203 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2205 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2210 if (rctx
->dcc_stats
[slot
].query_active
)
2211 vi_separate_dcc_stop_query(&rctx
->b
,
2212 rctx
->dcc_stats
[slot
].tex
);
2214 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2215 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2216 rctx
->b
.destroy_query(&rctx
->b
,
2217 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2218 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2221 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2225 * Return the per-context slot where DCC statistics queries for the texture live.
2227 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2228 struct r600_texture
*tex
)
2230 int i
, empty_slot
= -1;
2232 /* Remove zombie textures (textures kept alive by this array only). */
2233 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2234 if (rctx
->dcc_stats
[i
].tex
&&
2235 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2236 vi_dcc_clean_up_context_slot(rctx
, i
);
2238 /* Find the texture. */
2239 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2240 /* Return if found. */
2241 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2242 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2246 /* Record the first seen empty slot. */
2247 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2251 /* Not found. Remove the oldest member to make space in the array. */
2252 if (empty_slot
== -1) {
2253 int oldest_slot
= 0;
2255 /* Find the oldest slot. */
2256 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2257 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2258 rctx
->dcc_stats
[i
].last_use_timestamp
)
2261 /* Clean up the oldest slot. */
2262 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2263 empty_slot
= oldest_slot
;
2266 /* Add the texture to the new slot. */
2267 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2268 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2272 static struct pipe_query
*
2273 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2275 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2276 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2278 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2279 return (struct pipe_query
*)query
;
2283 * Called when binding a color buffer.
2285 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2286 struct r600_texture
*tex
)
2288 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2289 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2291 assert(!rctx
->dcc_stats
[i
].query_active
);
2293 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2294 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2296 /* begin or resume the query */
2297 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2298 rctx
->dcc_stats
[i
].query_active
= true;
2302 * Called when unbinding a color buffer.
2304 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2305 struct r600_texture
*tex
)
2307 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2308 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2310 assert(rctx
->dcc_stats
[i
].query_active
);
2311 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2313 /* pause or end the query */
2314 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2315 rctx
->dcc_stats
[i
].query_active
= false;
2318 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2320 /* The minimum number of fullscreen draws per frame that is required
2322 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2325 /* Called by fast clear. */
2326 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2327 struct r600_texture
*tex
)
2329 /* The intent is to use this with shared displayable back buffers,
2330 * but it's not strictly limited only to them.
2332 if (!tex
->resource
.b
.is_shared
||
2333 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2334 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2335 tex
->resource
.b
.b
.last_level
> 0 ||
2336 !tex
->surface
.dcc_size
)
2339 if (tex
->dcc_offset
)
2340 return; /* already enabled */
2342 /* Enable the DCC stat gathering. */
2343 if (!tex
->dcc_gather_statistics
) {
2344 tex
->dcc_gather_statistics
= true;
2345 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2348 if (!vi_should_enable_separate_dcc(tex
))
2349 return; /* stats show that DCC decompression is too expensive */
2351 assert(tex
->surface
.num_dcc_levels
);
2352 assert(!tex
->dcc_separate_buffer
);
2354 r600_texture_discard_cmask(rctx
->screen
, tex
);
2356 /* Get a DCC buffer. */
2357 if (tex
->last_dcc_separate_buffer
) {
2358 assert(tex
->dcc_gather_statistics
);
2359 assert(!tex
->dcc_separate_buffer
);
2360 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2361 tex
->last_dcc_separate_buffer
= NULL
;
2363 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2364 r600_aligned_buffer_create(rctx
->b
.screen
,
2365 R600_RESOURCE_FLAG_UNMAPPABLE
,
2367 tex
->surface
.dcc_size
,
2368 tex
->surface
.dcc_alignment
);
2369 if (!tex
->dcc_separate_buffer
)
2373 /* dcc_offset is the absolute GPUVM address. */
2374 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2376 /* no need to flag anything since this is called by fast clear that
2377 * flags framebuffer state
2382 * Called by pipe_context::flush_resource, the place where DCC decompression
2385 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2386 struct r600_texture
*tex
)
2388 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2389 struct pipe_query
*tmp
;
2390 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2391 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2392 bool disable
= false;
2394 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2395 union pipe_query_result result
;
2397 /* Read the results. */
2398 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2400 r600_query_hw_reset_buffers(rctx
,
2401 (struct r600_query_hw
*)
2402 rctx
->dcc_stats
[i
].ps_stats
[2]);
2404 /* Compute the approximate number of fullscreen draws. */
2405 tex
->ps_draw_ratio
=
2406 result
.pipeline_statistics
.ps_invocations
/
2407 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2408 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2410 disable
= tex
->dcc_separate_buffer
&&
2411 !vi_should_enable_separate_dcc(tex
);
2414 tex
->num_slow_clears
= 0;
2416 /* stop the statistics query for ps_stats[0] */
2418 vi_separate_dcc_stop_query(ctx
, tex
);
2420 /* Move the queries in the queue by one. */
2421 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2422 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2423 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2424 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2426 /* create and start a new query as ps_stats[0] */
2428 vi_separate_dcc_start_query(ctx
, tex
);
2431 assert(!tex
->last_dcc_separate_buffer
);
2432 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2433 tex
->dcc_separate_buffer
= NULL
;
2434 tex
->dcc_offset
= 0;
2435 /* no need to flag anything since this is called after
2436 * decompression that re-sets framebuffer state
2441 /* FAST COLOR CLEAR */
2443 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2444 enum pipe_format surface_format
,
2445 const union pipe_color_union
*color
)
2447 union util_color uc
;
2449 memset(&uc
, 0, sizeof(uc
));
2451 if (rtex
->surface
.bpe
== 16) {
2452 /* DCC fast clear only:
2453 * CLEAR_WORD0 = R = G = B
2456 assert(color
->ui
[0] == color
->ui
[1] &&
2457 color
->ui
[0] == color
->ui
[2]);
2458 uc
.ui
[0] = color
->ui
[0];
2459 uc
.ui
[1] = color
->ui
[3];
2460 } else if (util_format_is_pure_uint(surface_format
)) {
2461 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2462 } else if (util_format_is_pure_sint(surface_format
)) {
2463 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2465 util_pack_color(color
->f
, surface_format
, &uc
);
2468 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2471 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2472 const union pipe_color_union
*color
,
2473 uint32_t* reset_value
,
2474 bool* clear_words_needed
)
2476 bool values
[4] = {};
2478 bool main_value
= false;
2479 bool extra_value
= false;
2482 /* This is needed to get the correct DCC clear value for luminance formats.
2483 * 1) Get the linear format (because the next step can't handle L8_SRGB).
2484 * 2) Convert luminance to red. (the real hw format for luminance)
2486 surface_format
= util_format_linear(surface_format
);
2487 surface_format
= util_format_luminance_to_red(surface_format
);
2489 const struct util_format_description
*desc
= util_format_description(surface_format
);
2491 if (desc
->block
.bits
== 128 &&
2492 (color
->ui
[0] != color
->ui
[1] ||
2493 color
->ui
[0] != color
->ui
[2]))
2496 *clear_words_needed
= true;
2497 *reset_value
= 0x20202020U
;
2499 /* If we want to clear without needing a fast clear eliminate step, we
2500 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2501 * have two sets of flags, one for the last or first channel(extra) and
2502 * one for the other channels(main).
2505 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2506 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2507 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
||
2508 util_format_is_alpha(surface_format
)) {
2510 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2511 if(r600_translate_colorswap(surface_format
, false) <= 1)
2512 extra_channel
= desc
->nr_channels
- 1;
2518 for (i
= 0; i
< 4; ++i
) {
2519 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2521 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2522 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2525 if (desc
->channel
[i
].pure_integer
&&
2526 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2527 /* Use the maximum value for clamping the clear color. */
2528 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2530 values
[i
] = color
->i
[i
] != 0;
2531 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2533 } else if (desc
->channel
[i
].pure_integer
&&
2534 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2535 /* Use the maximum value for clamping the clear color. */
2536 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2538 values
[i
] = color
->ui
[i
] != 0U;
2539 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2542 values
[i
] = color
->f
[i
] != 0.0F
;
2543 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2547 if (index
== extra_channel
)
2548 extra_value
= values
[i
];
2550 main_value
= values
[i
];
2553 for (int i
= 0; i
< 4; ++i
)
2554 if (values
[i
] != main_value
&&
2555 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2556 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2557 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2560 *clear_words_needed
= false;
2562 *reset_value
|= 0x80808080U
;
2565 *reset_value
|= 0x40404040U
;
2569 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2570 struct r600_texture
*rtex
,
2571 unsigned level
, unsigned clear_value
)
2573 struct pipe_resource
*dcc_buffer
;
2574 uint64_t dcc_offset
, clear_size
;
2576 assert(vi_dcc_enabled(rtex
, level
));
2578 if (rtex
->dcc_separate_buffer
) {
2579 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2582 dcc_buffer
= &rtex
->resource
.b
.b
;
2583 dcc_offset
= rtex
->dcc_offset
;
2586 if (rctx
->chip_class
>= GFX9
) {
2587 /* Mipmap level clears aren't implemented. */
2588 assert(rtex
->resource
.b
.b
.last_level
== 0);
2589 /* MSAA needs a different clear size. */
2590 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2591 clear_size
= rtex
->surface
.dcc_size
;
2593 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2594 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2597 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2598 clear_value
, R600_COHERENCY_CB_META
);
2601 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2602 * This allows hitting the MSAA resolve fast path, which requires that both
2603 * src and dst micro tile modes match.
2605 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2606 struct r600_texture
*rtex
)
2608 if (rtex
->resource
.b
.is_shared
||
2609 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2610 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2613 assert(rscreen
->chip_class
>= GFX9
||
2614 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2615 assert(rtex
->resource
.b
.b
.last_level
== 0);
2617 if (rscreen
->chip_class
>= GFX9
) {
2618 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2619 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2621 /* If you do swizzle_mode % 4, you'll get:
2627 * Depth-sample order isn't allowed:
2629 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2631 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2632 case RADEON_MICRO_MODE_DISPLAY
:
2633 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2634 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2636 case RADEON_MICRO_MODE_THIN
:
2637 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2638 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2640 case RADEON_MICRO_MODE_ROTATED
:
2641 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2642 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2644 default: /* depth */
2645 assert(!"unexpected micro mode");
2648 } else if (rscreen
->chip_class
>= CIK
) {
2649 /* These magic numbers were copied from addrlib. It doesn't use
2650 * any definitions for them either. They are all 2D_TILED_THIN1
2651 * modes with different bpp and micro tile mode.
2653 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2654 case RADEON_MICRO_MODE_DISPLAY
:
2655 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2657 case RADEON_MICRO_MODE_THIN
:
2658 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2660 case RADEON_MICRO_MODE_ROTATED
:
2661 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2663 default: /* depth, thick */
2664 assert(!"unexpected micro mode");
2668 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2669 case RADEON_MICRO_MODE_DISPLAY
:
2670 switch (rtex
->surface
.bpe
) {
2672 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2675 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2678 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2682 case RADEON_MICRO_MODE_THIN
:
2683 switch (rtex
->surface
.bpe
) {
2685 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2688 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2691 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2693 default: /* 8, 16 */
2694 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2698 default: /* depth, thick */
2699 assert(!"unexpected micro mode");
2704 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2706 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2709 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2710 struct pipe_framebuffer_state
*fb
,
2711 struct r600_atom
*fb_state
,
2712 unsigned *buffers
, ubyte
*dirty_cbufs
,
2713 const union pipe_color_union
*color
)
2717 /* This function is broken in BE, so just disable this path for now */
2718 #ifdef PIPE_ARCH_BIG_ENDIAN
2722 if (rctx
->render_cond
)
2725 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2726 struct r600_texture
*tex
;
2727 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2732 /* if this colorbuffer is not being cleared */
2733 if (!(*buffers
& clear_bit
))
2736 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2738 /* the clear is allowed if all layers are bound */
2739 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2740 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2744 /* cannot clear mipmapped textures */
2745 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2749 /* only supported on tiled surfaces */
2750 if (tex
->surface
.is_linear
) {
2754 /* shared textures can't use fast clear without an explicit flush,
2755 * because there is no way to communicate the clear color among
2758 if (tex
->resource
.b
.is_shared
&&
2759 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2762 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2763 if (rctx
->chip_class
== CIK
&&
2764 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2765 rctx
->screen
->info
.drm_major
== 2 &&
2766 rctx
->screen
->info
.drm_minor
< 38) {
2770 /* Fast clear is the most appropriate place to enable DCC for
2771 * displayable surfaces.
2773 if (rctx
->chip_class
>= VI
&&
2774 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2775 vi_separate_dcc_try_enable(rctx
, tex
);
2777 /* RB+ isn't supported with a CMASK clear only on Stoney,
2778 * so all clears are considered to be hypothetically slow
2779 * clears, which is weighed when determining whether to
2780 * enable separate DCC.
2782 if (tex
->dcc_gather_statistics
&&
2783 rctx
->family
== CHIP_STONEY
)
2784 tex
->num_slow_clears
++;
2787 /* Try to clear DCC first, otherwise try CMASK. */
2788 if (vi_dcc_enabled(tex
, 0)) {
2789 uint32_t reset_value
;
2790 bool clear_words_needed
;
2792 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2795 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2796 color
, &reset_value
,
2797 &clear_words_needed
))
2800 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2802 unsigned level_bit
= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2803 if (clear_words_needed
) {
2804 bool need_compressed_update
= !tex
->dirty_level_mask
;
2806 tex
->dirty_level_mask
|= level_bit
;
2808 if (need_compressed_update
)
2809 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2811 tex
->separate_dcc_dirty
= true;
2813 /* 128-bit formats are unusupported */
2814 if (tex
->surface
.bpe
> 8) {
2818 /* RB+ doesn't work with CMASK fast clear on Stoney. */
2819 if (rctx
->family
== CHIP_STONEY
)
2822 /* ensure CMASK is enabled */
2823 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2824 if (tex
->cmask
.size
== 0) {
2828 /* Do the fast clear. */
2829 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2830 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2831 R600_COHERENCY_CB_META
);
2833 bool need_compressed_update
= !tex
->dirty_level_mask
;
2835 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2837 if (need_compressed_update
)
2838 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2841 /* We can change the micro tile mode before a full clear. */
2842 if (rctx
->screen
->chip_class
>= SI
)
2843 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2845 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2848 *dirty_cbufs
|= 1 << i
;
2849 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2850 *buffers
&= ~clear_bit
;
2854 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2856 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2857 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2860 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2862 rctx
->b
.create_surface
= r600_create_surface
;
2863 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2864 rctx
->b
.clear_texture
= r600_clear_texture
;