projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium/radeon: lower memory usage during texture transfers
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 static void r600_texture_discard_dcc(struct r600_common_screen *rscreen,
36 struct r600_texture *rtex);
37 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
38 struct r600_texture *rtex);
39 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
40 const struct pipe_resource *templ);
41
42
43 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
44 struct r600_texture *rdst,
45 unsigned dst_level, unsigned dstx,
46 unsigned dsty, unsigned dstz,
47 struct r600_texture *rsrc,
48 unsigned src_level,
49 const struct pipe_box *src_box)
50 {
51 if (!rctx->dma.cs)
52 return false;
53
54 if (util_format_get_blocksizebits(rdst->resource.b.b.format) !=
55 util_format_get_blocksizebits(rsrc->resource.b.b.format))
56 return false;
57
58 /* MSAA: Blits don't exist in the real world. */
59 if (rsrc->resource.b.b.nr_samples > 1 ||
60 rdst->resource.b.b.nr_samples > 1)
61 return false;
62
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
66 */
67 if (rsrc->is_depth || rdst->is_depth)
68 return false;
69
70 /* DCC as:
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: If overwriting the whole texture, discard DCC and use SDMA.
73 * Otherwise, use the 3D path.
74 */
75 if (rsrc->dcc_offset)
76 return false;
77
78 if (rdst->dcc_offset) {
79 /* We can't discard DCC if the texture has been exported.
80 * We can only discard DCC for the entire texture.
81 */
82 if (rdst->resource.is_shared ||
83 rdst->resource.b.b.last_level > 0 ||
84 !util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
85 dstx, dsty, dstz, src_box->width,
86 src_box->height, src_box->depth))
87 return false;
88
89 r600_texture_discard_dcc(rctx->screen, rdst);
90 }
91
92 /* CMASK as:
93 * src: Both texture and SDMA paths need decompression. Use SDMA.
94 * dst: If overwriting the whole texture, discard CMASK and use
95 * SDMA. Otherwise, use the 3D path.
96 */
97 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
98 /* The CMASK clear is only enabled for the first level. */
99 assert(dst_level == 0);
100 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
101 dstx, dsty, dstz, src_box->width,
102 src_box->height, src_box->depth))
103 return false;
104
105 r600_texture_discard_cmask(rctx->screen, rdst);
106 }
107
108 /* All requirements are met. Prepare textures for SDMA. */
109 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
110 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
111
112 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
113 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
114
115 return true;
116 }
117
118 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
119 static void r600_copy_region_with_blit(struct pipe_context *pipe,
120 struct pipe_resource *dst,
121 unsigned dst_level,
122 unsigned dstx, unsigned dsty, unsigned dstz,
123 struct pipe_resource *src,
124 unsigned src_level,
125 const struct pipe_box *src_box)
126 {
127 struct pipe_blit_info blit;
128
129 memset(&blit, 0, sizeof(blit));
130 blit.src.resource = src;
131 blit.src.format = src->format;
132 blit.src.level = src_level;
133 blit.src.box = *src_box;
134 blit.dst.resource = dst;
135 blit.dst.format = dst->format;
136 blit.dst.level = dst_level;
137 blit.dst.box.x = dstx;
138 blit.dst.box.y = dsty;
139 blit.dst.box.z = dstz;
140 blit.dst.box.width = src_box->width;
141 blit.dst.box.height = src_box->height;
142 blit.dst.box.depth = src_box->depth;
143 blit.mask = util_format_get_mask(src->format) &
144 util_format_get_mask(dst->format);
145 blit.filter = PIPE_TEX_FILTER_NEAREST;
146
147 if (blit.mask) {
148 pipe->blit(pipe, &blit);
149 }
150 }
151
152 /* Copy from a full GPU texture to a transfer's staging one. */
153 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
154 {
155 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
156 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
157 struct pipe_resource *dst = &rtransfer->staging->b.b;
158 struct pipe_resource *src = transfer->resource;
159
160 if (src->nr_samples > 1) {
161 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
162 src, transfer->level, &transfer->box);
163 return;
164 }
165
166 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
167 &transfer->box);
168 }
169
170 /* Copy from a transfer's staging texture to a full GPU one. */
171 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
172 {
173 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
174 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
175 struct pipe_resource *dst = transfer->resource;
176 struct pipe_resource *src = &rtransfer->staging->b.b;
177 struct pipe_box sbox;
178
179 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
180
181 if (dst->nr_samples > 1) {
182 r600_copy_region_with_blit(ctx, dst, transfer->level,
183 transfer->box.x, transfer->box.y, transfer->box.z,
184 src, 0, &sbox);
185 return;
186 }
187
188 rctx->dma_copy(ctx, dst, transfer->level,
189 transfer->box.x, transfer->box.y, transfer->box.z,
190 src, 0, &sbox);
191 }
192
193 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
194 const struct pipe_box *box)
195 {
196 enum pipe_format format = rtex->resource.b.b.format;
197
198 return rtex->surface.level[level].offset +
199 box->z * rtex->surface.level[level].slice_size +
200 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
201 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
202 }
203
204 static int r600_init_surface(struct r600_common_screen *rscreen,
205 struct radeon_surf *surface,
206 const struct pipe_resource *ptex,
207 unsigned array_mode,
208 bool is_flushed_depth)
209 {
210 const struct util_format_description *desc =
211 util_format_description(ptex->format);
212 bool is_depth, is_stencil;
213
214 is_depth = util_format_has_depth(desc);
215 is_stencil = util_format_has_stencil(desc);
216
217 surface->npix_x = ptex->width0;
218 surface->npix_y = ptex->height0;
219 surface->npix_z = ptex->depth0;
220 surface->blk_w = util_format_get_blockwidth(ptex->format);
221 surface->blk_h = util_format_get_blockheight(ptex->format);
222 surface->blk_d = 1;
223 surface->array_size = 1;
224 surface->last_level = ptex->last_level;
225
226 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
227 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
228 surface->bpe = 4; /* stencil is allocated separately on evergreen */
229 } else {
230 surface->bpe = util_format_get_blocksize(ptex->format);
231 /* align byte per element on dword */
232 if (surface->bpe == 3) {
233 surface->bpe = 4;
234 }
235 }
236
237 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
238 surface->flags = RADEON_SURF_SET(array_mode, MODE);
239
240 switch (ptex->target) {
241 case PIPE_TEXTURE_1D:
242 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
243 break;
244 case PIPE_TEXTURE_RECT:
245 case PIPE_TEXTURE_2D:
246 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
247 break;
248 case PIPE_TEXTURE_3D:
249 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
250 break;
251 case PIPE_TEXTURE_1D_ARRAY:
252 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
253 surface->array_size = ptex->array_size;
254 break;
255 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
256 assert(ptex->array_size % 6 == 0);
257 case PIPE_TEXTURE_2D_ARRAY:
258 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
259 surface->array_size = ptex->array_size;
260 break;
261 case PIPE_TEXTURE_CUBE:
262 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
263 break;
264 case PIPE_BUFFER:
265 default:
266 return -EINVAL;
267 }
268 if (ptex->bind & PIPE_BIND_SCANOUT) {
269 surface->flags |= RADEON_SURF_SCANOUT;
270 }
271
272 if (!is_flushed_depth && is_depth) {
273 surface->flags |= RADEON_SURF_ZBUFFER;
274
275 if (is_stencil) {
276 surface->flags |= RADEON_SURF_SBUFFER |
277 RADEON_SURF_HAS_SBUFFER_MIPTREE;
278 }
279 }
280 if (rscreen->chip_class >= SI) {
281 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
282 }
283 return 0;
284 }
285
286 static int r600_setup_surface(struct pipe_screen *screen,
287 struct r600_texture *rtex,
288 unsigned pitch_in_bytes_override,
289 unsigned offset)
290 {
291 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
292 unsigned i;
293 int r;
294
295 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
296 if (r) {
297 return r;
298 }
299
300 rtex->size = rtex->surface.bo_size;
301
302 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
303 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
304 * for those
305 */
306 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
307 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
308 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
309 }
310
311 if (offset) {
312 for (i = 0; i < ARRAY_SIZE(rtex->surface.level); ++i)
313 rtex->surface.level[i].offset += offset;
314 }
315 return 0;
316 }
317
318 static void r600_texture_init_metadata(struct r600_texture *rtex,
319 struct radeon_bo_metadata *metadata)
320 {
321 struct radeon_surf *surface = &rtex->surface;
322
323 memset(metadata, 0, sizeof(*metadata));
324 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
325 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
326 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
327 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
328 metadata->pipe_config = surface->pipe_config;
329 metadata->bankw = surface->bankw;
330 metadata->bankh = surface->bankh;
331 metadata->tile_split = surface->tile_split;
332 metadata->mtilea = surface->mtilea;
333 metadata->num_banks = surface->num_banks;
334 metadata->stride = surface->level[0].pitch_bytes;
335 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
336 }
337
338 static void r600_dirty_all_framebuffer_states(struct r600_common_screen *rscreen)
339 {
340 p_atomic_inc(&rscreen->dirty_fb_counter);
341 }
342
343 static void r600_eliminate_fast_color_clear(struct r600_common_screen *rscreen,
344 struct r600_texture *rtex)
345 {
346 struct pipe_context *ctx = rscreen->aux_context;
347
348 pipe_mutex_lock(rscreen->aux_context_lock);
349 ctx->flush_resource(ctx, &rtex->resource.b.b);
350 ctx->flush(ctx, NULL, 0);
351 pipe_mutex_unlock(rscreen->aux_context_lock);
352 }
353
354 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
355 struct r600_texture *rtex)
356 {
357 if (!rtex->cmask.size)
358 return;
359
360 assert(rtex->resource.b.b.nr_samples <= 1);
361
362 /* Disable CMASK. */
363 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
364 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
365
366 if (rscreen->chip_class >= SI)
367 rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1);
368 else
369 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
370
371 if (rtex->cmask_buffer != &rtex->resource)
372 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
373
374 /* Notify all contexts about the change. */
375 r600_dirty_all_framebuffer_states(rscreen);
376 p_atomic_inc(&rscreen->compressed_colortex_counter);
377 }
378
379 static void r600_texture_discard_dcc(struct r600_common_screen *rscreen,
380 struct r600_texture *rtex)
381 {
382 /* Disable DCC. */
383 rtex->dcc_offset = 0;
384 rtex->cb_color_info &= ~VI_S_028C70_DCC_ENABLE(1);
385
386 /* Notify all contexts about the change. */
387 r600_dirty_all_framebuffer_states(rscreen);
388 }
389
390 void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
391 struct r600_texture *rtex)
392 {
393 struct r600_common_context *rctx =
394 (struct r600_common_context *)rscreen->aux_context;
395
396 if (!rtex->dcc_offset)
397 return;
398
399 /* Decompress DCC. */
400 pipe_mutex_lock(rscreen->aux_context_lock);
401 rctx->decompress_dcc(&rctx->b, rtex);
402 rctx->b.flush(&rctx->b, NULL, 0);
403 pipe_mutex_unlock(rscreen->aux_context_lock);
404
405 r600_texture_discard_dcc(rscreen, rtex);
406 }
407
408 static void r600_degrade_tile_mode_to_linear(struct r600_common_context *rctx,
409 struct r600_texture *rtex,
410 bool invalidate_storage)
411 {
412 struct pipe_screen *screen = rctx->b.screen;
413 struct r600_texture *new_tex;
414 struct pipe_resource templ = rtex->resource.b.b;
415 unsigned i;
416
417 templ.bind |= PIPE_BIND_LINEAR;
418
419 /* r600g doesn't react to dirty_tex_descriptor_counter */
420 if (rctx->chip_class < SI)
421 return;
422
423 if (rtex->resource.is_shared ||
424 rtex->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
425 return;
426
427 /* This fails with MSAA, depth, and compressed textures. */
428 if (r600_choose_tiling(rctx->screen, &templ) !=
429 RADEON_SURF_MODE_LINEAR_ALIGNED)
430 return;
431
432 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
433 if (!new_tex)
434 return;
435
436 /* Copy the pixels to the new texture. */
437 if (!invalidate_storage) {
438 for (i = 0; i <= templ.last_level; i++) {
439 struct pipe_box box;
440
441 u_box_3d(0, 0, 0,
442 u_minify(templ.width0, i), u_minify(templ.height0, i),
443 util_max_layer(&templ, i) + 1, &box);
444
445 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
446 &rtex->resource.b.b, i, &box);
447 }
448 }
449
450 r600_texture_discard_cmask(rctx->screen, rtex);
451 r600_texture_discard_dcc(rctx->screen, rtex);
452
453 /* Replace the structure fields of rtex. */
454 rtex->resource.b.b.bind = templ.bind;
455 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
456 rtex->resource.gpu_address = new_tex->resource.gpu_address;
457 rtex->resource.domains = new_tex->resource.domains;
458 rtex->size = new_tex->size;
459 rtex->surface = new_tex->surface;
460 rtex->non_disp_tiling = new_tex->non_disp_tiling;
461 rtex->cb_color_info = new_tex->cb_color_info;
462 rtex->cmask = new_tex->cmask; /* needed even without CMASK */
463
464 assert(!rtex->htile_buffer);
465 assert(!rtex->cmask.size);
466 assert(!rtex->fmask.size);
467 assert(!rtex->dcc_offset);
468 assert(!rtex->is_depth);
469
470 pipe_resource_reference((struct pipe_resource**)&new_tex, NULL);
471
472 r600_dirty_all_framebuffer_states(rctx->screen);
473 p_atomic_inc(&rctx->screen->dirty_tex_descriptor_counter);
474 }
475
476 static boolean r600_texture_get_handle(struct pipe_screen* screen,
477 struct pipe_resource *resource,
478 struct winsys_handle *whandle,
479 unsigned usage)
480 {
481 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
482 struct r600_resource *res = (struct r600_resource*)resource;
483 struct r600_texture *rtex = (struct r600_texture*)resource;
484 struct radeon_bo_metadata metadata;
485 bool update_metadata = false;
486
487 /* This is not supported now, but it might be required for OpenCL
488 * interop in the future.
489 */
490 if (resource->target != PIPE_BUFFER &&
491 (resource->nr_samples > 1 || rtex->is_depth))
492 return false;
493
494 if (resource->target != PIPE_BUFFER) {
495 /* Since shader image stores don't support DCC on VI,
496 * disable it for external clients that want write
497 * access.
498 */
499 if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
500 r600_texture_disable_dcc(rscreen, rtex);
501 update_metadata = true;
502 }
503
504 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
505 rtex->cmask.size) {
506 /* Eliminate fast clear (both CMASK and DCC) */
507 r600_eliminate_fast_color_clear(rscreen, rtex);
508
509 /* Disable CMASK if flush_resource isn't going
510 * to be called.
511 */
512 r600_texture_discard_cmask(rscreen, rtex);
513 update_metadata = true;
514 }
515
516 /* Set metadata. */
517 if (!res->is_shared || update_metadata) {
518 r600_texture_init_metadata(rtex, &metadata);
519 if (rscreen->query_opaque_metadata)
520 rscreen->query_opaque_metadata(rscreen, rtex,
521 &metadata);
522
523 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
524 }
525 }
526
527 if (res->is_shared) {
528 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
529 * doesn't set it.
530 */
531 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
532 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
533 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
534 } else {
535 res->is_shared = true;
536 res->external_usage = usage;
537 }
538
539 return rscreen->ws->buffer_get_handle(res->buf,
540 rtex->surface.level[0].pitch_bytes,
541 rtex->surface.level[0].offset,
542 rtex->surface.level[0].slice_size,
543 whandle);
544 }
545
546 static void r600_texture_destroy(struct pipe_screen *screen,
547 struct pipe_resource *ptex)
548 {
549 struct r600_texture *rtex = (struct r600_texture*)ptex;
550 struct r600_resource *resource = &rtex->resource;
551
552 if (rtex->flushed_depth_texture)
553 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
554
555 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
556 if (rtex->cmask_buffer != &rtex->resource) {
557 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
558 }
559 pb_reference(&resource->buf, NULL);
560 FREE(rtex);
561 }
562
563 static const struct u_resource_vtbl r600_texture_vtbl;
564
565 /* The number of samples can be specified independently of the texture. */
566 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
567 struct r600_texture *rtex,
568 unsigned nr_samples,
569 struct r600_fmask_info *out)
570 {
571 /* FMASK is allocated like an ordinary texture. */
572 struct radeon_surf fmask = rtex->surface;
573
574 memset(out, 0, sizeof(*out));
575
576 fmask.bo_alignment = 0;
577 fmask.bo_size = 0;
578 fmask.nsamples = 1;
579 fmask.flags |= RADEON_SURF_FMASK;
580
581 /* Force 2D tiling if it wasn't set. This may occur when creating
582 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
583 * destination buffer must have an FMASK too. */
584 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
585 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
586
587 if (rscreen->chip_class >= SI) {
588 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
589 }
590
591 switch (nr_samples) {
592 case 2:
593 case 4:
594 fmask.bpe = 1;
595 if (rscreen->chip_class <= CAYMAN) {
596 fmask.bankh = 4;
597 }
598 break;
599 case 8:
600 fmask.bpe = 4;
601 break;
602 default:
603 R600_ERR("Invalid sample count for FMASK allocation.\n");
604 return;
605 }
606
607 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
608 * This can be fixed by writing a separate FMASK allocator specifically
609 * for R600-R700 asics. */
610 if (rscreen->chip_class <= R700) {
611 fmask.bpe *= 2;
612 }
613
614 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
615 R600_ERR("Got error in surface_init while allocating FMASK.\n");
616 return;
617 }
618
619 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
620
621 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
622 if (out->slice_tile_max)
623 out->slice_tile_max -= 1;
624
625 out->tile_mode_index = fmask.tiling_index[0];
626 out->pitch_in_pixels = fmask.level[0].nblk_x;
627 out->bank_height = fmask.bankh;
628 out->alignment = MAX2(256, fmask.bo_alignment);
629 out->size = fmask.bo_size;
630 }
631
632 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
633 struct r600_texture *rtex)
634 {
635 r600_texture_get_fmask_info(rscreen, rtex,
636 rtex->resource.b.b.nr_samples, &rtex->fmask);
637
638 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
639 rtex->size = rtex->fmask.offset + rtex->fmask.size;
640 }
641
642 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
643 struct r600_texture *rtex,
644 struct r600_cmask_info *out)
645 {
646 unsigned cmask_tile_width = 8;
647 unsigned cmask_tile_height = 8;
648 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
649 unsigned element_bits = 4;
650 unsigned cmask_cache_bits = 1024;
651 unsigned num_pipes = rscreen->info.num_tile_pipes;
652 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
653
654 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
655 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
656 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
657 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
658 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
659
660 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
661 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
662
663 unsigned base_align = num_pipes * pipe_interleave_bytes;
664 unsigned slice_bytes =
665 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
666
667 assert(macro_tile_width % 128 == 0);
668 assert(macro_tile_height % 128 == 0);
669
670 out->pitch = pitch_elements;
671 out->height = height;
672 out->xalign = macro_tile_width;
673 out->yalign = macro_tile_height;
674 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
675 out->alignment = MAX2(256, base_align);
676 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
677 align(slice_bytes, base_align);
678 }
679
680 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
681 struct r600_texture *rtex,
682 struct r600_cmask_info *out)
683 {
684 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
685 unsigned num_pipes = rscreen->info.num_tile_pipes;
686 unsigned cl_width, cl_height;
687
688 switch (num_pipes) {
689 case 2:
690 cl_width = 32;
691 cl_height = 16;
692 break;
693 case 4:
694 cl_width = 32;
695 cl_height = 32;
696 break;
697 case 8:
698 cl_width = 64;
699 cl_height = 32;
700 break;
701 case 16: /* Hawaii */
702 cl_width = 64;
703 cl_height = 64;
704 break;
705 default:
706 assert(0);
707 return;
708 }
709
710 unsigned base_align = num_pipes * pipe_interleave_bytes;
711
712 unsigned width = align(rtex->surface.npix_x, cl_width*8);
713 unsigned height = align(rtex->surface.npix_y, cl_height*8);
714 unsigned slice_elements = (width * height) / (8*8);
715
716 /* Each element of CMASK is a nibble. */
717 unsigned slice_bytes = slice_elements / 2;
718
719 out->pitch = width;
720 out->height = height;
721 out->xalign = cl_width * 8;
722 out->yalign = cl_height * 8;
723 out->slice_tile_max = (width * height) / (128*128);
724 if (out->slice_tile_max)
725 out->slice_tile_max -= 1;
726
727 out->alignment = MAX2(256, base_align);
728 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
729 align(slice_bytes, base_align);
730 }
731
732 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
733 struct r600_texture *rtex)
734 {
735 if (rscreen->chip_class >= SI) {
736 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
737 } else {
738 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
739 }
740
741 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
742 rtex->size = rtex->cmask.offset + rtex->cmask.size;
743
744 if (rscreen->chip_class >= SI)
745 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
746 else
747 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
748 }
749
750 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
751 struct r600_texture *rtex)
752 {
753 if (rtex->cmask_buffer)
754 return;
755
756 assert(rtex->cmask.size == 0);
757
758 if (rscreen->chip_class >= SI) {
759 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
760 } else {
761 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
762 }
763
764 rtex->cmask_buffer = (struct r600_resource *)
765 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
766 PIPE_USAGE_DEFAULT, rtex->cmask.size);
767 if (rtex->cmask_buffer == NULL) {
768 rtex->cmask.size = 0;
769 return;
770 }
771
772 /* update colorbuffer state bits */
773 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
774
775 if (rscreen->chip_class >= SI)
776 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
777 else
778 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
779
780 p_atomic_inc(&rscreen->compressed_colortex_counter);
781 }
782
783 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
784 struct r600_texture *rtex)
785 {
786 unsigned cl_width, cl_height, width, height;
787 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
788 unsigned num_pipes = rscreen->info.num_tile_pipes;
789
790 if (rscreen->chip_class <= EVERGREEN &&
791 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
792 return 0;
793
794 /* HW bug on R6xx. */
795 if (rscreen->chip_class == R600 &&
796 (rtex->surface.level[0].npix_x > 7680 ||
797 rtex->surface.level[0].npix_y > 7680))
798 return 0;
799
800 /* HTILE is broken with 1D tiling on old kernels and CIK. */
801 if (rscreen->chip_class >= CIK &&
802 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
803 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
804 return 0;
805
806 /* Overalign HTILE on P2 configs to work around GPU hangs in
807 * piglit/depthstencil-render-miplevels 585.
808 *
809 * This has been confirmed to help Kabini & Stoney, where the hangs
810 * are always reproducible. I think I have seen the test hang
811 * on Carrizo too, though it was very rare there.
812 */
813 if (rscreen->chip_class >= CIK && num_pipes < 4)
814 num_pipes = 4;
815
816 switch (num_pipes) {
817 case 1:
818 cl_width = 32;
819 cl_height = 16;
820 break;
821 case 2:
822 cl_width = 32;
823 cl_height = 32;
824 break;
825 case 4:
826 cl_width = 64;
827 cl_height = 32;
828 break;
829 case 8:
830 cl_width = 64;
831 cl_height = 64;
832 break;
833 case 16:
834 cl_width = 128;
835 cl_height = 64;
836 break;
837 default:
838 assert(0);
839 return 0;
840 }
841
842 width = align(rtex->surface.npix_x, cl_width * 8);
843 height = align(rtex->surface.npix_y, cl_height * 8);
844
845 slice_elements = (width * height) / (8 * 8);
846 slice_bytes = slice_elements * 4;
847
848 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
849 base_align = num_pipes * pipe_interleave_bytes;
850
851 rtex->htile.pitch = width;
852 rtex->htile.height = height;
853 rtex->htile.xalign = cl_width * 8;
854 rtex->htile.yalign = cl_height * 8;
855
856 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
857 align(slice_bytes, base_align);
858 }
859
860 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
861 struct r600_texture *rtex)
862 {
863 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
864
865 if (!htile_size)
866 return;
867
868 rtex->htile_buffer = (struct r600_resource*)
869 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
870 PIPE_USAGE_DEFAULT, htile_size);
871 if (rtex->htile_buffer == NULL) {
872 /* this is not a fatal error as we can still keep rendering
873 * without htile buffer */
874 R600_ERR("Failed to create buffer object for htile buffer.\n");
875 } else {
876 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
877 htile_size, 0, R600_COHERENCY_NONE);
878 }
879 }
880
881 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
882 {
883 int i;
884
885 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
886 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
887 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
888 rtex->surface.npix_x, rtex->surface.npix_y,
889 rtex->surface.npix_z, rtex->surface.blk_w,
890 rtex->surface.blk_h, rtex->surface.blk_d,
891 rtex->surface.array_size, rtex->surface.last_level,
892 rtex->surface.bpe, rtex->surface.nsamples,
893 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
894
895 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
896 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
897 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
898 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
899 rtex->surface.tile_split, rtex->surface.pipe_config,
900 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
901
902 if (rtex->fmask.size)
903 fprintf(f, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
904 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
905 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
906 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
907 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
908
909 if (rtex->cmask.size)
910 fprintf(f, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch=%u, "
911 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
912 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
913 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
914 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
915
916 if (rtex->htile_buffer)
917 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
918 "xalign=%u, yalign=%u\n",
919 rtex->htile_buffer->b.b.width0,
920 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
921 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
922
923 if (rtex->dcc_offset) {
924 fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64", alignment=%"PRIu64"\n",
925 rtex->dcc_offset, rtex->surface.dcc_size,
926 rtex->surface.dcc_alignment);
927 for (i = 0; i <= rtex->surface.last_level; i++)
928 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
929 i, rtex->surface.level[i].dcc_offset);
930 }
931
932 for (i = 0; i <= rtex->surface.last_level; i++)
933 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
934 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
935 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
936 i, rtex->surface.level[i].offset,
937 rtex->surface.level[i].slice_size,
938 u_minify(rtex->resource.b.b.width0, i),
939 u_minify(rtex->resource.b.b.height0, i),
940 u_minify(rtex->resource.b.b.depth0, i),
941 rtex->surface.level[i].nblk_x,
942 rtex->surface.level[i].nblk_y,
943 rtex->surface.level[i].nblk_z,
944 rtex->surface.level[i].pitch_bytes,
945 rtex->surface.level[i].mode);
946
947 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
948 for (i = 0; i <= rtex->surface.last_level; i++) {
949 fprintf(f, " StencilLayout: tilesplit=%u\n",
950 rtex->surface.stencil_tile_split);
951 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
952 "slice_size=%"PRIu64", npix_x=%u, "
953 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
954 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
955 i, rtex->surface.stencil_level[i].offset,
956 rtex->surface.stencil_level[i].slice_size,
957 u_minify(rtex->resource.b.b.width0, i),
958 u_minify(rtex->resource.b.b.height0, i),
959 u_minify(rtex->resource.b.b.depth0, i),
960 rtex->surface.stencil_level[i].nblk_x,
961 rtex->surface.stencil_level[i].nblk_y,
962 rtex->surface.stencil_level[i].nblk_z,
963 rtex->surface.stencil_level[i].pitch_bytes,
964 rtex->surface.stencil_level[i].mode);
965 }
966 }
967 }
968
969 /* Common processing for r600_texture_create and r600_texture_from_handle */
970 static struct r600_texture *
971 r600_texture_create_object(struct pipe_screen *screen,
972 const struct pipe_resource *base,
973 unsigned pitch_in_bytes_override,
974 unsigned offset,
975 struct pb_buffer *buf,
976 struct radeon_surf *surface)
977 {
978 struct r600_texture *rtex;
979 struct r600_resource *resource;
980 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
981
982 rtex = CALLOC_STRUCT(r600_texture);
983 if (!rtex)
984 return NULL;
985
986 resource = &rtex->resource;
987 resource->b.b = *base;
988 resource->b.vtbl = &r600_texture_vtbl;
989 pipe_reference_init(&resource->b.b.reference, 1);
990 resource->b.b.screen = screen;
991
992 /* don't include stencil-only formats which we don't support for rendering */
993 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
994
995 rtex->surface = *surface;
996 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override, offset)) {
997 FREE(rtex);
998 return NULL;
999 }
1000
1001 /* Tiled depth textures utilize the non-displayable tile order.
1002 * This must be done after r600_setup_surface.
1003 * Applies to R600-Cayman. */
1004 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
1005
1006 if (rtex->is_depth) {
1007 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
1008 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
1009 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
1010
1011 r600_texture_allocate_htile(rscreen, rtex);
1012 }
1013 } else {
1014 if (base->nr_samples > 1) {
1015 if (!buf) {
1016 r600_texture_allocate_fmask(rscreen, rtex);
1017 r600_texture_allocate_cmask(rscreen, rtex);
1018 rtex->cmask_buffer = &rtex->resource;
1019 }
1020 if (!rtex->fmask.size || !rtex->cmask.size) {
1021 FREE(rtex);
1022 return NULL;
1023 }
1024 }
1025
1026 if (!buf && rtex->surface.dcc_size &&
1027 !(rscreen->debug_flags & DBG_NO_DCC)) {
1028 /* Reserve space for the DCC buffer. */
1029 rtex->dcc_offset = align64(rtex->size, rtex->surface.dcc_alignment);
1030 rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
1031 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
1032 }
1033 }
1034
1035 /* Now create the backing buffer. */
1036 if (!buf) {
1037 if (!r600_init_resource(rscreen, resource, rtex->size,
1038 rtex->surface.bo_alignment)) {
1039 FREE(rtex);
1040 return NULL;
1041 }
1042 } else {
1043 resource->buf = buf;
1044 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
1045 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
1046 }
1047
1048 if (rtex->cmask.size) {
1049 /* Initialize the cmask to 0xCC (= compressed state). */
1050 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
1051 rtex->cmask.offset, rtex->cmask.size,
1052 0xCCCCCCCC, R600_COHERENCY_NONE);
1053 }
1054 if (rtex->dcc_offset) {
1055 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
1056 rtex->dcc_offset,
1057 rtex->surface.dcc_size,
1058 0xFFFFFFFF, R600_COHERENCY_NONE);
1059 }
1060
1061 /* Initialize the CMASK base register value. */
1062 rtex->cmask.base_address_reg =
1063 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1064
1065 if (rscreen->debug_flags & DBG_VM) {
1066 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1067 rtex->resource.gpu_address,
1068 rtex->resource.gpu_address + rtex->resource.buf->size,
1069 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
1070 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
1071 }
1072
1073 if (rscreen->debug_flags & DBG_TEX) {
1074 puts("Texture:");
1075 r600_print_texture_info(rtex, stdout);
1076 }
1077
1078 return rtex;
1079 }
1080
1081 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
1082 const struct pipe_resource *templ)
1083 {
1084 const struct util_format_description *desc = util_format_description(templ->format);
1085 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1086
1087 /* MSAA resources must be 2D tiled. */
1088 if (templ->nr_samples > 1)
1089 return RADEON_SURF_MODE_2D;
1090
1091 /* Transfer resources should be linear. */
1092 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1093 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1094
1095 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1096 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
1097 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
1098 (templ->target == PIPE_TEXTURE_2D ||
1099 templ->target == PIPE_TEXTURE_3D))
1100 force_tiling = true;
1101
1102 /* Handle common candidates for the linear mode.
1103 * Compressed textures and DB surfaces must always be tiled.
1104 */
1105 if (!force_tiling && !util_format_is_compressed(templ->format) &&
1106 (!util_format_is_depth_or_stencil(templ->format) ||
1107 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)) {
1108 if (rscreen->debug_flags & DBG_NO_TILING)
1109 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1110
1111 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1112 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1113 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1114
1115 /* Cursors are linear on SI.
1116 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1117 if (rscreen->chip_class >= SI &&
1118 (templ->bind & PIPE_BIND_CURSOR))
1119 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1120
1121 if (templ->bind & PIPE_BIND_LINEAR)
1122 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1123
1124 /* Textures with a very small height are recommended to be linear. */
1125 if (templ->target == PIPE_TEXTURE_1D ||
1126 templ->target == PIPE_TEXTURE_1D_ARRAY ||
1127 templ->height0 <= 4)
1128 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1129
1130 /* Textures likely to be mapped often. */
1131 if (templ->usage == PIPE_USAGE_STAGING ||
1132 templ->usage == PIPE_USAGE_STREAM)
1133 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1134 }
1135
1136 /* Make small textures 1D tiled. */
1137 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1138 (rscreen->debug_flags & DBG_NO_2D_TILING))
1139 return RADEON_SURF_MODE_1D;
1140
1141 /* The allocator will switch to 1D if needed. */
1142 return RADEON_SURF_MODE_2D;
1143 }
1144
1145 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
1146 const struct pipe_resource *templ)
1147 {
1148 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1149 struct radeon_surf surface = {0};
1150 int r;
1151
1152 r = r600_init_surface(rscreen, &surface, templ,
1153 r600_choose_tiling(rscreen, templ),
1154 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1155 if (r) {
1156 return NULL;
1157 }
1158 r = rscreen->ws->surface_best(rscreen->ws, &surface);
1159 if (r) {
1160 return NULL;
1161 }
1162 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 0,
1163 0, NULL, &surface);
1164 }
1165
1166 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1167 const struct pipe_resource *templ,
1168 struct winsys_handle *whandle,
1169 unsigned usage)
1170 {
1171 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1172 struct pb_buffer *buf = NULL;
1173 unsigned stride = 0, offset = 0;
1174 unsigned array_mode;
1175 struct radeon_surf surface;
1176 int r;
1177 struct radeon_bo_metadata metadata = {};
1178 struct r600_texture *rtex;
1179
1180 /* Support only 2D textures without mipmaps */
1181 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1182 templ->depth0 != 1 || templ->last_level != 0)
1183 return NULL;
1184
1185 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
1186 if (!buf)
1187 return NULL;
1188
1189 rscreen->ws->buffer_get_metadata(buf, &metadata);
1190
1191 surface.pipe_config = metadata.pipe_config;
1192 surface.bankw = metadata.bankw;
1193 surface.bankh = metadata.bankh;
1194 surface.tile_split = metadata.tile_split;
1195 surface.mtilea = metadata.mtilea;
1196 surface.num_banks = metadata.num_banks;
1197
1198 if (metadata.macrotile == RADEON_LAYOUT_TILED)
1199 array_mode = RADEON_SURF_MODE_2D;
1200 else if (metadata.microtile == RADEON_LAYOUT_TILED)
1201 array_mode = RADEON_SURF_MODE_1D;
1202 else
1203 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1204
1205 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
1206 if (r) {
1207 return NULL;
1208 }
1209
1210 if (metadata.scanout)
1211 surface.flags |= RADEON_SURF_SCANOUT;
1212
1213 rtex = r600_texture_create_object(screen, templ, stride,
1214 offset, buf, &surface);
1215 if (!rtex)
1216 return NULL;
1217
1218 rtex->resource.is_shared = true;
1219 rtex->resource.external_usage = usage;
1220 return &rtex->resource.b.b;
1221 }
1222
1223 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1224 struct pipe_resource *texture,
1225 struct r600_texture **staging)
1226 {
1227 struct r600_texture *rtex = (struct r600_texture*)texture;
1228 struct pipe_resource resource;
1229 struct r600_texture **flushed_depth_texture = staging ?
1230 staging : &rtex->flushed_depth_texture;
1231
1232 if (!staging && rtex->flushed_depth_texture)
1233 return true; /* it's ready */
1234
1235 resource.target = texture->target;
1236 resource.format = texture->format;
1237 resource.width0 = texture->width0;
1238 resource.height0 = texture->height0;
1239 resource.depth0 = texture->depth0;
1240 resource.array_size = texture->array_size;
1241 resource.last_level = texture->last_level;
1242 resource.nr_samples = texture->nr_samples;
1243 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1244 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1245 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1246
1247 if (staging)
1248 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1249
1250 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1251 if (*flushed_depth_texture == NULL) {
1252 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1253 return false;
1254 }
1255
1256 (*flushed_depth_texture)->is_flushing_texture = TRUE;
1257 (*flushed_depth_texture)->non_disp_tiling = false;
1258 return true;
1259 }
1260
1261 /**
1262 * Initialize the pipe_resource descriptor to be of the same size as the box,
1263 * which is supposed to hold a subregion of the texture "orig" at the given
1264 * mipmap level.
1265 */
1266 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1267 struct pipe_resource *orig,
1268 const struct pipe_box *box,
1269 unsigned level, unsigned flags)
1270 {
1271 memset(res, 0, sizeof(*res));
1272 res->format = orig->format;
1273 res->width0 = box->width;
1274 res->height0 = box->height;
1275 res->depth0 = 1;
1276 res->array_size = 1;
1277 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1278 res->flags = flags;
1279
1280 /* We must set the correct texture target and dimensions for a 3D box. */
1281 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1282 res->target = PIPE_TEXTURE_2D_ARRAY;
1283 res->array_size = box->depth;
1284 } else {
1285 res->target = PIPE_TEXTURE_2D;
1286 }
1287 }
1288
1289 static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
1290 struct r600_texture *rtex,
1291 unsigned transfer_usage,
1292 const struct pipe_box *box)
1293 {
1294 /* r600g doesn't react to dirty_tex_descriptor_counter */
1295 return rscreen->chip_class >= SI &&
1296 !rtex->resource.is_shared &&
1297 !(transfer_usage & PIPE_TRANSFER_READ) &&
1298 rtex->resource.b.b.last_level == 0 &&
1299 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1300 box->x, box->y, box->z,
1301 box->width, box->height,
1302 box->depth);
1303 }
1304
1305 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1306 struct r600_texture *rtex)
1307 {
1308 struct r600_common_screen *rscreen = rctx->screen;
1309
1310 /* There is no point in discarding depth and tiled buffers. */
1311 assert(!rtex->is_depth);
1312 assert(rtex->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED);
1313
1314 /* Reallocate the buffer in the same pipe_resource. */
1315 r600_init_resource(rscreen, &rtex->resource, rtex->size,
1316 rtex->surface.bo_alignment);
1317
1318 /* Initialize the CMASK base address (needed even without CMASK). */
1319 rtex->cmask.base_address_reg =
1320 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1321
1322 r600_dirty_all_framebuffer_states(rscreen);
1323 p_atomic_inc(&rscreen->dirty_tex_descriptor_counter);
1324
1325 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1326 }
1327
1328 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1329 struct pipe_resource *texture,
1330 unsigned level,
1331 unsigned usage,
1332 const struct pipe_box *box,
1333 struct pipe_transfer **ptransfer)
1334 {
1335 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1336 struct r600_texture *rtex = (struct r600_texture*)texture;
1337 struct r600_transfer *trans;
1338 struct r600_resource *buf;
1339 unsigned offset = 0;
1340 char *map;
1341 bool use_staging_texture = false;
1342
1343 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1344
1345 /* Depth textures use staging unconditionally. */
1346 if (!rtex->is_depth) {
1347 /* Degrade the tile mode if we get too many transfers on APUs.
1348 * On dGPUs, the staging texture is always faster.
1349 * Only count uploads that are at least 4x4 pixels large.
1350 */
1351 if (!rctx->screen->info.has_dedicated_vram &&
1352 level == 0 &&
1353 box->width >= 4 && box->height >= 4 &&
1354 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1355 bool can_invalidate =
1356 r600_can_invalidate_texture(rctx->screen, rtex,
1357 usage, box);
1358
1359 r600_degrade_tile_mode_to_linear(rctx, rtex,
1360 can_invalidate);
1361 }
1362
1363 /* Tiled textures need to be converted into a linear texture for CPU
1364 * access. The staging texture is always linear and is placed in GART.
1365 *
1366 * Reading from VRAM is slow, always use the staging texture in
1367 * this case.
1368 *
1369 * Use the staging texture for uploads if the underlying BO
1370 * is busy.
1371 */
1372 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D)
1373 use_staging_texture = true;
1374 else if (usage & PIPE_TRANSFER_READ)
1375 use_staging_texture = (rtex->resource.domains &
1376 RADEON_DOMAIN_VRAM) != 0;
1377 /* Write & linear only: */
1378 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1379 RADEON_USAGE_READWRITE) ||
1380 !rctx->ws->buffer_wait(rtex->resource.buf, 0,
1381 RADEON_USAGE_READWRITE)) {
1382 /* It's busy. */
1383 if (r600_can_invalidate_texture(rctx->screen, rtex,
1384 usage, box))
1385 r600_texture_invalidate_storage(rctx, rtex);
1386 else
1387 use_staging_texture = true;
1388 }
1389 }
1390
1391 trans = CALLOC_STRUCT(r600_transfer);
1392 if (!trans)
1393 return NULL;
1394 trans->transfer.resource = texture;
1395 trans->transfer.level = level;
1396 trans->transfer.usage = usage;
1397 trans->transfer.box = *box;
1398
1399 if (rtex->is_depth) {
1400 struct r600_texture *staging_depth;
1401
1402 if (rtex->resource.b.b.nr_samples > 1) {
1403 /* MSAA depth buffers need to be converted to single sample buffers.
1404 *
1405 * Mapping MSAA depth buffers can occur if ReadPixels is called
1406 * with a multisample GLX visual.
1407 *
1408 * First downsample the depth buffer to a temporary texture,
1409 * then decompress the temporary one to staging.
1410 *
1411 * Only the region being mapped is transfered.
1412 */
1413 struct pipe_resource resource;
1414
1415 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1416
1417 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1418 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1419 FREE(trans);
1420 return NULL;
1421 }
1422
1423 if (usage & PIPE_TRANSFER_READ) {
1424 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1425 if (!temp) {
1426 R600_ERR("failed to create a temporary depth texture\n");
1427 FREE(trans);
1428 return NULL;
1429 }
1430
1431 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1432 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1433 0, 0, 0, box->depth, 0, 0);
1434 pipe_resource_reference(&temp, NULL);
1435 }
1436 }
1437 else {
1438 /* XXX: only readback the rectangle which is being mapped? */
1439 /* XXX: when discard is true, no need to read back from depth texture */
1440 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1441 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1442 FREE(trans);
1443 return NULL;
1444 }
1445
1446 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1447 level, level,
1448 box->z, box->z + box->depth - 1,
1449 0, 0);
1450
1451 offset = r600_texture_get_offset(staging_depth, level, box);
1452 }
1453
1454 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1455 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1456 trans->staging = (struct r600_resource*)staging_depth;
1457 buf = trans->staging;
1458 } else if (use_staging_texture) {
1459 struct pipe_resource resource;
1460 struct r600_texture *staging;
1461
1462 r600_init_temp_resource_from_box(&resource, texture, box, level,
1463 R600_RESOURCE_FLAG_TRANSFER);
1464 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1465 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1466
1467 /* Create the temporary texture. */
1468 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1469 if (!staging) {
1470 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1471 FREE(trans);
1472 return NULL;
1473 }
1474 trans->staging = &staging->resource;
1475 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1476 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1477
1478 if (usage & PIPE_TRANSFER_READ)
1479 r600_copy_to_staging_texture(ctx, trans);
1480 else
1481 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1482
1483 buf = trans->staging;
1484 } else {
1485 /* the resource is mapped directly */
1486 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1487 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1488 offset = r600_texture_get_offset(rtex, level, box);
1489 buf = &rtex->resource;
1490 }
1491
1492 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1493 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1494 FREE(trans);
1495 return NULL;
1496 }
1497
1498 *ptransfer = &trans->transfer;
1499 return map + offset;
1500 }
1501
1502 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1503 struct pipe_transfer* transfer)
1504 {
1505 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1506 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1507 struct pipe_resource *texture = transfer->resource;
1508 struct r600_texture *rtex = (struct r600_texture*)texture;
1509
1510 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1511 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1512 ctx->resource_copy_region(ctx, texture, transfer->level,
1513 transfer->box.x, transfer->box.y, transfer->box.z,
1514 &rtransfer->staging->b.b, transfer->level,
1515 &transfer->box);
1516 } else {
1517 r600_copy_from_staging_texture(ctx, rtransfer);
1518 }
1519 }
1520
1521 if (rtransfer->staging) {
1522 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1523 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1524 }
1525
1526 /* Heuristic for {upload, draw, upload, draw, ..}:
1527 *
1528 * Flush the gfx IB if we've allocated too much texture storage.
1529 *
1530 * The idea is that we don't want to build IBs that use too much
1531 * memory and put pressure on the kernel memory manager and we also
1532 * want to make temporary and invalidated buffers go idle ASAP to
1533 * decrease the total memory usage or make them reusable. The memory
1534 * usage will be slightly higher than given here because of the buffer
1535 * cache in the winsys.
1536 *
1537 * The result is that the kernel memory manager is never a bottleneck.
1538 */
1539 if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
1540 rctx->gfx.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1541 rctx->num_alloc_tex_transfer_bytes = 0;
1542 }
1543
1544 FREE(transfer);
1545 }
1546
1547 static const struct u_resource_vtbl r600_texture_vtbl =
1548 {
1549 NULL, /* get_handle */
1550 r600_texture_destroy, /* resource_destroy */
1551 r600_texture_transfer_map, /* transfer_map */
1552 u_default_transfer_flush_region, /* transfer_flush_region */
1553 r600_texture_transfer_unmap, /* transfer_unmap */
1554 NULL /* transfer_inline_write */
1555 };
1556
1557 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1558 struct pipe_resource *texture,
1559 const struct pipe_surface *templ,
1560 unsigned width, unsigned height)
1561 {
1562 struct r600_texture *rtex = (struct r600_texture*)texture;
1563 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1564
1565 if (!surface)
1566 return NULL;
1567
1568 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1569 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1570
1571 pipe_reference_init(&surface->base.reference, 1);
1572 pipe_resource_reference(&surface->base.texture, texture);
1573 surface->base.context = pipe;
1574 surface->base.format = templ->format;
1575 surface->base.width = width;
1576 surface->base.height = height;
1577 surface->base.u = templ->u;
1578 surface->level_info = &rtex->surface.level[templ->u.tex.level];
1579 return &surface->base;
1580 }
1581
1582 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1583 struct pipe_resource *tex,
1584 const struct pipe_surface *templ)
1585 {
1586 unsigned level = templ->u.tex.level;
1587 unsigned width = u_minify(tex->width0, level);
1588 unsigned height = u_minify(tex->height0, level);
1589
1590 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1591 const struct util_format_description *tex_desc
1592 = util_format_description(tex->format);
1593 const struct util_format_description *templ_desc
1594 = util_format_description(templ->format);
1595
1596 assert(tex_desc->block.bits == templ_desc->block.bits);
1597
1598 /* Adjust size of surface if and only if the block width or
1599 * height is changed. */
1600 if (tex_desc->block.width != templ_desc->block.width ||
1601 tex_desc->block.height != templ_desc->block.height) {
1602 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1603 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1604
1605 width = nblks_x * templ_desc->block.width;
1606 height = nblks_y * templ_desc->block.height;
1607 }
1608 }
1609
1610 return r600_create_surface_custom(pipe, tex, templ, width, height);
1611 }
1612
1613 static void r600_surface_destroy(struct pipe_context *pipe,
1614 struct pipe_surface *surface)
1615 {
1616 struct r600_surface *surf = (struct r600_surface*)surface;
1617 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1618 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1619 pipe_resource_reference(&surface->texture, NULL);
1620 FREE(surface);
1621 }
1622
1623 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1624 {
1625 const struct util_format_description *desc = util_format_description(format);
1626
1627 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1628
1629 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1630 return V_0280A0_SWAP_STD;
1631
1632 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1633 return ~0U;
1634
1635 switch (desc->nr_channels) {
1636 case 1:
1637 if (HAS_SWIZZLE(0,X))
1638 return V_0280A0_SWAP_STD; /* X___ */
1639 else if (HAS_SWIZZLE(3,X))
1640 return V_0280A0_SWAP_ALT_REV; /* ___X */
1641 break;
1642 case 2:
1643 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1644 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1645 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1646 return V_0280A0_SWAP_STD; /* XY__ */
1647 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1648 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1649 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1650 /* YX__ */
1651 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1652 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1653 return V_0280A0_SWAP_ALT; /* X__Y */
1654 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1655 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1656 break;
1657 case 3:
1658 if (HAS_SWIZZLE(0,X))
1659 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1660 else if (HAS_SWIZZLE(0,Z))
1661 return V_0280A0_SWAP_STD_REV; /* ZYX */
1662 break;
1663 case 4:
1664 /* check the middle channels, the 1st and 4th channel can be NONE */
1665 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1666 return V_0280A0_SWAP_STD; /* XYZW */
1667 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1668 return V_0280A0_SWAP_STD_REV; /* WZYX */
1669 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1670 return V_0280A0_SWAP_ALT; /* ZYXW */
1671 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1672 /* YZWX */
1673 if (desc->is_array)
1674 return V_0280A0_SWAP_ALT_REV;
1675 else
1676 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1677 }
1678 break;
1679 }
1680 return ~0U;
1681 }
1682
1683 static void evergreen_set_clear_color(struct r600_texture *rtex,
1684 enum pipe_format surface_format,
1685 const union pipe_color_union *color)
1686 {
1687 union util_color uc;
1688
1689 memset(&uc, 0, sizeof(uc));
1690
1691 if (util_format_is_pure_uint(surface_format)) {
1692 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1693 } else if (util_format_is_pure_sint(surface_format)) {
1694 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1695 } else {
1696 util_pack_color(color->f, surface_format, &uc);
1697 }
1698
1699 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1700 }
1701
1702 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1703 const union pipe_color_union *color,
1704 uint32_t* reset_value,
1705 bool* clear_words_needed)
1706 {
1707 bool values[4] = {};
1708 int i;
1709 bool main_value = false;
1710 bool extra_value = false;
1711 int extra_channel;
1712 const struct util_format_description *desc = util_format_description(surface_format);
1713
1714 *clear_words_needed = true;
1715 *reset_value = 0x20202020U;
1716
1717 /* If we want to clear without needing a fast clear eliminate step, we
1718 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1719 * have two sets of flags, one for the last or first channel(extra) and
1720 * one for the other channels(main).
1721 */
1722
1723 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1724 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1725 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1726 extra_channel = -1;
1727 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1728 if(r600_translate_colorswap(surface_format, FALSE) <= 1)
1729 extra_channel = desc->nr_channels - 1;
1730 else
1731 extra_channel = 0;
1732 } else
1733 return;
1734
1735 for (i = 0; i < 4; ++i) {
1736 int index = desc->swizzle[i] - PIPE_SWIZZLE_X;
1737
1738 if (desc->swizzle[i] < PIPE_SWIZZLE_X ||
1739 desc->swizzle[i] > PIPE_SWIZZLE_W)
1740 continue;
1741
1742 if (util_format_is_pure_sint(surface_format)) {
1743 values[i] = color->i[i] != 0;
1744 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1745 return;
1746 } else if (util_format_is_pure_uint(surface_format)) {
1747 values[i] = color->ui[i] != 0U;
1748 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1749 return;
1750 } else {
1751 values[i] = color->f[i] != 0.0F;
1752 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1753 return;
1754 }
1755
1756 if (index == extra_channel)
1757 extra_value = values[i];
1758 else
1759 main_value = values[i];
1760 }
1761
1762 for (int i = 0; i < 4; ++i)
1763 if (values[i] != main_value &&
1764 desc->swizzle[i] - PIPE_SWIZZLE_X != extra_channel &&
1765 desc->swizzle[i] >= PIPE_SWIZZLE_X &&
1766 desc->swizzle[i] <= PIPE_SWIZZLE_W)
1767 return;
1768
1769 *clear_words_needed = false;
1770 if (main_value)
1771 *reset_value |= 0x80808080U;
1772
1773 if (extra_value)
1774 *reset_value |= 0x40404040U;
1775 }
1776
1777 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1778 struct pipe_framebuffer_state *fb,
1779 struct r600_atom *fb_state,
1780 unsigned *buffers, unsigned *dirty_cbufs,
1781 const union pipe_color_union *color)
1782 {
1783 int i;
1784
1785 /* This function is broken in BE, so just disable this path for now */
1786 #ifdef PIPE_ARCH_BIG_ENDIAN
1787 return;
1788 #endif
1789
1790 if (rctx->render_cond)
1791 return;
1792
1793 for (i = 0; i < fb->nr_cbufs; i++) {
1794 struct r600_texture *tex;
1795 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1796
1797 if (!fb->cbufs[i])
1798 continue;
1799
1800 /* if this colorbuffer is not being cleared */
1801 if (!(*buffers & clear_bit))
1802 continue;
1803
1804 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1805
1806 /* 128-bit formats are unusupported */
1807 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1808 continue;
1809 }
1810
1811 /* the clear is allowed if all layers are bound */
1812 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1813 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1814 continue;
1815 }
1816
1817 /* cannot clear mipmapped textures */
1818 if (fb->cbufs[i]->texture->last_level != 0) {
1819 continue;
1820 }
1821
1822 /* only supported on tiled surfaces */
1823 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1824 continue;
1825 }
1826
1827 /* shared textures can't use fast clear without an explicit flush,
1828 * because there is no way to communicate the clear color among
1829 * all clients
1830 */
1831 if (tex->resource.is_shared &&
1832 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1833 continue;
1834
1835 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1836 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1837 rctx->chip_class >= CIK &&
1838 rctx->screen->info.drm_major == 2 &&
1839 rctx->screen->info.drm_minor < 38) {
1840 continue;
1841 }
1842
1843 if (tex->dcc_offset) {
1844 uint32_t reset_value;
1845 bool clear_words_needed;
1846
1847 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1848 continue;
1849
1850 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1851
1852 rctx->clear_buffer(&rctx->b, &tex->resource.b.b,
1853 tex->dcc_offset, tex->surface.dcc_size,
1854 reset_value, R600_COHERENCY_CB_META);
1855
1856 if (clear_words_needed)
1857 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1858 } else {
1859 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1860 if (rctx->family == CHIP_STONEY)
1861 continue;
1862
1863 /* ensure CMASK is enabled */
1864 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1865 if (tex->cmask.size == 0) {
1866 continue;
1867 }
1868
1869 /* Do the fast clear. */
1870 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1871 tex->cmask.offset, tex->cmask.size, 0,
1872 R600_COHERENCY_CB_META);
1873
1874 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1875 }
1876
1877 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1878
1879 if (dirty_cbufs)
1880 *dirty_cbufs |= 1 << i;
1881 rctx->set_atom_dirty(rctx, fb_state, true);
1882 *buffers &= ~clear_bit;
1883 }
1884 }
1885
1886 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1887 {
1888 rscreen->b.resource_from_handle = r600_texture_from_handle;
1889 rscreen->b.resource_get_handle = r600_texture_get_handle;
1890 }
1891
1892 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1893 {
1894 rctx->b.create_surface = r600_create_surface;
1895 rctx->b.surface_destroy = r600_surface_destroy;
1896 }