2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "radeonsi/si_pipe.h"
26 #include "r600_query.h"
27 #include "util/u_format.h"
28 #include "util/u_log.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/u_resource.h"
32 #include "util/u_surface.h"
33 #include "util/os_time.h"
36 #include "state_tracker/drm_driver.h"
37 #include "amd/common/sid.h"
39 static void r600_texture_discard_cmask(struct si_screen
*sscreen
,
40 struct r600_texture
*rtex
);
41 static enum radeon_surf_mode
42 r600_choose_tiling(struct si_screen
*sscreen
,
43 const struct pipe_resource
*templ
);
46 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
47 struct r600_texture
*rdst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct r600_texture
*rsrc
,
52 const struct pipe_box
*src_box
)
57 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
62 rdst
->resource
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (rsrc
->is_depth
|| rdst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if (vi_dcc_enabled(rsrc
, src_level
) ||
77 vi_dcc_enabled(rdst
, dst_level
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 r600_texture_discard_cmask(rctx
->screen
, rdst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
98 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
100 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
143 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
145 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
161 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned r600_texture_get_offset(struct si_screen
*sscreen
,
182 struct r600_texture
*rtex
, unsigned level
,
183 const struct pipe_box
*box
,
185 unsigned *layer_stride
)
187 if (sscreen
->info
.chip_class
>= GFX9
) {
188 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
189 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
194 /* Each texture is an array of slices. Each slice is an array
195 * of mipmap levels. */
196 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
197 rtex
->surface
.u
.gfx9
.offset
[level
] +
198 (box
->y
/ rtex
->surface
.blk_h
*
199 rtex
->surface
.u
.gfx9
.surf_pitch
+
200 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
202 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
204 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
205 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
208 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
214 (box
->y
/ rtex
->surface
.blk_h
*
215 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
220 static int r600_init_surface(struct si_screen
*sscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 enum radeon_surf_mode array_mode
,
224 unsigned pitch_in_bytes_override
,
228 bool is_flushed_depth
,
229 bool tc_compatible_htile
)
231 const struct util_format_description
*desc
=
232 util_format_description(ptex
->format
);
233 bool is_depth
, is_stencil
;
235 unsigned i
, bpe
, flags
= 0;
237 is_depth
= util_format_has_depth(desc
);
238 is_stencil
= util_format_has_stencil(desc
);
240 if (!is_flushed_depth
&&
241 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
242 bpe
= 4; /* stencil is allocated separately on evergreen */
244 bpe
= util_format_get_blocksize(ptex
->format
);
245 assert(util_is_power_of_two(bpe
));
248 if (!is_flushed_depth
&& is_depth
) {
249 flags
|= RADEON_SURF_ZBUFFER
;
251 if (tc_compatible_htile
&&
252 (sscreen
->info
.chip_class
>= GFX9
||
253 array_mode
== RADEON_SURF_MODE_2D
)) {
254 /* TC-compatible HTILE only supports Z32_FLOAT.
255 * GFX9 also supports Z16_UNORM.
256 * On VI, promote Z16 to Z32. DB->CB copies will convert
257 * the format for transfers.
259 if (sscreen
->info
.chip_class
== VI
)
262 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
266 flags
|= RADEON_SURF_SBUFFER
;
269 if (sscreen
->info
.chip_class
>= VI
&&
270 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
271 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
272 /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
273 (ptex
->nr_samples
>= 2 &&
274 (!sscreen
->dcc_msaa_allowed
|| ptex
->array_size
> 1))))
275 flags
|= RADEON_SURF_DISABLE_DCC
;
277 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
278 /* This should catch bugs in gallium users setting incorrect flags. */
279 assert(ptex
->nr_samples
<= 1 &&
280 ptex
->array_size
== 1 &&
282 ptex
->last_level
== 0 &&
283 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
285 flags
|= RADEON_SURF_SCANOUT
;
288 if (ptex
->bind
& PIPE_BIND_SHARED
)
289 flags
|= RADEON_SURF_SHAREABLE
;
291 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
292 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
293 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
295 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
296 array_mode
, surface
);
301 if (sscreen
->info
.chip_class
>= GFX9
) {
302 assert(!pitch_in_bytes_override
||
303 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
304 surface
->u
.gfx9
.surf_offset
= offset
;
307 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
308 surface
->u
.legacy
.level
[i
].offset
+= offset
;
314 static void r600_texture_init_metadata(struct si_screen
*sscreen
,
315 struct r600_texture
*rtex
,
316 struct radeon_bo_metadata
*metadata
)
318 struct radeon_surf
*surface
= &rtex
->surface
;
320 memset(metadata
, 0, sizeof(*metadata
));
322 if (sscreen
->info
.chip_class
>= GFX9
) {
323 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
325 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
326 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
327 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
328 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
329 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
330 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
331 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
332 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
333 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
334 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
335 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
336 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
340 static void r600_surface_import_metadata(struct si_screen
*sscreen
,
341 struct radeon_surf
*surf
,
342 struct radeon_bo_metadata
*metadata
,
343 enum radeon_surf_mode
*array_mode
,
346 if (sscreen
->info
.chip_class
>= GFX9
) {
347 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
348 *array_mode
= RADEON_SURF_MODE_2D
;
350 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
352 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
353 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
355 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
357 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
358 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
359 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
360 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
361 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
362 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
364 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
365 *array_mode
= RADEON_SURF_MODE_2D
;
366 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
367 *array_mode
= RADEON_SURF_MODE_1D
;
369 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
371 *is_scanout
= metadata
->u
.legacy
.scanout
;
375 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
376 struct r600_texture
*rtex
)
378 struct si_screen
*sscreen
= rctx
->screen
;
379 struct pipe_context
*ctx
= &rctx
->b
;
381 if (ctx
== sscreen
->aux_context
)
382 mtx_lock(&sscreen
->aux_context_lock
);
384 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
385 ctx
->flush(ctx
, NULL
, 0);
387 if (ctx
== sscreen
->aux_context
)
388 mtx_unlock(&sscreen
->aux_context_lock
);
391 static void r600_texture_discard_cmask(struct si_screen
*sscreen
,
392 struct r600_texture
*rtex
)
394 if (!rtex
->cmask
.size
)
397 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
400 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
401 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
402 rtex
->dirty_level_mask
= 0;
404 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
406 if (rtex
->cmask_buffer
!= &rtex
->resource
)
407 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
409 /* Notify all contexts about the change. */
410 p_atomic_inc(&sscreen
->dirty_tex_counter
);
411 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
414 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
416 /* We can't disable DCC if it can be written by another process. */
417 return rtex
->dcc_offset
&&
418 (!rtex
->resource
.b
.is_shared
||
419 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
422 static bool r600_texture_discard_dcc(struct si_screen
*sscreen
,
423 struct r600_texture
*rtex
)
425 if (!r600_can_disable_dcc(rtex
))
428 assert(rtex
->dcc_separate_buffer
== NULL
);
431 rtex
->dcc_offset
= 0;
433 /* Notify all contexts about the change. */
434 p_atomic_inc(&sscreen
->dirty_tex_counter
);
439 * Disable DCC for the texture. (first decompress, then discard metadata).
441 * There is unresolved multi-context synchronization issue between
442 * screen::aux_context and the current context. If applications do this with
443 * multiple contexts, it's already undefined behavior for them and we don't
444 * have to worry about that. The scenario is:
446 * If context 1 disables DCC and context 2 has queued commands that write
447 * to the texture via CB with DCC enabled, and the order of operations is
449 * context 2 queues draw calls rendering to the texture, but doesn't flush
450 * context 1 disables DCC and flushes
451 * context 1 & 2 reset descriptors and FB state
452 * context 2 flushes (new compressed tiles written by the draw calls)
453 * context 1 & 2 read garbage, because DCC is disabled, yet there are
456 * \param rctx the current context if you have one, or rscreen->aux_context
459 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
460 struct r600_texture
*rtex
)
462 struct si_screen
*sscreen
= rctx
->screen
;
464 if (!r600_can_disable_dcc(rtex
))
467 if (&rctx
->b
== sscreen
->aux_context
)
468 mtx_lock(&sscreen
->aux_context_lock
);
470 /* Decompress DCC. */
471 rctx
->decompress_dcc(&rctx
->b
, rtex
);
472 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
474 if (&rctx
->b
== sscreen
->aux_context
)
475 mtx_unlock(&sscreen
->aux_context_lock
);
477 return r600_texture_discard_dcc(sscreen
, rtex
);
480 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
481 struct r600_texture
*rtex
,
482 unsigned new_bind_flag
,
483 bool invalidate_storage
)
485 struct pipe_screen
*screen
= rctx
->b
.screen
;
486 struct r600_texture
*new_tex
;
487 struct pipe_resource templ
= rtex
->resource
.b
.b
;
490 templ
.bind
|= new_bind_flag
;
492 if (rtex
->resource
.b
.is_shared
)
495 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
496 if (rtex
->surface
.is_linear
)
499 /* This fails with MSAA, depth, and compressed textures. */
500 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
501 RADEON_SURF_MODE_LINEAR_ALIGNED
)
505 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
509 /* Copy the pixels to the new texture. */
510 if (!invalidate_storage
) {
511 for (i
= 0; i
<= templ
.last_level
; i
++) {
515 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
516 util_max_layer(&templ
, i
) + 1, &box
);
518 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
519 &rtex
->resource
.b
.b
, i
, &box
);
523 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
524 r600_texture_discard_cmask(rctx
->screen
, rtex
);
525 r600_texture_discard_dcc(rctx
->screen
, rtex
);
528 /* Replace the structure fields of rtex. */
529 rtex
->resource
.b
.b
.bind
= templ
.bind
;
530 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
531 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
532 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
533 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
534 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
535 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
536 rtex
->resource
.domains
= new_tex
->resource
.domains
;
537 rtex
->resource
.flags
= new_tex
->resource
.flags
;
538 rtex
->size
= new_tex
->size
;
539 rtex
->db_render_format
= new_tex
->db_render_format
;
540 rtex
->db_compatible
= new_tex
->db_compatible
;
541 rtex
->can_sample_z
= new_tex
->can_sample_z
;
542 rtex
->can_sample_s
= new_tex
->can_sample_s
;
543 rtex
->surface
= new_tex
->surface
;
544 rtex
->fmask
= new_tex
->fmask
;
545 rtex
->cmask
= new_tex
->cmask
;
546 rtex
->cb_color_info
= new_tex
->cb_color_info
;
547 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
548 rtex
->htile_offset
= new_tex
->htile_offset
;
549 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
550 rtex
->depth_cleared
= new_tex
->depth_cleared
;
551 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
552 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
553 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
555 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
556 assert(!rtex
->htile_offset
);
557 assert(!rtex
->cmask
.size
);
558 assert(!rtex
->fmask
.size
);
559 assert(!rtex
->dcc_offset
);
560 assert(!rtex
->is_depth
);
563 r600_texture_reference(&new_tex
, NULL
);
565 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
568 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
570 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
573 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
574 struct r600_texture
*rtex
,
575 struct radeon_bo_metadata
*md
)
577 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
578 static const unsigned char swizzle
[] = {
585 bool is_array
= util_resource_is_array_texture(res
);
587 /* DRM 2.x.x doesn't support this. */
588 if (sscreen
->info
.drm_major
!= 3)
591 assert(rtex
->dcc_separate_buffer
== NULL
);
592 assert(rtex
->fmask
.size
== 0);
594 /* Metadata image format format version 1:
595 * [0] = 1 (metadata format identifier)
596 * [1] = (VENDOR_ID << 16) | PCI_ID
597 * [2:9] = image descriptor for the whole resource
598 * [2] is always 0, because the base address is cleared
599 * [9] is the DCC offset bits [39:8] from the beginning of
601 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
604 md
->metadata
[0] = 1; /* metadata image format version 1 */
606 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
607 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
609 si_make_texture_descriptor(sscreen
, rtex
, true,
610 res
->target
, res
->format
,
611 swizzle
, 0, res
->last_level
, 0,
612 is_array
? res
->array_size
- 1 : 0,
613 res
->width0
, res
->height0
, res
->depth0
,
616 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
617 0, 0, rtex
->surface
.blk_w
, false, desc
);
619 /* Clear the base address and set the relative DCC offset. */
621 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
622 desc
[7] = rtex
->dcc_offset
>> 8;
624 /* Dwords [2:9] contain the image descriptor. */
625 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
626 md
->size_metadata
= 10 * 4;
628 /* Dwords [10:..] contain the mipmap level offsets. */
629 if (sscreen
->info
.chip_class
<= VI
) {
630 for (i
= 0; i
<= res
->last_level
; i
++)
631 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
633 md
->size_metadata
+= (1 + res
->last_level
) * 4;
637 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
638 struct r600_texture
*rtex
,
639 struct radeon_bo_metadata
*md
)
641 uint32_t *desc
= &md
->metadata
[2];
643 if (sscreen
->info
.chip_class
< VI
)
646 /* Return if DCC is enabled. The texture should be set up with it
649 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
650 md
->metadata
[0] != 0 &&
651 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
652 G_008F28_COMPRESSION_EN(desc
[6])) {
653 rtex
->dcc_offset
= (uint64_t)desc
[7] << 8;
657 /* Disable DCC. These are always set by texture_from_handle and must
660 rtex
->dcc_offset
= 0;
663 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
664 struct pipe_context
*ctx
,
665 struct pipe_resource
*resource
,
666 struct winsys_handle
*whandle
,
669 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
670 struct r600_common_context
*rctx
;
671 struct r600_resource
*res
= (struct r600_resource
*)resource
;
672 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
673 struct radeon_bo_metadata metadata
;
674 bool update_metadata
= false;
675 unsigned stride
, offset
, slice_size
;
678 ctx
= threaded_context_unwrap_sync(ctx
);
679 rctx
= (struct r600_common_context
*)(ctx
? ctx
: sscreen
->aux_context
);
681 if (resource
->target
!= PIPE_BUFFER
) {
682 /* This is not supported now, but it might be required for OpenCL
683 * interop in the future.
685 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
688 /* Move a suballocated texture into a non-suballocated allocation. */
689 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
690 rtex
->surface
.tile_swizzle
||
691 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
692 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
693 assert(!res
->b
.is_shared
);
694 r600_reallocate_texture_inplace(rctx
, rtex
,
695 PIPE_BIND_SHARED
, false);
697 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
698 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
699 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
700 assert(rtex
->surface
.tile_swizzle
== 0);
703 /* Since shader image stores don't support DCC on VI,
704 * disable it for external clients that want write
707 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
708 if (si_texture_disable_dcc(rctx
, rtex
)) {
709 update_metadata
= true;
710 /* si_texture_disable_dcc flushes the context */
715 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
716 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
717 /* Eliminate fast clear (both CMASK and DCC) */
718 r600_eliminate_fast_color_clear(rctx
, rtex
);
719 /* eliminate_fast_color_clear flushes the context */
722 /* Disable CMASK if flush_resource isn't going
725 if (rtex
->cmask
.size
)
726 r600_texture_discard_cmask(sscreen
, rtex
);
730 if (!res
->b
.is_shared
|| update_metadata
) {
731 r600_texture_init_metadata(sscreen
, rtex
, &metadata
);
732 si_query_opaque_metadata(sscreen
, rtex
, &metadata
);
734 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
737 if (sscreen
->info
.chip_class
>= GFX9
) {
738 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
739 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
741 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
743 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
744 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
746 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
749 /* Move a suballocated buffer into a non-suballocated allocation. */
750 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
751 assert(!res
->b
.is_shared
);
753 /* Allocate a new buffer with PIPE_BIND_SHARED. */
754 struct pipe_resource templ
= res
->b
.b
;
755 templ
.bind
|= PIPE_BIND_SHARED
;
757 struct pipe_resource
*newb
=
758 screen
->resource_create(screen
, &templ
);
762 /* Copy the old buffer contents to the new one. */
764 u_box_1d(0, newb
->width0
, &box
);
765 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
768 /* Move the new buffer storage to the old pipe_resource. */
769 si_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
770 pipe_resource_reference(&newb
, NULL
);
772 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
773 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
783 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
785 if (res
->b
.is_shared
) {
786 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
789 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
790 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
791 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
793 res
->b
.is_shared
= true;
794 res
->external_usage
= usage
;
797 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
798 slice_size
, whandle
);
801 static void r600_texture_destroy(struct pipe_screen
*screen
,
802 struct pipe_resource
*ptex
)
804 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
805 struct r600_resource
*resource
= &rtex
->resource
;
807 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
809 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
810 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
812 pb_reference(&resource
->buf
, NULL
);
813 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
814 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
818 static const struct u_resource_vtbl r600_texture_vtbl
;
820 /* The number of samples can be specified independently of the texture. */
821 void si_texture_get_fmask_info(struct si_screen
*sscreen
,
822 struct r600_texture
*rtex
,
824 struct r600_fmask_info
*out
)
826 /* FMASK is allocated like an ordinary texture. */
827 struct pipe_resource templ
= rtex
->resource
.b
.b
;
828 struct radeon_surf fmask
= {};
831 memset(out
, 0, sizeof(*out
));
833 if (sscreen
->info
.chip_class
>= GFX9
) {
834 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
835 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
839 templ
.nr_samples
= 1;
840 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
842 switch (nr_samples
) {
851 R600_ERR("Invalid sample count for FMASK allocation.\n");
855 if (sscreen
->ws
->surface_init(sscreen
->ws
, &templ
, flags
, bpe
,
856 RADEON_SURF_MODE_2D
, &fmask
)) {
857 R600_ERR("Got error in surface_init while allocating FMASK.\n");
861 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
863 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
864 if (out
->slice_tile_max
)
865 out
->slice_tile_max
-= 1;
867 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
868 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
869 out
->bank_height
= fmask
.u
.legacy
.bankh
;
870 out
->tile_swizzle
= fmask
.tile_swizzle
;
871 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
872 out
->size
= fmask
.surf_size
;
875 static void r600_texture_allocate_fmask(struct si_screen
*sscreen
,
876 struct r600_texture
*rtex
)
878 si_texture_get_fmask_info(sscreen
, rtex
,
879 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
881 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
882 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
885 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
886 struct r600_texture
*rtex
,
887 struct r600_cmask_info
*out
)
889 unsigned pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
890 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
891 unsigned cl_width
, cl_height
;
893 if (sscreen
->info
.chip_class
>= GFX9
) {
894 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
895 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
912 case 16: /* Hawaii */
921 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
923 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
924 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
925 unsigned slice_elements
= (width
* height
) / (8*8);
927 /* Each element of CMASK is a nibble. */
928 unsigned slice_bytes
= slice_elements
/ 2;
930 out
->slice_tile_max
= (width
* height
) / (128*128);
931 if (out
->slice_tile_max
)
932 out
->slice_tile_max
-= 1;
934 out
->alignment
= MAX2(256, base_align
);
935 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
936 align(slice_bytes
, base_align
);
939 static void r600_texture_allocate_cmask(struct si_screen
*sscreen
,
940 struct r600_texture
*rtex
)
942 si_texture_get_cmask_info(sscreen
, rtex
, &rtex
->cmask
);
944 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
945 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
947 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
950 static void r600_texture_get_htile_size(struct si_screen
*sscreen
,
951 struct r600_texture
*rtex
)
953 unsigned cl_width
, cl_height
, width
, height
;
954 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
955 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
957 assert(sscreen
->info
.chip_class
<= VI
);
959 rtex
->surface
.htile_size
= 0;
961 /* HTILE is broken with 1D tiling on old kernels and CIK. */
962 if (sscreen
->info
.chip_class
>= CIK
&&
963 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
964 sscreen
->info
.drm_major
== 2 && sscreen
->info
.drm_minor
< 38)
967 /* Overalign HTILE on P2 configs to work around GPU hangs in
968 * piglit/depthstencil-render-miplevels 585.
970 * This has been confirmed to help Kabini & Stoney, where the hangs
971 * are always reproducible. I think I have seen the test hang
972 * on Carrizo too, though it was very rare there.
974 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
1003 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
1004 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
1006 slice_elements
= (width
* height
) / (8 * 8);
1007 slice_bytes
= slice_elements
* 4;
1009 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1010 base_align
= num_pipes
* pipe_interleave_bytes
;
1012 rtex
->surface
.htile_alignment
= base_align
;
1013 rtex
->surface
.htile_size
=
1014 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
1015 align(slice_bytes
, base_align
);
1018 static void r600_texture_allocate_htile(struct si_screen
*sscreen
,
1019 struct r600_texture
*rtex
)
1021 if (sscreen
->info
.chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
1022 r600_texture_get_htile_size(sscreen
, rtex
);
1024 if (!rtex
->surface
.htile_size
)
1027 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
1028 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
1031 void si_print_texture_info(struct si_screen
*sscreen
,
1032 struct r600_texture
*rtex
, struct u_log_context
*log
)
1036 /* Common parameters. */
1037 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1038 "blk_h=%u, array_size=%u, last_level=%u, "
1039 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1040 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
1041 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1042 rtex
->surface
.blk_h
,
1043 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
1044 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
1045 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
1047 if (sscreen
->info
.chip_class
>= GFX9
) {
1048 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1049 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1050 rtex
->surface
.surf_size
,
1051 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1052 rtex
->surface
.surf_alignment
,
1053 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1054 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1055 rtex
->surface
.u
.gfx9
.surf_pitch
);
1057 if (rtex
->fmask
.size
) {
1058 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1059 "alignment=%u, swmode=%u, epitch=%u\n",
1061 rtex
->surface
.u
.gfx9
.fmask_size
,
1062 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1063 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1064 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1067 if (rtex
->cmask
.size
) {
1068 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1069 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1071 rtex
->surface
.u
.gfx9
.cmask_size
,
1072 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1073 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1074 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1077 if (rtex
->htile_offset
) {
1078 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1079 "rb_aligned=%u, pipe_aligned=%u\n",
1081 rtex
->surface
.htile_size
,
1082 rtex
->surface
.htile_alignment
,
1083 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1084 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1087 if (rtex
->dcc_offset
) {
1088 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1089 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1090 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1091 rtex
->surface
.dcc_alignment
,
1092 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1093 rtex
->surface
.num_dcc_levels
);
1096 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1097 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1098 rtex
->surface
.u
.gfx9
.stencil_offset
,
1099 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1100 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1105 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1106 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1107 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1108 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1109 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1110 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1112 if (rtex
->fmask
.size
)
1113 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1114 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1115 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1116 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1117 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1119 if (rtex
->cmask
.size
)
1120 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1121 "slice_tile_max=%u\n",
1122 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1123 rtex
->cmask
.slice_tile_max
);
1125 if (rtex
->htile_offset
)
1126 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1127 "alignment=%u, TC_compatible = %u\n",
1128 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1129 rtex
->surface
.htile_alignment
,
1130 rtex
->tc_compatible_htile
);
1132 if (rtex
->dcc_offset
) {
1133 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1134 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1135 rtex
->surface
.dcc_alignment
);
1136 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1137 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1138 "fast_clear_size=%u\n",
1139 i
, i
< rtex
->surface
.num_dcc_levels
,
1140 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1141 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1144 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1145 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1146 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1147 "mode=%u, tiling_index = %u\n",
1148 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1149 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1150 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1151 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1152 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1153 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1154 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1155 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1156 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1158 if (rtex
->surface
.has_stencil
) {
1159 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1160 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1161 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1162 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1163 "slice_size=%"PRIu64
", npix_x=%u, "
1164 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1165 "mode=%u, tiling_index = %u\n",
1166 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1167 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1168 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1169 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1170 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1171 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1172 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1173 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1174 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1179 /* Common processing for r600_texture_create and r600_texture_from_handle */
1180 static struct r600_texture
*
1181 r600_texture_create_object(struct pipe_screen
*screen
,
1182 const struct pipe_resource
*base
,
1183 struct pb_buffer
*buf
,
1184 struct radeon_surf
*surface
)
1186 struct r600_texture
*rtex
;
1187 struct r600_resource
*resource
;
1188 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1190 rtex
= CALLOC_STRUCT(r600_texture
);
1194 resource
= &rtex
->resource
;
1195 resource
->b
.b
= *base
;
1196 resource
->b
.b
.next
= NULL
;
1197 resource
->b
.vtbl
= &r600_texture_vtbl
;
1198 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1199 resource
->b
.b
.screen
= screen
;
1201 /* don't include stencil-only formats which we don't support for rendering */
1202 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1204 rtex
->surface
= *surface
;
1205 rtex
->size
= rtex
->surface
.surf_size
;
1207 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1208 (rtex
->surface
.flags
&
1209 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1211 /* TC-compatible HTILE:
1212 * - VI only supports Z32_FLOAT.
1213 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1214 if (rtex
->tc_compatible_htile
) {
1215 if (sscreen
->info
.chip_class
>= GFX9
&&
1216 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1217 rtex
->db_render_format
= base
->format
;
1219 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1220 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1221 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1224 rtex
->db_render_format
= base
->format
;
1227 /* Applies to GCN. */
1228 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1230 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1231 * between frames, so the only thing that can enable separate DCC
1232 * with DRI2 is multiple slow clears within a frame.
1234 rtex
->ps_draw_ratio
= 0;
1236 if (rtex
->is_depth
) {
1237 if (sscreen
->info
.chip_class
>= GFX9
) {
1238 rtex
->can_sample_z
= true;
1239 rtex
->can_sample_s
= true;
1241 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1242 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1245 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1246 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1247 rtex
->db_compatible
= true;
1249 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1250 r600_texture_allocate_htile(sscreen
, rtex
);
1253 if (base
->nr_samples
> 1) {
1255 r600_texture_allocate_fmask(sscreen
, rtex
);
1256 r600_texture_allocate_cmask(sscreen
, rtex
);
1257 rtex
->cmask_buffer
= &rtex
->resource
;
1259 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1265 /* Shared textures must always set up DCC here.
1266 * If it's not present, it will be disabled by
1267 * apply_opaque_metadata later.
1269 if (rtex
->surface
.dcc_size
&&
1270 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1271 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1272 /* Reserve space for the DCC buffer. */
1273 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1274 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1278 /* Now create the backing buffer. */
1280 si_init_resource_fields(sscreen
, resource
, rtex
->size
,
1281 rtex
->surface
.surf_alignment
);
1283 if (!si_alloc_resource(sscreen
, resource
)) {
1288 resource
->buf
= buf
;
1289 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1290 resource
->bo_size
= buf
->size
;
1291 resource
->bo_alignment
= buf
->alignment
;
1292 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1293 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1294 resource
->vram_usage
= buf
->size
;
1295 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1296 resource
->gart_usage
= buf
->size
;
1299 if (rtex
->cmask
.size
) {
1300 /* Initialize the cmask to 0xCC (= compressed state). */
1301 si_screen_clear_buffer(sscreen
, &rtex
->cmask_buffer
->b
.b
,
1302 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1305 if (rtex
->htile_offset
) {
1306 uint32_t clear_value
= 0;
1308 if (sscreen
->info
.chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1309 clear_value
= 0x0000030F;
1311 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1313 rtex
->surface
.htile_size
,
1317 /* Initialize DCC only if the texture is not being imported. */
1318 if (!buf
&& rtex
->dcc_offset
) {
1319 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1321 rtex
->surface
.dcc_size
,
1325 /* Initialize the CMASK base register value. */
1326 rtex
->cmask
.base_address_reg
=
1327 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1329 if (sscreen
->debug_flags
& DBG(VM
)) {
1330 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1331 rtex
->resource
.gpu_address
,
1332 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1333 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1334 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1337 if (sscreen
->debug_flags
& DBG(TEX
)) {
1339 struct u_log_context log
;
1340 u_log_context_init(&log
);
1341 si_print_texture_info(sscreen
, rtex
, &log
);
1342 u_log_new_page_print(&log
, stdout
);
1344 u_log_context_destroy(&log
);
1350 static enum radeon_surf_mode
1351 r600_choose_tiling(struct si_screen
*sscreen
,
1352 const struct pipe_resource
*templ
)
1354 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1355 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1356 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1357 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1359 /* MSAA resources must be 2D tiled. */
1360 if (templ
->nr_samples
> 1)
1361 return RADEON_SURF_MODE_2D
;
1363 /* Transfer resources should be linear. */
1364 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1365 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1367 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1368 * which requires 2D tiling.
1370 if (sscreen
->info
.chip_class
== VI
&&
1372 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1373 return RADEON_SURF_MODE_2D
;
1375 /* Handle common candidates for the linear mode.
1376 * Compressed textures and DB surfaces must always be tiled.
1378 if (!force_tiling
&&
1379 !is_depth_stencil
&&
1380 !util_format_is_compressed(templ
->format
)) {
1381 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1382 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1384 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1385 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1386 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1388 /* Cursors are linear on SI.
1389 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1390 if (templ
->bind
& PIPE_BIND_CURSOR
)
1391 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1393 if (templ
->bind
& PIPE_BIND_LINEAR
)
1394 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1396 /* Textures with a very small height are recommended to be linear. */
1397 if (templ
->target
== PIPE_TEXTURE_1D
||
1398 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1399 /* Only very thin and long 2D textures should benefit from
1400 * linear_aligned. */
1401 (templ
->width0
> 8 && templ
->height0
<= 2))
1402 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1404 /* Textures likely to be mapped often. */
1405 if (templ
->usage
== PIPE_USAGE_STAGING
||
1406 templ
->usage
== PIPE_USAGE_STREAM
)
1407 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1410 /* Make small textures 1D tiled. */
1411 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1412 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1413 return RADEON_SURF_MODE_1D
;
1415 /* The allocator will switch to 1D if needed. */
1416 return RADEON_SURF_MODE_2D
;
1419 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1420 const struct pipe_resource
*templ
)
1422 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1423 struct radeon_surf surface
= {0};
1424 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1425 bool tc_compatible_htile
=
1426 sscreen
->info
.chip_class
>= VI
&&
1427 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1428 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1429 !is_flushed_depth
&&
1430 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1431 util_format_is_depth_or_stencil(templ
->format
);
1435 r
= r600_init_surface(sscreen
, &surface
, templ
,
1436 r600_choose_tiling(sscreen
, templ
), 0, 0,
1437 false, false, is_flushed_depth
,
1438 tc_compatible_htile
);
1443 return (struct pipe_resource
*)
1444 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1447 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1448 const struct pipe_resource
*templ
,
1449 struct winsys_handle
*whandle
,
1452 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1453 struct pb_buffer
*buf
= NULL
;
1454 unsigned stride
= 0, offset
= 0;
1455 enum radeon_surf_mode array_mode
;
1456 struct radeon_surf surface
= {};
1458 struct radeon_bo_metadata metadata
= {};
1459 struct r600_texture
*rtex
;
1462 /* Support only 2D textures without mipmaps */
1463 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1464 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1467 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1471 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1472 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
1473 &array_mode
, &is_scanout
);
1475 r
= r600_init_surface(sscreen
, &surface
, templ
, array_mode
, stride
,
1476 offset
, true, is_scanout
, false, false);
1481 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1485 rtex
->resource
.b
.is_shared
= true;
1486 rtex
->resource
.external_usage
= usage
;
1488 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
1490 assert(rtex
->surface
.tile_swizzle
== 0);
1491 return &rtex
->resource
.b
.b
;
1494 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1495 struct pipe_resource
*texture
,
1496 struct r600_texture
**staging
)
1498 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1499 struct pipe_resource resource
;
1500 struct r600_texture
**flushed_depth_texture
= staging
?
1501 staging
: &rtex
->flushed_depth_texture
;
1502 enum pipe_format pipe_format
= texture
->format
;
1505 if (rtex
->flushed_depth_texture
)
1506 return true; /* it's ready */
1508 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1509 switch (pipe_format
) {
1510 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1511 /* Save memory by not allocating the S plane. */
1512 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1514 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1515 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1516 /* Save memory bandwidth by not copying the
1517 * stencil part during flush.
1519 * This potentially increases memory bandwidth
1520 * if an application uses both Z and S texturing
1521 * simultaneously (a flushed Z24S8 texture
1522 * would be stored compactly), but how often
1523 * does that really happen?
1525 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1529 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1530 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1532 /* DB->CB copies to an 8bpp surface don't work. */
1533 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1537 memset(&resource
, 0, sizeof(resource
));
1538 resource
.target
= texture
->target
;
1539 resource
.format
= pipe_format
;
1540 resource
.width0
= texture
->width0
;
1541 resource
.height0
= texture
->height0
;
1542 resource
.depth0
= texture
->depth0
;
1543 resource
.array_size
= texture
->array_size
;
1544 resource
.last_level
= texture
->last_level
;
1545 resource
.nr_samples
= texture
->nr_samples
;
1546 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1547 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1548 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1551 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1553 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1554 if (*flushed_depth_texture
== NULL
) {
1555 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1562 * Initialize the pipe_resource descriptor to be of the same size as the box,
1563 * which is supposed to hold a subregion of the texture "orig" at the given
1566 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1567 struct pipe_resource
*orig
,
1568 const struct pipe_box
*box
,
1569 unsigned level
, unsigned flags
)
1571 memset(res
, 0, sizeof(*res
));
1572 res
->format
= orig
->format
;
1573 res
->width0
= box
->width
;
1574 res
->height0
= box
->height
;
1576 res
->array_size
= 1;
1577 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1580 /* We must set the correct texture target and dimensions for a 3D box. */
1581 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1582 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1583 res
->array_size
= box
->depth
;
1585 res
->target
= PIPE_TEXTURE_2D
;
1589 static bool r600_can_invalidate_texture(struct si_screen
*sscreen
,
1590 struct r600_texture
*rtex
,
1591 unsigned transfer_usage
,
1592 const struct pipe_box
*box
)
1594 return !rtex
->resource
.b
.is_shared
&&
1595 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1596 rtex
->resource
.b
.b
.last_level
== 0 &&
1597 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1598 box
->x
, box
->y
, box
->z
,
1599 box
->width
, box
->height
,
1603 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1604 struct r600_texture
*rtex
)
1606 struct si_screen
*sscreen
= rctx
->screen
;
1608 /* There is no point in discarding depth and tiled buffers. */
1609 assert(!rtex
->is_depth
);
1610 assert(rtex
->surface
.is_linear
);
1612 /* Reallocate the buffer in the same pipe_resource. */
1613 si_alloc_resource(sscreen
, &rtex
->resource
);
1615 /* Initialize the CMASK base address (needed even without CMASK). */
1616 rtex
->cmask
.base_address_reg
=
1617 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1619 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1621 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1624 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1625 struct pipe_resource
*texture
,
1628 const struct pipe_box
*box
,
1629 struct pipe_transfer
**ptransfer
)
1631 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1632 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1633 struct r600_transfer
*trans
;
1634 struct r600_resource
*buf
;
1635 unsigned offset
= 0;
1637 bool use_staging_texture
= false;
1639 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1640 assert(box
->width
&& box
->height
&& box
->depth
);
1642 /* Depth textures use staging unconditionally. */
1643 if (!rtex
->is_depth
) {
1644 /* Degrade the tile mode if we get too many transfers on APUs.
1645 * On dGPUs, the staging texture is always faster.
1646 * Only count uploads that are at least 4x4 pixels large.
1648 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1650 box
->width
>= 4 && box
->height
>= 4 &&
1651 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1652 bool can_invalidate
=
1653 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1656 r600_reallocate_texture_inplace(rctx
, rtex
,
1661 /* Tiled textures need to be converted into a linear texture for CPU
1662 * access. The staging texture is always linear and is placed in GART.
1664 * Reading from VRAM or GTT WC is slow, always use the staging
1665 * texture in this case.
1667 * Use the staging texture for uploads if the underlying BO
1670 if (!rtex
->surface
.is_linear
)
1671 use_staging_texture
= true;
1672 else if (usage
& PIPE_TRANSFER_READ
)
1673 use_staging_texture
=
1674 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1675 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1676 /* Write & linear only: */
1677 else if (si_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1678 RADEON_USAGE_READWRITE
) ||
1679 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1680 RADEON_USAGE_READWRITE
)) {
1682 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1684 r600_texture_invalidate_storage(rctx
, rtex
);
1686 use_staging_texture
= true;
1690 trans
= CALLOC_STRUCT(r600_transfer
);
1693 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1694 trans
->b
.b
.level
= level
;
1695 trans
->b
.b
.usage
= usage
;
1696 trans
->b
.b
.box
= *box
;
1698 if (rtex
->is_depth
) {
1699 struct r600_texture
*staging_depth
;
1701 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1702 /* MSAA depth buffers need to be converted to single sample buffers.
1704 * Mapping MSAA depth buffers can occur if ReadPixels is called
1705 * with a multisample GLX visual.
1707 * First downsample the depth buffer to a temporary texture,
1708 * then decompress the temporary one to staging.
1710 * Only the region being mapped is transfered.
1712 struct pipe_resource resource
;
1714 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1716 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1717 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1722 if (usage
& PIPE_TRANSFER_READ
) {
1723 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1725 R600_ERR("failed to create a temporary depth texture\n");
1730 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1731 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1732 0, 0, 0, box
->depth
, 0, 0);
1733 pipe_resource_reference(&temp
, NULL
);
1736 /* Just get the strides. */
1737 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1739 &trans
->b
.b
.layer_stride
);
1741 /* XXX: only readback the rectangle which is being mapped? */
1742 /* XXX: when discard is true, no need to read back from depth texture */
1743 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1744 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1749 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1751 box
->z
, box
->z
+ box
->depth
- 1,
1754 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1757 &trans
->b
.b
.layer_stride
);
1760 trans
->staging
= (struct r600_resource
*)staging_depth
;
1761 buf
= trans
->staging
;
1762 } else if (use_staging_texture
) {
1763 struct pipe_resource resource
;
1764 struct r600_texture
*staging
;
1766 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1767 R600_RESOURCE_FLAG_TRANSFER
);
1768 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1769 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1771 /* Create the temporary texture. */
1772 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1774 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1778 trans
->staging
= &staging
->resource
;
1780 /* Just get the strides. */
1781 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1783 &trans
->b
.b
.layer_stride
);
1785 if (usage
& PIPE_TRANSFER_READ
)
1786 r600_copy_to_staging_texture(ctx
, trans
);
1788 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1790 buf
= trans
->staging
;
1792 /* the resource is mapped directly */
1793 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1795 &trans
->b
.b
.layer_stride
);
1796 buf
= &rtex
->resource
;
1799 if (!(map
= si_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1800 r600_resource_reference(&trans
->staging
, NULL
);
1805 *ptransfer
= &trans
->b
.b
;
1806 return map
+ offset
;
1809 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1810 struct pipe_transfer
* transfer
)
1812 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1813 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1814 struct pipe_resource
*texture
= transfer
->resource
;
1815 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1817 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1818 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1819 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1820 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1821 &rtransfer
->staging
->b
.b
, transfer
->level
,
1824 r600_copy_from_staging_texture(ctx
, rtransfer
);
1828 if (rtransfer
->staging
) {
1829 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1830 r600_resource_reference(&rtransfer
->staging
, NULL
);
1833 /* Heuristic for {upload, draw, upload, draw, ..}:
1835 * Flush the gfx IB if we've allocated too much texture storage.
1837 * The idea is that we don't want to build IBs that use too much
1838 * memory and put pressure on the kernel memory manager and we also
1839 * want to make temporary and invalidated buffers go idle ASAP to
1840 * decrease the total memory usage or make them reusable. The memory
1841 * usage will be slightly higher than given here because of the buffer
1842 * cache in the winsys.
1844 * The result is that the kernel memory manager is never a bottleneck.
1846 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1847 rctx
->gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
1848 rctx
->num_alloc_tex_transfer_bytes
= 0;
1851 pipe_resource_reference(&transfer
->resource
, NULL
);
1855 static const struct u_resource_vtbl r600_texture_vtbl
=
1857 NULL
, /* get_handle */
1858 r600_texture_destroy
, /* resource_destroy */
1859 r600_texture_transfer_map
, /* transfer_map */
1860 u_default_transfer_flush_region
, /* transfer_flush_region */
1861 r600_texture_transfer_unmap
, /* transfer_unmap */
1864 /* DCC channel type categories within which formats can be reinterpreted
1865 * while keeping the same DCC encoding. The swizzle must also match. */
1866 enum dcc_channel_type
{
1867 dcc_channel_float32
,
1870 dcc_channel_float16
,
1873 dcc_channel_uint_10_10_10_2
,
1876 dcc_channel_incompatible
,
1879 /* Return the type of DCC encoding. */
1880 static enum dcc_channel_type
1881 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1885 /* Find the first non-void channel. */
1886 for (i
= 0; i
< desc
->nr_channels
; i
++)
1887 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1889 if (i
== desc
->nr_channels
)
1890 return dcc_channel_incompatible
;
1892 switch (desc
->channel
[i
].size
) {
1894 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1895 return dcc_channel_float32
;
1896 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1897 return dcc_channel_uint32
;
1898 return dcc_channel_sint32
;
1900 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1901 return dcc_channel_float16
;
1902 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1903 return dcc_channel_uint16
;
1904 return dcc_channel_sint16
;
1906 return dcc_channel_uint_10_10_10_2
;
1908 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1909 return dcc_channel_uint8
;
1910 return dcc_channel_sint8
;
1912 return dcc_channel_incompatible
;
1916 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1917 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1918 enum pipe_format format2
)
1920 const struct util_format_description
*desc1
, *desc2
;
1921 enum dcc_channel_type type1
, type2
;
1924 if (format1
== format2
)
1927 desc1
= util_format_description(format1
);
1928 desc2
= util_format_description(format2
);
1930 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1933 /* Swizzles must be the same. */
1934 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1935 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1936 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1937 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1940 type1
= vi_get_dcc_channel_type(desc1
);
1941 type2
= vi_get_dcc_channel_type(desc2
);
1943 return type1
!= dcc_channel_incompatible
&&
1944 type2
!= dcc_channel_incompatible
&&
1948 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1950 enum pipe_format view_format
)
1952 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1954 return vi_dcc_enabled(rtex
, level
) &&
1955 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1958 /* This can't be merged with the above function, because
1959 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1960 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1961 struct pipe_resource
*tex
,
1963 enum pipe_format view_format
)
1965 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1967 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1968 if (!si_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1969 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1972 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1973 struct pipe_resource
*texture
,
1974 const struct pipe_surface
*templ
,
1975 unsigned width0
, unsigned height0
,
1976 unsigned width
, unsigned height
)
1978 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1983 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1984 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1986 pipe_reference_init(&surface
->base
.reference
, 1);
1987 pipe_resource_reference(&surface
->base
.texture
, texture
);
1988 surface
->base
.context
= pipe
;
1989 surface
->base
.format
= templ
->format
;
1990 surface
->base
.width
= width
;
1991 surface
->base
.height
= height
;
1992 surface
->base
.u
= templ
->u
;
1994 surface
->width0
= width0
;
1995 surface
->height0
= height0
;
1997 surface
->dcc_incompatible
=
1998 texture
->target
!= PIPE_BUFFER
&&
1999 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2001 return &surface
->base
;
2004 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
2005 struct pipe_resource
*tex
,
2006 const struct pipe_surface
*templ
)
2008 unsigned level
= templ
->u
.tex
.level
;
2009 unsigned width
= u_minify(tex
->width0
, level
);
2010 unsigned height
= u_minify(tex
->height0
, level
);
2011 unsigned width0
= tex
->width0
;
2012 unsigned height0
= tex
->height0
;
2014 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2015 const struct util_format_description
*tex_desc
2016 = util_format_description(tex
->format
);
2017 const struct util_format_description
*templ_desc
2018 = util_format_description(templ
->format
);
2020 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2022 /* Adjust size of surface if and only if the block width or
2023 * height is changed. */
2024 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2025 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2026 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2027 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2029 width
= nblks_x
* templ_desc
->block
.width
;
2030 height
= nblks_y
* templ_desc
->block
.height
;
2032 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2033 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2037 return si_create_surface_custom(pipe
, tex
, templ
,
2042 static void r600_surface_destroy(struct pipe_context
*pipe
,
2043 struct pipe_surface
*surface
)
2045 pipe_resource_reference(&surface
->texture
, NULL
);
2049 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2051 const struct util_format_description
*desc
= util_format_description(format
);
2053 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2055 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2056 return V_028C70_SWAP_STD
;
2058 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2061 switch (desc
->nr_channels
) {
2063 if (HAS_SWIZZLE(0,X
))
2064 return V_028C70_SWAP_STD
; /* X___ */
2065 else if (HAS_SWIZZLE(3,X
))
2066 return V_028C70_SWAP_ALT_REV
; /* ___X */
2069 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2070 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2071 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2072 return V_028C70_SWAP_STD
; /* XY__ */
2073 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2074 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2075 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2077 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2078 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2079 return V_028C70_SWAP_ALT
; /* X__Y */
2080 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2081 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2084 if (HAS_SWIZZLE(0,X
))
2085 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2086 else if (HAS_SWIZZLE(0,Z
))
2087 return V_028C70_SWAP_STD_REV
; /* ZYX */
2090 /* check the middle channels, the 1st and 4th channel can be NONE */
2091 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2092 return V_028C70_SWAP_STD
; /* XYZW */
2093 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2094 return V_028C70_SWAP_STD_REV
; /* WZYX */
2095 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2096 return V_028C70_SWAP_ALT
; /* ZYXW */
2097 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2100 return V_028C70_SWAP_ALT_REV
;
2102 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2109 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2111 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2116 if (rctx
->dcc_stats
[slot
].query_active
)
2117 vi_separate_dcc_stop_query(&rctx
->b
,
2118 rctx
->dcc_stats
[slot
].tex
);
2120 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2121 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2122 rctx
->b
.destroy_query(&rctx
->b
,
2123 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2124 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2127 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2131 * Return the per-context slot where DCC statistics queries for the texture live.
2133 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2134 struct r600_texture
*tex
)
2136 int i
, empty_slot
= -1;
2138 /* Remove zombie textures (textures kept alive by this array only). */
2139 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2140 if (rctx
->dcc_stats
[i
].tex
&&
2141 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2142 vi_dcc_clean_up_context_slot(rctx
, i
);
2144 /* Find the texture. */
2145 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2146 /* Return if found. */
2147 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2148 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2152 /* Record the first seen empty slot. */
2153 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2157 /* Not found. Remove the oldest member to make space in the array. */
2158 if (empty_slot
== -1) {
2159 int oldest_slot
= 0;
2161 /* Find the oldest slot. */
2162 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2163 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2164 rctx
->dcc_stats
[i
].last_use_timestamp
)
2167 /* Clean up the oldest slot. */
2168 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2169 empty_slot
= oldest_slot
;
2172 /* Add the texture to the new slot. */
2173 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2174 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2178 static struct pipe_query
*
2179 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2181 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2182 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2184 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2185 return (struct pipe_query
*)query
;
2189 * Called when binding a color buffer.
2191 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2192 struct r600_texture
*tex
)
2194 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2195 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2197 assert(!rctx
->dcc_stats
[i
].query_active
);
2199 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2200 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2202 /* begin or resume the query */
2203 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2204 rctx
->dcc_stats
[i
].query_active
= true;
2208 * Called when unbinding a color buffer.
2210 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2211 struct r600_texture
*tex
)
2213 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2214 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2216 assert(rctx
->dcc_stats
[i
].query_active
);
2217 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2219 /* pause or end the query */
2220 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2221 rctx
->dcc_stats
[i
].query_active
= false;
2224 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2226 /* The minimum number of fullscreen draws per frame that is required
2228 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2231 /* Called by fast clear. */
2232 void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2233 struct r600_texture
*tex
)
2235 /* The intent is to use this with shared displayable back buffers,
2236 * but it's not strictly limited only to them.
2238 if (!tex
->resource
.b
.is_shared
||
2239 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2240 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2241 tex
->resource
.b
.b
.last_level
> 0 ||
2242 !tex
->surface
.dcc_size
)
2245 if (tex
->dcc_offset
)
2246 return; /* already enabled */
2248 /* Enable the DCC stat gathering. */
2249 if (!tex
->dcc_gather_statistics
) {
2250 tex
->dcc_gather_statistics
= true;
2251 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2254 if (!vi_should_enable_separate_dcc(tex
))
2255 return; /* stats show that DCC decompression is too expensive */
2257 assert(tex
->surface
.num_dcc_levels
);
2258 assert(!tex
->dcc_separate_buffer
);
2260 r600_texture_discard_cmask(rctx
->screen
, tex
);
2262 /* Get a DCC buffer. */
2263 if (tex
->last_dcc_separate_buffer
) {
2264 assert(tex
->dcc_gather_statistics
);
2265 assert(!tex
->dcc_separate_buffer
);
2266 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2267 tex
->last_dcc_separate_buffer
= NULL
;
2269 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2270 si_aligned_buffer_create(rctx
->b
.screen
,
2271 R600_RESOURCE_FLAG_UNMAPPABLE
,
2273 tex
->surface
.dcc_size
,
2274 tex
->surface
.dcc_alignment
);
2275 if (!tex
->dcc_separate_buffer
)
2279 /* dcc_offset is the absolute GPUVM address. */
2280 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2282 /* no need to flag anything since this is called by fast clear that
2283 * flags framebuffer state
2288 * Called by pipe_context::flush_resource, the place where DCC decompression
2291 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2292 struct r600_texture
*tex
)
2294 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2295 struct pipe_query
*tmp
;
2296 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2297 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2298 bool disable
= false;
2300 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2301 union pipe_query_result result
;
2303 /* Read the results. */
2304 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2306 si_query_hw_reset_buffers(rctx
,
2307 (struct r600_query_hw
*)
2308 rctx
->dcc_stats
[i
].ps_stats
[2]);
2310 /* Compute the approximate number of fullscreen draws. */
2311 tex
->ps_draw_ratio
=
2312 result
.pipeline_statistics
.ps_invocations
/
2313 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2314 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2316 disable
= tex
->dcc_separate_buffer
&&
2317 !vi_should_enable_separate_dcc(tex
);
2320 tex
->num_slow_clears
= 0;
2322 /* stop the statistics query for ps_stats[0] */
2324 vi_separate_dcc_stop_query(ctx
, tex
);
2326 /* Move the queries in the queue by one. */
2327 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2328 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2329 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2330 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2332 /* create and start a new query as ps_stats[0] */
2334 vi_separate_dcc_start_query(ctx
, tex
);
2337 assert(!tex
->last_dcc_separate_buffer
);
2338 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2339 tex
->dcc_separate_buffer
= NULL
;
2340 tex
->dcc_offset
= 0;
2341 /* no need to flag anything since this is called after
2342 * decompression that re-sets framebuffer state
2347 static struct pipe_memory_object
*
2348 r600_memobj_from_handle(struct pipe_screen
*screen
,
2349 struct winsys_handle
*whandle
,
2352 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2353 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2354 struct pb_buffer
*buf
= NULL
;
2355 uint32_t stride
, offset
;
2360 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2367 memobj
->b
.dedicated
= dedicated
;
2369 memobj
->stride
= stride
;
2370 memobj
->offset
= offset
;
2372 return (struct pipe_memory_object
*)memobj
;
2377 r600_memobj_destroy(struct pipe_screen
*screen
,
2378 struct pipe_memory_object
*_memobj
)
2380 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2382 pb_reference(&memobj
->buf
, NULL
);
2386 static struct pipe_resource
*
2387 r600_texture_from_memobj(struct pipe_screen
*screen
,
2388 const struct pipe_resource
*templ
,
2389 struct pipe_memory_object
*_memobj
,
2393 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2394 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2395 struct r600_texture
*rtex
;
2396 struct radeon_surf surface
= {};
2397 struct radeon_bo_metadata metadata
= {};
2398 enum radeon_surf_mode array_mode
;
2400 struct pb_buffer
*buf
= NULL
;
2402 if (memobj
->b
.dedicated
) {
2403 sscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2404 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
2405 &array_mode
, &is_scanout
);
2408 * The bo metadata is unset for un-dedicated images. So we fall
2409 * back to linear. See answer to question 5 of the
2410 * VK_KHX_external_memory spec for some details.
2412 * It is possible that this case isn't going to work if the
2413 * surface pitch isn't correctly aligned by default.
2415 * In order to support it correctly we require multi-image
2416 * metadata to be syncrhonized between radv and radeonsi. The
2417 * semantics of associating multiple image metadata to a memory
2418 * object on the vulkan export side are not concretely defined
2421 * All the use cases we are aware of at the moment for memory
2422 * objects use dedicated allocations. So lets keep the initial
2423 * implementation simple.
2425 * A possible alternative is to attempt to reconstruct the
2426 * tiling information when the TexParameter TEXTURE_TILING_EXT
2429 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2434 r
= r600_init_surface(sscreen
, &surface
, templ
,
2435 array_mode
, memobj
->stride
,
2436 offset
, true, is_scanout
,
2441 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2445 /* r600_texture_create_object doesn't increment refcount of
2446 * memobj->buf, so increment it here.
2448 pb_reference(&buf
, memobj
->buf
);
2450 rtex
->resource
.b
.is_shared
= true;
2451 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2453 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
2455 return &rtex
->resource
.b
.b
;
2458 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2459 struct pipe_resource
*resource
,
2462 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2464 /* Buffers only support the linear flag. */
2465 if (resource
->target
== PIPE_BUFFER
)
2466 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2468 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2471 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2474 /* TODO: PIPE_BIND_CURSOR - do we care? */
2478 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2480 sscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2481 sscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2482 sscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2483 sscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2484 sscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2485 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2488 void si_init_context_texture_functions(struct r600_common_context
*rctx
)
2490 rctx
->b
.create_surface
= r600_create_surface
;
2491 rctx
->b
.surface_destroy
= r600_surface_destroy
;