2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "radeonsi/si_pipe.h"
26 #include "r600_query.h"
27 #include "util/u_format.h"
28 #include "util/u_log.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/u_resource.h"
32 #include "util/u_surface.h"
33 #include "util/os_time.h"
36 #include "state_tracker/drm_driver.h"
37 #include "amd/common/sid.h"
39 static enum radeon_surf_mode
40 r600_choose_tiling(struct si_screen
*sscreen
,
41 const struct pipe_resource
*templ
);
44 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
58 /* MSAA: Blits don't exist in the real world. */
59 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
60 rdst
->resource
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (rsrc
->is_depth
|| rdst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(rsrc
, src_level
) ||
75 vi_dcc_enabled(rdst
, dst_level
))
79 * src: Both texture and SDMA paths need decompression. Use SDMA.
80 * dst: If overwriting the whole texture, discard CMASK and use
81 * SDMA. Otherwise, use the 3D path.
83 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
84 /* The CMASK clear is only enabled for the first level. */
85 assert(dst_level
== 0);
86 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
87 dstx
, dsty
, dstz
, src_box
->width
,
88 src_box
->height
, src_box
->depth
))
91 si_texture_discard_cmask(rctx
->screen
, rdst
);
94 /* All requirements are met. Prepare textures for SDMA. */
95 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
96 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
98 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
99 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
104 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
105 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
106 struct pipe_resource
*dst
,
108 unsigned dstx
, unsigned dsty
, unsigned dstz
,
109 struct pipe_resource
*src
,
111 const struct pipe_box
*src_box
)
113 struct pipe_blit_info blit
;
115 memset(&blit
, 0, sizeof(blit
));
116 blit
.src
.resource
= src
;
117 blit
.src
.format
= src
->format
;
118 blit
.src
.level
= src_level
;
119 blit
.src
.box
= *src_box
;
120 blit
.dst
.resource
= dst
;
121 blit
.dst
.format
= dst
->format
;
122 blit
.dst
.level
= dst_level
;
123 blit
.dst
.box
.x
= dstx
;
124 blit
.dst
.box
.y
= dsty
;
125 blit
.dst
.box
.z
= dstz
;
126 blit
.dst
.box
.width
= src_box
->width
;
127 blit
.dst
.box
.height
= src_box
->height
;
128 blit
.dst
.box
.depth
= src_box
->depth
;
129 blit
.mask
= util_format_get_mask(src
->format
) &
130 util_format_get_mask(dst
->format
);
131 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
134 pipe
->blit(pipe
, &blit
);
138 /* Copy from a full GPU texture to a transfer's staging one. */
139 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
141 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
142 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
143 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
144 struct pipe_resource
*src
= transfer
->resource
;
146 if (src
->nr_samples
> 1) {
147 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
148 src
, transfer
->level
, &transfer
->box
);
152 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
156 /* Copy from a transfer's staging texture to a full GPU one. */
157 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
159 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
160 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
161 struct pipe_resource
*dst
= transfer
->resource
;
162 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
163 struct pipe_box sbox
;
165 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
167 if (dst
->nr_samples
> 1) {
168 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
169 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
174 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
175 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
179 static unsigned r600_texture_get_offset(struct si_screen
*sscreen
,
180 struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
,
183 unsigned *layer_stride
)
185 if (sscreen
->info
.chip_class
>= GFX9
) {
186 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
187 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
192 /* Each texture is an array of slices. Each slice is an array
193 * of mipmap levels. */
194 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
195 rtex
->surface
.u
.gfx9
.offset
[level
] +
196 (box
->y
/ rtex
->surface
.blk_h
*
197 rtex
->surface
.u
.gfx9
.surf_pitch
+
198 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
200 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
202 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
203 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
206 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
208 /* Each texture is an array of mipmap levels. Each level is
209 * an array of slices. */
210 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
211 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
212 (box
->y
/ rtex
->surface
.blk_h
*
213 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
214 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
218 static int r600_init_surface(struct si_screen
*sscreen
,
219 struct radeon_surf
*surface
,
220 const struct pipe_resource
*ptex
,
221 enum radeon_surf_mode array_mode
,
222 unsigned pitch_in_bytes_override
,
226 bool is_flushed_depth
,
227 bool tc_compatible_htile
)
229 const struct util_format_description
*desc
=
230 util_format_description(ptex
->format
);
231 bool is_depth
, is_stencil
;
233 unsigned i
, bpe
, flags
= 0;
235 is_depth
= util_format_has_depth(desc
);
236 is_stencil
= util_format_has_stencil(desc
);
238 if (!is_flushed_depth
&&
239 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
240 bpe
= 4; /* stencil is allocated separately on evergreen */
242 bpe
= util_format_get_blocksize(ptex
->format
);
243 assert(util_is_power_of_two(bpe
));
246 if (!is_flushed_depth
&& is_depth
) {
247 flags
|= RADEON_SURF_ZBUFFER
;
249 if (tc_compatible_htile
&&
250 (sscreen
->info
.chip_class
>= GFX9
||
251 array_mode
== RADEON_SURF_MODE_2D
)) {
252 /* TC-compatible HTILE only supports Z32_FLOAT.
253 * GFX9 also supports Z16_UNORM.
254 * On VI, promote Z16 to Z32. DB->CB copies will convert
255 * the format for transfers.
257 if (sscreen
->info
.chip_class
== VI
)
260 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
264 flags
|= RADEON_SURF_SBUFFER
;
267 if (sscreen
->info
.chip_class
>= VI
&&
268 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
269 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
270 /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
271 (ptex
->nr_samples
>= 2 &&
272 (!sscreen
->dcc_msaa_allowed
|| ptex
->array_size
> 1))))
273 flags
|= RADEON_SURF_DISABLE_DCC
;
275 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
276 /* This should catch bugs in gallium users setting incorrect flags. */
277 assert(ptex
->nr_samples
<= 1 &&
278 ptex
->array_size
== 1 &&
280 ptex
->last_level
== 0 &&
281 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
283 flags
|= RADEON_SURF_SCANOUT
;
286 if (ptex
->bind
& PIPE_BIND_SHARED
)
287 flags
|= RADEON_SURF_SHAREABLE
;
289 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
290 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
291 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
293 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
294 array_mode
, surface
);
299 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
301 if (sscreen
->info
.chip_class
>= GFX9
) {
303 surface
->u
.gfx9
.surf_pitch
= pitch
;
304 surface
->u
.gfx9
.surf_slice_size
=
305 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
307 surface
->u
.gfx9
.surf_offset
= offset
;
310 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
311 surface
->u
.legacy
.level
[0].slice_size_dw
=
312 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
315 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
316 surface
->u
.legacy
.level
[i
].offset
+= offset
;
322 static void r600_texture_init_metadata(struct si_screen
*sscreen
,
323 struct r600_texture
*rtex
,
324 struct radeon_bo_metadata
*metadata
)
326 struct radeon_surf
*surface
= &rtex
->surface
;
328 memset(metadata
, 0, sizeof(*metadata
));
330 if (sscreen
->info
.chip_class
>= GFX9
) {
331 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
333 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
334 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
335 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
336 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
337 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
338 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
339 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
340 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
341 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
342 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
343 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
344 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
348 static void r600_surface_import_metadata(struct si_screen
*sscreen
,
349 struct radeon_surf
*surf
,
350 struct radeon_bo_metadata
*metadata
,
351 enum radeon_surf_mode
*array_mode
,
354 if (sscreen
->info
.chip_class
>= GFX9
) {
355 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
356 *array_mode
= RADEON_SURF_MODE_2D
;
358 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
360 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
361 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
363 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
365 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
366 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
367 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
368 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
369 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
370 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
372 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
373 *array_mode
= RADEON_SURF_MODE_2D
;
374 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
375 *array_mode
= RADEON_SURF_MODE_1D
;
377 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
379 *is_scanout
= metadata
->u
.legacy
.scanout
;
383 void si_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
384 struct r600_texture
*rtex
)
386 struct si_screen
*sscreen
= rctx
->screen
;
387 struct pipe_context
*ctx
= &rctx
->b
;
389 if (ctx
== sscreen
->aux_context
)
390 mtx_lock(&sscreen
->aux_context_lock
);
392 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
393 ctx
->flush(ctx
, NULL
, 0);
395 if (ctx
== sscreen
->aux_context
)
396 mtx_unlock(&sscreen
->aux_context_lock
);
399 void si_texture_discard_cmask(struct si_screen
*sscreen
,
400 struct r600_texture
*rtex
)
402 if (!rtex
->cmask
.size
)
405 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
408 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
409 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
410 rtex
->dirty_level_mask
= 0;
412 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
414 if (rtex
->cmask_buffer
!= &rtex
->resource
)
415 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
417 /* Notify all contexts about the change. */
418 p_atomic_inc(&sscreen
->dirty_tex_counter
);
419 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
422 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
424 /* We can't disable DCC if it can be written by another process. */
425 return rtex
->dcc_offset
&&
426 (!rtex
->resource
.b
.is_shared
||
427 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
430 static bool r600_texture_discard_dcc(struct si_screen
*sscreen
,
431 struct r600_texture
*rtex
)
433 if (!r600_can_disable_dcc(rtex
))
436 assert(rtex
->dcc_separate_buffer
== NULL
);
439 rtex
->dcc_offset
= 0;
441 /* Notify all contexts about the change. */
442 p_atomic_inc(&sscreen
->dirty_tex_counter
);
447 * Disable DCC for the texture. (first decompress, then discard metadata).
449 * There is unresolved multi-context synchronization issue between
450 * screen::aux_context and the current context. If applications do this with
451 * multiple contexts, it's already undefined behavior for them and we don't
452 * have to worry about that. The scenario is:
454 * If context 1 disables DCC and context 2 has queued commands that write
455 * to the texture via CB with DCC enabled, and the order of operations is
457 * context 2 queues draw calls rendering to the texture, but doesn't flush
458 * context 1 disables DCC and flushes
459 * context 1 & 2 reset descriptors and FB state
460 * context 2 flushes (new compressed tiles written by the draw calls)
461 * context 1 & 2 read garbage, because DCC is disabled, yet there are
464 * \param rctx the current context if you have one, or rscreen->aux_context
467 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
468 struct r600_texture
*rtex
)
470 struct si_screen
*sscreen
= rctx
->screen
;
472 if (!r600_can_disable_dcc(rtex
))
475 if (&rctx
->b
== sscreen
->aux_context
)
476 mtx_lock(&sscreen
->aux_context_lock
);
478 /* Decompress DCC. */
479 rctx
->decompress_dcc(&rctx
->b
, rtex
);
480 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
482 if (&rctx
->b
== sscreen
->aux_context
)
483 mtx_unlock(&sscreen
->aux_context_lock
);
485 return r600_texture_discard_dcc(sscreen
, rtex
);
488 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
489 struct r600_texture
*rtex
,
490 unsigned new_bind_flag
,
491 bool invalidate_storage
)
493 struct pipe_screen
*screen
= rctx
->b
.screen
;
494 struct r600_texture
*new_tex
;
495 struct pipe_resource templ
= rtex
->resource
.b
.b
;
498 templ
.bind
|= new_bind_flag
;
500 if (rtex
->resource
.b
.is_shared
)
503 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
504 if (rtex
->surface
.is_linear
)
507 /* This fails with MSAA, depth, and compressed textures. */
508 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
509 RADEON_SURF_MODE_LINEAR_ALIGNED
)
513 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
517 /* Copy the pixels to the new texture. */
518 if (!invalidate_storage
) {
519 for (i
= 0; i
<= templ
.last_level
; i
++) {
523 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
524 util_num_layers(&templ
, i
), &box
);
526 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
527 &rtex
->resource
.b
.b
, i
, &box
);
531 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
532 si_texture_discard_cmask(rctx
->screen
, rtex
);
533 r600_texture_discard_dcc(rctx
->screen
, rtex
);
536 /* Replace the structure fields of rtex. */
537 rtex
->resource
.b
.b
.bind
= templ
.bind
;
538 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
539 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
540 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
541 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
542 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
543 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
544 rtex
->resource
.domains
= new_tex
->resource
.domains
;
545 rtex
->resource
.flags
= new_tex
->resource
.flags
;
546 rtex
->size
= new_tex
->size
;
547 rtex
->db_render_format
= new_tex
->db_render_format
;
548 rtex
->db_compatible
= new_tex
->db_compatible
;
549 rtex
->can_sample_z
= new_tex
->can_sample_z
;
550 rtex
->can_sample_s
= new_tex
->can_sample_s
;
551 rtex
->surface
= new_tex
->surface
;
552 rtex
->fmask
= new_tex
->fmask
;
553 rtex
->cmask
= new_tex
->cmask
;
554 rtex
->cb_color_info
= new_tex
->cb_color_info
;
555 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
556 rtex
->htile_offset
= new_tex
->htile_offset
;
557 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
558 rtex
->depth_cleared
= new_tex
->depth_cleared
;
559 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
560 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
561 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
563 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
564 assert(!rtex
->htile_offset
);
565 assert(!rtex
->cmask
.size
);
566 assert(!rtex
->fmask
.size
);
567 assert(!rtex
->dcc_offset
);
568 assert(!rtex
->is_depth
);
571 r600_texture_reference(&new_tex
, NULL
);
573 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
576 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
578 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
581 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
582 struct r600_texture
*rtex
,
583 struct radeon_bo_metadata
*md
)
585 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
586 static const unsigned char swizzle
[] = {
593 bool is_array
= util_texture_is_array(res
->target
);
595 /* DRM 2.x.x doesn't support this. */
596 if (sscreen
->info
.drm_major
!= 3)
599 assert(rtex
->dcc_separate_buffer
== NULL
);
600 assert(rtex
->fmask
.size
== 0);
602 /* Metadata image format format version 1:
603 * [0] = 1 (metadata format identifier)
604 * [1] = (VENDOR_ID << 16) | PCI_ID
605 * [2:9] = image descriptor for the whole resource
606 * [2] is always 0, because the base address is cleared
607 * [9] is the DCC offset bits [39:8] from the beginning of
609 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
612 md
->metadata
[0] = 1; /* metadata image format version 1 */
614 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
615 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
617 si_make_texture_descriptor(sscreen
, rtex
, true,
618 res
->target
, res
->format
,
619 swizzle
, 0, res
->last_level
, 0,
620 is_array
? res
->array_size
- 1 : 0,
621 res
->width0
, res
->height0
, res
->depth0
,
624 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
625 0, 0, rtex
->surface
.blk_w
, false, desc
);
627 /* Clear the base address and set the relative DCC offset. */
629 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
630 desc
[7] = rtex
->dcc_offset
>> 8;
632 /* Dwords [2:9] contain the image descriptor. */
633 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
634 md
->size_metadata
= 10 * 4;
636 /* Dwords [10:..] contain the mipmap level offsets. */
637 if (sscreen
->info
.chip_class
<= VI
) {
638 for (i
= 0; i
<= res
->last_level
; i
++)
639 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
641 md
->size_metadata
+= (1 + res
->last_level
) * 4;
645 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
646 struct r600_texture
*rtex
,
647 struct radeon_bo_metadata
*md
)
649 uint32_t *desc
= &md
->metadata
[2];
651 if (sscreen
->info
.chip_class
< VI
)
654 /* Return if DCC is enabled. The texture should be set up with it
657 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
658 md
->metadata
[0] != 0 &&
659 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
660 G_008F28_COMPRESSION_EN(desc
[6])) {
661 rtex
->dcc_offset
= (uint64_t)desc
[7] << 8;
665 /* Disable DCC. These are always set by texture_from_handle and must
668 rtex
->dcc_offset
= 0;
671 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
672 struct pipe_context
*ctx
,
673 struct pipe_resource
*resource
,
674 struct winsys_handle
*whandle
,
677 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
678 struct r600_common_context
*rctx
;
679 struct r600_resource
*res
= (struct r600_resource
*)resource
;
680 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
681 struct radeon_bo_metadata metadata
;
682 bool update_metadata
= false;
683 unsigned stride
, offset
, slice_size
;
686 ctx
= threaded_context_unwrap_sync(ctx
);
687 rctx
= (struct r600_common_context
*)(ctx
? ctx
: sscreen
->aux_context
);
689 if (resource
->target
!= PIPE_BUFFER
) {
690 /* This is not supported now, but it might be required for OpenCL
691 * interop in the future.
693 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
696 /* Move a suballocated texture into a non-suballocated allocation. */
697 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
698 rtex
->surface
.tile_swizzle
||
699 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
700 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
701 assert(!res
->b
.is_shared
);
702 r600_reallocate_texture_inplace(rctx
, rtex
,
703 PIPE_BIND_SHARED
, false);
705 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
706 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
707 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
708 assert(rtex
->surface
.tile_swizzle
== 0);
711 /* Since shader image stores don't support DCC on VI,
712 * disable it for external clients that want write
715 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
716 if (si_texture_disable_dcc(rctx
, rtex
)) {
717 update_metadata
= true;
718 /* si_texture_disable_dcc flushes the context */
723 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
724 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
725 /* Eliminate fast clear (both CMASK and DCC) */
726 si_eliminate_fast_color_clear(rctx
, rtex
);
727 /* eliminate_fast_color_clear flushes the context */
730 /* Disable CMASK if flush_resource isn't going
733 if (rtex
->cmask
.size
)
734 si_texture_discard_cmask(sscreen
, rtex
);
738 if (!res
->b
.is_shared
|| update_metadata
) {
739 r600_texture_init_metadata(sscreen
, rtex
, &metadata
);
740 si_query_opaque_metadata(sscreen
, rtex
, &metadata
);
742 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
745 if (sscreen
->info
.chip_class
>= GFX9
) {
746 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
747 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
749 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
751 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
752 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
754 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
757 /* Buffer exports are for the OpenCL interop. */
758 /* Move a suballocated buffer into a non-suballocated allocation. */
759 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
760 /* A DMABUF export always fails if the BO is local. */
761 rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
) {
762 assert(!res
->b
.is_shared
);
764 /* Allocate a new buffer with PIPE_BIND_SHARED. */
765 struct pipe_resource templ
= res
->b
.b
;
766 templ
.bind
|= PIPE_BIND_SHARED
;
768 struct pipe_resource
*newb
=
769 screen
->resource_create(screen
, &templ
);
773 /* Copy the old buffer contents to the new one. */
775 u_box_1d(0, newb
->width0
, &box
);
776 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
779 /* Move the new buffer storage to the old pipe_resource. */
780 si_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
781 pipe_resource_reference(&newb
, NULL
);
783 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
784 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
794 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
796 if (res
->b
.is_shared
) {
797 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
800 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
801 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
802 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
804 res
->b
.is_shared
= true;
805 res
->external_usage
= usage
;
808 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
809 slice_size
, whandle
);
812 static void r600_texture_destroy(struct pipe_screen
*screen
,
813 struct pipe_resource
*ptex
)
815 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
816 struct r600_resource
*resource
= &rtex
->resource
;
818 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
820 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
821 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
823 pb_reference(&resource
->buf
, NULL
);
824 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
825 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
829 static const struct u_resource_vtbl r600_texture_vtbl
;
831 /* The number of samples can be specified independently of the texture. */
832 void si_texture_get_fmask_info(struct si_screen
*sscreen
,
833 struct r600_texture
*rtex
,
835 struct r600_fmask_info
*out
)
837 /* FMASK is allocated like an ordinary texture. */
838 struct pipe_resource templ
= rtex
->resource
.b
.b
;
839 struct radeon_surf fmask
= {};
842 memset(out
, 0, sizeof(*out
));
844 if (sscreen
->info
.chip_class
>= GFX9
) {
845 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
846 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
850 templ
.nr_samples
= 1;
851 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
853 switch (nr_samples
) {
862 R600_ERR("Invalid sample count for FMASK allocation.\n");
866 if (sscreen
->ws
->surface_init(sscreen
->ws
, &templ
, flags
, bpe
,
867 RADEON_SURF_MODE_2D
, &fmask
)) {
868 R600_ERR("Got error in surface_init while allocating FMASK.\n");
872 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
874 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
875 if (out
->slice_tile_max
)
876 out
->slice_tile_max
-= 1;
878 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
879 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
880 out
->bank_height
= fmask
.u
.legacy
.bankh
;
881 out
->tile_swizzle
= fmask
.tile_swizzle
;
882 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
883 out
->size
= fmask
.surf_size
;
886 static void r600_texture_allocate_fmask(struct si_screen
*sscreen
,
887 struct r600_texture
*rtex
)
889 si_texture_get_fmask_info(sscreen
, rtex
,
890 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
892 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
893 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
896 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
897 struct r600_texture
*rtex
,
898 struct r600_cmask_info
*out
)
900 unsigned pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
901 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
902 unsigned cl_width
, cl_height
;
904 if (sscreen
->info
.chip_class
>= GFX9
) {
905 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
906 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
923 case 16: /* Hawaii */
932 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
934 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
935 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
936 unsigned slice_elements
= (width
* height
) / (8*8);
938 /* Each element of CMASK is a nibble. */
939 unsigned slice_bytes
= slice_elements
/ 2;
941 out
->slice_tile_max
= (width
* height
) / (128*128);
942 if (out
->slice_tile_max
)
943 out
->slice_tile_max
-= 1;
945 out
->alignment
= MAX2(256, base_align
);
946 out
->size
= util_num_layers(&rtex
->resource
.b
.b
, 0) *
947 align(slice_bytes
, base_align
);
950 static void r600_texture_allocate_cmask(struct si_screen
*sscreen
,
951 struct r600_texture
*rtex
)
953 si_texture_get_cmask_info(sscreen
, rtex
, &rtex
->cmask
);
955 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
956 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
958 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
961 static void r600_texture_get_htile_size(struct si_screen
*sscreen
,
962 struct r600_texture
*rtex
)
964 unsigned cl_width
, cl_height
, width
, height
;
965 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
966 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
968 assert(sscreen
->info
.chip_class
<= VI
);
970 rtex
->surface
.htile_size
= 0;
972 /* HTILE is broken with 1D tiling on old kernels and CIK. */
973 if (sscreen
->info
.chip_class
>= CIK
&&
974 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
975 sscreen
->info
.drm_major
== 2 && sscreen
->info
.drm_minor
< 38)
978 /* Overalign HTILE on P2 configs to work around GPU hangs in
979 * piglit/depthstencil-render-miplevels 585.
981 * This has been confirmed to help Kabini & Stoney, where the hangs
982 * are always reproducible. I think I have seen the test hang
983 * on Carrizo too, though it was very rare there.
985 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
1014 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
1015 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
1017 slice_elements
= (width
* height
) / (8 * 8);
1018 slice_bytes
= slice_elements
* 4;
1020 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1021 base_align
= num_pipes
* pipe_interleave_bytes
;
1023 rtex
->surface
.htile_alignment
= base_align
;
1024 rtex
->surface
.htile_size
=
1025 util_num_layers(&rtex
->resource
.b
.b
, 0) *
1026 align(slice_bytes
, base_align
);
1029 static void r600_texture_allocate_htile(struct si_screen
*sscreen
,
1030 struct r600_texture
*rtex
)
1032 if (sscreen
->info
.chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
1033 r600_texture_get_htile_size(sscreen
, rtex
);
1035 if (!rtex
->surface
.htile_size
)
1038 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
1039 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
1042 void si_print_texture_info(struct si_screen
*sscreen
,
1043 struct r600_texture
*rtex
, struct u_log_context
*log
)
1047 /* Common parameters. */
1048 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1049 "blk_h=%u, array_size=%u, last_level=%u, "
1050 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1051 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
1052 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1053 rtex
->surface
.blk_h
,
1054 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
1055 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
1056 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
1058 if (sscreen
->info
.chip_class
>= GFX9
) {
1059 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1060 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1061 rtex
->surface
.surf_size
,
1062 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1063 rtex
->surface
.surf_alignment
,
1064 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1065 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1066 rtex
->surface
.u
.gfx9
.surf_pitch
);
1068 if (rtex
->fmask
.size
) {
1069 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1070 "alignment=%u, swmode=%u, epitch=%u\n",
1072 rtex
->surface
.u
.gfx9
.fmask_size
,
1073 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1074 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1075 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1078 if (rtex
->cmask
.size
) {
1079 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1080 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1082 rtex
->surface
.u
.gfx9
.cmask_size
,
1083 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1084 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1085 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1088 if (rtex
->htile_offset
) {
1089 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1090 "rb_aligned=%u, pipe_aligned=%u\n",
1092 rtex
->surface
.htile_size
,
1093 rtex
->surface
.htile_alignment
,
1094 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1095 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1098 if (rtex
->dcc_offset
) {
1099 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1100 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1101 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1102 rtex
->surface
.dcc_alignment
,
1103 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1104 rtex
->surface
.num_dcc_levels
);
1107 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1108 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1109 rtex
->surface
.u
.gfx9
.stencil_offset
,
1110 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1111 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1116 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1117 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1118 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1119 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1120 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1121 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1123 if (rtex
->fmask
.size
)
1124 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1125 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1126 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1127 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1128 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1130 if (rtex
->cmask
.size
)
1131 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1132 "slice_tile_max=%u\n",
1133 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1134 rtex
->cmask
.slice_tile_max
);
1136 if (rtex
->htile_offset
)
1137 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1138 "alignment=%u, TC_compatible = %u\n",
1139 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1140 rtex
->surface
.htile_alignment
,
1141 rtex
->tc_compatible_htile
);
1143 if (rtex
->dcc_offset
) {
1144 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1145 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1146 rtex
->surface
.dcc_alignment
);
1147 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1148 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1149 "fast_clear_size=%u\n",
1150 i
, i
< rtex
->surface
.num_dcc_levels
,
1151 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1152 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1155 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1156 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1157 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1158 "mode=%u, tiling_index = %u\n",
1159 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1160 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1161 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1162 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1163 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1164 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1165 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1166 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1167 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1169 if (rtex
->surface
.has_stencil
) {
1170 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1171 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1172 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1173 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1174 "slice_size=%"PRIu64
", npix_x=%u, "
1175 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1176 "mode=%u, tiling_index = %u\n",
1177 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1178 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1179 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1180 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1181 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1182 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1183 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1184 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1185 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1190 /* Common processing for r600_texture_create and r600_texture_from_handle */
1191 static struct r600_texture
*
1192 r600_texture_create_object(struct pipe_screen
*screen
,
1193 const struct pipe_resource
*base
,
1194 struct pb_buffer
*buf
,
1195 struct radeon_surf
*surface
)
1197 struct r600_texture
*rtex
;
1198 struct r600_resource
*resource
;
1199 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1201 rtex
= CALLOC_STRUCT(r600_texture
);
1205 resource
= &rtex
->resource
;
1206 resource
->b
.b
= *base
;
1207 resource
->b
.b
.next
= NULL
;
1208 resource
->b
.vtbl
= &r600_texture_vtbl
;
1209 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1210 resource
->b
.b
.screen
= screen
;
1212 /* don't include stencil-only formats which we don't support for rendering */
1213 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1215 rtex
->surface
= *surface
;
1216 rtex
->size
= rtex
->surface
.surf_size
;
1218 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1219 (rtex
->surface
.flags
&
1220 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1222 /* TC-compatible HTILE:
1223 * - VI only supports Z32_FLOAT.
1224 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1225 if (rtex
->tc_compatible_htile
) {
1226 if (sscreen
->info
.chip_class
>= GFX9
&&
1227 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1228 rtex
->db_render_format
= base
->format
;
1230 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1231 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1232 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1235 rtex
->db_render_format
= base
->format
;
1238 /* Applies to GCN. */
1239 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1241 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1242 * between frames, so the only thing that can enable separate DCC
1243 * with DRI2 is multiple slow clears within a frame.
1245 rtex
->ps_draw_ratio
= 0;
1247 if (rtex
->is_depth
) {
1248 if (sscreen
->info
.chip_class
>= GFX9
) {
1249 rtex
->can_sample_z
= true;
1250 rtex
->can_sample_s
= true;
1252 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1253 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1256 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1257 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1258 rtex
->db_compatible
= true;
1260 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1261 r600_texture_allocate_htile(sscreen
, rtex
);
1264 if (base
->nr_samples
> 1) {
1266 r600_texture_allocate_fmask(sscreen
, rtex
);
1267 r600_texture_allocate_cmask(sscreen
, rtex
);
1268 rtex
->cmask_buffer
= &rtex
->resource
;
1270 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1276 /* Shared textures must always set up DCC here.
1277 * If it's not present, it will be disabled by
1278 * apply_opaque_metadata later.
1280 if (rtex
->surface
.dcc_size
&&
1281 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1282 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1283 /* Reserve space for the DCC buffer. */
1284 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1285 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1289 /* Now create the backing buffer. */
1291 si_init_resource_fields(sscreen
, resource
, rtex
->size
,
1292 rtex
->surface
.surf_alignment
);
1294 if (!si_alloc_resource(sscreen
, resource
)) {
1299 resource
->buf
= buf
;
1300 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1301 resource
->bo_size
= buf
->size
;
1302 resource
->bo_alignment
= buf
->alignment
;
1303 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1304 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1305 resource
->vram_usage
= buf
->size
;
1306 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1307 resource
->gart_usage
= buf
->size
;
1310 if (rtex
->cmask
.size
) {
1311 /* Initialize the cmask to 0xCC (= compressed state). */
1312 si_screen_clear_buffer(sscreen
, &rtex
->cmask_buffer
->b
.b
,
1313 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1316 if (rtex
->htile_offset
) {
1317 uint32_t clear_value
= 0;
1319 if (sscreen
->info
.chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1320 clear_value
= 0x0000030F;
1322 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1324 rtex
->surface
.htile_size
,
1328 /* Initialize DCC only if the texture is not being imported. */
1329 if (!buf
&& rtex
->dcc_offset
) {
1330 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1332 rtex
->surface
.dcc_size
,
1336 /* Initialize the CMASK base register value. */
1337 rtex
->cmask
.base_address_reg
=
1338 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1340 if (sscreen
->debug_flags
& DBG(VM
)) {
1341 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1342 rtex
->resource
.gpu_address
,
1343 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1344 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1345 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1348 if (sscreen
->debug_flags
& DBG(TEX
)) {
1350 struct u_log_context log
;
1351 u_log_context_init(&log
);
1352 si_print_texture_info(sscreen
, rtex
, &log
);
1353 u_log_new_page_print(&log
, stdout
);
1355 u_log_context_destroy(&log
);
1361 static enum radeon_surf_mode
1362 r600_choose_tiling(struct si_screen
*sscreen
,
1363 const struct pipe_resource
*templ
)
1365 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1366 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1367 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1368 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1370 /* MSAA resources must be 2D tiled. */
1371 if (templ
->nr_samples
> 1)
1372 return RADEON_SURF_MODE_2D
;
1374 /* Transfer resources should be linear. */
1375 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1376 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1378 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1379 * which requires 2D tiling.
1381 if (sscreen
->info
.chip_class
== VI
&&
1383 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1384 return RADEON_SURF_MODE_2D
;
1386 /* Handle common candidates for the linear mode.
1387 * Compressed textures and DB surfaces must always be tiled.
1389 if (!force_tiling
&&
1390 !is_depth_stencil
&&
1391 !util_format_is_compressed(templ
->format
)) {
1392 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1393 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1395 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1396 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1397 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1399 /* Cursors are linear on SI.
1400 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1401 if (templ
->bind
& PIPE_BIND_CURSOR
)
1402 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1404 if (templ
->bind
& PIPE_BIND_LINEAR
)
1405 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1407 /* Textures with a very small height are recommended to be linear. */
1408 if (templ
->target
== PIPE_TEXTURE_1D
||
1409 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1410 /* Only very thin and long 2D textures should benefit from
1411 * linear_aligned. */
1412 (templ
->width0
> 8 && templ
->height0
<= 2))
1413 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1415 /* Textures likely to be mapped often. */
1416 if (templ
->usage
== PIPE_USAGE_STAGING
||
1417 templ
->usage
== PIPE_USAGE_STREAM
)
1418 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1421 /* Make small textures 1D tiled. */
1422 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1423 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1424 return RADEON_SURF_MODE_1D
;
1426 /* The allocator will switch to 1D if needed. */
1427 return RADEON_SURF_MODE_2D
;
1430 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1431 const struct pipe_resource
*templ
)
1433 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1434 struct radeon_surf surface
= {0};
1435 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1436 bool tc_compatible_htile
=
1437 sscreen
->info
.chip_class
>= VI
&&
1438 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1439 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1440 !is_flushed_depth
&&
1441 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1442 util_format_is_depth_or_stencil(templ
->format
);
1446 r
= r600_init_surface(sscreen
, &surface
, templ
,
1447 r600_choose_tiling(sscreen
, templ
), 0, 0,
1448 false, false, is_flushed_depth
,
1449 tc_compatible_htile
);
1454 return (struct pipe_resource
*)
1455 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1458 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1459 const struct pipe_resource
*templ
,
1460 struct winsys_handle
*whandle
,
1463 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1464 struct pb_buffer
*buf
= NULL
;
1465 unsigned stride
= 0, offset
= 0;
1466 enum radeon_surf_mode array_mode
;
1467 struct radeon_surf surface
= {};
1469 struct radeon_bo_metadata metadata
= {};
1470 struct r600_texture
*rtex
;
1473 /* Support only 2D textures without mipmaps */
1474 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1475 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1478 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1482 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1483 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
1484 &array_mode
, &is_scanout
);
1486 r
= r600_init_surface(sscreen
, &surface
, templ
, array_mode
, stride
,
1487 offset
, true, is_scanout
, false, false);
1492 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1496 rtex
->resource
.b
.is_shared
= true;
1497 rtex
->resource
.external_usage
= usage
;
1499 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
1501 assert(rtex
->surface
.tile_swizzle
== 0);
1502 return &rtex
->resource
.b
.b
;
1505 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1506 struct pipe_resource
*texture
,
1507 struct r600_texture
**staging
)
1509 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1510 struct pipe_resource resource
;
1511 struct r600_texture
**flushed_depth_texture
= staging
?
1512 staging
: &rtex
->flushed_depth_texture
;
1513 enum pipe_format pipe_format
= texture
->format
;
1516 if (rtex
->flushed_depth_texture
)
1517 return true; /* it's ready */
1519 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1520 switch (pipe_format
) {
1521 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1522 /* Save memory by not allocating the S plane. */
1523 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1525 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1526 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1527 /* Save memory bandwidth by not copying the
1528 * stencil part during flush.
1530 * This potentially increases memory bandwidth
1531 * if an application uses both Z and S texturing
1532 * simultaneously (a flushed Z24S8 texture
1533 * would be stored compactly), but how often
1534 * does that really happen?
1536 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1540 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1541 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1543 /* DB->CB copies to an 8bpp surface don't work. */
1544 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1548 memset(&resource
, 0, sizeof(resource
));
1549 resource
.target
= texture
->target
;
1550 resource
.format
= pipe_format
;
1551 resource
.width0
= texture
->width0
;
1552 resource
.height0
= texture
->height0
;
1553 resource
.depth0
= texture
->depth0
;
1554 resource
.array_size
= texture
->array_size
;
1555 resource
.last_level
= texture
->last_level
;
1556 resource
.nr_samples
= texture
->nr_samples
;
1557 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1558 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1559 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1562 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1564 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1565 if (*flushed_depth_texture
== NULL
) {
1566 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1573 * Initialize the pipe_resource descriptor to be of the same size as the box,
1574 * which is supposed to hold a subregion of the texture "orig" at the given
1577 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1578 struct pipe_resource
*orig
,
1579 const struct pipe_box
*box
,
1580 unsigned level
, unsigned flags
)
1582 memset(res
, 0, sizeof(*res
));
1583 res
->format
= orig
->format
;
1584 res
->width0
= box
->width
;
1585 res
->height0
= box
->height
;
1587 res
->array_size
= 1;
1588 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1591 /* We must set the correct texture target and dimensions for a 3D box. */
1592 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1593 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1594 res
->array_size
= box
->depth
;
1596 res
->target
= PIPE_TEXTURE_2D
;
1600 static bool r600_can_invalidate_texture(struct si_screen
*sscreen
,
1601 struct r600_texture
*rtex
,
1602 unsigned transfer_usage
,
1603 const struct pipe_box
*box
)
1605 return !rtex
->resource
.b
.is_shared
&&
1606 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1607 rtex
->resource
.b
.b
.last_level
== 0 &&
1608 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1609 box
->x
, box
->y
, box
->z
,
1610 box
->width
, box
->height
,
1614 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1615 struct r600_texture
*rtex
)
1617 struct si_screen
*sscreen
= rctx
->screen
;
1619 /* There is no point in discarding depth and tiled buffers. */
1620 assert(!rtex
->is_depth
);
1621 assert(rtex
->surface
.is_linear
);
1623 /* Reallocate the buffer in the same pipe_resource. */
1624 si_alloc_resource(sscreen
, &rtex
->resource
);
1626 /* Initialize the CMASK base address (needed even without CMASK). */
1627 rtex
->cmask
.base_address_reg
=
1628 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1630 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1632 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1635 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1636 struct pipe_resource
*texture
,
1639 const struct pipe_box
*box
,
1640 struct pipe_transfer
**ptransfer
)
1642 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1643 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1644 struct r600_transfer
*trans
;
1645 struct r600_resource
*buf
;
1646 unsigned offset
= 0;
1648 bool use_staging_texture
= false;
1650 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1651 assert(box
->width
&& box
->height
&& box
->depth
);
1653 /* Depth textures use staging unconditionally. */
1654 if (!rtex
->is_depth
) {
1655 /* Degrade the tile mode if we get too many transfers on APUs.
1656 * On dGPUs, the staging texture is always faster.
1657 * Only count uploads that are at least 4x4 pixels large.
1659 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1661 box
->width
>= 4 && box
->height
>= 4 &&
1662 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1663 bool can_invalidate
=
1664 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1667 r600_reallocate_texture_inplace(rctx
, rtex
,
1672 /* Tiled textures need to be converted into a linear texture for CPU
1673 * access. The staging texture is always linear and is placed in GART.
1675 * Reading from VRAM or GTT WC is slow, always use the staging
1676 * texture in this case.
1678 * Use the staging texture for uploads if the underlying BO
1681 if (!rtex
->surface
.is_linear
)
1682 use_staging_texture
= true;
1683 else if (usage
& PIPE_TRANSFER_READ
)
1684 use_staging_texture
=
1685 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1686 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1687 /* Write & linear only: */
1688 else if (si_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1689 RADEON_USAGE_READWRITE
) ||
1690 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1691 RADEON_USAGE_READWRITE
)) {
1693 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1695 r600_texture_invalidate_storage(rctx
, rtex
);
1697 use_staging_texture
= true;
1701 trans
= CALLOC_STRUCT(r600_transfer
);
1704 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1705 trans
->b
.b
.level
= level
;
1706 trans
->b
.b
.usage
= usage
;
1707 trans
->b
.b
.box
= *box
;
1709 if (rtex
->is_depth
) {
1710 struct r600_texture
*staging_depth
;
1712 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1713 /* MSAA depth buffers need to be converted to single sample buffers.
1715 * Mapping MSAA depth buffers can occur if ReadPixels is called
1716 * with a multisample GLX visual.
1718 * First downsample the depth buffer to a temporary texture,
1719 * then decompress the temporary one to staging.
1721 * Only the region being mapped is transfered.
1723 struct pipe_resource resource
;
1725 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1727 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1728 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1733 if (usage
& PIPE_TRANSFER_READ
) {
1734 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1736 R600_ERR("failed to create a temporary depth texture\n");
1741 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1742 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1743 0, 0, 0, box
->depth
, 0, 0);
1744 pipe_resource_reference(&temp
, NULL
);
1747 /* Just get the strides. */
1748 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1750 &trans
->b
.b
.layer_stride
);
1752 /* XXX: only readback the rectangle which is being mapped? */
1753 /* XXX: when discard is true, no need to read back from depth texture */
1754 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1755 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1760 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1762 box
->z
, box
->z
+ box
->depth
- 1,
1765 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1768 &trans
->b
.b
.layer_stride
);
1771 trans
->staging
= (struct r600_resource
*)staging_depth
;
1772 buf
= trans
->staging
;
1773 } else if (use_staging_texture
) {
1774 struct pipe_resource resource
;
1775 struct r600_texture
*staging
;
1777 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1778 R600_RESOURCE_FLAG_TRANSFER
);
1779 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1780 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1782 /* Create the temporary texture. */
1783 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1785 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1789 trans
->staging
= &staging
->resource
;
1791 /* Just get the strides. */
1792 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1794 &trans
->b
.b
.layer_stride
);
1796 if (usage
& PIPE_TRANSFER_READ
)
1797 r600_copy_to_staging_texture(ctx
, trans
);
1799 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1801 buf
= trans
->staging
;
1803 /* the resource is mapped directly */
1804 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1806 &trans
->b
.b
.layer_stride
);
1807 buf
= &rtex
->resource
;
1810 if (!(map
= si_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1811 r600_resource_reference(&trans
->staging
, NULL
);
1816 *ptransfer
= &trans
->b
.b
;
1817 return map
+ offset
;
1820 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1821 struct pipe_transfer
* transfer
)
1823 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1824 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1825 struct pipe_resource
*texture
= transfer
->resource
;
1826 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1828 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1829 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1830 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1831 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1832 &rtransfer
->staging
->b
.b
, transfer
->level
,
1835 r600_copy_from_staging_texture(ctx
, rtransfer
);
1839 if (rtransfer
->staging
) {
1840 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1841 r600_resource_reference(&rtransfer
->staging
, NULL
);
1844 /* Heuristic for {upload, draw, upload, draw, ..}:
1846 * Flush the gfx IB if we've allocated too much texture storage.
1848 * The idea is that we don't want to build IBs that use too much
1849 * memory and put pressure on the kernel memory manager and we also
1850 * want to make temporary and invalidated buffers go idle ASAP to
1851 * decrease the total memory usage or make them reusable. The memory
1852 * usage will be slightly higher than given here because of the buffer
1853 * cache in the winsys.
1855 * The result is that the kernel memory manager is never a bottleneck.
1857 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1858 rctx
->gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
1859 rctx
->num_alloc_tex_transfer_bytes
= 0;
1862 pipe_resource_reference(&transfer
->resource
, NULL
);
1866 static const struct u_resource_vtbl r600_texture_vtbl
=
1868 NULL
, /* get_handle */
1869 r600_texture_destroy
, /* resource_destroy */
1870 r600_texture_transfer_map
, /* transfer_map */
1871 u_default_transfer_flush_region
, /* transfer_flush_region */
1872 r600_texture_transfer_unmap
, /* transfer_unmap */
1875 /* DCC channel type categories within which formats can be reinterpreted
1876 * while keeping the same DCC encoding. The swizzle must also match. */
1877 enum dcc_channel_type
{
1878 dcc_channel_float32
,
1881 dcc_channel_float16
,
1884 dcc_channel_uint_10_10_10_2
,
1887 dcc_channel_incompatible
,
1890 /* Return the type of DCC encoding. */
1891 static enum dcc_channel_type
1892 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1896 /* Find the first non-void channel. */
1897 for (i
= 0; i
< desc
->nr_channels
; i
++)
1898 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1900 if (i
== desc
->nr_channels
)
1901 return dcc_channel_incompatible
;
1903 switch (desc
->channel
[i
].size
) {
1905 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1906 return dcc_channel_float32
;
1907 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1908 return dcc_channel_uint32
;
1909 return dcc_channel_sint32
;
1911 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1912 return dcc_channel_float16
;
1913 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1914 return dcc_channel_uint16
;
1915 return dcc_channel_sint16
;
1917 return dcc_channel_uint_10_10_10_2
;
1919 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1920 return dcc_channel_uint8
;
1921 return dcc_channel_sint8
;
1923 return dcc_channel_incompatible
;
1927 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1928 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1929 enum pipe_format format2
)
1931 const struct util_format_description
*desc1
, *desc2
;
1932 enum dcc_channel_type type1
, type2
;
1935 if (format1
== format2
)
1938 desc1
= util_format_description(format1
);
1939 desc2
= util_format_description(format2
);
1941 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1944 /* Swizzles must be the same. */
1945 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1946 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1947 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1948 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1951 type1
= vi_get_dcc_channel_type(desc1
);
1952 type2
= vi_get_dcc_channel_type(desc2
);
1954 return type1
!= dcc_channel_incompatible
&&
1955 type2
!= dcc_channel_incompatible
&&
1959 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1961 enum pipe_format view_format
)
1963 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1965 return vi_dcc_enabled(rtex
, level
) &&
1966 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1969 /* This can't be merged with the above function, because
1970 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1971 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1972 struct pipe_resource
*tex
,
1974 enum pipe_format view_format
)
1976 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1978 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1979 if (!si_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1980 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1983 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1984 struct pipe_resource
*texture
,
1985 const struct pipe_surface
*templ
,
1986 unsigned width0
, unsigned height0
,
1987 unsigned width
, unsigned height
)
1989 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1994 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1995 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1997 pipe_reference_init(&surface
->base
.reference
, 1);
1998 pipe_resource_reference(&surface
->base
.texture
, texture
);
1999 surface
->base
.context
= pipe
;
2000 surface
->base
.format
= templ
->format
;
2001 surface
->base
.width
= width
;
2002 surface
->base
.height
= height
;
2003 surface
->base
.u
= templ
->u
;
2005 surface
->width0
= width0
;
2006 surface
->height0
= height0
;
2008 surface
->dcc_incompatible
=
2009 texture
->target
!= PIPE_BUFFER
&&
2010 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2012 return &surface
->base
;
2015 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
2016 struct pipe_resource
*tex
,
2017 const struct pipe_surface
*templ
)
2019 unsigned level
= templ
->u
.tex
.level
;
2020 unsigned width
= u_minify(tex
->width0
, level
);
2021 unsigned height
= u_minify(tex
->height0
, level
);
2022 unsigned width0
= tex
->width0
;
2023 unsigned height0
= tex
->height0
;
2025 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2026 const struct util_format_description
*tex_desc
2027 = util_format_description(tex
->format
);
2028 const struct util_format_description
*templ_desc
2029 = util_format_description(templ
->format
);
2031 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2033 /* Adjust size of surface if and only if the block width or
2034 * height is changed. */
2035 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2036 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2037 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2038 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2040 width
= nblks_x
* templ_desc
->block
.width
;
2041 height
= nblks_y
* templ_desc
->block
.height
;
2043 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2044 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2048 return si_create_surface_custom(pipe
, tex
, templ
,
2053 static void r600_surface_destroy(struct pipe_context
*pipe
,
2054 struct pipe_surface
*surface
)
2056 pipe_resource_reference(&surface
->texture
, NULL
);
2060 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2062 const struct util_format_description
*desc
= util_format_description(format
);
2064 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2066 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2067 return V_028C70_SWAP_STD
;
2069 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2072 switch (desc
->nr_channels
) {
2074 if (HAS_SWIZZLE(0,X
))
2075 return V_028C70_SWAP_STD
; /* X___ */
2076 else if (HAS_SWIZZLE(3,X
))
2077 return V_028C70_SWAP_ALT_REV
; /* ___X */
2080 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2081 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2082 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2083 return V_028C70_SWAP_STD
; /* XY__ */
2084 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2085 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2086 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2088 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2089 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2090 return V_028C70_SWAP_ALT
; /* X__Y */
2091 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2092 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2095 if (HAS_SWIZZLE(0,X
))
2096 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2097 else if (HAS_SWIZZLE(0,Z
))
2098 return V_028C70_SWAP_STD_REV
; /* ZYX */
2101 /* check the middle channels, the 1st and 4th channel can be NONE */
2102 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2103 return V_028C70_SWAP_STD
; /* XYZW */
2104 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2105 return V_028C70_SWAP_STD_REV
; /* WZYX */
2106 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2107 return V_028C70_SWAP_ALT
; /* ZYXW */
2108 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2111 return V_028C70_SWAP_ALT_REV
;
2113 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2120 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2122 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2127 if (rctx
->dcc_stats
[slot
].query_active
)
2128 vi_separate_dcc_stop_query(&rctx
->b
,
2129 rctx
->dcc_stats
[slot
].tex
);
2131 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2132 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2133 rctx
->b
.destroy_query(&rctx
->b
,
2134 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2135 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2138 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2142 * Return the per-context slot where DCC statistics queries for the texture live.
2144 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2145 struct r600_texture
*tex
)
2147 int i
, empty_slot
= -1;
2149 /* Remove zombie textures (textures kept alive by this array only). */
2150 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2151 if (rctx
->dcc_stats
[i
].tex
&&
2152 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2153 vi_dcc_clean_up_context_slot(rctx
, i
);
2155 /* Find the texture. */
2156 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2157 /* Return if found. */
2158 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2159 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2163 /* Record the first seen empty slot. */
2164 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2168 /* Not found. Remove the oldest member to make space in the array. */
2169 if (empty_slot
== -1) {
2170 int oldest_slot
= 0;
2172 /* Find the oldest slot. */
2173 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2174 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2175 rctx
->dcc_stats
[i
].last_use_timestamp
)
2178 /* Clean up the oldest slot. */
2179 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2180 empty_slot
= oldest_slot
;
2183 /* Add the texture to the new slot. */
2184 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2185 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2189 static struct pipe_query
*
2190 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2192 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2193 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2195 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2196 return (struct pipe_query
*)query
;
2200 * Called when binding a color buffer.
2202 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2203 struct r600_texture
*tex
)
2205 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2206 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2208 assert(!rctx
->dcc_stats
[i
].query_active
);
2210 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2211 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2213 /* begin or resume the query */
2214 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2215 rctx
->dcc_stats
[i
].query_active
= true;
2219 * Called when unbinding a color buffer.
2221 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2222 struct r600_texture
*tex
)
2224 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2225 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2227 assert(rctx
->dcc_stats
[i
].query_active
);
2228 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2230 /* pause or end the query */
2231 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2232 rctx
->dcc_stats
[i
].query_active
= false;
2235 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2237 /* The minimum number of fullscreen draws per frame that is required
2239 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2242 /* Called by fast clear. */
2243 void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2244 struct r600_texture
*tex
)
2246 /* The intent is to use this with shared displayable back buffers,
2247 * but it's not strictly limited only to them.
2249 if (!tex
->resource
.b
.is_shared
||
2250 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2251 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2252 tex
->resource
.b
.b
.last_level
> 0 ||
2253 !tex
->surface
.dcc_size
)
2256 if (tex
->dcc_offset
)
2257 return; /* already enabled */
2259 /* Enable the DCC stat gathering. */
2260 if (!tex
->dcc_gather_statistics
) {
2261 tex
->dcc_gather_statistics
= true;
2262 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2265 if (!vi_should_enable_separate_dcc(tex
))
2266 return; /* stats show that DCC decompression is too expensive */
2268 assert(tex
->surface
.num_dcc_levels
);
2269 assert(!tex
->dcc_separate_buffer
);
2271 si_texture_discard_cmask(rctx
->screen
, tex
);
2273 /* Get a DCC buffer. */
2274 if (tex
->last_dcc_separate_buffer
) {
2275 assert(tex
->dcc_gather_statistics
);
2276 assert(!tex
->dcc_separate_buffer
);
2277 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2278 tex
->last_dcc_separate_buffer
= NULL
;
2280 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2281 si_aligned_buffer_create(rctx
->b
.screen
,
2282 R600_RESOURCE_FLAG_UNMAPPABLE
,
2284 tex
->surface
.dcc_size
,
2285 tex
->surface
.dcc_alignment
);
2286 if (!tex
->dcc_separate_buffer
)
2290 /* dcc_offset is the absolute GPUVM address. */
2291 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2293 /* no need to flag anything since this is called by fast clear that
2294 * flags framebuffer state
2299 * Called by pipe_context::flush_resource, the place where DCC decompression
2302 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2303 struct r600_texture
*tex
)
2305 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2306 struct pipe_query
*tmp
;
2307 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2308 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2309 bool disable
= false;
2311 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2312 union pipe_query_result result
;
2314 /* Read the results. */
2315 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2317 si_query_hw_reset_buffers(rctx
,
2318 (struct r600_query_hw
*)
2319 rctx
->dcc_stats
[i
].ps_stats
[2]);
2321 /* Compute the approximate number of fullscreen draws. */
2322 tex
->ps_draw_ratio
=
2323 result
.pipeline_statistics
.ps_invocations
/
2324 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2325 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2327 disable
= tex
->dcc_separate_buffer
&&
2328 !vi_should_enable_separate_dcc(tex
);
2331 tex
->num_slow_clears
= 0;
2333 /* stop the statistics query for ps_stats[0] */
2335 vi_separate_dcc_stop_query(ctx
, tex
);
2337 /* Move the queries in the queue by one. */
2338 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2339 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2340 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2341 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2343 /* create and start a new query as ps_stats[0] */
2345 vi_separate_dcc_start_query(ctx
, tex
);
2348 assert(!tex
->last_dcc_separate_buffer
);
2349 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2350 tex
->dcc_separate_buffer
= NULL
;
2351 tex
->dcc_offset
= 0;
2352 /* no need to flag anything since this is called after
2353 * decompression that re-sets framebuffer state
2358 static struct pipe_memory_object
*
2359 r600_memobj_from_handle(struct pipe_screen
*screen
,
2360 struct winsys_handle
*whandle
,
2363 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2364 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2365 struct pb_buffer
*buf
= NULL
;
2366 uint32_t stride
, offset
;
2371 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2378 memobj
->b
.dedicated
= dedicated
;
2380 memobj
->stride
= stride
;
2381 memobj
->offset
= offset
;
2383 return (struct pipe_memory_object
*)memobj
;
2388 r600_memobj_destroy(struct pipe_screen
*screen
,
2389 struct pipe_memory_object
*_memobj
)
2391 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2393 pb_reference(&memobj
->buf
, NULL
);
2397 static struct pipe_resource
*
2398 r600_texture_from_memobj(struct pipe_screen
*screen
,
2399 const struct pipe_resource
*templ
,
2400 struct pipe_memory_object
*_memobj
,
2404 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2405 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2406 struct r600_texture
*rtex
;
2407 struct radeon_surf surface
= {};
2408 struct radeon_bo_metadata metadata
= {};
2409 enum radeon_surf_mode array_mode
;
2411 struct pb_buffer
*buf
= NULL
;
2413 if (memobj
->b
.dedicated
) {
2414 sscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2415 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
2416 &array_mode
, &is_scanout
);
2419 * The bo metadata is unset for un-dedicated images. So we fall
2420 * back to linear. See answer to question 5 of the
2421 * VK_KHX_external_memory spec for some details.
2423 * It is possible that this case isn't going to work if the
2424 * surface pitch isn't correctly aligned by default.
2426 * In order to support it correctly we require multi-image
2427 * metadata to be syncrhonized between radv and radeonsi. The
2428 * semantics of associating multiple image metadata to a memory
2429 * object on the vulkan export side are not concretely defined
2432 * All the use cases we are aware of at the moment for memory
2433 * objects use dedicated allocations. So lets keep the initial
2434 * implementation simple.
2436 * A possible alternative is to attempt to reconstruct the
2437 * tiling information when the TexParameter TEXTURE_TILING_EXT
2440 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2445 r
= r600_init_surface(sscreen
, &surface
, templ
,
2446 array_mode
, memobj
->stride
,
2447 offset
, true, is_scanout
,
2452 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2456 /* r600_texture_create_object doesn't increment refcount of
2457 * memobj->buf, so increment it here.
2459 pb_reference(&buf
, memobj
->buf
);
2461 rtex
->resource
.b
.is_shared
= true;
2462 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2464 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
2466 return &rtex
->resource
.b
.b
;
2469 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2470 struct pipe_resource
*resource
,
2473 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2475 /* Buffers only support the linear flag. */
2476 if (resource
->target
== PIPE_BUFFER
)
2477 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2479 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2482 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2485 /* TODO: PIPE_BIND_CURSOR - do we care? */
2489 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2491 sscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2492 sscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2493 sscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2494 sscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2495 sscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2496 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2499 void si_init_context_texture_functions(struct r600_common_context
*rctx
)
2501 rctx
->b
.create_surface
= r600_create_surface
;
2502 rctx
->b
.surface_destroy
= r600_surface_destroy
;