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gallium/radeon: disable CMASK on handle export if sharing doesn't allow it (v2)
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static void r600_texture_init_metadata(struct r600_texture *rtex,
232 struct radeon_bo_metadata *metadata)
233 {
234 struct radeon_surf *surface = &rtex->surface;
235
236 memset(metadata, 0, sizeof(*metadata));
237 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
238 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
239 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
240 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
241 metadata->pipe_config = surface->pipe_config;
242 metadata->bankw = surface->bankw;
243 metadata->bankh = surface->bankh;
244 metadata->tile_split = surface->tile_split;
245 metadata->stencil_tile_split = surface->stencil_tile_split;
246 metadata->mtilea = surface->mtilea;
247 metadata->num_banks = surface->num_banks;
248 metadata->stride = surface->level[0].pitch_bytes;
249 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
250 }
251
252 static void r600_dirty_all_framebuffer_states(struct r600_common_screen *rscreen)
253 {
254 p_atomic_inc(&rscreen->dirty_fb_counter);
255 }
256
257 static void r600_eliminate_fast_color_clear(struct r600_common_screen *rscreen,
258 struct r600_texture *rtex)
259 {
260 struct pipe_context *ctx = rscreen->aux_context;
261
262 pipe_mutex_lock(rscreen->aux_context_lock);
263 ctx->flush_resource(ctx, &rtex->resource.b.b);
264 ctx->flush(ctx, NULL, 0);
265 pipe_mutex_unlock(rscreen->aux_context_lock);
266 }
267
268 static void r600_texture_disable_cmask(struct r600_common_screen *rscreen,
269 struct r600_texture *rtex)
270 {
271 if (!rtex->cmask.size)
272 return;
273
274 assert(rtex->resource.b.b.nr_samples <= 1);
275
276 /* Disable CMASK. */
277 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
278 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
279
280 if (rscreen->chip_class >= SI)
281 rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1);
282 else
283 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
284
285 if (rtex->cmask_buffer != &rtex->resource)
286 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
287
288 /* Notify all contexts about the change. */
289 r600_dirty_all_framebuffer_states(rscreen);
290 }
291
292 static boolean r600_texture_get_handle(struct pipe_screen* screen,
293 struct pipe_resource *resource,
294 struct winsys_handle *whandle,
295 unsigned usage)
296 {
297 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
298 struct r600_resource *res = (struct r600_resource*)resource;
299 struct r600_texture *rtex = (struct r600_texture*)resource;
300 struct radeon_bo_metadata metadata;
301
302 /* This is not supported now, but it might be required for OpenCL
303 * interop in the future.
304 */
305 if (resource->target != PIPE_BUFFER &&
306 (resource->nr_samples > 1 || rtex->is_depth))
307 return NULL;
308
309 if (!res->is_shared) {
310 res->is_shared = true;
311 res->external_usage = usage;
312
313 if (resource->target != PIPE_BUFFER) {
314 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
315 /* Eliminate fast clear (both CMASK and DCC) */
316 r600_eliminate_fast_color_clear(rscreen, rtex);
317
318 /* Disable CMASK if flush_resource isn't going
319 * to be called.
320 */
321 r600_texture_disable_cmask(rscreen, rtex);
322 }
323
324 r600_texture_init_metadata(rtex, &metadata);
325 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
326 }
327 } else {
328 assert(res->external_usage == usage);
329 }
330
331 return rscreen->ws->buffer_get_handle(res->buf,
332 rtex->surface.level[0].pitch_bytes,
333 whandle);
334 }
335
336 static void r600_texture_destroy(struct pipe_screen *screen,
337 struct pipe_resource *ptex)
338 {
339 struct r600_texture *rtex = (struct r600_texture*)ptex;
340 struct r600_resource *resource = &rtex->resource;
341
342 if (rtex->flushed_depth_texture)
343 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
344
345 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
346 if (rtex->cmask_buffer != &rtex->resource) {
347 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
348 }
349 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
350 pb_reference(&resource->buf, NULL);
351 FREE(rtex);
352 }
353
354 static const struct u_resource_vtbl r600_texture_vtbl;
355
356 /* The number of samples can be specified independently of the texture. */
357 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
358 struct r600_texture *rtex,
359 unsigned nr_samples,
360 struct r600_fmask_info *out)
361 {
362 /* FMASK is allocated like an ordinary texture. */
363 struct radeon_surf fmask = rtex->surface;
364
365 memset(out, 0, sizeof(*out));
366
367 fmask.bo_alignment = 0;
368 fmask.bo_size = 0;
369 fmask.nsamples = 1;
370 fmask.flags |= RADEON_SURF_FMASK;
371
372 /* Force 2D tiling if it wasn't set. This may occur when creating
373 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
374 * destination buffer must have an FMASK too. */
375 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
376 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
377
378 if (rscreen->chip_class >= SI) {
379 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
380 }
381
382 switch (nr_samples) {
383 case 2:
384 case 4:
385 fmask.bpe = 1;
386 if (rscreen->chip_class <= CAYMAN) {
387 fmask.bankh = 4;
388 }
389 break;
390 case 8:
391 fmask.bpe = 4;
392 break;
393 default:
394 R600_ERR("Invalid sample count for FMASK allocation.\n");
395 return;
396 }
397
398 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
399 * This can be fixed by writing a separate FMASK allocator specifically
400 * for R600-R700 asics. */
401 if (rscreen->chip_class <= R700) {
402 fmask.bpe *= 2;
403 }
404
405 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
406 R600_ERR("Got error in surface_init while allocating FMASK.\n");
407 return;
408 }
409
410 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
411
412 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
413 if (out->slice_tile_max)
414 out->slice_tile_max -= 1;
415
416 out->tile_mode_index = fmask.tiling_index[0];
417 out->pitch_in_pixels = fmask.level[0].nblk_x;
418 out->bank_height = fmask.bankh;
419 out->alignment = MAX2(256, fmask.bo_alignment);
420 out->size = fmask.bo_size;
421 }
422
423 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
424 struct r600_texture *rtex)
425 {
426 r600_texture_get_fmask_info(rscreen, rtex,
427 rtex->resource.b.b.nr_samples, &rtex->fmask);
428
429 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
430 rtex->size = rtex->fmask.offset + rtex->fmask.size;
431 }
432
433 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
434 struct r600_texture *rtex,
435 struct r600_cmask_info *out)
436 {
437 unsigned cmask_tile_width = 8;
438 unsigned cmask_tile_height = 8;
439 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
440 unsigned element_bits = 4;
441 unsigned cmask_cache_bits = 1024;
442 unsigned num_pipes = rscreen->info.num_tile_pipes;
443 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
444
445 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
446 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
447 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
448 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
449 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
450
451 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
452 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
453
454 unsigned base_align = num_pipes * pipe_interleave_bytes;
455 unsigned slice_bytes =
456 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
457
458 assert(macro_tile_width % 128 == 0);
459 assert(macro_tile_height % 128 == 0);
460
461 out->pitch = pitch_elements;
462 out->height = height;
463 out->xalign = macro_tile_width;
464 out->yalign = macro_tile_height;
465 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
466 out->alignment = MAX2(256, base_align);
467 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
468 align(slice_bytes, base_align);
469 }
470
471 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
472 struct r600_texture *rtex,
473 struct r600_cmask_info *out)
474 {
475 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
476 unsigned num_pipes = rscreen->info.num_tile_pipes;
477 unsigned cl_width, cl_height;
478
479 switch (num_pipes) {
480 case 2:
481 cl_width = 32;
482 cl_height = 16;
483 break;
484 case 4:
485 cl_width = 32;
486 cl_height = 32;
487 break;
488 case 8:
489 cl_width = 64;
490 cl_height = 32;
491 break;
492 case 16: /* Hawaii */
493 cl_width = 64;
494 cl_height = 64;
495 break;
496 default:
497 assert(0);
498 return;
499 }
500
501 unsigned base_align = num_pipes * pipe_interleave_bytes;
502
503 unsigned width = align(rtex->surface.npix_x, cl_width*8);
504 unsigned height = align(rtex->surface.npix_y, cl_height*8);
505 unsigned slice_elements = (width * height) / (8*8);
506
507 /* Each element of CMASK is a nibble. */
508 unsigned slice_bytes = slice_elements / 2;
509
510 out->pitch = width;
511 out->height = height;
512 out->xalign = cl_width * 8;
513 out->yalign = cl_height * 8;
514 out->slice_tile_max = (width * height) / (128*128);
515 if (out->slice_tile_max)
516 out->slice_tile_max -= 1;
517
518 out->alignment = MAX2(256, base_align);
519 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
520 align(slice_bytes, base_align);
521 }
522
523 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
524 struct r600_texture *rtex)
525 {
526 if (rscreen->chip_class >= SI) {
527 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
528 } else {
529 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
530 }
531
532 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
533 rtex->size = rtex->cmask.offset + rtex->cmask.size;
534
535 if (rscreen->chip_class >= SI)
536 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
537 else
538 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
539 }
540
541 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
542 struct r600_texture *rtex)
543 {
544 if (rtex->cmask_buffer)
545 return;
546
547 assert(rtex->cmask.size == 0);
548
549 if (rscreen->chip_class >= SI) {
550 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
551 } else {
552 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
553 }
554
555 rtex->cmask_buffer = (struct r600_resource *)
556 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
557 PIPE_USAGE_DEFAULT, rtex->cmask.size);
558 if (rtex->cmask_buffer == NULL) {
559 rtex->cmask.size = 0;
560 return;
561 }
562
563 /* update colorbuffer state bits */
564 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
565
566 if (rscreen->chip_class >= SI)
567 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
568 else
569 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
570 }
571
572 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
573 struct r600_texture *rtex)
574 {
575 if (rscreen->debug_flags & DBG_NO_DCC)
576 return;
577
578 rtex->dcc_buffer = (struct r600_resource *)
579 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
580 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
581 if (rtex->dcc_buffer == NULL) {
582 return;
583 }
584
585 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
586 0xFFFFFFFF, true);
587
588 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
589 }
590
591 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
592 struct r600_texture *rtex)
593 {
594 unsigned cl_width, cl_height, width, height;
595 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
596 unsigned num_pipes = rscreen->info.num_tile_pipes;
597
598 if (rscreen->chip_class <= EVERGREEN &&
599 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
600 return 0;
601
602 /* HW bug on R6xx. */
603 if (rscreen->chip_class == R600 &&
604 (rtex->surface.level[0].npix_x > 7680 ||
605 rtex->surface.level[0].npix_y > 7680))
606 return 0;
607
608 /* HTILE is broken with 1D tiling on old kernels and CIK. */
609 if (rscreen->chip_class >= CIK &&
610 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
611 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
612 return 0;
613
614 /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
615 if (rscreen->family == CHIP_STONEY)
616 num_pipes = 4;
617
618 switch (num_pipes) {
619 case 1:
620 cl_width = 32;
621 cl_height = 16;
622 break;
623 case 2:
624 cl_width = 32;
625 cl_height = 32;
626 break;
627 case 4:
628 cl_width = 64;
629 cl_height = 32;
630 break;
631 case 8:
632 cl_width = 64;
633 cl_height = 64;
634 break;
635 case 16:
636 cl_width = 128;
637 cl_height = 64;
638 break;
639 default:
640 assert(0);
641 return 0;
642 }
643
644 width = align(rtex->surface.npix_x, cl_width * 8);
645 height = align(rtex->surface.npix_y, cl_height * 8);
646
647 slice_elements = (width * height) / (8 * 8);
648 slice_bytes = slice_elements * 4;
649
650 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
651 base_align = num_pipes * pipe_interleave_bytes;
652
653 rtex->htile.pitch = width;
654 rtex->htile.height = height;
655 rtex->htile.xalign = cl_width * 8;
656 rtex->htile.yalign = cl_height * 8;
657
658 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
659 align(slice_bytes, base_align);
660 }
661
662 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
663 struct r600_texture *rtex)
664 {
665 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
666
667 if (!htile_size)
668 return;
669
670 rtex->htile_buffer = (struct r600_resource*)
671 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
672 PIPE_USAGE_DEFAULT, htile_size);
673 if (rtex->htile_buffer == NULL) {
674 /* this is not a fatal error as we can still keep rendering
675 * without htile buffer */
676 R600_ERR("Failed to create buffer object for htile buffer.\n");
677 } else {
678 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
679 htile_size, 0, true);
680 }
681 }
682
683 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
684 {
685 int i;
686
687 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
688 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
689 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
690 rtex->surface.npix_x, rtex->surface.npix_y,
691 rtex->surface.npix_z, rtex->surface.blk_w,
692 rtex->surface.blk_h, rtex->surface.blk_d,
693 rtex->surface.array_size, rtex->surface.last_level,
694 rtex->surface.bpe, rtex->surface.nsamples,
695 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
696
697 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
698 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
699 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
700 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
701 rtex->surface.tile_split, rtex->surface.pipe_config,
702 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
703
704 if (rtex->fmask.size)
705 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
706 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
707 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
708 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
709 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
710
711 if (rtex->cmask.size)
712 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
713 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
714 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
715 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
716 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
717
718 if (rtex->htile_buffer)
719 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
720 "xalign=%u, yalign=%u\n",
721 rtex->htile_buffer->b.b.width0,
722 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
723 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
724
725 if (rtex->dcc_buffer) {
726 fprintf(f, " DCC: size=%u, alignment=%u\n",
727 rtex->dcc_buffer->b.b.width0,
728 rtex->dcc_buffer->buf->alignment);
729 for (i = 0; i <= rtex->surface.last_level; i++)
730 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
731 i, rtex->surface.level[i].dcc_offset);
732 }
733
734 for (i = 0; i <= rtex->surface.last_level; i++)
735 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
736 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
737 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
738 i, rtex->surface.level[i].offset,
739 rtex->surface.level[i].slice_size,
740 u_minify(rtex->resource.b.b.width0, i),
741 u_minify(rtex->resource.b.b.height0, i),
742 u_minify(rtex->resource.b.b.depth0, i),
743 rtex->surface.level[i].nblk_x,
744 rtex->surface.level[i].nblk_y,
745 rtex->surface.level[i].nblk_z,
746 rtex->surface.level[i].pitch_bytes,
747 rtex->surface.level[i].mode);
748
749 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
750 for (i = 0; i <= rtex->surface.last_level; i++) {
751 fprintf(f, " StencilLayout: tilesplit=%u\n",
752 rtex->surface.stencil_tile_split);
753 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
754 "slice_size=%"PRIu64", npix_x=%u, "
755 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
756 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
757 i, rtex->surface.stencil_level[i].offset,
758 rtex->surface.stencil_level[i].slice_size,
759 u_minify(rtex->resource.b.b.width0, i),
760 u_minify(rtex->resource.b.b.height0, i),
761 u_minify(rtex->resource.b.b.depth0, i),
762 rtex->surface.stencil_level[i].nblk_x,
763 rtex->surface.stencil_level[i].nblk_y,
764 rtex->surface.stencil_level[i].nblk_z,
765 rtex->surface.stencil_level[i].pitch_bytes,
766 rtex->surface.stencil_level[i].mode);
767 }
768 }
769 }
770
771 /* Common processing for r600_texture_create and r600_texture_from_handle */
772 static struct r600_texture *
773 r600_texture_create_object(struct pipe_screen *screen,
774 const struct pipe_resource *base,
775 unsigned pitch_in_bytes_override,
776 struct pb_buffer *buf,
777 struct radeon_surf *surface)
778 {
779 struct r600_texture *rtex;
780 struct r600_resource *resource;
781 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
782
783 rtex = CALLOC_STRUCT(r600_texture);
784 if (!rtex)
785 return NULL;
786
787 resource = &rtex->resource;
788 resource->b.b = *base;
789 resource->b.vtbl = &r600_texture_vtbl;
790 pipe_reference_init(&resource->b.b.reference, 1);
791 resource->b.b.screen = screen;
792
793 /* don't include stencil-only formats which we don't support for rendering */
794 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
795
796 rtex->surface = *surface;
797 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
798 FREE(rtex);
799 return NULL;
800 }
801
802 /* Tiled depth textures utilize the non-displayable tile order.
803 * This must be done after r600_setup_surface.
804 * Applies to R600-Cayman. */
805 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
806
807 if (rtex->is_depth) {
808 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
809 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
810 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
811
812 r600_texture_allocate_htile(rscreen, rtex);
813 }
814 } else {
815 if (base->nr_samples > 1) {
816 if (!buf) {
817 r600_texture_allocate_fmask(rscreen, rtex);
818 r600_texture_allocate_cmask(rscreen, rtex);
819 rtex->cmask_buffer = &rtex->resource;
820 }
821 if (!rtex->fmask.size || !rtex->cmask.size) {
822 FREE(rtex);
823 return NULL;
824 }
825 }
826 if (rtex->surface.dcc_size)
827 vi_texture_alloc_dcc_separate(rscreen, rtex);
828 }
829
830 /* Now create the backing buffer. */
831 if (!buf) {
832 if (!r600_init_resource(rscreen, resource, rtex->size,
833 rtex->surface.bo_alignment, TRUE)) {
834 FREE(rtex);
835 return NULL;
836 }
837 } else {
838 resource->buf = buf;
839 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
840 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
841 }
842
843 if (rtex->cmask.size) {
844 /* Initialize the cmask to 0xCC (= compressed state). */
845 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
846 rtex->cmask.offset, rtex->cmask.size,
847 0xCCCCCCCC, true);
848 }
849
850 /* Initialize the CMASK base register value. */
851 rtex->cmask.base_address_reg =
852 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
853
854 if (rscreen->debug_flags & DBG_VM) {
855 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
856 rtex->resource.gpu_address,
857 rtex->resource.gpu_address + rtex->resource.buf->size,
858 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
859 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
860 }
861
862 if (rscreen->debug_flags & DBG_TEX) {
863 puts("Texture:");
864 r600_print_texture_info(rtex, stdout);
865 }
866
867 return rtex;
868 }
869
870 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
871 const struct pipe_resource *templ)
872 {
873 const struct util_format_description *desc = util_format_description(templ->format);
874 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
875
876 /* MSAA resources must be 2D tiled. */
877 if (templ->nr_samples > 1)
878 return RADEON_SURF_MODE_2D;
879
880 /* Transfer resources should be linear. */
881 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
882 return RADEON_SURF_MODE_LINEAR_ALIGNED;
883
884 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
885 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
886 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
887 (templ->target == PIPE_TEXTURE_2D ||
888 templ->target == PIPE_TEXTURE_3D))
889 force_tiling = true;
890
891 /* Handle common candidates for the linear mode.
892 * Compressed textures must always be tiled. */
893 if (!force_tiling && !util_format_is_compressed(templ->format)) {
894 /* Not everything can be linear, so we cannot enforce it
895 * for all textures. */
896 if ((rscreen->debug_flags & DBG_NO_TILING) &&
897 (!util_format_is_depth_or_stencil(templ->format) ||
898 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
899 return RADEON_SURF_MODE_LINEAR_ALIGNED;
900
901 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
902 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
903 return RADEON_SURF_MODE_LINEAR_ALIGNED;
904
905 /* Cursors are linear on SI.
906 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
907 if (rscreen->chip_class >= SI &&
908 (templ->bind & PIPE_BIND_CURSOR))
909 return RADEON_SURF_MODE_LINEAR_ALIGNED;
910
911 if (templ->bind & PIPE_BIND_LINEAR)
912 return RADEON_SURF_MODE_LINEAR_ALIGNED;
913
914 /* Textures with a very small height are recommended to be linear. */
915 if (templ->target == PIPE_TEXTURE_1D ||
916 templ->target == PIPE_TEXTURE_1D_ARRAY ||
917 templ->height0 <= 4)
918 return RADEON_SURF_MODE_LINEAR_ALIGNED;
919
920 /* Textures likely to be mapped often. */
921 if (templ->usage == PIPE_USAGE_STAGING ||
922 templ->usage == PIPE_USAGE_STREAM)
923 return RADEON_SURF_MODE_LINEAR_ALIGNED;
924 }
925
926 /* Make small textures 1D tiled. */
927 if (templ->width0 <= 16 || templ->height0 <= 16 ||
928 (rscreen->debug_flags & DBG_NO_2D_TILING))
929 return RADEON_SURF_MODE_1D;
930
931 /* The allocator will switch to 1D if needed. */
932 return RADEON_SURF_MODE_2D;
933 }
934
935 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
936 const struct pipe_resource *templ)
937 {
938 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
939 struct radeon_surf surface = {0};
940 int r;
941
942 r = r600_init_surface(rscreen, &surface, templ,
943 r600_choose_tiling(rscreen, templ),
944 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
945 if (r) {
946 return NULL;
947 }
948 r = rscreen->ws->surface_best(rscreen->ws, &surface);
949 if (r) {
950 return NULL;
951 }
952 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
953 0, NULL, &surface);
954 }
955
956 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
957 const struct pipe_resource *templ,
958 struct winsys_handle *whandle,
959 unsigned usage)
960 {
961 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
962 struct pb_buffer *buf = NULL;
963 unsigned stride = 0;
964 unsigned array_mode;
965 struct radeon_surf surface;
966 int r;
967 struct radeon_bo_metadata metadata = {};
968 struct r600_texture *rtex;
969
970 /* Support only 2D textures without mipmaps */
971 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
972 templ->depth0 != 1 || templ->last_level != 0)
973 return NULL;
974
975 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
976 if (!buf)
977 return NULL;
978
979 rscreen->ws->buffer_get_metadata(buf, &metadata);
980
981 surface.bankw = metadata.bankw;
982 surface.bankh = metadata.bankh;
983 surface.tile_split = metadata.tile_split;
984 surface.stencil_tile_split = metadata.stencil_tile_split;
985 surface.mtilea = metadata.mtilea;
986
987 if (metadata.macrotile == RADEON_LAYOUT_TILED)
988 array_mode = RADEON_SURF_MODE_2D;
989 else if (metadata.microtile == RADEON_LAYOUT_TILED)
990 array_mode = RADEON_SURF_MODE_1D;
991 else
992 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
993
994 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
995 if (r) {
996 return NULL;
997 }
998
999 if (metadata.scanout)
1000 surface.flags |= RADEON_SURF_SCANOUT;
1001
1002 rtex = r600_texture_create_object(screen, templ,
1003 stride, buf, &surface);
1004 if (!rtex)
1005 return NULL;
1006
1007 rtex->resource.is_shared = true;
1008 rtex->resource.external_usage = usage;
1009 return &rtex->resource.b.b;
1010 }
1011
1012 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1013 struct pipe_resource *texture,
1014 struct r600_texture **staging)
1015 {
1016 struct r600_texture *rtex = (struct r600_texture*)texture;
1017 struct pipe_resource resource;
1018 struct r600_texture **flushed_depth_texture = staging ?
1019 staging : &rtex->flushed_depth_texture;
1020
1021 if (!staging && rtex->flushed_depth_texture)
1022 return true; /* it's ready */
1023
1024 resource.target = texture->target;
1025 resource.format = texture->format;
1026 resource.width0 = texture->width0;
1027 resource.height0 = texture->height0;
1028 resource.depth0 = texture->depth0;
1029 resource.array_size = texture->array_size;
1030 resource.last_level = texture->last_level;
1031 resource.nr_samples = texture->nr_samples;
1032 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1033 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1034 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1035
1036 if (staging)
1037 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1038
1039 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1040 if (*flushed_depth_texture == NULL) {
1041 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1042 return false;
1043 }
1044
1045 (*flushed_depth_texture)->is_flushing_texture = TRUE;
1046 (*flushed_depth_texture)->non_disp_tiling = false;
1047 return true;
1048 }
1049
1050 /**
1051 * Initialize the pipe_resource descriptor to be of the same size as the box,
1052 * which is supposed to hold a subregion of the texture "orig" at the given
1053 * mipmap level.
1054 */
1055 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1056 struct pipe_resource *orig,
1057 const struct pipe_box *box,
1058 unsigned level, unsigned flags)
1059 {
1060 memset(res, 0, sizeof(*res));
1061 res->format = orig->format;
1062 res->width0 = box->width;
1063 res->height0 = box->height;
1064 res->depth0 = 1;
1065 res->array_size = 1;
1066 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1067 res->flags = flags;
1068
1069 /* We must set the correct texture target and dimensions for a 3D box. */
1070 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1071 res->target = orig->target;
1072 else
1073 res->target = PIPE_TEXTURE_2D;
1074
1075 switch (res->target) {
1076 case PIPE_TEXTURE_1D_ARRAY:
1077 case PIPE_TEXTURE_2D_ARRAY:
1078 case PIPE_TEXTURE_CUBE_ARRAY:
1079 res->array_size = box->depth;
1080 break;
1081 case PIPE_TEXTURE_3D:
1082 res->depth0 = box->depth;
1083 break;
1084 default:;
1085 }
1086 }
1087
1088 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1089 struct pipe_resource *texture,
1090 unsigned level,
1091 unsigned usage,
1092 const struct pipe_box *box,
1093 struct pipe_transfer **ptransfer)
1094 {
1095 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1096 struct r600_texture *rtex = (struct r600_texture*)texture;
1097 struct r600_transfer *trans;
1098 boolean use_staging_texture = FALSE;
1099 struct r600_resource *buf;
1100 unsigned offset = 0;
1101 char *map;
1102
1103 /* We cannot map a tiled texture directly because the data is
1104 * in a different order, therefore we do detiling using a blit.
1105 *
1106 * Also, use a temporary in GTT memory for read transfers, as
1107 * the CPU is much happier reading out of cached system memory
1108 * than uncached VRAM.
1109 */
1110 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1111 use_staging_texture = TRUE;
1112 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1113 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1114 /* Untiled buffers in VRAM, which is slow for CPU reads */
1115 use_staging_texture = TRUE;
1116 } else if (!(usage & PIPE_TRANSFER_READ) &&
1117 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1118 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1119 /* Use a staging texture for uploads if the underlying BO is busy. */
1120 use_staging_texture = TRUE;
1121 }
1122
1123 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1124 use_staging_texture = FALSE;
1125 }
1126
1127 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1128 return NULL;
1129 }
1130
1131 trans = CALLOC_STRUCT(r600_transfer);
1132 if (!trans)
1133 return NULL;
1134 trans->transfer.resource = texture;
1135 trans->transfer.level = level;
1136 trans->transfer.usage = usage;
1137 trans->transfer.box = *box;
1138
1139 if (rtex->is_depth) {
1140 struct r600_texture *staging_depth;
1141
1142 if (rtex->resource.b.b.nr_samples > 1) {
1143 /* MSAA depth buffers need to be converted to single sample buffers.
1144 *
1145 * Mapping MSAA depth buffers can occur if ReadPixels is called
1146 * with a multisample GLX visual.
1147 *
1148 * First downsample the depth buffer to a temporary texture,
1149 * then decompress the temporary one to staging.
1150 *
1151 * Only the region being mapped is transfered.
1152 */
1153 struct pipe_resource resource;
1154
1155 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1156
1157 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1158 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1159 FREE(trans);
1160 return NULL;
1161 }
1162
1163 if (usage & PIPE_TRANSFER_READ) {
1164 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1165 if (!temp) {
1166 R600_ERR("failed to create a temporary depth texture\n");
1167 FREE(trans);
1168 return NULL;
1169 }
1170
1171 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1172 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1173 0, 0, 0, box->depth, 0, 0);
1174 pipe_resource_reference(&temp, NULL);
1175 }
1176 }
1177 else {
1178 /* XXX: only readback the rectangle which is being mapped? */
1179 /* XXX: when discard is true, no need to read back from depth texture */
1180 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1181 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1182 FREE(trans);
1183 return NULL;
1184 }
1185
1186 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1187 level, level,
1188 box->z, box->z + box->depth - 1,
1189 0, 0);
1190
1191 offset = r600_texture_get_offset(staging_depth, level, box);
1192 }
1193
1194 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1195 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1196 trans->staging = (struct r600_resource*)staging_depth;
1197 } else if (use_staging_texture) {
1198 struct pipe_resource resource;
1199 struct r600_texture *staging;
1200
1201 r600_init_temp_resource_from_box(&resource, texture, box, level,
1202 R600_RESOURCE_FLAG_TRANSFER);
1203 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1204 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1205
1206 /* Create the temporary texture. */
1207 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1208 if (!staging) {
1209 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1210 FREE(trans);
1211 return NULL;
1212 }
1213 trans->staging = &staging->resource;
1214 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1215 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1216 if (usage & PIPE_TRANSFER_READ) {
1217 r600_copy_to_staging_texture(ctx, trans);
1218 }
1219 } else {
1220 /* the resource is mapped directly */
1221 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1222 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1223 offset = r600_texture_get_offset(rtex, level, box);
1224 }
1225
1226 if (trans->staging) {
1227 buf = trans->staging;
1228 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1229 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1230 } else {
1231 buf = &rtex->resource;
1232 }
1233
1234 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1235 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1236 FREE(trans);
1237 return NULL;
1238 }
1239
1240 *ptransfer = &trans->transfer;
1241 return map + offset;
1242 }
1243
1244 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1245 struct pipe_transfer* transfer)
1246 {
1247 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1248 struct pipe_resource *texture = transfer->resource;
1249 struct r600_texture *rtex = (struct r600_texture*)texture;
1250
1251 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1252 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1253 ctx->resource_copy_region(ctx, texture, transfer->level,
1254 transfer->box.x, transfer->box.y, transfer->box.z,
1255 &rtransfer->staging->b.b, transfer->level,
1256 &transfer->box);
1257 } else {
1258 r600_copy_from_staging_texture(ctx, rtransfer);
1259 }
1260 }
1261
1262 if (rtransfer->staging)
1263 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1264
1265 FREE(transfer);
1266 }
1267
1268 static const struct u_resource_vtbl r600_texture_vtbl =
1269 {
1270 NULL, /* get_handle */
1271 r600_texture_destroy, /* resource_destroy */
1272 r600_texture_transfer_map, /* transfer_map */
1273 u_default_transfer_flush_region, /* transfer_flush_region */
1274 r600_texture_transfer_unmap, /* transfer_unmap */
1275 NULL /* transfer_inline_write */
1276 };
1277
1278 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1279 struct pipe_resource *texture,
1280 const struct pipe_surface *templ,
1281 unsigned width, unsigned height)
1282 {
1283 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1284
1285 if (!surface)
1286 return NULL;
1287
1288 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1289 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1290
1291 pipe_reference_init(&surface->base.reference, 1);
1292 pipe_resource_reference(&surface->base.texture, texture);
1293 surface->base.context = pipe;
1294 surface->base.format = templ->format;
1295 surface->base.width = width;
1296 surface->base.height = height;
1297 surface->base.u = templ->u;
1298 return &surface->base;
1299 }
1300
1301 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1302 struct pipe_resource *tex,
1303 const struct pipe_surface *templ)
1304 {
1305 unsigned level = templ->u.tex.level;
1306 unsigned width = u_minify(tex->width0, level);
1307 unsigned height = u_minify(tex->height0, level);
1308
1309 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1310 const struct util_format_description *tex_desc
1311 = util_format_description(tex->format);
1312 const struct util_format_description *templ_desc
1313 = util_format_description(templ->format);
1314
1315 assert(tex_desc->block.bits == templ_desc->block.bits);
1316
1317 /* Adjust size of surface if and only if the block width or
1318 * height is changed. */
1319 if (tex_desc->block.width != templ_desc->block.width ||
1320 tex_desc->block.height != templ_desc->block.height) {
1321 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1322 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1323
1324 width = nblks_x * templ_desc->block.width;
1325 height = nblks_y * templ_desc->block.height;
1326 }
1327 }
1328
1329 return r600_create_surface_custom(pipe, tex, templ, width, height);
1330 }
1331
1332 static void r600_surface_destroy(struct pipe_context *pipe,
1333 struct pipe_surface *surface)
1334 {
1335 struct r600_surface *surf = (struct r600_surface*)surface;
1336 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1337 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1338 pipe_resource_reference(&surface->texture, NULL);
1339 FREE(surface);
1340 }
1341
1342 unsigned r600_translate_colorswap(enum pipe_format format)
1343 {
1344 const struct util_format_description *desc = util_format_description(format);
1345
1346 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1347
1348 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1349 return V_0280A0_SWAP_STD;
1350
1351 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1352 return ~0U;
1353
1354 switch (desc->nr_channels) {
1355 case 1:
1356 if (HAS_SWIZZLE(0,X))
1357 return V_0280A0_SWAP_STD; /* X___ */
1358 else if (HAS_SWIZZLE(3,X))
1359 return V_0280A0_SWAP_ALT_REV; /* ___X */
1360 break;
1361 case 2:
1362 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1363 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1364 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1365 return V_0280A0_SWAP_STD; /* XY__ */
1366 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1367 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1368 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1369 return V_0280A0_SWAP_STD_REV; /* YX__ */
1370 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1371 return V_0280A0_SWAP_ALT; /* X__Y */
1372 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1373 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1374 break;
1375 case 3:
1376 if (HAS_SWIZZLE(0,X))
1377 return V_0280A0_SWAP_STD; /* XYZ */
1378 else if (HAS_SWIZZLE(0,Z))
1379 return V_0280A0_SWAP_STD_REV; /* ZYX */
1380 break;
1381 case 4:
1382 /* check the middle channels, the 1st and 4th channel can be NONE */
1383 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1384 return V_0280A0_SWAP_STD; /* XYZW */
1385 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1386 return V_0280A0_SWAP_STD_REV; /* WZYX */
1387 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1388 return V_0280A0_SWAP_ALT; /* ZYXW */
1389 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
1390 return V_0280A0_SWAP_ALT_REV; /* YZWX */
1391 break;
1392 }
1393 return ~0U;
1394 }
1395
1396 static void evergreen_set_clear_color(struct r600_texture *rtex,
1397 enum pipe_format surface_format,
1398 const union pipe_color_union *color)
1399 {
1400 union util_color uc;
1401
1402 memset(&uc, 0, sizeof(uc));
1403
1404 if (util_format_is_pure_uint(surface_format)) {
1405 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1406 } else if (util_format_is_pure_sint(surface_format)) {
1407 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1408 } else {
1409 util_pack_color(color->f, surface_format, &uc);
1410 }
1411
1412 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1413 }
1414
1415 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1416 const union pipe_color_union *color,
1417 uint32_t* reset_value,
1418 bool* clear_words_needed)
1419 {
1420 bool values[4] = {};
1421 int i;
1422 bool main_value = false;
1423 bool extra_value = false;
1424 int extra_channel;
1425 const struct util_format_description *desc = util_format_description(surface_format);
1426
1427 *clear_words_needed = true;
1428 *reset_value = 0x20202020U;
1429
1430 /* If we want to clear without needing a fast clear eliminate step, we
1431 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1432 * have two sets of flags, one for the last or first channel(extra) and
1433 * one for the other channels(main).
1434 */
1435
1436 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1437 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1438 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1439 extra_channel = -1;
1440 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1441 if(r600_translate_colorswap(surface_format) <= 1)
1442 extra_channel = desc->nr_channels - 1;
1443 else
1444 extra_channel = 0;
1445 } else
1446 return;
1447
1448 for (i = 0; i < 4; ++i) {
1449 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1450
1451 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1452 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1453 continue;
1454
1455 if (util_format_is_pure_sint(surface_format)) {
1456 values[i] = color->i[i] != 0;
1457 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1458 return;
1459 } else if (util_format_is_pure_uint(surface_format)) {
1460 values[i] = color->ui[i] != 0U;
1461 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1462 return;
1463 } else {
1464 values[i] = color->f[i] != 0.0F;
1465 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1466 return;
1467 }
1468
1469 if (index == extra_channel)
1470 extra_value = values[i];
1471 else
1472 main_value = values[i];
1473 }
1474
1475 for (int i = 0; i < 4; ++i)
1476 if (values[i] != main_value &&
1477 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1478 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1479 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1480 return;
1481
1482 *clear_words_needed = false;
1483 if (main_value)
1484 *reset_value |= 0x80808080U;
1485
1486 if (extra_value)
1487 *reset_value |= 0x40404040U;
1488 }
1489
1490 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1491 struct pipe_framebuffer_state *fb,
1492 struct r600_atom *fb_state,
1493 unsigned *buffers, unsigned *dirty_cbufs,
1494 const union pipe_color_union *color)
1495 {
1496 int i;
1497
1498 /* This function is broken in BE, so just disable this path for now */
1499 #ifdef PIPE_ARCH_BIG_ENDIAN
1500 return;
1501 #endif
1502
1503 if (rctx->render_cond)
1504 return;
1505
1506 for (i = 0; i < fb->nr_cbufs; i++) {
1507 struct r600_texture *tex;
1508 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1509
1510 if (!fb->cbufs[i])
1511 continue;
1512
1513 /* if this colorbuffer is not being cleared */
1514 if (!(*buffers & clear_bit))
1515 continue;
1516
1517 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1518
1519 /* 128-bit formats are unusupported */
1520 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1521 continue;
1522 }
1523
1524 /* the clear is allowed if all layers are bound */
1525 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1526 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1527 continue;
1528 }
1529
1530 /* cannot clear mipmapped textures */
1531 if (fb->cbufs[i]->texture->last_level != 0) {
1532 continue;
1533 }
1534
1535 /* only supported on tiled surfaces */
1536 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1537 continue;
1538 }
1539
1540 /* shared textures can't use fast clear without an explicit flush,
1541 * because there is no way to communicate the clear color among
1542 * all clients
1543 */
1544 if (tex->resource.is_shared &&
1545 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1546 continue;
1547
1548 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1549 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1550 rctx->chip_class >= CIK &&
1551 rctx->screen->info.drm_major == 2 &&
1552 rctx->screen->info.drm_minor < 38) {
1553 continue;
1554 }
1555
1556 if (tex->dcc_buffer) {
1557 uint32_t reset_value;
1558 bool clear_words_needed;
1559
1560 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1561 continue;
1562
1563 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1564
1565 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1566 0, tex->surface.dcc_size, reset_value, true);
1567
1568 if (clear_words_needed)
1569 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1570 } else {
1571 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1572 if (rctx->family == CHIP_STONEY)
1573 continue;
1574
1575 /* ensure CMASK is enabled */
1576 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1577 if (tex->cmask.size == 0) {
1578 continue;
1579 }
1580
1581 /* Do the fast clear. */
1582 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1583 tex->cmask.offset, tex->cmask.size, 0, true);
1584
1585 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1586 }
1587
1588 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1589
1590 if (dirty_cbufs)
1591 *dirty_cbufs |= 1 << i;
1592 rctx->set_atom_dirty(rctx, fb_state, true);
1593 *buffers &= ~clear_bit;
1594 }
1595 }
1596
1597 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1598 {
1599 rscreen->b.resource_from_handle = r600_texture_from_handle;
1600 rscreen->b.resource_get_handle = r600_texture_get_handle;
1601 }
1602
1603 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1604 {
1605 rctx->b.create_surface = r600_create_surface;
1606 rctx->b.surface_destroy = r600_surface_destroy;
1607 }