2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& src_level
< rsrc
->surface
.num_dcc_levels
) ||
76 (rdst
->dcc_offset
&& dst_level
< rdst
->surface
.num_dcc_levels
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 return rtex
->surface
.level
[level
].offset
+
184 box
->z
* rtex
->surface
.level
[level
].slice_size
+
185 (box
->y
/ rtex
->surface
.blk_h
*
186 rtex
->surface
.level
[level
].nblk_x
+
187 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
190 static int r600_init_surface(struct r600_common_screen
*rscreen
,
191 struct radeon_surf
*surface
,
192 const struct pipe_resource
*ptex
,
193 enum radeon_surf_mode array_mode
,
194 unsigned pitch_in_bytes_override
,
198 bool is_flushed_depth
,
199 bool tc_compatible_htile
)
201 const struct util_format_description
*desc
=
202 util_format_description(ptex
->format
);
203 bool is_depth
, is_stencil
;
205 unsigned i
, bpe
, flags
= 0;
207 is_depth
= util_format_has_depth(desc
);
208 is_stencil
= util_format_has_stencil(desc
);
210 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
211 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
212 bpe
= 4; /* stencil is allocated separately on evergreen */
214 bpe
= util_format_get_blocksize(ptex
->format
);
215 /* align byte per element on dword */
221 if (!is_flushed_depth
&& is_depth
) {
222 flags
|= RADEON_SURF_ZBUFFER
;
224 if (tc_compatible_htile
&&
225 array_mode
== RADEON_SURF_MODE_2D
) {
226 /* TC-compatible HTILE only supports Z32_FLOAT.
227 * GFX9 also supports Z16_UNORM.
228 * On VI, promote Z16 to Z32. DB->CB copies will convert
229 * the format for transfers.
231 if (rscreen
->chip_class
== VI
)
234 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
238 flags
|= RADEON_SURF_SBUFFER
;
241 if (rscreen
->chip_class
>= VI
&&
242 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
243 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
244 flags
|= RADEON_SURF_DISABLE_DCC
;
246 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
247 /* This should catch bugs in gallium users setting incorrect flags. */
248 assert(ptex
->nr_samples
<= 1 &&
249 ptex
->array_size
== 1 &&
251 ptex
->last_level
== 0 &&
252 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
254 flags
|= RADEON_SURF_SCANOUT
;
258 flags
|= RADEON_SURF_IMPORTED
;
259 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
260 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
262 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
263 array_mode
, surface
);
268 if (pitch_in_bytes_override
&&
269 pitch_in_bytes_override
!= surface
->level
[0].nblk_x
* bpe
) {
270 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
273 surface
->level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
274 surface
->level
[0].slice_size
= pitch_in_bytes_override
* surface
->level
[0].nblk_y
;
278 for (i
= 0; i
< ARRAY_SIZE(surface
->level
); ++i
)
279 surface
->level
[i
].offset
+= offset
;
284 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
285 struct radeon_bo_metadata
*metadata
)
287 struct radeon_surf
*surface
= &rtex
->surface
;
289 memset(metadata
, 0, sizeof(*metadata
));
290 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
291 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
292 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
293 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
294 metadata
->pipe_config
= surface
->pipe_config
;
295 metadata
->bankw
= surface
->bankw
;
296 metadata
->bankh
= surface
->bankh
;
297 metadata
->tile_split
= surface
->tile_split
;
298 metadata
->mtilea
= surface
->mtilea
;
299 metadata
->num_banks
= surface
->num_banks
;
300 metadata
->stride
= surface
->level
[0].nblk_x
* surface
->bpe
;
301 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
304 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
305 struct r600_texture
*rtex
)
307 struct r600_common_screen
*rscreen
= rctx
->screen
;
308 struct pipe_context
*ctx
= &rctx
->b
;
310 if (ctx
== rscreen
->aux_context
)
311 mtx_lock(&rscreen
->aux_context_lock
);
313 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
314 ctx
->flush(ctx
, NULL
, 0);
316 if (ctx
== rscreen
->aux_context
)
317 mtx_unlock(&rscreen
->aux_context_lock
);
320 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
321 struct r600_texture
*rtex
)
323 if (!rtex
->cmask
.size
)
326 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
329 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
330 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
331 rtex
->dirty_level_mask
= 0;
333 if (rscreen
->chip_class
>= SI
)
334 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
336 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
338 if (rtex
->cmask_buffer
!= &rtex
->resource
)
339 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
341 /* Notify all contexts about the change. */
342 p_atomic_inc(&rscreen
->dirty_tex_counter
);
343 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
346 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
348 /* We can't disable DCC if it can be written by another process. */
349 return rtex
->dcc_offset
&&
350 (!rtex
->resource
.is_shared
||
351 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
354 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
355 struct r600_texture
*rtex
)
357 if (!r600_can_disable_dcc(rtex
))
360 assert(rtex
->dcc_separate_buffer
== NULL
);
363 rtex
->dcc_offset
= 0;
365 /* Notify all contexts about the change. */
366 p_atomic_inc(&rscreen
->dirty_tex_counter
);
371 * Disable DCC for the texture. (first decompress, then discard metadata).
373 * There is unresolved multi-context synchronization issue between
374 * screen::aux_context and the current context. If applications do this with
375 * multiple contexts, it's already undefined behavior for them and we don't
376 * have to worry about that. The scenario is:
378 * If context 1 disables DCC and context 2 has queued commands that write
379 * to the texture via CB with DCC enabled, and the order of operations is
381 * context 2 queues draw calls rendering to the texture, but doesn't flush
382 * context 1 disables DCC and flushes
383 * context 1 & 2 reset descriptors and FB state
384 * context 2 flushes (new compressed tiles written by the draw calls)
385 * context 1 & 2 read garbage, because DCC is disabled, yet there are
388 * \param rctx the current context if you have one, or rscreen->aux_context
391 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
392 struct r600_texture
*rtex
)
394 struct r600_common_screen
*rscreen
= rctx
->screen
;
396 if (!r600_can_disable_dcc(rtex
))
399 if (&rctx
->b
== rscreen
->aux_context
)
400 mtx_lock(&rscreen
->aux_context_lock
);
402 /* Decompress DCC. */
403 rctx
->decompress_dcc(&rctx
->b
, rtex
);
404 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
406 if (&rctx
->b
== rscreen
->aux_context
)
407 mtx_unlock(&rscreen
->aux_context_lock
);
409 return r600_texture_discard_dcc(rscreen
, rtex
);
412 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
413 struct r600_texture
*rtex
,
414 bool invalidate_storage
)
416 struct pipe_screen
*screen
= rctx
->b
.screen
;
417 struct r600_texture
*new_tex
;
418 struct pipe_resource templ
= rtex
->resource
.b
.b
;
421 templ
.bind
|= PIPE_BIND_LINEAR
;
423 /* r600g doesn't react to dirty_tex_descriptor_counter */
424 if (rctx
->chip_class
< SI
)
427 if (rtex
->resource
.is_shared
||
428 rtex
->surface
.is_linear
)
431 /* This fails with MSAA, depth, and compressed textures. */
432 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
433 RADEON_SURF_MODE_LINEAR_ALIGNED
)
436 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
440 /* Copy the pixels to the new texture. */
441 if (!invalidate_storage
) {
442 for (i
= 0; i
<= templ
.last_level
; i
++) {
446 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
447 util_max_layer(&templ
, i
) + 1, &box
);
449 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
450 &rtex
->resource
.b
.b
, i
, &box
);
454 r600_texture_discard_cmask(rctx
->screen
, rtex
);
455 r600_texture_discard_dcc(rctx
->screen
, rtex
);
457 /* Replace the structure fields of rtex. */
458 rtex
->resource
.b
.b
.bind
= templ
.bind
;
459 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
460 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
461 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
462 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
463 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
464 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
465 rtex
->resource
.domains
= new_tex
->resource
.domains
;
466 rtex
->resource
.flags
= new_tex
->resource
.flags
;
467 rtex
->size
= new_tex
->size
;
468 rtex
->surface
= new_tex
->surface
;
469 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
470 rtex
->cb_color_info
= new_tex
->cb_color_info
;
471 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
473 assert(!rtex
->htile_buffer
);
474 assert(!rtex
->cmask
.size
);
475 assert(!rtex
->fmask
.size
);
476 assert(!rtex
->dcc_offset
);
477 assert(!rtex
->is_depth
);
479 r600_texture_reference(&new_tex
, NULL
);
481 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
484 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
485 struct pipe_context
*ctx
,
486 struct pipe_resource
*resource
,
487 struct winsys_handle
*whandle
,
490 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
491 struct r600_common_context
*rctx
= (struct r600_common_context
*)
492 (ctx
? ctx
: rscreen
->aux_context
);
493 struct r600_resource
*res
= (struct r600_resource
*)resource
;
494 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
495 struct radeon_bo_metadata metadata
;
496 bool update_metadata
= false;
498 /* This is not supported now, but it might be required for OpenCL
499 * interop in the future.
501 if (resource
->target
!= PIPE_BUFFER
&&
502 (resource
->nr_samples
> 1 || rtex
->is_depth
))
505 if (resource
->target
!= PIPE_BUFFER
) {
506 /* Since shader image stores don't support DCC on VI,
507 * disable it for external clients that want write
510 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
511 if (r600_texture_disable_dcc(rctx
, rtex
))
512 update_metadata
= true;
515 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
516 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
517 /* Eliminate fast clear (both CMASK and DCC) */
518 r600_eliminate_fast_color_clear(rctx
, rtex
);
520 /* Disable CMASK if flush_resource isn't going
523 if (rtex
->cmask
.size
)
524 r600_texture_discard_cmask(rscreen
, rtex
);
528 if (!res
->is_shared
|| update_metadata
) {
529 r600_texture_init_metadata(rtex
, &metadata
);
530 if (rscreen
->query_opaque_metadata
)
531 rscreen
->query_opaque_metadata(rscreen
, rtex
,
534 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
538 if (res
->is_shared
) {
539 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
542 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
543 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
544 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
546 res
->is_shared
= true;
547 res
->external_usage
= usage
;
550 return rscreen
->ws
->buffer_get_handle(res
->buf
,
551 rtex
->surface
.level
[0].nblk_x
*
553 rtex
->surface
.level
[0].offset
,
554 rtex
->surface
.level
[0].slice_size
,
558 static void r600_texture_destroy(struct pipe_screen
*screen
,
559 struct pipe_resource
*ptex
)
561 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
562 struct r600_resource
*resource
= &rtex
->resource
;
564 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
566 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
567 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
568 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
570 pb_reference(&resource
->buf
, NULL
);
571 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
572 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
576 static const struct u_resource_vtbl r600_texture_vtbl
;
578 /* The number of samples can be specified independently of the texture. */
579 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
580 struct r600_texture
*rtex
,
582 struct r600_fmask_info
*out
)
584 /* FMASK is allocated like an ordinary texture. */
585 struct pipe_resource templ
= rtex
->resource
.b
.b
;
586 struct radeon_surf fmask
= {};
589 memset(out
, 0, sizeof(*out
));
591 templ
.nr_samples
= 1;
592 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
594 if (rscreen
->chip_class
<= CAYMAN
) {
595 /* Use the same parameters and tile mode. */
596 fmask
.bankw
= rtex
->surface
.bankw
;
597 fmask
.bankh
= rtex
->surface
.bankh
;
598 fmask
.mtilea
= rtex
->surface
.mtilea
;
599 fmask
.tile_split
= rtex
->surface
.tile_split
;
605 switch (nr_samples
) {
614 R600_ERR("Invalid sample count for FMASK allocation.\n");
618 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
619 * This can be fixed by writing a separate FMASK allocator specifically
620 * for R600-R700 asics. */
621 if (rscreen
->chip_class
<= R700
) {
625 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
626 RADEON_SURF_MODE_2D
, &fmask
)) {
627 R600_ERR("Got error in surface_init while allocating FMASK.\n");
631 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
633 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
634 if (out
->slice_tile_max
)
635 out
->slice_tile_max
-= 1;
637 out
->tile_mode_index
= fmask
.tiling_index
[0];
638 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
639 out
->bank_height
= fmask
.bankh
;
640 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
641 out
->size
= fmask
.surf_size
;
644 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
645 struct r600_texture
*rtex
)
647 r600_texture_get_fmask_info(rscreen
, rtex
,
648 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
650 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
651 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
654 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
655 struct r600_texture
*rtex
,
656 struct r600_cmask_info
*out
)
658 unsigned cmask_tile_width
= 8;
659 unsigned cmask_tile_height
= 8;
660 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
661 unsigned element_bits
= 4;
662 unsigned cmask_cache_bits
= 1024;
663 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
664 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
666 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
667 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
668 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
669 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
670 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
672 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
673 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
675 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
676 unsigned slice_bytes
=
677 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
679 assert(macro_tile_width
% 128 == 0);
680 assert(macro_tile_height
% 128 == 0);
682 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
683 out
->alignment
= MAX2(256, base_align
);
684 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
685 align(slice_bytes
, base_align
);
688 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
689 struct r600_texture
*rtex
,
690 struct r600_cmask_info
*out
)
692 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
693 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
694 unsigned cl_width
, cl_height
;
709 case 16: /* Hawaii */
718 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
720 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
721 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
722 unsigned slice_elements
= (width
* height
) / (8*8);
724 /* Each element of CMASK is a nibble. */
725 unsigned slice_bytes
= slice_elements
/ 2;
727 out
->slice_tile_max
= (width
* height
) / (128*128);
728 if (out
->slice_tile_max
)
729 out
->slice_tile_max
-= 1;
731 out
->alignment
= MAX2(256, base_align
);
732 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
733 align(slice_bytes
, base_align
);
736 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
737 struct r600_texture
*rtex
)
739 if (rscreen
->chip_class
>= SI
) {
740 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
742 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
745 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
746 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
748 if (rscreen
->chip_class
>= SI
)
749 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
751 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
754 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
755 struct r600_texture
*rtex
)
757 if (rtex
->cmask_buffer
)
760 assert(rtex
->cmask
.size
== 0);
762 if (rscreen
->chip_class
>= SI
) {
763 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
765 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
768 rtex
->cmask_buffer
= (struct r600_resource
*)
769 r600_aligned_buffer_create(&rscreen
->b
,
770 R600_RESOURCE_FLAG_UNMAPPABLE
,
773 rtex
->cmask
.alignment
);
774 if (rtex
->cmask_buffer
== NULL
) {
775 rtex
->cmask
.size
= 0;
779 /* update colorbuffer state bits */
780 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
782 if (rscreen
->chip_class
>= SI
)
783 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
785 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
787 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
790 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
791 struct r600_texture
*rtex
)
793 unsigned cl_width
, cl_height
, width
, height
;
794 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
795 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
797 rtex
->surface
.htile_size
= 0;
799 if (rscreen
->chip_class
<= EVERGREEN
&&
800 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
803 /* HW bug on R6xx. */
804 if (rscreen
->chip_class
== R600
&&
805 (rtex
->resource
.b
.b
.width0
> 7680 ||
806 rtex
->resource
.b
.b
.height0
> 7680))
809 /* HTILE is broken with 1D tiling on old kernels and CIK. */
810 if (rscreen
->chip_class
>= CIK
&&
811 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
812 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
815 /* Overalign HTILE on P2 configs to work around GPU hangs in
816 * piglit/depthstencil-render-miplevels 585.
818 * This has been confirmed to help Kabini & Stoney, where the hangs
819 * are always reproducible. I think I have seen the test hang
820 * on Carrizo too, though it was very rare there.
822 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
851 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
852 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
854 slice_elements
= (width
* height
) / (8 * 8);
855 slice_bytes
= slice_elements
* 4;
857 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
858 base_align
= num_pipes
* pipe_interleave_bytes
;
860 rtex
->surface
.htile_alignment
= base_align
;
861 rtex
->surface
.htile_size
=
862 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
863 align(slice_bytes
, base_align
);
866 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
867 struct r600_texture
*rtex
)
869 uint32_t clear_value
;
871 if (rtex
->tc_compatible_htile
) {
872 clear_value
= 0x0000030F;
874 r600_texture_get_htile_size(rscreen
, rtex
);
878 if (!rtex
->surface
.htile_size
)
881 rtex
->htile_buffer
= (struct r600_resource
*)
882 r600_aligned_buffer_create(&rscreen
->b
,
883 R600_RESOURCE_FLAG_UNMAPPABLE
,
885 rtex
->surface
.htile_size
,
886 rtex
->surface
.htile_alignment
);
887 if (rtex
->htile_buffer
== NULL
) {
888 /* this is not a fatal error as we can still keep rendering
889 * without htile buffer */
890 R600_ERR("Failed to create buffer object for htile buffer.\n");
892 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
893 0, rtex
->surface
.htile_size
,
898 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
902 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
903 "blk_h=%u, array_size=%u, last_level=%u, "
904 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
905 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
906 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
908 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
909 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
910 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
912 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
913 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
914 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.bankw
,
915 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
916 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
917 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
919 if (rtex
->fmask
.size
)
920 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
921 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
922 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
923 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
924 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
926 if (rtex
->cmask
.size
)
927 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
928 "slice_tile_max=%u\n",
929 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
930 rtex
->cmask
.slice_tile_max
);
932 if (rtex
->htile_buffer
)
933 fprintf(f
, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
934 rtex
->htile_buffer
->b
.b
.width0
,
935 rtex
->htile_buffer
->buf
->alignment
,
936 rtex
->tc_compatible_htile
);
938 if (rtex
->dcc_offset
) {
939 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
940 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
941 rtex
->surface
.dcc_alignment
);
942 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
943 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
944 "fast_clear_size=%"PRIu64
"\n",
945 i
, i
< rtex
->surface
.num_dcc_levels
,
946 rtex
->surface
.level
[i
].dcc_offset
,
947 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
950 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
951 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
952 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
953 "mode=%u, tiling_index = %u\n",
954 i
, rtex
->surface
.level
[i
].offset
,
955 rtex
->surface
.level
[i
].slice_size
,
956 u_minify(rtex
->resource
.b
.b
.width0
, i
),
957 u_minify(rtex
->resource
.b
.b
.height0
, i
),
958 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
959 rtex
->surface
.level
[i
].nblk_x
,
960 rtex
->surface
.level
[i
].nblk_y
,
961 rtex
->surface
.level
[i
].mode
,
962 rtex
->surface
.tiling_index
[i
]);
964 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
965 fprintf(f
, " StencilLayout: tilesplit=%u\n",
966 rtex
->surface
.stencil_tile_split
);
967 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
968 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
969 "slice_size=%"PRIu64
", npix_x=%u, "
970 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
971 "mode=%u, tiling_index = %u\n",
972 i
, rtex
->surface
.stencil_level
[i
].offset
,
973 rtex
->surface
.stencil_level
[i
].slice_size
,
974 u_minify(rtex
->resource
.b
.b
.width0
, i
),
975 u_minify(rtex
->resource
.b
.b
.height0
, i
),
976 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
977 rtex
->surface
.stencil_level
[i
].nblk_x
,
978 rtex
->surface
.stencil_level
[i
].nblk_y
,
979 rtex
->surface
.stencil_level
[i
].mode
,
980 rtex
->surface
.stencil_tiling_index
[i
]);
985 /* Common processing for r600_texture_create and r600_texture_from_handle */
986 static struct r600_texture
*
987 r600_texture_create_object(struct pipe_screen
*screen
,
988 const struct pipe_resource
*base
,
989 struct pb_buffer
*buf
,
990 struct radeon_surf
*surface
)
992 struct r600_texture
*rtex
;
993 struct r600_resource
*resource
;
994 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
996 rtex
= CALLOC_STRUCT(r600_texture
);
1000 resource
= &rtex
->resource
;
1001 resource
->b
.b
= *base
;
1002 resource
->b
.b
.next
= NULL
;
1003 resource
->b
.vtbl
= &r600_texture_vtbl
;
1004 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1005 resource
->b
.b
.screen
= screen
;
1007 /* don't include stencil-only formats which we don't support for rendering */
1008 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1010 rtex
->surface
= *surface
;
1011 rtex
->size
= rtex
->surface
.surf_size
;
1013 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1014 (rtex
->surface
.flags
&
1015 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1017 /* TC-compatible HTILE:
1018 * - VI only supports Z32_FLOAT.
1019 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1020 if (rtex
->tc_compatible_htile
) {
1021 if (rscreen
->chip_class
>= GFX9
&&
1022 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1023 rtex
->db_render_format
= base
->format
;
1025 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1027 rtex
->db_render_format
= base
->format
;
1030 /* Tiled depth textures utilize the non-displayable tile order.
1031 * This must be done after r600_setup_surface.
1032 * Applies to R600-Cayman. */
1033 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1034 /* Applies to GCN. */
1035 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1037 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1038 * between frames, so the only thing that can enable separate DCC
1039 * with DRI2 is multiple slow clears within a frame.
1041 rtex
->ps_draw_ratio
= 0;
1043 if (rtex
->is_depth
) {
1044 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1045 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1046 rscreen
->chip_class
>= EVERGREEN
) {
1047 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1048 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1050 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1051 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1052 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1053 rtex
->can_sample_z
= true;
1056 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1057 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1058 rtex
->db_compatible
= true;
1060 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1061 r600_texture_allocate_htile(rscreen
, rtex
);
1064 if (base
->nr_samples
> 1) {
1066 r600_texture_allocate_fmask(rscreen
, rtex
);
1067 r600_texture_allocate_cmask(rscreen
, rtex
);
1068 rtex
->cmask_buffer
= &rtex
->resource
;
1070 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1076 /* Shared textures must always set up DCC here.
1077 * If it's not present, it will be disabled by
1078 * apply_opaque_metadata later.
1080 if (rtex
->surface
.dcc_size
&&
1081 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1082 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1083 /* Reserve space for the DCC buffer. */
1084 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1085 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1089 /* Now create the backing buffer. */
1091 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1092 rtex
->surface
.surf_alignment
);
1094 resource
->flags
|= RADEON_FLAG_HANDLE
;
1096 if (!r600_alloc_resource(rscreen
, resource
)) {
1101 resource
->buf
= buf
;
1102 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1103 resource
->bo_size
= buf
->size
;
1104 resource
->bo_alignment
= buf
->alignment
;
1105 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1106 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1107 resource
->vram_usage
= buf
->size
;
1108 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1109 resource
->gart_usage
= buf
->size
;
1112 if (rtex
->cmask
.size
) {
1113 /* Initialize the cmask to 0xCC (= compressed state). */
1114 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1115 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1119 /* Initialize DCC only if the texture is not being imported. */
1120 if (!buf
&& rtex
->dcc_offset
) {
1121 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1123 rtex
->surface
.dcc_size
,
1127 /* Initialize the CMASK base register value. */
1128 rtex
->cmask
.base_address_reg
=
1129 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1131 if (rscreen
->debug_flags
& DBG_VM
) {
1132 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1133 rtex
->resource
.gpu_address
,
1134 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1135 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1136 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1139 if (rscreen
->debug_flags
& DBG_TEX
) {
1141 r600_print_texture_info(rtex
, stdout
);
1148 static enum radeon_surf_mode
1149 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1150 const struct pipe_resource
*templ
)
1152 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1153 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1155 /* MSAA resources must be 2D tiled. */
1156 if (templ
->nr_samples
> 1)
1157 return RADEON_SURF_MODE_2D
;
1159 /* Transfer resources should be linear. */
1160 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1161 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1163 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1164 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1165 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1166 (templ
->target
== PIPE_TEXTURE_2D
||
1167 templ
->target
== PIPE_TEXTURE_3D
))
1168 force_tiling
= true;
1170 /* Handle common candidates for the linear mode.
1171 * Compressed textures and DB surfaces must always be tiled.
1173 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1174 (!util_format_is_depth_or_stencil(templ
->format
) ||
1175 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1176 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1177 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1179 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1180 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1181 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1183 /* Cursors are linear on SI.
1184 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1185 if (rscreen
->chip_class
>= SI
&&
1186 (templ
->bind
& PIPE_BIND_CURSOR
))
1187 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1189 if (templ
->bind
& PIPE_BIND_LINEAR
)
1190 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1192 /* Textures with a very small height are recommended to be linear. */
1193 if (templ
->target
== PIPE_TEXTURE_1D
||
1194 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1195 /* Only very thin and long 2D textures should benefit from
1196 * linear_aligned. */
1197 (templ
->width0
> 8 && templ
->height0
<= 2))
1198 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1200 /* Textures likely to be mapped often. */
1201 if (templ
->usage
== PIPE_USAGE_STAGING
||
1202 templ
->usage
== PIPE_USAGE_STREAM
)
1203 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1206 /* Make small textures 1D tiled. */
1207 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1208 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1209 return RADEON_SURF_MODE_1D
;
1211 /* The allocator will switch to 1D if needed. */
1212 return RADEON_SURF_MODE_2D
;
1215 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1216 const struct pipe_resource
*templ
)
1218 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1219 struct radeon_surf surface
= {0};
1220 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1221 bool tc_compatible_htile
=
1222 rscreen
->chip_class
>= VI
&&
1223 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1224 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1225 !is_flushed_depth
&&
1226 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1227 util_format_is_depth_or_stencil(templ
->format
);
1231 r
= r600_init_surface(rscreen
, &surface
, templ
,
1232 r600_choose_tiling(rscreen
, templ
), 0, 0,
1233 false, false, is_flushed_depth
,
1234 tc_compatible_htile
);
1239 return (struct pipe_resource
*)
1240 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1243 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1244 const struct pipe_resource
*templ
,
1245 struct winsys_handle
*whandle
,
1248 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1249 struct pb_buffer
*buf
= NULL
;
1250 unsigned stride
= 0, offset
= 0;
1251 unsigned array_mode
;
1252 struct radeon_surf surface
;
1254 struct radeon_bo_metadata metadata
= {};
1255 struct r600_texture
*rtex
;
1257 /* Support only 2D textures without mipmaps */
1258 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1259 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1262 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1266 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1268 surface
.pipe_config
= metadata
.pipe_config
;
1269 surface
.bankw
= metadata
.bankw
;
1270 surface
.bankh
= metadata
.bankh
;
1271 surface
.tile_split
= metadata
.tile_split
;
1272 surface
.mtilea
= metadata
.mtilea
;
1273 surface
.num_banks
= metadata
.num_banks
;
1275 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1276 array_mode
= RADEON_SURF_MODE_2D
;
1277 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1278 array_mode
= RADEON_SURF_MODE_1D
;
1280 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1282 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1283 offset
, true, metadata
.scanout
, false, false);
1288 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1292 rtex
->resource
.is_shared
= true;
1293 rtex
->resource
.external_usage
= usage
;
1295 if (rscreen
->apply_opaque_metadata
)
1296 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1298 return &rtex
->resource
.b
.b
;
1301 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1302 struct pipe_resource
*texture
,
1303 struct r600_texture
**staging
)
1305 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1306 struct pipe_resource resource
;
1307 struct r600_texture
**flushed_depth_texture
= staging
?
1308 staging
: &rtex
->flushed_depth_texture
;
1309 enum pipe_format pipe_format
= texture
->format
;
1312 if (rtex
->flushed_depth_texture
)
1313 return true; /* it's ready */
1315 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1316 switch (pipe_format
) {
1317 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1318 /* Save memory by not allocating the S plane. */
1319 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1321 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1322 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1323 /* Save memory bandwidth by not copying the
1324 * stencil part during flush.
1326 * This potentially increases memory bandwidth
1327 * if an application uses both Z and S texturing
1328 * simultaneously (a flushed Z24S8 texture
1329 * would be stored compactly), but how often
1330 * does that really happen?
1332 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1336 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1337 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1339 /* DB->CB copies to an 8bpp surface don't work. */
1340 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1344 memset(&resource
, 0, sizeof(resource
));
1345 resource
.target
= texture
->target
;
1346 resource
.format
= pipe_format
;
1347 resource
.width0
= texture
->width0
;
1348 resource
.height0
= texture
->height0
;
1349 resource
.depth0
= texture
->depth0
;
1350 resource
.array_size
= texture
->array_size
;
1351 resource
.last_level
= texture
->last_level
;
1352 resource
.nr_samples
= texture
->nr_samples
;
1353 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1354 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1355 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1358 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1360 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1361 if (*flushed_depth_texture
== NULL
) {
1362 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1366 (*flushed_depth_texture
)->non_disp_tiling
= false;
1371 * Initialize the pipe_resource descriptor to be of the same size as the box,
1372 * which is supposed to hold a subregion of the texture "orig" at the given
1375 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1376 struct pipe_resource
*orig
,
1377 const struct pipe_box
*box
,
1378 unsigned level
, unsigned flags
)
1380 memset(res
, 0, sizeof(*res
));
1381 res
->format
= orig
->format
;
1382 res
->width0
= box
->width
;
1383 res
->height0
= box
->height
;
1385 res
->array_size
= 1;
1386 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1389 /* We must set the correct texture target and dimensions for a 3D box. */
1390 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1391 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1392 res
->array_size
= box
->depth
;
1394 res
->target
= PIPE_TEXTURE_2D
;
1398 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1399 struct r600_texture
*rtex
,
1400 unsigned transfer_usage
,
1401 const struct pipe_box
*box
)
1403 /* r600g doesn't react to dirty_tex_descriptor_counter */
1404 return rscreen
->chip_class
>= SI
&&
1405 !rtex
->resource
.is_shared
&&
1406 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1407 rtex
->resource
.b
.b
.last_level
== 0 &&
1408 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1409 box
->x
, box
->y
, box
->z
,
1410 box
->width
, box
->height
,
1414 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1415 struct r600_texture
*rtex
)
1417 struct r600_common_screen
*rscreen
= rctx
->screen
;
1419 /* There is no point in discarding depth and tiled buffers. */
1420 assert(!rtex
->is_depth
);
1421 assert(rtex
->surface
.is_linear
);
1423 /* Reallocate the buffer in the same pipe_resource. */
1424 r600_alloc_resource(rscreen
, &rtex
->resource
);
1426 /* Initialize the CMASK base address (needed even without CMASK). */
1427 rtex
->cmask
.base_address_reg
=
1428 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1430 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1432 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1435 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1436 struct pipe_resource
*texture
,
1439 const struct pipe_box
*box
,
1440 struct pipe_transfer
**ptransfer
)
1442 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1443 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1444 struct r600_transfer
*trans
;
1445 struct r600_resource
*buf
;
1446 unsigned offset
= 0;
1448 bool use_staging_texture
= false;
1450 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1451 assert(box
->width
&& box
->height
&& box
->depth
);
1453 /* Depth textures use staging unconditionally. */
1454 if (!rtex
->is_depth
) {
1455 /* Degrade the tile mode if we get too many transfers on APUs.
1456 * On dGPUs, the staging texture is always faster.
1457 * Only count uploads that are at least 4x4 pixels large.
1459 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1461 box
->width
>= 4 && box
->height
>= 4 &&
1462 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1463 bool can_invalidate
=
1464 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1467 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1471 /* Tiled textures need to be converted into a linear texture for CPU
1472 * access. The staging texture is always linear and is placed in GART.
1474 * Reading from VRAM or GTT WC is slow, always use the staging
1475 * texture in this case.
1477 * Use the staging texture for uploads if the underlying BO
1480 if (!rtex
->surface
.is_linear
)
1481 use_staging_texture
= true;
1482 else if (usage
& PIPE_TRANSFER_READ
)
1483 use_staging_texture
=
1484 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1485 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1486 /* Write & linear only: */
1487 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1488 RADEON_USAGE_READWRITE
) ||
1489 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1490 RADEON_USAGE_READWRITE
)) {
1492 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1494 r600_texture_invalidate_storage(rctx
, rtex
);
1496 use_staging_texture
= true;
1500 trans
= CALLOC_STRUCT(r600_transfer
);
1503 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
1504 trans
->transfer
.level
= level
;
1505 trans
->transfer
.usage
= usage
;
1506 trans
->transfer
.box
= *box
;
1508 if (rtex
->is_depth
) {
1509 struct r600_texture
*staging_depth
;
1511 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1512 /* MSAA depth buffers need to be converted to single sample buffers.
1514 * Mapping MSAA depth buffers can occur if ReadPixels is called
1515 * with a multisample GLX visual.
1517 * First downsample the depth buffer to a temporary texture,
1518 * then decompress the temporary one to staging.
1520 * Only the region being mapped is transfered.
1522 struct pipe_resource resource
;
1524 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1526 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1527 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1532 if (usage
& PIPE_TRANSFER_READ
) {
1533 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1535 R600_ERR("failed to create a temporary depth texture\n");
1540 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1541 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1542 0, 0, 0, box
->depth
, 0, 0);
1543 pipe_resource_reference(&temp
, NULL
);
1547 /* XXX: only readback the rectangle which is being mapped? */
1548 /* XXX: when discard is true, no need to read back from depth texture */
1549 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1550 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1555 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1557 box
->z
, box
->z
+ box
->depth
- 1,
1560 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1563 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].nblk_x
*
1564 staging_depth
->surface
.bpe
;
1565 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1566 trans
->staging
= (struct r600_resource
*)staging_depth
;
1567 buf
= trans
->staging
;
1568 } else if (use_staging_texture
) {
1569 struct pipe_resource resource
;
1570 struct r600_texture
*staging
;
1572 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1573 R600_RESOURCE_FLAG_TRANSFER
);
1574 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1575 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1577 /* Create the temporary texture. */
1578 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1580 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1584 trans
->staging
= &staging
->resource
;
1585 trans
->transfer
.stride
= staging
->surface
.level
[0].nblk_x
*
1586 staging
->surface
.bpe
;
1587 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1589 if (usage
& PIPE_TRANSFER_READ
)
1590 r600_copy_to_staging_texture(ctx
, trans
);
1592 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1594 buf
= trans
->staging
;
1596 /* the resource is mapped directly */
1597 trans
->transfer
.stride
= rtex
->surface
.level
[level
].nblk_x
*
1599 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1600 offset
= r600_texture_get_offset(rtex
, level
, box
);
1601 buf
= &rtex
->resource
;
1604 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1605 r600_resource_reference(&trans
->staging
, NULL
);
1610 *ptransfer
= &trans
->transfer
;
1611 return map
+ offset
;
1614 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1615 struct pipe_transfer
* transfer
)
1617 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1618 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1619 struct pipe_resource
*texture
= transfer
->resource
;
1620 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1622 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1623 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1624 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1625 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1626 &rtransfer
->staging
->b
.b
, transfer
->level
,
1629 r600_copy_from_staging_texture(ctx
, rtransfer
);
1633 if (rtransfer
->staging
) {
1634 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1635 r600_resource_reference(&rtransfer
->staging
, NULL
);
1638 /* Heuristic for {upload, draw, upload, draw, ..}:
1640 * Flush the gfx IB if we've allocated too much texture storage.
1642 * The idea is that we don't want to build IBs that use too much
1643 * memory and put pressure on the kernel memory manager and we also
1644 * want to make temporary and invalidated buffers go idle ASAP to
1645 * decrease the total memory usage or make them reusable. The memory
1646 * usage will be slightly higher than given here because of the buffer
1647 * cache in the winsys.
1649 * The result is that the kernel memory manager is never a bottleneck.
1651 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1652 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1653 rctx
->num_alloc_tex_transfer_bytes
= 0;
1656 pipe_resource_reference(&transfer
->resource
, NULL
);
1660 static const struct u_resource_vtbl r600_texture_vtbl
=
1662 NULL
, /* get_handle */
1663 r600_texture_destroy
, /* resource_destroy */
1664 r600_texture_transfer_map
, /* transfer_map */
1665 u_default_transfer_flush_region
, /* transfer_flush_region */
1666 r600_texture_transfer_unmap
, /* transfer_unmap */
1669 /* DCC channel type categories within which formats can be reinterpreted
1670 * while keeping the same DCC encoding. The swizzle must also match. */
1671 enum dcc_channel_type
{
1672 dcc_channel_float32
,
1675 dcc_channel_float16
,
1678 dcc_channel_uint_10_10_10_2
,
1681 dcc_channel_incompatible
,
1684 /* Return the type of DCC encoding. */
1685 static enum dcc_channel_type
1686 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1690 /* Find the first non-void channel. */
1691 for (i
= 0; i
< desc
->nr_channels
; i
++)
1692 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1694 if (i
== desc
->nr_channels
)
1695 return dcc_channel_incompatible
;
1697 switch (desc
->channel
[i
].size
) {
1699 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1700 return dcc_channel_float32
;
1701 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1702 return dcc_channel_uint32
;
1703 return dcc_channel_sint32
;
1705 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1706 return dcc_channel_float16
;
1707 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1708 return dcc_channel_uint16
;
1709 return dcc_channel_sint16
;
1711 return dcc_channel_uint_10_10_10_2
;
1713 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1714 return dcc_channel_uint8
;
1715 return dcc_channel_sint8
;
1717 return dcc_channel_incompatible
;
1721 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1722 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1723 enum pipe_format format2
)
1725 const struct util_format_description
*desc1
, *desc2
;
1726 enum dcc_channel_type type1
, type2
;
1729 if (format1
== format2
)
1732 desc1
= util_format_description(format1
);
1733 desc2
= util_format_description(format2
);
1735 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1738 /* Swizzles must be the same. */
1739 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1740 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1741 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1742 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1745 type1
= vi_get_dcc_channel_type(desc1
);
1746 type2
= vi_get_dcc_channel_type(desc2
);
1748 return type1
!= dcc_channel_incompatible
&&
1749 type2
!= dcc_channel_incompatible
&&
1753 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1754 struct pipe_resource
*tex
,
1756 enum pipe_format view_format
)
1758 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1760 if (rtex
->dcc_offset
&&
1761 level
< rtex
->surface
.num_dcc_levels
&&
1762 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1763 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1764 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1767 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1768 struct pipe_resource
*texture
,
1769 const struct pipe_surface
*templ
,
1770 unsigned width
, unsigned height
)
1772 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1773 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1778 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1779 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1781 pipe_reference_init(&surface
->base
.reference
, 1);
1782 pipe_resource_reference(&surface
->base
.texture
, texture
);
1783 surface
->base
.context
= pipe
;
1784 surface
->base
.format
= templ
->format
;
1785 surface
->base
.width
= width
;
1786 surface
->base
.height
= height
;
1787 surface
->base
.u
= templ
->u
;
1789 if (texture
->target
!= PIPE_BUFFER
)
1790 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1794 return &surface
->base
;
1797 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1798 struct pipe_resource
*tex
,
1799 const struct pipe_surface
*templ
)
1801 unsigned level
= templ
->u
.tex
.level
;
1802 unsigned width
= u_minify(tex
->width0
, level
);
1803 unsigned height
= u_minify(tex
->height0
, level
);
1805 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1806 const struct util_format_description
*tex_desc
1807 = util_format_description(tex
->format
);
1808 const struct util_format_description
*templ_desc
1809 = util_format_description(templ
->format
);
1811 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1813 /* Adjust size of surface if and only if the block width or
1814 * height is changed. */
1815 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1816 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1817 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1818 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1820 width
= nblks_x
* templ_desc
->block
.width
;
1821 height
= nblks_y
* templ_desc
->block
.height
;
1825 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1828 static void r600_surface_destroy(struct pipe_context
*pipe
,
1829 struct pipe_surface
*surface
)
1831 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1832 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1833 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1834 pipe_resource_reference(&surface
->texture
, NULL
);
1838 static void r600_clear_texture(struct pipe_context
*pipe
,
1839 struct pipe_resource
*tex
,
1841 const struct pipe_box
*box
,
1844 struct pipe_screen
*screen
= pipe
->screen
;
1845 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1846 struct pipe_surface tmpl
= {{0}};
1847 struct pipe_surface
*sf
;
1848 const struct util_format_description
*desc
=
1849 util_format_description(tex
->format
);
1851 tmpl
.format
= tex
->format
;
1852 tmpl
.u
.tex
.first_layer
= box
->z
;
1853 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1854 tmpl
.u
.tex
.level
= level
;
1855 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1859 if (rtex
->is_depth
) {
1862 uint8_t stencil
= 0;
1864 /* Depth is always present. */
1865 clear
= PIPE_CLEAR_DEPTH
;
1866 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1868 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1869 clear
|= PIPE_CLEAR_STENCIL
;
1870 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1873 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1875 box
->width
, box
->height
, false);
1877 union pipe_color_union color
;
1879 /* pipe_color_union requires the full vec4 representation. */
1880 if (util_format_is_pure_uint(tex
->format
))
1881 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1882 else if (util_format_is_pure_sint(tex
->format
))
1883 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1885 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1887 if (screen
->is_format_supported(screen
, tex
->format
,
1889 PIPE_BIND_RENDER_TARGET
)) {
1890 pipe
->clear_render_target(pipe
, sf
, &color
,
1892 box
->width
, box
->height
, false);
1894 /* Software fallback - just for R9G9B9E5_FLOAT */
1895 util_clear_render_target(pipe
, sf
, &color
,
1897 box
->width
, box
->height
);
1900 pipe_surface_reference(&sf
, NULL
);
1903 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1905 const struct util_format_description
*desc
= util_format_description(format
);
1907 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1909 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1910 return V_0280A0_SWAP_STD
;
1912 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1915 switch (desc
->nr_channels
) {
1917 if (HAS_SWIZZLE(0,X
))
1918 return V_0280A0_SWAP_STD
; /* X___ */
1919 else if (HAS_SWIZZLE(3,X
))
1920 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1923 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1924 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1925 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1926 return V_0280A0_SWAP_STD
; /* XY__ */
1927 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1928 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1929 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1931 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1932 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1933 return V_0280A0_SWAP_ALT
; /* X__Y */
1934 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1935 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1938 if (HAS_SWIZZLE(0,X
))
1939 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1940 else if (HAS_SWIZZLE(0,Z
))
1941 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1944 /* check the middle channels, the 1st and 4th channel can be NONE */
1945 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1946 return V_0280A0_SWAP_STD
; /* XYZW */
1947 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1948 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1949 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1950 return V_0280A0_SWAP_ALT
; /* ZYXW */
1951 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1954 return V_0280A0_SWAP_ALT_REV
;
1956 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1963 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1965 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1970 if (rctx
->dcc_stats
[slot
].query_active
)
1971 vi_separate_dcc_stop_query(&rctx
->b
,
1972 rctx
->dcc_stats
[slot
].tex
);
1974 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1975 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1976 rctx
->b
.destroy_query(&rctx
->b
,
1977 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1978 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1981 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1985 * Return the per-context slot where DCC statistics queries for the texture live.
1987 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1988 struct r600_texture
*tex
)
1990 int i
, empty_slot
= -1;
1992 /* Remove zombie textures (textures kept alive by this array only). */
1993 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1994 if (rctx
->dcc_stats
[i
].tex
&&
1995 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
1996 vi_dcc_clean_up_context_slot(rctx
, i
);
1998 /* Find the texture. */
1999 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2000 /* Return if found. */
2001 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2002 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2006 /* Record the first seen empty slot. */
2007 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2011 /* Not found. Remove the oldest member to make space in the array. */
2012 if (empty_slot
== -1) {
2013 int oldest_slot
= 0;
2015 /* Find the oldest slot. */
2016 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2017 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2018 rctx
->dcc_stats
[i
].last_use_timestamp
)
2021 /* Clean up the oldest slot. */
2022 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2023 empty_slot
= oldest_slot
;
2026 /* Add the texture to the new slot. */
2027 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2028 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2032 static struct pipe_query
*
2033 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2035 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2036 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2038 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2039 return (struct pipe_query
*)query
;
2043 * Called when binding a color buffer.
2045 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2046 struct r600_texture
*tex
)
2048 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2049 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2051 assert(!rctx
->dcc_stats
[i
].query_active
);
2053 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2054 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2056 /* begin or resume the query */
2057 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2058 rctx
->dcc_stats
[i
].query_active
= true;
2062 * Called when unbinding a color buffer.
2064 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2065 struct r600_texture
*tex
)
2067 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2068 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2070 assert(rctx
->dcc_stats
[i
].query_active
);
2071 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2073 /* pause or end the query */
2074 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2075 rctx
->dcc_stats
[i
].query_active
= false;
2078 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2080 /* The minimum number of fullscreen draws per frame that is required
2082 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2085 /* Called by fast clear. */
2086 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2087 struct r600_texture
*tex
)
2089 /* The intent is to use this with shared displayable back buffers,
2090 * but it's not strictly limited only to them.
2092 if (!tex
->resource
.is_shared
||
2093 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2094 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2095 tex
->resource
.b
.b
.last_level
> 0 ||
2096 !tex
->surface
.dcc_size
)
2099 if (tex
->dcc_offset
)
2100 return; /* already enabled */
2102 /* Enable the DCC stat gathering. */
2103 if (!tex
->dcc_gather_statistics
) {
2104 tex
->dcc_gather_statistics
= true;
2105 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2108 if (!vi_should_enable_separate_dcc(tex
))
2109 return; /* stats show that DCC decompression is too expensive */
2111 assert(tex
->surface
.num_dcc_levels
);
2112 assert(!tex
->dcc_separate_buffer
);
2114 r600_texture_discard_cmask(rctx
->screen
, tex
);
2116 /* Get a DCC buffer. */
2117 if (tex
->last_dcc_separate_buffer
) {
2118 assert(tex
->dcc_gather_statistics
);
2119 assert(!tex
->dcc_separate_buffer
);
2120 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2121 tex
->last_dcc_separate_buffer
= NULL
;
2123 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2124 r600_aligned_buffer_create(rctx
->b
.screen
,
2125 R600_RESOURCE_FLAG_UNMAPPABLE
,
2127 tex
->surface
.dcc_size
,
2128 tex
->surface
.dcc_alignment
);
2129 if (!tex
->dcc_separate_buffer
)
2133 /* dcc_offset is the absolute GPUVM address. */
2134 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2136 /* no need to flag anything since this is called by fast clear that
2137 * flags framebuffer state
2142 * Called by pipe_context::flush_resource, the place where DCC decompression
2145 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2146 struct r600_texture
*tex
)
2148 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2149 struct pipe_query
*tmp
;
2150 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2151 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2152 bool disable
= false;
2154 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2155 union pipe_query_result result
;
2157 /* Read the results. */
2158 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2160 r600_query_hw_reset_buffers(rctx
,
2161 (struct r600_query_hw
*)
2162 rctx
->dcc_stats
[i
].ps_stats
[2]);
2164 /* Compute the approximate number of fullscreen draws. */
2165 tex
->ps_draw_ratio
=
2166 result
.pipeline_statistics
.ps_invocations
/
2167 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2168 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2170 disable
= tex
->dcc_separate_buffer
&&
2171 !vi_should_enable_separate_dcc(tex
);
2174 tex
->num_slow_clears
= 0;
2176 /* stop the statistics query for ps_stats[0] */
2178 vi_separate_dcc_stop_query(ctx
, tex
);
2180 /* Move the queries in the queue by one. */
2181 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2182 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2183 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2184 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2186 /* create and start a new query as ps_stats[0] */
2188 vi_separate_dcc_start_query(ctx
, tex
);
2191 assert(!tex
->last_dcc_separate_buffer
);
2192 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2193 tex
->dcc_separate_buffer
= NULL
;
2194 tex
->dcc_offset
= 0;
2195 /* no need to flag anything since this is called after
2196 * decompression that re-sets framebuffer state
2201 /* FAST COLOR CLEAR */
2203 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2204 enum pipe_format surface_format
,
2205 const union pipe_color_union
*color
)
2207 union util_color uc
;
2209 memset(&uc
, 0, sizeof(uc
));
2211 if (rtex
->surface
.bpe
== 16) {
2212 /* DCC fast clear only:
2213 * CLEAR_WORD0 = R = G = B
2216 assert(color
->ui
[0] == color
->ui
[1] &&
2217 color
->ui
[0] == color
->ui
[2]);
2218 uc
.ui
[0] = color
->ui
[0];
2219 uc
.ui
[1] = color
->ui
[3];
2220 } else if (util_format_is_pure_uint(surface_format
)) {
2221 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2222 } else if (util_format_is_pure_sint(surface_format
)) {
2223 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2225 util_pack_color(color
->f
, surface_format
, &uc
);
2228 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2231 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2232 const union pipe_color_union
*color
,
2233 uint32_t* reset_value
,
2234 bool* clear_words_needed
)
2236 bool values
[4] = {};
2238 bool main_value
= false;
2239 bool extra_value
= false;
2241 const struct util_format_description
*desc
= util_format_description(surface_format
);
2243 if (desc
->block
.bits
== 128 &&
2244 (color
->ui
[0] != color
->ui
[1] ||
2245 color
->ui
[0] != color
->ui
[2]))
2248 *clear_words_needed
= true;
2249 *reset_value
= 0x20202020U
;
2251 /* If we want to clear without needing a fast clear eliminate step, we
2252 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2253 * have two sets of flags, one for the last or first channel(extra) and
2254 * one for the other channels(main).
2257 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2258 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2259 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2261 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2262 if(r600_translate_colorswap(surface_format
, false) <= 1)
2263 extra_channel
= desc
->nr_channels
- 1;
2269 for (i
= 0; i
< 4; ++i
) {
2270 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2272 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2273 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2276 if (desc
->channel
[i
].pure_integer
&&
2277 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2278 /* Use the maximum value for clamping the clear color. */
2279 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2281 values
[i
] = color
->i
[i
] != 0;
2282 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2284 } else if (desc
->channel
[i
].pure_integer
&&
2285 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2286 /* Use the maximum value for clamping the clear color. */
2287 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2289 values
[i
] = color
->ui
[i
] != 0U;
2290 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2293 values
[i
] = color
->f
[i
] != 0.0F
;
2294 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2298 if (index
== extra_channel
)
2299 extra_value
= values
[i
];
2301 main_value
= values
[i
];
2304 for (int i
= 0; i
< 4; ++i
)
2305 if (values
[i
] != main_value
&&
2306 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2307 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2308 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2311 *clear_words_needed
= false;
2313 *reset_value
|= 0x80808080U
;
2316 *reset_value
|= 0x40404040U
;
2320 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2321 struct r600_texture
*rtex
,
2322 unsigned level
, unsigned clear_value
)
2324 struct pipe_resource
*dcc_buffer
;
2325 uint64_t dcc_offset
;
2327 assert(rtex
->dcc_offset
&& level
< rtex
->surface
.num_dcc_levels
);
2329 if (rtex
->dcc_separate_buffer
) {
2330 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2333 dcc_buffer
= &rtex
->resource
.b
.b
;
2334 dcc_offset
= rtex
->dcc_offset
;
2337 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2339 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2340 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2341 clear_value
, R600_COHERENCY_CB_META
);
2344 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2345 * This allows hitting the MSAA resolve fast path, which requires that both
2346 * src and dst micro tile modes match.
2348 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2349 struct r600_texture
*rtex
)
2351 if (rtex
->resource
.is_shared
||
2352 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2353 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2356 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2357 assert(rtex
->resource
.b
.b
.last_level
== 0);
2359 /* These magic numbers were copied from addrlib. It doesn't use any
2360 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2361 * different bpp and micro tile mode.
2363 if (rscreen
->chip_class
>= CIK
) {
2364 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2365 case RADEON_MICRO_MODE_DISPLAY
:
2366 rtex
->surface
.tiling_index
[0] = 10;
2368 case RADEON_MICRO_MODE_THIN
:
2369 rtex
->surface
.tiling_index
[0] = 14;
2371 case RADEON_MICRO_MODE_ROTATED
:
2372 rtex
->surface
.tiling_index
[0] = 28;
2374 default: /* depth, thick */
2375 assert(!"unexpected micro mode");
2379 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2380 case RADEON_MICRO_MODE_DISPLAY
:
2381 switch (rtex
->surface
.bpe
) {
2383 rtex
->surface
.tiling_index
[0] = 10;
2386 rtex
->surface
.tiling_index
[0] = 11;
2389 rtex
->surface
.tiling_index
[0] = 12;
2393 case RADEON_MICRO_MODE_THIN
:
2394 switch (rtex
->surface
.bpe
) {
2396 rtex
->surface
.tiling_index
[0] = 14;
2399 rtex
->surface
.tiling_index
[0] = 15;
2402 rtex
->surface
.tiling_index
[0] = 16;
2404 default: /* 8, 16 */
2405 rtex
->surface
.tiling_index
[0] = 17;
2409 default: /* depth, thick */
2410 assert(!"unexpected micro mode");
2415 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2417 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2420 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2421 struct pipe_framebuffer_state
*fb
,
2422 struct r600_atom
*fb_state
,
2423 unsigned *buffers
, unsigned *dirty_cbufs
,
2424 const union pipe_color_union
*color
)
2428 /* This function is broken in BE, so just disable this path for now */
2429 #ifdef PIPE_ARCH_BIG_ENDIAN
2433 if (rctx
->render_cond
)
2436 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2437 struct r600_texture
*tex
;
2438 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2443 /* if this colorbuffer is not being cleared */
2444 if (!(*buffers
& clear_bit
))
2447 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2449 /* the clear is allowed if all layers are bound */
2450 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2451 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2455 /* cannot clear mipmapped textures */
2456 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2460 /* only supported on tiled surfaces */
2461 if (tex
->surface
.is_linear
) {
2465 /* shared textures can't use fast clear without an explicit flush,
2466 * because there is no way to communicate the clear color among
2469 if (tex
->resource
.is_shared
&&
2470 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2473 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2474 if (rctx
->chip_class
== CIK
&&
2475 tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2476 rctx
->screen
->info
.drm_major
== 2 &&
2477 rctx
->screen
->info
.drm_minor
< 38) {
2481 /* Fast clear is the most appropriate place to enable DCC for
2482 * displayable surfaces.
2484 if (rctx
->chip_class
>= VI
&&
2485 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2486 vi_separate_dcc_try_enable(rctx
, tex
);
2488 /* RB+ isn't supported with a CMASK-based clear, so all
2489 * clears are considered to be hypothetically slow
2490 * clears, which is weighed when determining whether to
2491 * enable separate DCC.
2493 if (tex
->dcc_gather_statistics
&&
2494 rctx
->screen
->rbplus_allowed
)
2495 tex
->num_slow_clears
++;
2498 /* Try to clear DCC first, otherwise try CMASK. */
2499 if (tex
->dcc_offset
&& tex
->surface
.num_dcc_levels
) {
2500 uint32_t reset_value
;
2501 bool clear_words_needed
;
2503 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2506 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2507 color
, &reset_value
,
2508 &clear_words_needed
))
2511 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2513 if (clear_words_needed
)
2514 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2515 tex
->separate_dcc_dirty
= true;
2517 /* 128-bit formats are unusupported */
2518 if (tex
->surface
.bpe
> 8) {
2522 /* RB+ doesn't work with CMASK fast clear. */
2523 if (rctx
->screen
->rbplus_allowed
)
2526 /* ensure CMASK is enabled */
2527 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2528 if (tex
->cmask
.size
== 0) {
2532 /* Do the fast clear. */
2533 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2534 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2535 R600_COHERENCY_CB_META
);
2537 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2540 /* We can change the micro tile mode before a full clear. */
2541 if (rctx
->screen
->chip_class
>= SI
)
2542 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2544 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2547 *dirty_cbufs
|= 1 << i
;
2548 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2549 *buffers
&= ~clear_bit
;
2553 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2555 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2556 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2559 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2561 rctx
->b
.create_surface
= r600_create_surface
;
2562 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2563 rctx
->b
.clear_texture
= r600_clear_texture
;