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radeonsi: Implement DCC fast clear.
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static boolean r600_texture_get_handle(struct pipe_screen* screen,
232 struct pipe_resource *ptex,
233 struct winsys_handle *whandle)
234 {
235 struct r600_texture *rtex = (struct r600_texture*)ptex;
236 struct r600_resource *resource = &rtex->resource;
237 struct radeon_surf *surface = &rtex->surface;
238 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
239
240 rscreen->ws->buffer_set_tiling(resource->buf,
241 NULL,
242 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
243 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
244 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
245 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
246 surface->pipe_config,
247 surface->bankw, surface->bankh,
248 surface->tile_split,
249 surface->stencil_tile_split,
250 surface->mtilea, surface->num_banks,
251 surface->level[0].pitch_bytes,
252 (surface->flags & RADEON_SURF_SCANOUT) != 0);
253
254 return rscreen->ws->buffer_get_handle(resource->buf,
255 surface->level[0].pitch_bytes, whandle);
256 }
257
258 static void r600_texture_destroy(struct pipe_screen *screen,
259 struct pipe_resource *ptex)
260 {
261 struct r600_texture *rtex = (struct r600_texture*)ptex;
262 struct r600_resource *resource = &rtex->resource;
263
264 if (rtex->flushed_depth_texture)
265 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
266
267 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
268 if (rtex->cmask_buffer != &rtex->resource) {
269 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
270 }
271 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
272 pb_reference(&resource->buf, NULL);
273 FREE(rtex);
274 }
275
276 static const struct u_resource_vtbl r600_texture_vtbl;
277
278 /* The number of samples can be specified independently of the texture. */
279 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
280 struct r600_texture *rtex,
281 unsigned nr_samples,
282 struct r600_fmask_info *out)
283 {
284 /* FMASK is allocated like an ordinary texture. */
285 struct radeon_surf fmask = rtex->surface;
286
287 memset(out, 0, sizeof(*out));
288
289 fmask.bo_alignment = 0;
290 fmask.bo_size = 0;
291 fmask.nsamples = 1;
292 fmask.flags |= RADEON_SURF_FMASK;
293
294 /* Force 2D tiling if it wasn't set. This may occur when creating
295 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
296 * destination buffer must have an FMASK too. */
297 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
298 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
299
300 if (rscreen->chip_class >= SI) {
301 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
302 }
303
304 switch (nr_samples) {
305 case 2:
306 case 4:
307 fmask.bpe = 1;
308 if (rscreen->chip_class <= CAYMAN) {
309 fmask.bankh = 4;
310 }
311 break;
312 case 8:
313 fmask.bpe = 4;
314 break;
315 default:
316 R600_ERR("Invalid sample count for FMASK allocation.\n");
317 return;
318 }
319
320 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
321 * This can be fixed by writing a separate FMASK allocator specifically
322 * for R600-R700 asics. */
323 if (rscreen->chip_class <= R700) {
324 fmask.bpe *= 2;
325 }
326
327 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
328 R600_ERR("Got error in surface_init while allocating FMASK.\n");
329 return;
330 }
331
332 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
333
334 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
335 if (out->slice_tile_max)
336 out->slice_tile_max -= 1;
337
338 out->tile_mode_index = fmask.tiling_index[0];
339 out->pitch = fmask.level[0].nblk_x;
340 out->bank_height = fmask.bankh;
341 out->alignment = MAX2(256, fmask.bo_alignment);
342 out->size = fmask.bo_size;
343 }
344
345 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
346 struct r600_texture *rtex)
347 {
348 r600_texture_get_fmask_info(rscreen, rtex,
349 rtex->resource.b.b.nr_samples, &rtex->fmask);
350
351 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
352 rtex->size = rtex->fmask.offset + rtex->fmask.size;
353 }
354
355 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
356 struct r600_texture *rtex,
357 struct r600_cmask_info *out)
358 {
359 unsigned cmask_tile_width = 8;
360 unsigned cmask_tile_height = 8;
361 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
362 unsigned element_bits = 4;
363 unsigned cmask_cache_bits = 1024;
364 unsigned num_pipes = rscreen->tiling_info.num_channels;
365 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
366
367 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
368 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
369 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
370 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
371 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
372
373 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
374 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
375
376 unsigned base_align = num_pipes * pipe_interleave_bytes;
377 unsigned slice_bytes =
378 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
379
380 assert(macro_tile_width % 128 == 0);
381 assert(macro_tile_height % 128 == 0);
382
383 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
384 out->alignment = MAX2(256, base_align);
385 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
386 align(slice_bytes, base_align);
387 }
388
389 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
390 struct r600_texture *rtex,
391 struct r600_cmask_info *out)
392 {
393 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
394 unsigned num_pipes = rscreen->tiling_info.num_channels;
395 unsigned cl_width, cl_height;
396
397 switch (num_pipes) {
398 case 2:
399 cl_width = 32;
400 cl_height = 16;
401 break;
402 case 4:
403 cl_width = 32;
404 cl_height = 32;
405 break;
406 case 8:
407 cl_width = 64;
408 cl_height = 32;
409 break;
410 case 16: /* Hawaii */
411 cl_width = 64;
412 cl_height = 64;
413 break;
414 default:
415 assert(0);
416 return;
417 }
418
419 unsigned base_align = num_pipes * pipe_interleave_bytes;
420
421 unsigned width = align(rtex->surface.npix_x, cl_width*8);
422 unsigned height = align(rtex->surface.npix_y, cl_height*8);
423 unsigned slice_elements = (width * height) / (8*8);
424
425 /* Each element of CMASK is a nibble. */
426 unsigned slice_bytes = slice_elements / 2;
427
428 out->slice_tile_max = (width * height) / (128*128);
429 if (out->slice_tile_max)
430 out->slice_tile_max -= 1;
431
432 out->alignment = MAX2(256, base_align);
433 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
434 align(slice_bytes, base_align);
435 }
436
437 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
438 struct r600_texture *rtex)
439 {
440 if (rscreen->chip_class >= SI) {
441 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
442 } else {
443 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
444 }
445
446 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
447 rtex->size = rtex->cmask.offset + rtex->cmask.size;
448
449 if (rscreen->chip_class >= SI)
450 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
451 else
452 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
453 }
454
455 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
456 struct r600_texture *rtex)
457 {
458 if (rtex->cmask_buffer)
459 return;
460
461 assert(rtex->cmask.size == 0);
462
463 if (rscreen->chip_class >= SI) {
464 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
465 } else {
466 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
467 }
468
469 rtex->cmask_buffer = (struct r600_resource *)
470 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
471 PIPE_USAGE_DEFAULT, rtex->cmask.size);
472 if (rtex->cmask_buffer == NULL) {
473 rtex->cmask.size = 0;
474 return;
475 }
476
477 /* update colorbuffer state bits */
478 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
479
480 if (rscreen->chip_class >= SI)
481 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
482 else
483 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
484 }
485
486 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
487 struct r600_texture *rtex)
488 {
489 rtex->dcc_buffer = (struct r600_resource *)
490 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
491 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
492 if (rtex->dcc_buffer == NULL) {
493 return;
494 }
495
496 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
497 0xFFFFFFFF, true);
498
499 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
500 }
501
502 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
503 struct r600_texture *rtex)
504 {
505 unsigned cl_width, cl_height, width, height;
506 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
507 unsigned num_pipes = rscreen->tiling_info.num_channels;
508
509 if (rscreen->chip_class <= EVERGREEN &&
510 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
511 return 0;
512
513 /* HW bug on R6xx. */
514 if (rscreen->chip_class == R600 &&
515 (rtex->surface.level[0].npix_x > 7680 ||
516 rtex->surface.level[0].npix_y > 7680))
517 return 0;
518
519 /* HTILE is broken with 1D tiling on old kernels and CIK. */
520 if (rscreen->chip_class >= CIK &&
521 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
522 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
523 return 0;
524
525 switch (num_pipes) {
526 case 1:
527 cl_width = 32;
528 cl_height = 16;
529 break;
530 case 2:
531 cl_width = 32;
532 cl_height = 32;
533 break;
534 case 4:
535 cl_width = 64;
536 cl_height = 32;
537 break;
538 case 8:
539 cl_width = 64;
540 cl_height = 64;
541 break;
542 case 16:
543 cl_width = 128;
544 cl_height = 64;
545 break;
546 default:
547 assert(0);
548 return 0;
549 }
550
551 width = align(rtex->surface.npix_x, cl_width * 8);
552 height = align(rtex->surface.npix_y, cl_height * 8);
553
554 slice_elements = (width * height) / (8 * 8);
555 slice_bytes = slice_elements * 4;
556
557 pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
558 base_align = num_pipes * pipe_interleave_bytes;
559
560 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
561 align(slice_bytes, base_align);
562 }
563
564 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
565 struct r600_texture *rtex)
566 {
567 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
568
569 if (!htile_size)
570 return;
571
572 rtex->htile_buffer = (struct r600_resource*)
573 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
574 PIPE_USAGE_DEFAULT, htile_size);
575 if (rtex->htile_buffer == NULL) {
576 /* this is not a fatal error as we can still keep rendering
577 * without htile buffer */
578 R600_ERR("Failed to create buffer object for htile buffer.\n");
579 } else {
580 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
581 htile_size, 0, true);
582 }
583 }
584
585 /* Common processing for r600_texture_create and r600_texture_from_handle */
586 static struct r600_texture *
587 r600_texture_create_object(struct pipe_screen *screen,
588 const struct pipe_resource *base,
589 unsigned pitch_in_bytes_override,
590 struct pb_buffer *buf,
591 struct radeon_surf *surface)
592 {
593 struct r600_texture *rtex;
594 struct r600_resource *resource;
595 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
596
597 rtex = CALLOC_STRUCT(r600_texture);
598 if (rtex == NULL)
599 return NULL;
600
601 resource = &rtex->resource;
602 resource->b.b = *base;
603 resource->b.vtbl = &r600_texture_vtbl;
604 pipe_reference_init(&resource->b.b.reference, 1);
605 resource->b.b.screen = screen;
606 rtex->pitch_override = pitch_in_bytes_override;
607
608 /* don't include stencil-only formats which we don't support for rendering */
609 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
610
611 rtex->surface = *surface;
612 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
613 FREE(rtex);
614 return NULL;
615 }
616
617 /* Tiled depth textures utilize the non-displayable tile order.
618 * This must be done after r600_setup_surface.
619 * Applies to R600-Cayman. */
620 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
621
622 if (rtex->is_depth) {
623 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
624 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
625 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
626
627 r600_texture_allocate_htile(rscreen, rtex);
628 }
629 } else {
630 if (base->nr_samples > 1) {
631 if (!buf) {
632 r600_texture_allocate_fmask(rscreen, rtex);
633 r600_texture_allocate_cmask(rscreen, rtex);
634 rtex->cmask_buffer = &rtex->resource;
635 }
636 if (!rtex->fmask.size || !rtex->cmask.size) {
637 FREE(rtex);
638 return NULL;
639 }
640 }
641 if (rtex->surface.dcc_enabled) {
642 vi_texture_alloc_dcc_separate(rscreen, rtex);
643 }
644 }
645
646 /* Now create the backing buffer. */
647 if (!buf) {
648 if (!r600_init_resource(rscreen, resource, rtex->size,
649 rtex->surface.bo_alignment, TRUE)) {
650 FREE(rtex);
651 return NULL;
652 }
653 } else {
654 resource->buf = buf;
655 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
656 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->cs_buf);
657 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->cs_buf);
658 }
659
660 if (rtex->cmask.size) {
661 /* Initialize the cmask to 0xCC (= compressed state). */
662 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
663 rtex->cmask.offset, rtex->cmask.size,
664 0xCCCCCCCC, true);
665 }
666
667 /* Initialize the CMASK base register value. */
668 rtex->cmask.base_address_reg =
669 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
670
671 if (rscreen->debug_flags & DBG_VM) {
672 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
673 rtex->resource.gpu_address,
674 rtex->resource.gpu_address + rtex->resource.buf->size,
675 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
676 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
677 }
678
679 if (rscreen->debug_flags & DBG_TEX ||
680 (rtex->resource.b.b.last_level > 0 && rscreen->debug_flags & DBG_TEXMIP)) {
681 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
682 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
683 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
684 rtex->surface.npix_x, rtex->surface.npix_y,
685 rtex->surface.npix_z, rtex->surface.blk_w,
686 rtex->surface.blk_h, rtex->surface.blk_d,
687 rtex->surface.array_size, rtex->surface.last_level,
688 rtex->surface.bpe, rtex->surface.nsamples,
689 rtex->surface.flags, util_format_short_name(base->format));
690 for (int i = 0; i <= rtex->surface.last_level; i++) {
691 printf(" L %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
692 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
693 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
694 i, rtex->surface.level[i].offset,
695 rtex->surface.level[i].slice_size,
696 u_minify(rtex->resource.b.b.width0, i),
697 u_minify(rtex->resource.b.b.height0, i),
698 u_minify(rtex->resource.b.b.depth0, i),
699 rtex->surface.level[i].nblk_x,
700 rtex->surface.level[i].nblk_y,
701 rtex->surface.level[i].nblk_z,
702 rtex->surface.level[i].pitch_bytes,
703 rtex->surface.level[i].mode);
704 }
705 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
706 for (int i = 0; i <= rtex->surface.last_level; i++) {
707 printf(" S %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
708 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
709 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
710 i, rtex->surface.stencil_level[i].offset,
711 rtex->surface.stencil_level[i].slice_size,
712 u_minify(rtex->resource.b.b.width0, i),
713 u_minify(rtex->resource.b.b.height0, i),
714 u_minify(rtex->resource.b.b.depth0, i),
715 rtex->surface.stencil_level[i].nblk_x,
716 rtex->surface.stencil_level[i].nblk_y,
717 rtex->surface.stencil_level[i].nblk_z,
718 rtex->surface.stencil_level[i].pitch_bytes,
719 rtex->surface.stencil_level[i].mode);
720 }
721 }
722 }
723 return rtex;
724 }
725
726 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
727 const struct pipe_resource *templ)
728 {
729 const struct util_format_description *desc = util_format_description(templ->format);
730 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
731
732 /* MSAA resources must be 2D tiled. */
733 if (templ->nr_samples > 1)
734 return RADEON_SURF_MODE_2D;
735
736 /* Transfer resources should be linear. */
737 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
738 return RADEON_SURF_MODE_LINEAR_ALIGNED;
739
740 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
741 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
742 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
743 (templ->target == PIPE_TEXTURE_2D ||
744 templ->target == PIPE_TEXTURE_3D))
745 force_tiling = true;
746
747 /* Handle common candidates for the linear mode.
748 * Compressed textures must always be tiled. */
749 if (!force_tiling && !util_format_is_compressed(templ->format)) {
750 /* Not everything can be linear, so we cannot enforce it
751 * for all textures. */
752 if ((rscreen->debug_flags & DBG_NO_TILING) &&
753 (!util_format_is_depth_or_stencil(templ->format) ||
754 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
755 return RADEON_SURF_MODE_LINEAR_ALIGNED;
756
757 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
758 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
759 return RADEON_SURF_MODE_LINEAR_ALIGNED;
760
761 /* Cursors are linear on SI.
762 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
763 if (rscreen->chip_class >= SI &&
764 (templ->bind & PIPE_BIND_CURSOR))
765 return RADEON_SURF_MODE_LINEAR_ALIGNED;
766
767 if (templ->bind & PIPE_BIND_LINEAR)
768 return RADEON_SURF_MODE_LINEAR_ALIGNED;
769
770 /* Textures with a very small height are recommended to be linear. */
771 if (templ->target == PIPE_TEXTURE_1D ||
772 templ->target == PIPE_TEXTURE_1D_ARRAY ||
773 templ->height0 <= 4)
774 return RADEON_SURF_MODE_LINEAR_ALIGNED;
775
776 /* Textures likely to be mapped often. */
777 if (templ->usage == PIPE_USAGE_STAGING ||
778 templ->usage == PIPE_USAGE_STREAM)
779 return RADEON_SURF_MODE_LINEAR_ALIGNED;
780 }
781
782 /* Make small textures 1D tiled. */
783 if (templ->width0 <= 16 || templ->height0 <= 16 ||
784 (rscreen->debug_flags & DBG_NO_2D_TILING))
785 return RADEON_SURF_MODE_1D;
786
787 /* The allocator will switch to 1D if needed. */
788 return RADEON_SURF_MODE_2D;
789 }
790
791 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
792 const struct pipe_resource *templ)
793 {
794 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
795 struct radeon_surf surface = {0};
796 int r;
797
798 r = r600_init_surface(rscreen, &surface, templ,
799 r600_choose_tiling(rscreen, templ),
800 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
801 if (r) {
802 return NULL;
803 }
804 r = rscreen->ws->surface_best(rscreen->ws, &surface);
805 if (r) {
806 return NULL;
807 }
808 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
809 0, NULL, &surface);
810 }
811
812 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
813 const struct pipe_resource *templ,
814 struct winsys_handle *whandle)
815 {
816 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
817 struct pb_buffer *buf = NULL;
818 unsigned stride = 0;
819 unsigned array_mode;
820 enum radeon_bo_layout micro, macro;
821 struct radeon_surf surface;
822 bool scanout;
823 int r;
824
825 /* Support only 2D textures without mipmaps */
826 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
827 templ->depth0 != 1 || templ->last_level != 0)
828 return NULL;
829
830 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
831 if (!buf)
832 return NULL;
833
834 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
835 &surface.bankw, &surface.bankh,
836 &surface.tile_split,
837 &surface.stencil_tile_split,
838 &surface.mtilea, &scanout);
839
840 if (macro == RADEON_LAYOUT_TILED)
841 array_mode = RADEON_SURF_MODE_2D;
842 else if (micro == RADEON_LAYOUT_TILED)
843 array_mode = RADEON_SURF_MODE_1D;
844 else
845 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
846
847 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
848 if (r) {
849 return NULL;
850 }
851
852 if (scanout)
853 surface.flags |= RADEON_SURF_SCANOUT;
854
855 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
856 stride, buf, &surface);
857 }
858
859 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
860 struct pipe_resource *texture,
861 struct r600_texture **staging)
862 {
863 struct r600_texture *rtex = (struct r600_texture*)texture;
864 struct pipe_resource resource;
865 struct r600_texture **flushed_depth_texture = staging ?
866 staging : &rtex->flushed_depth_texture;
867
868 if (!staging && rtex->flushed_depth_texture)
869 return true; /* it's ready */
870
871 resource.target = texture->target;
872 resource.format = texture->format;
873 resource.width0 = texture->width0;
874 resource.height0 = texture->height0;
875 resource.depth0 = texture->depth0;
876 resource.array_size = texture->array_size;
877 resource.last_level = texture->last_level;
878 resource.nr_samples = texture->nr_samples;
879 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
880 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
881 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
882
883 if (staging)
884 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
885
886 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
887 if (*flushed_depth_texture == NULL) {
888 R600_ERR("failed to create temporary texture to hold flushed depth\n");
889 return false;
890 }
891
892 (*flushed_depth_texture)->is_flushing_texture = TRUE;
893 (*flushed_depth_texture)->non_disp_tiling = false;
894 return true;
895 }
896
897 /**
898 * Initialize the pipe_resource descriptor to be of the same size as the box,
899 * which is supposed to hold a subregion of the texture "orig" at the given
900 * mipmap level.
901 */
902 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
903 struct pipe_resource *orig,
904 const struct pipe_box *box,
905 unsigned level, unsigned flags)
906 {
907 memset(res, 0, sizeof(*res));
908 res->format = orig->format;
909 res->width0 = box->width;
910 res->height0 = box->height;
911 res->depth0 = 1;
912 res->array_size = 1;
913 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
914 res->flags = flags;
915
916 /* We must set the correct texture target and dimensions for a 3D box. */
917 if (box->depth > 1 && util_max_layer(orig, level) > 0)
918 res->target = orig->target;
919 else
920 res->target = PIPE_TEXTURE_2D;
921
922 switch (res->target) {
923 case PIPE_TEXTURE_1D_ARRAY:
924 case PIPE_TEXTURE_2D_ARRAY:
925 case PIPE_TEXTURE_CUBE_ARRAY:
926 res->array_size = box->depth;
927 break;
928 case PIPE_TEXTURE_3D:
929 res->depth0 = box->depth;
930 break;
931 default:;
932 }
933 }
934
935 static void *r600_texture_transfer_map(struct pipe_context *ctx,
936 struct pipe_resource *texture,
937 unsigned level,
938 unsigned usage,
939 const struct pipe_box *box,
940 struct pipe_transfer **ptransfer)
941 {
942 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
943 struct r600_texture *rtex = (struct r600_texture*)texture;
944 struct r600_transfer *trans;
945 boolean use_staging_texture = FALSE;
946 struct r600_resource *buf;
947 unsigned offset = 0;
948 char *map;
949
950 /* We cannot map a tiled texture directly because the data is
951 * in a different order, therefore we do detiling using a blit.
952 *
953 * Also, use a temporary in GTT memory for read transfers, as
954 * the CPU is much happier reading out of cached system memory
955 * than uncached VRAM.
956 */
957 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
958 use_staging_texture = TRUE;
959 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
960 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
961 /* Untiled buffers in VRAM, which is slow for CPU reads */
962 use_staging_texture = TRUE;
963 } else if (!(usage & PIPE_TRANSFER_READ) &&
964 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
965 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
966 /* Use a staging texture for uploads if the underlying BO is busy. */
967 use_staging_texture = TRUE;
968 }
969
970 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
971 use_staging_texture = FALSE;
972 }
973
974 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
975 return NULL;
976 }
977
978 trans = CALLOC_STRUCT(r600_transfer);
979 if (trans == NULL)
980 return NULL;
981 trans->transfer.resource = texture;
982 trans->transfer.level = level;
983 trans->transfer.usage = usage;
984 trans->transfer.box = *box;
985
986 if (rtex->is_depth) {
987 struct r600_texture *staging_depth;
988
989 if (rtex->resource.b.b.nr_samples > 1) {
990 /* MSAA depth buffers need to be converted to single sample buffers.
991 *
992 * Mapping MSAA depth buffers can occur if ReadPixels is called
993 * with a multisample GLX visual.
994 *
995 * First downsample the depth buffer to a temporary texture,
996 * then decompress the temporary one to staging.
997 *
998 * Only the region being mapped is transfered.
999 */
1000 struct pipe_resource resource;
1001
1002 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1003
1004 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1005 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1006 FREE(trans);
1007 return NULL;
1008 }
1009
1010 if (usage & PIPE_TRANSFER_READ) {
1011 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1012 if (!temp) {
1013 R600_ERR("failed to create a temporary depth texture\n");
1014 FREE(trans);
1015 return NULL;
1016 }
1017
1018 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1019 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1020 0, 0, 0, box->depth, 0, 0);
1021 pipe_resource_reference((struct pipe_resource**)&temp, NULL);
1022 }
1023 }
1024 else {
1025 /* XXX: only readback the rectangle which is being mapped? */
1026 /* XXX: when discard is true, no need to read back from depth texture */
1027 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1028 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1029 FREE(trans);
1030 return NULL;
1031 }
1032
1033 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1034 level, level,
1035 box->z, box->z + box->depth - 1,
1036 0, 0);
1037
1038 offset = r600_texture_get_offset(staging_depth, level, box);
1039 }
1040
1041 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1042 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1043 trans->staging = (struct r600_resource*)staging_depth;
1044 } else if (use_staging_texture) {
1045 struct pipe_resource resource;
1046 struct r600_texture *staging;
1047
1048 r600_init_temp_resource_from_box(&resource, texture, box, level,
1049 R600_RESOURCE_FLAG_TRANSFER);
1050 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1051 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1052
1053 /* Create the temporary texture. */
1054 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1055 if (staging == NULL) {
1056 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1057 FREE(trans);
1058 return NULL;
1059 }
1060 trans->staging = &staging->resource;
1061 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1062 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1063 if (usage & PIPE_TRANSFER_READ) {
1064 r600_copy_to_staging_texture(ctx, trans);
1065 }
1066 } else {
1067 /* the resource is mapped directly */
1068 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1069 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1070 offset = r600_texture_get_offset(rtex, level, box);
1071 }
1072
1073 if (trans->staging) {
1074 buf = trans->staging;
1075 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1076 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1077 } else {
1078 buf = &rtex->resource;
1079 }
1080
1081 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1082 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1083 FREE(trans);
1084 return NULL;
1085 }
1086
1087 *ptransfer = &trans->transfer;
1088 return map + offset;
1089 }
1090
1091 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1092 struct pipe_transfer* transfer)
1093 {
1094 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1095 struct pipe_resource *texture = transfer->resource;
1096 struct r600_texture *rtex = (struct r600_texture*)texture;
1097
1098 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1099 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1100 ctx->resource_copy_region(ctx, texture, transfer->level,
1101 transfer->box.x, transfer->box.y, transfer->box.z,
1102 &rtransfer->staging->b.b, transfer->level,
1103 &transfer->box);
1104 } else {
1105 r600_copy_from_staging_texture(ctx, rtransfer);
1106 }
1107 }
1108
1109 if (rtransfer->staging)
1110 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1111
1112 FREE(transfer);
1113 }
1114
1115 static const struct u_resource_vtbl r600_texture_vtbl =
1116 {
1117 NULL, /* get_handle */
1118 r600_texture_destroy, /* resource_destroy */
1119 r600_texture_transfer_map, /* transfer_map */
1120 u_default_transfer_flush_region, /* transfer_flush_region */
1121 r600_texture_transfer_unmap, /* transfer_unmap */
1122 NULL /* transfer_inline_write */
1123 };
1124
1125 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1126 struct pipe_resource *texture,
1127 const struct pipe_surface *templ,
1128 unsigned width, unsigned height)
1129 {
1130 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1131
1132 if (surface == NULL)
1133 return NULL;
1134
1135 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1136 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1137
1138 pipe_reference_init(&surface->base.reference, 1);
1139 pipe_resource_reference(&surface->base.texture, texture);
1140 surface->base.context = pipe;
1141 surface->base.format = templ->format;
1142 surface->base.width = width;
1143 surface->base.height = height;
1144 surface->base.u = templ->u;
1145 return &surface->base;
1146 }
1147
1148 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1149 struct pipe_resource *tex,
1150 const struct pipe_surface *templ)
1151 {
1152 unsigned level = templ->u.tex.level;
1153
1154 return r600_create_surface_custom(pipe, tex, templ,
1155 u_minify(tex->width0, level),
1156 u_minify(tex->height0, level));
1157 }
1158
1159 static void r600_surface_destroy(struct pipe_context *pipe,
1160 struct pipe_surface *surface)
1161 {
1162 struct r600_surface *surf = (struct r600_surface*)surface;
1163 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1164 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1165 pipe_resource_reference(&surface->texture, NULL);
1166 FREE(surface);
1167 }
1168
1169 unsigned r600_translate_colorswap(enum pipe_format format)
1170 {
1171 const struct util_format_description *desc = util_format_description(format);
1172
1173 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1174
1175 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1176 return V_0280A0_SWAP_STD;
1177
1178 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1179 return ~0U;
1180
1181 switch (desc->nr_channels) {
1182 case 1:
1183 if (HAS_SWIZZLE(0,X))
1184 return V_0280A0_SWAP_STD; /* X___ */
1185 else if (HAS_SWIZZLE(3,X))
1186 return V_0280A0_SWAP_ALT_REV; /* ___X */
1187 break;
1188 case 2:
1189 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1190 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1191 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1192 return V_0280A0_SWAP_STD; /* XY__ */
1193 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1194 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1195 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1196 return V_0280A0_SWAP_STD_REV; /* YX__ */
1197 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1198 return V_0280A0_SWAP_ALT; /* X__Y */
1199 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1200 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1201 break;
1202 case 3:
1203 if (HAS_SWIZZLE(0,X))
1204 return V_0280A0_SWAP_STD; /* XYZ */
1205 else if (HAS_SWIZZLE(0,Z))
1206 return V_0280A0_SWAP_STD_REV; /* ZYX */
1207 break;
1208 case 4:
1209 /* check the middle channels, the 1st and 4th channel can be NONE */
1210 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1211 return V_0280A0_SWAP_STD; /* XYZW */
1212 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1213 return V_0280A0_SWAP_STD_REV; /* WZYX */
1214 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1215 return V_0280A0_SWAP_ALT; /* ZYXW */
1216 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
1217 return V_0280A0_SWAP_ALT_REV; /* WXYZ */
1218 break;
1219 }
1220 return ~0U;
1221 }
1222
1223 static void evergreen_set_clear_color(struct r600_texture *rtex,
1224 enum pipe_format surface_format,
1225 const union pipe_color_union *color)
1226 {
1227 union util_color uc;
1228
1229 memset(&uc, 0, sizeof(uc));
1230
1231 if (util_format_is_pure_uint(surface_format)) {
1232 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1233 } else if (util_format_is_pure_sint(surface_format)) {
1234 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1235 } else {
1236 util_pack_color(color->f, surface_format, &uc);
1237 }
1238
1239 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1240 }
1241
1242 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1243 const union pipe_color_union *color,
1244 uint32_t* reset_value,
1245 bool* clear_words_needed)
1246 {
1247 bool values[4] = {};
1248 int i;
1249 bool main_value = false;
1250 bool extra_value = false;
1251 int extra_channel;
1252 const struct util_format_description *desc = util_format_description(surface_format);
1253
1254 *clear_words_needed = true;
1255 *reset_value = 0x20202020U;
1256
1257 /* If we want to clear without needing a fast clear eliminate step, we
1258 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1259 * have two sets of flags, one for the last or first channel(extra) and
1260 * one for the other channels(main).
1261 */
1262
1263 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1264 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1265 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1266 extra_channel = -1;
1267 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1268 if(r600_translate_colorswap(surface_format) <= 1)
1269 extra_channel = desc->nr_channels - 1;
1270 else
1271 extra_channel = 0;
1272 } else
1273 return;
1274
1275 for (i = 0; i < 4; ++i) {
1276 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1277
1278 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1279 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1280 continue;
1281
1282 if (util_format_is_pure_sint(surface_format)) {
1283 values[i] = color->i[i] != 0;
1284 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1285 return;
1286 } else if (util_format_is_pure_uint(surface_format)) {
1287 values[i] = color->ui[i] != 0U;
1288 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1289 return;
1290 } else {
1291 values[i] = color->f[i] != 0.0F;
1292 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1293 return;
1294 }
1295
1296 if (index == extra_channel)
1297 extra_value = values[i];
1298 else
1299 main_value = values[i];
1300 }
1301
1302 for (int i = 0; i < 4; ++i)
1303 if (values[i] != main_value &&
1304 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1305 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1306 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1307 return;
1308
1309 *clear_words_needed = false;
1310 if (main_value)
1311 *reset_value |= 0x80808080U;
1312
1313 if (extra_value)
1314 *reset_value |= 0x40404040U;
1315 }
1316
1317 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1318 struct pipe_framebuffer_state *fb,
1319 struct r600_atom *fb_state,
1320 unsigned *buffers, unsigned *dirty_cbufs,
1321 const union pipe_color_union *color)
1322 {
1323 int i;
1324
1325 if (rctx->current_render_cond)
1326 return;
1327
1328 for (i = 0; i < fb->nr_cbufs; i++) {
1329 struct r600_texture *tex;
1330 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1331
1332 if (!fb->cbufs[i])
1333 continue;
1334
1335 /* if this colorbuffer is not being cleared */
1336 if (!(*buffers & clear_bit))
1337 continue;
1338
1339 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1340
1341 /* 128-bit formats are unusupported */
1342 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1343 continue;
1344 }
1345
1346 /* the clear is allowed if all layers are bound */
1347 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1348 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1349 continue;
1350 }
1351
1352 /* cannot clear mipmapped textures */
1353 if (fb->cbufs[i]->texture->last_level != 0) {
1354 continue;
1355 }
1356
1357 /* only supported on tiled surfaces */
1358 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1359 continue;
1360 }
1361
1362 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1363 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1364 rctx->chip_class >= CIK &&
1365 rctx->screen->info.drm_major == 2 &&
1366 rctx->screen->info.drm_minor < 38) {
1367 continue;
1368 }
1369
1370 if (tex->surface.dcc_enabled) {
1371 uint32_t reset_value;
1372 bool clear_words_needed;
1373
1374 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1375
1376 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1377 0, tex->surface.dcc_size, reset_value, true);
1378
1379 if (clear_words_needed)
1380 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1381 } else {
1382 /* ensure CMASK is enabled */
1383 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1384 if (tex->cmask.size == 0) {
1385 continue;
1386 }
1387
1388 /* Do the fast clear. */
1389 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1390 tex->cmask.offset, tex->cmask.size, 0, true);
1391
1392 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1393 }
1394
1395 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1396
1397 if (dirty_cbufs)
1398 *dirty_cbufs |= 1 << i;
1399 rctx->set_atom_dirty(rctx, fb_state, true);
1400 *buffers &= ~clear_bit;
1401 }
1402 }
1403
1404 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1405 {
1406 rscreen->b.resource_from_handle = r600_texture_from_handle;
1407 rscreen->b.resource_get_handle = r600_texture_get_handle;
1408 }
1409
1410 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1411 {
1412 rctx->b.create_surface = r600_create_surface;
1413 rctx->b.surface_destroy = r600_surface_destroy;
1414 }