2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
41 const struct pipe_resource
*templ
);
44 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
56 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
76 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
185 return rtex
->surface
.level
[level
].offset
+
186 box
->z
* rtex
->surface
.level
[level
].slice_size
+
187 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
188 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
191 static int r600_init_surface(struct r600_common_screen
*rscreen
,
192 struct radeon_surf
*surface
,
193 const struct pipe_resource
*ptex
,
195 bool is_flushed_depth
)
197 const struct util_format_description
*desc
=
198 util_format_description(ptex
->format
);
199 bool is_depth
, is_stencil
;
201 is_depth
= util_format_has_depth(desc
);
202 is_stencil
= util_format_has_stencil(desc
);
204 surface
->npix_x
= ptex
->width0
;
205 surface
->npix_y
= ptex
->height0
;
206 surface
->npix_z
= ptex
->depth0
;
207 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
208 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
210 surface
->array_size
= 1;
211 surface
->last_level
= ptex
->last_level
;
213 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
214 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
215 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
217 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
218 /* align byte per element on dword */
219 if (surface
->bpe
== 3) {
224 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
225 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
227 switch (ptex
->target
) {
228 case PIPE_TEXTURE_1D
:
229 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
231 case PIPE_TEXTURE_RECT
:
232 case PIPE_TEXTURE_2D
:
233 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
235 case PIPE_TEXTURE_3D
:
236 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
238 case PIPE_TEXTURE_1D_ARRAY
:
239 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
240 surface
->array_size
= ptex
->array_size
;
242 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
243 assert(ptex
->array_size
% 6 == 0);
244 case PIPE_TEXTURE_2D_ARRAY
:
245 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
246 surface
->array_size
= ptex
->array_size
;
248 case PIPE_TEXTURE_CUBE
:
249 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
256 if (!is_flushed_depth
&& is_depth
) {
257 surface
->flags
|= RADEON_SURF_ZBUFFER
;
260 surface
->flags
|= RADEON_SURF_SBUFFER
|
261 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
264 if (rscreen
->chip_class
>= SI
) {
265 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
268 if (rscreen
->chip_class
>= VI
&&
269 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
270 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
271 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
273 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
274 /* This should catch bugs in gallium users setting incorrect flags. */
275 assert(surface
->nsamples
== 1 &&
276 surface
->array_size
== 1 &&
277 surface
->npix_z
== 1 &&
278 surface
->last_level
== 0 &&
279 !(surface
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
281 surface
->flags
|= RADEON_SURF_SCANOUT
;
286 static int r600_setup_surface(struct pipe_screen
*screen
,
287 struct r600_texture
*rtex
,
288 unsigned pitch_in_bytes_override
,
291 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
295 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
300 rtex
->size
= rtex
->surface
.bo_size
;
302 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
303 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
306 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
307 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
308 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
312 for (i
= 0; i
< ARRAY_SIZE(rtex
->surface
.level
); ++i
)
313 rtex
->surface
.level
[i
].offset
+= offset
;
318 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
319 struct radeon_bo_metadata
*metadata
)
321 struct radeon_surf
*surface
= &rtex
->surface
;
323 memset(metadata
, 0, sizeof(*metadata
));
324 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
325 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
326 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
327 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
328 metadata
->pipe_config
= surface
->pipe_config
;
329 metadata
->bankw
= surface
->bankw
;
330 metadata
->bankh
= surface
->bankh
;
331 metadata
->tile_split
= surface
->tile_split
;
332 metadata
->mtilea
= surface
->mtilea
;
333 metadata
->num_banks
= surface
->num_banks
;
334 metadata
->stride
= surface
->level
[0].pitch_bytes
;
335 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
338 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
340 p_atomic_inc(&rscreen
->dirty_fb_counter
);
343 static void r600_eliminate_fast_color_clear(struct r600_common_screen
*rscreen
,
344 struct r600_texture
*rtex
)
346 struct pipe_context
*ctx
= rscreen
->aux_context
;
348 pipe_mutex_lock(rscreen
->aux_context_lock
);
349 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
350 ctx
->flush(ctx
, NULL
, 0);
351 pipe_mutex_unlock(rscreen
->aux_context_lock
);
354 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
355 struct r600_texture
*rtex
)
357 if (!rtex
->cmask
.size
)
360 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
363 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
364 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
366 if (rscreen
->chip_class
>= SI
)
367 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
369 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
371 if (rtex
->cmask_buffer
!= &rtex
->resource
)
372 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
374 /* Notify all contexts about the change. */
375 r600_dirty_all_framebuffer_states(rscreen
);
376 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
379 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
381 /* We can't disable DCC if it can be written by another process. */
382 return rtex
->dcc_offset
&&
383 (!rtex
->resource
.is_shared
||
384 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
387 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
388 struct r600_texture
*rtex
)
390 if (!r600_can_disable_dcc(rtex
))
393 assert(rtex
->dcc_separate_buffer
== NULL
);
396 rtex
->dcc_offset
= 0;
398 /* Notify all contexts about the change. */
399 r600_dirty_all_framebuffer_states(rscreen
);
403 bool r600_texture_disable_dcc(struct r600_common_screen
*rscreen
,
404 struct r600_texture
*rtex
)
406 struct r600_common_context
*rctx
=
407 (struct r600_common_context
*)rscreen
->aux_context
;
409 if (!r600_can_disable_dcc(rtex
))
412 /* Decompress DCC. */
413 pipe_mutex_lock(rscreen
->aux_context_lock
);
414 rctx
->decompress_dcc(&rctx
->b
, rtex
);
415 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
416 pipe_mutex_unlock(rscreen
->aux_context_lock
);
418 return r600_texture_discard_dcc(rscreen
, rtex
);
421 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
422 struct r600_texture
*rtex
,
423 bool invalidate_storage
)
425 struct pipe_screen
*screen
= rctx
->b
.screen
;
426 struct r600_texture
*new_tex
;
427 struct pipe_resource templ
= rtex
->resource
.b
.b
;
430 templ
.bind
|= PIPE_BIND_LINEAR
;
432 /* r600g doesn't react to dirty_tex_descriptor_counter */
433 if (rctx
->chip_class
< SI
)
436 if (rtex
->resource
.is_shared
||
437 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
440 /* This fails with MSAA, depth, and compressed textures. */
441 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
442 RADEON_SURF_MODE_LINEAR_ALIGNED
)
445 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
449 /* Copy the pixels to the new texture. */
450 if (!invalidate_storage
) {
451 for (i
= 0; i
<= templ
.last_level
; i
++) {
455 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
456 util_max_layer(&templ
, i
) + 1, &box
);
458 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
459 &rtex
->resource
.b
.b
, i
, &box
);
463 r600_texture_discard_cmask(rctx
->screen
, rtex
);
464 r600_texture_discard_dcc(rctx
->screen
, rtex
);
466 /* Replace the structure fields of rtex. */
467 rtex
->resource
.b
.b
.bind
= templ
.bind
;
468 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
469 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
470 rtex
->resource
.domains
= new_tex
->resource
.domains
;
471 rtex
->size
= new_tex
->size
;
472 rtex
->surface
= new_tex
->surface
;
473 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
474 rtex
->cb_color_info
= new_tex
->cb_color_info
;
475 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
477 assert(!rtex
->htile_buffer
);
478 assert(!rtex
->cmask
.size
);
479 assert(!rtex
->fmask
.size
);
480 assert(!rtex
->dcc_offset
);
481 assert(!rtex
->is_depth
);
483 r600_texture_reference(&new_tex
, NULL
);
485 r600_dirty_all_framebuffer_states(rctx
->screen
);
486 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
489 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
490 struct pipe_resource
*resource
,
491 struct winsys_handle
*whandle
,
494 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
495 struct r600_resource
*res
= (struct r600_resource
*)resource
;
496 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
497 struct radeon_bo_metadata metadata
;
498 bool update_metadata
= false;
500 /* This is not supported now, but it might be required for OpenCL
501 * interop in the future.
503 if (resource
->target
!= PIPE_BUFFER
&&
504 (resource
->nr_samples
> 1 || rtex
->is_depth
))
507 if (resource
->target
!= PIPE_BUFFER
) {
508 /* Since shader image stores don't support DCC on VI,
509 * disable it for external clients that want write
512 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
513 if (r600_texture_disable_dcc(rscreen
, rtex
))
514 update_metadata
= true;
517 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
519 /* Eliminate fast clear (both CMASK and DCC) */
520 r600_eliminate_fast_color_clear(rscreen
, rtex
);
522 /* Disable CMASK if flush_resource isn't going
525 r600_texture_discard_cmask(rscreen
, rtex
);
529 if (!res
->is_shared
|| update_metadata
) {
530 r600_texture_init_metadata(rtex
, &metadata
);
531 if (rscreen
->query_opaque_metadata
)
532 rscreen
->query_opaque_metadata(rscreen
, rtex
,
535 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
539 if (res
->is_shared
) {
540 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
543 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
544 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
545 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
547 res
->is_shared
= true;
548 res
->external_usage
= usage
;
551 return rscreen
->ws
->buffer_get_handle(res
->buf
,
552 rtex
->surface
.level
[0].pitch_bytes
,
553 rtex
->surface
.level
[0].offset
,
554 rtex
->surface
.level
[0].slice_size
,
558 static void r600_texture_destroy(struct pipe_screen
*screen
,
559 struct pipe_resource
*ptex
)
561 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
562 struct r600_resource
*resource
= &rtex
->resource
;
564 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
566 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
567 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
568 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
570 pb_reference(&resource
->buf
, NULL
);
571 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
572 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
576 static const struct u_resource_vtbl r600_texture_vtbl
;
578 /* The number of samples can be specified independently of the texture. */
579 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
580 struct r600_texture
*rtex
,
582 struct r600_fmask_info
*out
)
584 /* FMASK is allocated like an ordinary texture. */
585 struct radeon_surf fmask
= rtex
->surface
;
587 memset(out
, 0, sizeof(*out
));
589 fmask
.bo_alignment
= 0;
592 fmask
.flags
|= RADEON_SURF_FMASK
;
594 /* Force 2D tiling if it wasn't set. This may occur when creating
595 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
596 * destination buffer must have an FMASK too. */
597 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
598 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
600 if (rscreen
->chip_class
>= SI
) {
601 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
604 switch (nr_samples
) {
608 if (rscreen
->chip_class
<= CAYMAN
) {
616 R600_ERR("Invalid sample count for FMASK allocation.\n");
620 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
621 * This can be fixed by writing a separate FMASK allocator specifically
622 * for R600-R700 asics. */
623 if (rscreen
->chip_class
<= R700
) {
627 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
628 R600_ERR("Got error in surface_init while allocating FMASK.\n");
632 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
634 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
635 if (out
->slice_tile_max
)
636 out
->slice_tile_max
-= 1;
638 out
->tile_mode_index
= fmask
.tiling_index
[0];
639 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
640 out
->bank_height
= fmask
.bankh
;
641 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
642 out
->size
= fmask
.bo_size
;
645 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
646 struct r600_texture
*rtex
)
648 r600_texture_get_fmask_info(rscreen
, rtex
,
649 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
651 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
652 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
655 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
656 struct r600_texture
*rtex
,
657 struct r600_cmask_info
*out
)
659 unsigned cmask_tile_width
= 8;
660 unsigned cmask_tile_height
= 8;
661 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
662 unsigned element_bits
= 4;
663 unsigned cmask_cache_bits
= 1024;
664 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
665 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
667 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
668 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
669 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
670 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
671 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
673 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
674 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
676 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
677 unsigned slice_bytes
=
678 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
680 assert(macro_tile_width
% 128 == 0);
681 assert(macro_tile_height
% 128 == 0);
683 out
->pitch
= pitch_elements
;
684 out
->height
= height
;
685 out
->xalign
= macro_tile_width
;
686 out
->yalign
= macro_tile_height
;
687 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
688 out
->alignment
= MAX2(256, base_align
);
689 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
690 align(slice_bytes
, base_align
);
693 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
694 struct r600_texture
*rtex
,
695 struct r600_cmask_info
*out
)
697 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
698 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
699 unsigned cl_width
, cl_height
;
714 case 16: /* Hawaii */
723 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
725 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
726 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
727 unsigned slice_elements
= (width
* height
) / (8*8);
729 /* Each element of CMASK is a nibble. */
730 unsigned slice_bytes
= slice_elements
/ 2;
733 out
->height
= height
;
734 out
->xalign
= cl_width
* 8;
735 out
->yalign
= cl_height
* 8;
736 out
->slice_tile_max
= (width
* height
) / (128*128);
737 if (out
->slice_tile_max
)
738 out
->slice_tile_max
-= 1;
740 out
->alignment
= MAX2(256, base_align
);
741 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
742 align(slice_bytes
, base_align
);
745 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
746 struct r600_texture
*rtex
)
748 if (rscreen
->chip_class
>= SI
) {
749 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
751 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
754 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
755 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
757 if (rscreen
->chip_class
>= SI
)
758 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
760 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
763 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
764 struct r600_texture
*rtex
)
766 if (rtex
->cmask_buffer
)
769 assert(rtex
->cmask
.size
== 0);
771 if (rscreen
->chip_class
>= SI
) {
772 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
774 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
777 rtex
->cmask_buffer
= (struct r600_resource
*)
778 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
779 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
780 if (rtex
->cmask_buffer
== NULL
) {
781 rtex
->cmask
.size
= 0;
785 /* update colorbuffer state bits */
786 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
788 if (rscreen
->chip_class
>= SI
)
789 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
791 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
793 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
796 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
797 struct r600_texture
*rtex
)
799 unsigned cl_width
, cl_height
, width
, height
;
800 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
801 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
803 if (rscreen
->chip_class
<= EVERGREEN
&&
804 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
807 /* HW bug on R6xx. */
808 if (rscreen
->chip_class
== R600
&&
809 (rtex
->surface
.level
[0].npix_x
> 7680 ||
810 rtex
->surface
.level
[0].npix_y
> 7680))
813 /* HTILE is broken with 1D tiling on old kernels and CIK. */
814 if (rscreen
->chip_class
>= CIK
&&
815 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
816 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
819 /* Overalign HTILE on P2 configs to work around GPU hangs in
820 * piglit/depthstencil-render-miplevels 585.
822 * This has been confirmed to help Kabini & Stoney, where the hangs
823 * are always reproducible. I think I have seen the test hang
824 * on Carrizo too, though it was very rare there.
826 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
855 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
856 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
858 slice_elements
= (width
* height
) / (8 * 8);
859 slice_bytes
= slice_elements
* 4;
861 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
862 base_align
= num_pipes
* pipe_interleave_bytes
;
864 rtex
->htile
.pitch
= width
;
865 rtex
->htile
.height
= height
;
866 rtex
->htile
.xalign
= cl_width
* 8;
867 rtex
->htile
.yalign
= cl_height
* 8;
869 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
870 align(slice_bytes
, base_align
);
873 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
874 struct r600_texture
*rtex
)
876 unsigned htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
881 rtex
->htile_buffer
= (struct r600_resource
*)
882 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
883 PIPE_USAGE_DEFAULT
, htile_size
);
884 if (rtex
->htile_buffer
== NULL
) {
885 /* this is not a fatal error as we can still keep rendering
886 * without htile buffer */
887 R600_ERR("Failed to create buffer object for htile buffer.\n");
889 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0,
890 htile_size
, 0, R600_COHERENCY_NONE
);
894 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
898 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
899 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
900 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
901 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
902 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
903 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
904 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
905 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
906 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
908 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
909 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
910 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
911 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
912 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
913 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
915 if (rtex
->fmask
.size
)
916 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
917 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
918 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
919 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
920 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
922 if (rtex
->cmask
.size
)
923 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
924 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
925 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
926 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
927 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
929 if (rtex
->htile_buffer
)
930 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
931 "xalign=%u, yalign=%u\n",
932 rtex
->htile_buffer
->b
.b
.width0
,
933 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
934 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
);
936 if (rtex
->dcc_offset
) {
937 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
938 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
939 rtex
->surface
.dcc_alignment
);
940 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
941 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
942 "fast_clear_size=%"PRIu64
"\n",
943 i
, rtex
->surface
.level
[i
].dcc_enabled
,
944 rtex
->surface
.level
[i
].dcc_offset
,
945 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
948 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
949 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
950 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
951 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
952 i
, rtex
->surface
.level
[i
].offset
,
953 rtex
->surface
.level
[i
].slice_size
,
954 u_minify(rtex
->resource
.b
.b
.width0
, i
),
955 u_minify(rtex
->resource
.b
.b
.height0
, i
),
956 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
957 rtex
->surface
.level
[i
].nblk_x
,
958 rtex
->surface
.level
[i
].nblk_y
,
959 rtex
->surface
.level
[i
].nblk_z
,
960 rtex
->surface
.level
[i
].pitch_bytes
,
961 rtex
->surface
.level
[i
].mode
);
963 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
964 fprintf(f
, " StencilLayout: tilesplit=%u\n",
965 rtex
->surface
.stencil_tile_split
);
966 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
967 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
968 "slice_size=%"PRIu64
", npix_x=%u, "
969 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
970 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
971 i
, rtex
->surface
.stencil_level
[i
].offset
,
972 rtex
->surface
.stencil_level
[i
].slice_size
,
973 u_minify(rtex
->resource
.b
.b
.width0
, i
),
974 u_minify(rtex
->resource
.b
.b
.height0
, i
),
975 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
976 rtex
->surface
.stencil_level
[i
].nblk_x
,
977 rtex
->surface
.stencil_level
[i
].nblk_y
,
978 rtex
->surface
.stencil_level
[i
].nblk_z
,
979 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
980 rtex
->surface
.stencil_level
[i
].mode
);
985 /* Common processing for r600_texture_create and r600_texture_from_handle */
986 static struct r600_texture
*
987 r600_texture_create_object(struct pipe_screen
*screen
,
988 const struct pipe_resource
*base
,
989 unsigned pitch_in_bytes_override
,
991 struct pb_buffer
*buf
,
992 struct radeon_surf
*surface
)
994 struct r600_texture
*rtex
;
995 struct r600_resource
*resource
;
996 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
998 rtex
= CALLOC_STRUCT(r600_texture
);
1002 resource
= &rtex
->resource
;
1003 resource
->b
.b
= *base
;
1004 resource
->b
.vtbl
= &r600_texture_vtbl
;
1005 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1006 resource
->b
.b
.screen
= screen
;
1008 /* don't include stencil-only formats which we don't support for rendering */
1009 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1011 rtex
->surface
= *surface
;
1012 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
, offset
)) {
1017 /* Tiled depth textures utilize the non-displayable tile order.
1018 * This must be done after r600_setup_surface.
1019 * Applies to R600-Cayman. */
1020 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1021 /* Applies to GCN. */
1022 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1024 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1025 * between frames, so the only thing that can enable separate DCC
1026 * with DRI2 is multiple slow clears within a frame.
1028 rtex
->ps_draw_ratio
= 0;
1030 if (rtex
->is_depth
) {
1031 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1032 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1033 rscreen
->chip_class
>= EVERGREEN
) {
1034 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1035 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1037 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1038 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1039 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1040 rtex
->can_sample_z
= true;
1043 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1044 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1045 rtex
->db_compatible
= true;
1047 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1048 r600_texture_allocate_htile(rscreen
, rtex
);
1051 if (base
->nr_samples
> 1) {
1053 r600_texture_allocate_fmask(rscreen
, rtex
);
1054 r600_texture_allocate_cmask(rscreen
, rtex
);
1055 rtex
->cmask_buffer
= &rtex
->resource
;
1057 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1063 /* Shared textures must always set up DCC here.
1064 * If it's not present, it will be disabled by
1065 * apply_opaque_metadata later.
1067 if (rtex
->surface
.dcc_size
&&
1068 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1069 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1070 /* Reserve space for the DCC buffer. */
1071 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1072 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1076 /* Now create the backing buffer. */
1078 if (!r600_init_resource(rscreen
, resource
, rtex
->size
,
1079 rtex
->surface
.bo_alignment
)) {
1084 resource
->buf
= buf
;
1085 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1086 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1089 if (rtex
->cmask
.size
) {
1090 /* Initialize the cmask to 0xCC (= compressed state). */
1091 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1092 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1093 0xCCCCCCCC, R600_COHERENCY_NONE
);
1096 /* Initialize DCC only if the texture is not being imported. */
1097 if (!buf
&& rtex
->dcc_offset
) {
1098 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1100 rtex
->surface
.dcc_size
,
1101 0xFFFFFFFF, R600_COHERENCY_NONE
);
1104 /* Initialize the CMASK base register value. */
1105 rtex
->cmask
.base_address_reg
=
1106 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1108 if (rscreen
->debug_flags
& DBG_VM
) {
1109 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1110 rtex
->resource
.gpu_address
,
1111 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1112 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1113 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1116 if (rscreen
->debug_flags
& DBG_TEX
) {
1118 r600_print_texture_info(rtex
, stdout
);
1125 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
1126 const struct pipe_resource
*templ
)
1128 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1129 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1131 /* MSAA resources must be 2D tiled. */
1132 if (templ
->nr_samples
> 1)
1133 return RADEON_SURF_MODE_2D
;
1135 /* Transfer resources should be linear. */
1136 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1137 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1139 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1140 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1141 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1142 (templ
->target
== PIPE_TEXTURE_2D
||
1143 templ
->target
== PIPE_TEXTURE_3D
))
1144 force_tiling
= true;
1146 /* Handle common candidates for the linear mode.
1147 * Compressed textures and DB surfaces must always be tiled.
1149 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1150 (!util_format_is_depth_or_stencil(templ
->format
) ||
1151 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1152 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1153 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1155 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1156 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1157 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1159 /* Cursors are linear on SI.
1160 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1161 if (rscreen
->chip_class
>= SI
&&
1162 (templ
->bind
& PIPE_BIND_CURSOR
))
1163 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1165 if (templ
->bind
& PIPE_BIND_LINEAR
)
1166 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1168 /* Textures with a very small height are recommended to be linear. */
1169 if (templ
->target
== PIPE_TEXTURE_1D
||
1170 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1171 templ
->height0
<= 4)
1172 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1174 /* Textures likely to be mapped often. */
1175 if (templ
->usage
== PIPE_USAGE_STAGING
||
1176 templ
->usage
== PIPE_USAGE_STREAM
)
1177 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1180 /* Make small textures 1D tiled. */
1181 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1182 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1183 return RADEON_SURF_MODE_1D
;
1185 /* The allocator will switch to 1D if needed. */
1186 return RADEON_SURF_MODE_2D
;
1189 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1190 const struct pipe_resource
*templ
)
1192 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1193 struct radeon_surf surface
= {0};
1196 r
= r600_init_surface(rscreen
, &surface
, templ
,
1197 r600_choose_tiling(rscreen
, templ
),
1198 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1202 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
1206 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, 0,
1210 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1211 const struct pipe_resource
*templ
,
1212 struct winsys_handle
*whandle
,
1215 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1216 struct pb_buffer
*buf
= NULL
;
1217 unsigned stride
= 0, offset
= 0;
1218 unsigned array_mode
;
1219 struct radeon_surf surface
;
1221 struct radeon_bo_metadata metadata
= {};
1222 struct r600_texture
*rtex
;
1224 /* Support only 2D textures without mipmaps */
1225 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1226 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1229 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1233 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1235 surface
.pipe_config
= metadata
.pipe_config
;
1236 surface
.bankw
= metadata
.bankw
;
1237 surface
.bankh
= metadata
.bankh
;
1238 surface
.tile_split
= metadata
.tile_split
;
1239 surface
.mtilea
= metadata
.mtilea
;
1240 surface
.num_banks
= metadata
.num_banks
;
1242 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1243 array_mode
= RADEON_SURF_MODE_2D
;
1244 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1245 array_mode
= RADEON_SURF_MODE_1D
;
1247 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1249 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
1254 if (metadata
.scanout
)
1255 surface
.flags
|= RADEON_SURF_SCANOUT
;
1257 rtex
= r600_texture_create_object(screen
, templ
, stride
,
1258 offset
, buf
, &surface
);
1262 rtex
->resource
.is_shared
= true;
1263 rtex
->resource
.external_usage
= usage
;
1265 if (rscreen
->apply_opaque_metadata
)
1266 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1268 return &rtex
->resource
.b
.b
;
1271 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1272 struct pipe_resource
*texture
,
1273 struct r600_texture
**staging
)
1275 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1276 struct pipe_resource resource
;
1277 struct r600_texture
**flushed_depth_texture
= staging
?
1278 staging
: &rtex
->flushed_depth_texture
;
1279 enum pipe_format pipe_format
= texture
->format
;
1282 if (rtex
->flushed_depth_texture
)
1283 return true; /* it's ready */
1285 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1286 switch (pipe_format
) {
1287 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1288 /* Save memory by not allocating the S plane. */
1289 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1291 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1292 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1293 /* Save memory bandwidth by not copying the
1294 * stencil part during flush.
1296 * This potentially increases memory bandwidth
1297 * if an application uses both Z and S texturing
1298 * simultaneously (a flushed Z24S8 texture
1299 * would be stored compactly), but how often
1300 * does that really happen?
1302 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1306 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1307 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1309 /* DB->CB copies to an 8bpp surface don't work. */
1310 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1314 resource
.target
= texture
->target
;
1315 resource
.format
= pipe_format
;
1316 resource
.width0
= texture
->width0
;
1317 resource
.height0
= texture
->height0
;
1318 resource
.depth0
= texture
->depth0
;
1319 resource
.array_size
= texture
->array_size
;
1320 resource
.last_level
= texture
->last_level
;
1321 resource
.nr_samples
= texture
->nr_samples
;
1322 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1323 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1324 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1327 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1329 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1330 if (*flushed_depth_texture
== NULL
) {
1331 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1335 (*flushed_depth_texture
)->non_disp_tiling
= false;
1340 * Initialize the pipe_resource descriptor to be of the same size as the box,
1341 * which is supposed to hold a subregion of the texture "orig" at the given
1344 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1345 struct pipe_resource
*orig
,
1346 const struct pipe_box
*box
,
1347 unsigned level
, unsigned flags
)
1349 memset(res
, 0, sizeof(*res
));
1350 res
->format
= orig
->format
;
1351 res
->width0
= box
->width
;
1352 res
->height0
= box
->height
;
1354 res
->array_size
= 1;
1355 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1358 /* We must set the correct texture target and dimensions for a 3D box. */
1359 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1360 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1361 res
->array_size
= box
->depth
;
1363 res
->target
= PIPE_TEXTURE_2D
;
1367 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1368 struct r600_texture
*rtex
,
1369 unsigned transfer_usage
,
1370 const struct pipe_box
*box
)
1372 /* r600g doesn't react to dirty_tex_descriptor_counter */
1373 return rscreen
->chip_class
>= SI
&&
1374 !rtex
->resource
.is_shared
&&
1375 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1376 rtex
->resource
.b
.b
.last_level
== 0 &&
1377 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1378 box
->x
, box
->y
, box
->z
,
1379 box
->width
, box
->height
,
1383 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1384 struct r600_texture
*rtex
)
1386 struct r600_common_screen
*rscreen
= rctx
->screen
;
1388 /* There is no point in discarding depth and tiled buffers. */
1389 assert(!rtex
->is_depth
);
1390 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1392 /* Reallocate the buffer in the same pipe_resource. */
1393 r600_init_resource(rscreen
, &rtex
->resource
, rtex
->size
,
1394 rtex
->surface
.bo_alignment
);
1396 /* Initialize the CMASK base address (needed even without CMASK). */
1397 rtex
->cmask
.base_address_reg
=
1398 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1400 r600_dirty_all_framebuffer_states(rscreen
);
1401 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1403 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1406 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1407 struct pipe_resource
*texture
,
1410 const struct pipe_box
*box
,
1411 struct pipe_transfer
**ptransfer
)
1413 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1414 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1415 struct r600_transfer
*trans
;
1416 struct r600_resource
*buf
;
1417 unsigned offset
= 0;
1419 bool use_staging_texture
= false;
1421 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1423 /* Depth textures use staging unconditionally. */
1424 if (!rtex
->is_depth
) {
1425 /* Degrade the tile mode if we get too many transfers on APUs.
1426 * On dGPUs, the staging texture is always faster.
1427 * Only count uploads that are at least 4x4 pixels large.
1429 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1431 box
->width
>= 4 && box
->height
>= 4 &&
1432 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1433 bool can_invalidate
=
1434 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1437 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1441 /* Tiled textures need to be converted into a linear texture for CPU
1442 * access. The staging texture is always linear and is placed in GART.
1444 * Reading from VRAM is slow, always use the staging texture in
1447 * Use the staging texture for uploads if the underlying BO
1450 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1451 use_staging_texture
= true;
1452 else if (usage
& PIPE_TRANSFER_READ
)
1453 use_staging_texture
= (rtex
->resource
.domains
&
1454 RADEON_DOMAIN_VRAM
) != 0;
1455 /* Write & linear only: */
1456 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1457 RADEON_USAGE_READWRITE
) ||
1458 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1459 RADEON_USAGE_READWRITE
)) {
1461 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1463 r600_texture_invalidate_storage(rctx
, rtex
);
1465 use_staging_texture
= true;
1469 trans
= CALLOC_STRUCT(r600_transfer
);
1472 trans
->transfer
.resource
= texture
;
1473 trans
->transfer
.level
= level
;
1474 trans
->transfer
.usage
= usage
;
1475 trans
->transfer
.box
= *box
;
1477 if (rtex
->is_depth
) {
1478 struct r600_texture
*staging_depth
;
1480 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1481 /* MSAA depth buffers need to be converted to single sample buffers.
1483 * Mapping MSAA depth buffers can occur if ReadPixels is called
1484 * with a multisample GLX visual.
1486 * First downsample the depth buffer to a temporary texture,
1487 * then decompress the temporary one to staging.
1489 * Only the region being mapped is transfered.
1491 struct pipe_resource resource
;
1493 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1495 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1496 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1501 if (usage
& PIPE_TRANSFER_READ
) {
1502 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1504 R600_ERR("failed to create a temporary depth texture\n");
1509 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1510 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1511 0, 0, 0, box
->depth
, 0, 0);
1512 pipe_resource_reference(&temp
, NULL
);
1516 /* XXX: only readback the rectangle which is being mapped? */
1517 /* XXX: when discard is true, no need to read back from depth texture */
1518 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1519 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1524 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1526 box
->z
, box
->z
+ box
->depth
- 1,
1529 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1532 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1533 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1534 trans
->staging
= (struct r600_resource
*)staging_depth
;
1535 buf
= trans
->staging
;
1536 } else if (use_staging_texture
) {
1537 struct pipe_resource resource
;
1538 struct r600_texture
*staging
;
1540 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1541 R600_RESOURCE_FLAG_TRANSFER
);
1542 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1543 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1545 /* Create the temporary texture. */
1546 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1548 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1552 trans
->staging
= &staging
->resource
;
1553 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1554 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1556 if (usage
& PIPE_TRANSFER_READ
)
1557 r600_copy_to_staging_texture(ctx
, trans
);
1559 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1561 buf
= trans
->staging
;
1563 /* the resource is mapped directly */
1564 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1565 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1566 offset
= r600_texture_get_offset(rtex
, level
, box
);
1567 buf
= &rtex
->resource
;
1570 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1571 r600_resource_reference(&trans
->staging
, NULL
);
1576 *ptransfer
= &trans
->transfer
;
1577 return map
+ offset
;
1580 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1581 struct pipe_transfer
* transfer
)
1583 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1584 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1585 struct pipe_resource
*texture
= transfer
->resource
;
1586 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1588 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1589 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1590 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1591 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1592 &rtransfer
->staging
->b
.b
, transfer
->level
,
1595 r600_copy_from_staging_texture(ctx
, rtransfer
);
1599 if (rtransfer
->staging
) {
1600 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1601 r600_resource_reference(&rtransfer
->staging
, NULL
);
1604 /* Heuristic for {upload, draw, upload, draw, ..}:
1606 * Flush the gfx IB if we've allocated too much texture storage.
1608 * The idea is that we don't want to build IBs that use too much
1609 * memory and put pressure on the kernel memory manager and we also
1610 * want to make temporary and invalidated buffers go idle ASAP to
1611 * decrease the total memory usage or make them reusable. The memory
1612 * usage will be slightly higher than given here because of the buffer
1613 * cache in the winsys.
1615 * The result is that the kernel memory manager is never a bottleneck.
1617 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1618 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1619 rctx
->num_alloc_tex_transfer_bytes
= 0;
1625 static const struct u_resource_vtbl r600_texture_vtbl
=
1627 NULL
, /* get_handle */
1628 r600_texture_destroy
, /* resource_destroy */
1629 r600_texture_transfer_map
, /* transfer_map */
1630 u_default_transfer_flush_region
, /* transfer_flush_region */
1631 r600_texture_transfer_unmap
, /* transfer_unmap */
1634 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1635 struct pipe_resource
*texture
,
1636 const struct pipe_surface
*templ
,
1637 unsigned width
, unsigned height
)
1639 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1640 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1645 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1646 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1648 pipe_reference_init(&surface
->base
.reference
, 1);
1649 pipe_resource_reference(&surface
->base
.texture
, texture
);
1650 surface
->base
.context
= pipe
;
1651 surface
->base
.format
= templ
->format
;
1652 surface
->base
.width
= width
;
1653 surface
->base
.height
= height
;
1654 surface
->base
.u
= templ
->u
;
1655 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1656 return &surface
->base
;
1659 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1660 struct pipe_resource
*tex
,
1661 const struct pipe_surface
*templ
)
1663 unsigned level
= templ
->u
.tex
.level
;
1664 unsigned width
= u_minify(tex
->width0
, level
);
1665 unsigned height
= u_minify(tex
->height0
, level
);
1667 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1668 const struct util_format_description
*tex_desc
1669 = util_format_description(tex
->format
);
1670 const struct util_format_description
*templ_desc
1671 = util_format_description(templ
->format
);
1673 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1675 /* Adjust size of surface if and only if the block width or
1676 * height is changed. */
1677 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1678 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1679 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1680 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1682 width
= nblks_x
* templ_desc
->block
.width
;
1683 height
= nblks_y
* templ_desc
->block
.height
;
1687 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1690 static void r600_surface_destroy(struct pipe_context
*pipe
,
1691 struct pipe_surface
*surface
)
1693 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1694 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1695 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1696 pipe_resource_reference(&surface
->texture
, NULL
);
1700 static void r600_clear_texture(struct pipe_context
*pipe
,
1701 struct pipe_resource
*tex
,
1703 const struct pipe_box
*box
,
1706 struct pipe_screen
*screen
= pipe
->screen
;
1707 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1708 struct pipe_surface tmpl
= {{0}};
1709 struct pipe_surface
*sf
;
1710 const struct util_format_description
*desc
=
1711 util_format_description(tex
->format
);
1713 tmpl
.format
= tex
->format
;
1714 tmpl
.u
.tex
.first_layer
= box
->z
;
1715 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1716 tmpl
.u
.tex
.level
= level
;
1717 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1721 if (rtex
->is_depth
) {
1724 uint8_t stencil
= 0;
1726 /* Depth is always present. */
1727 clear
= PIPE_CLEAR_DEPTH
;
1728 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1730 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1731 clear
|= PIPE_CLEAR_STENCIL
;
1732 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1735 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1737 box
->width
, box
->height
, false);
1739 union pipe_color_union color
;
1741 /* pipe_color_union requires the full vec4 representation. */
1742 if (util_format_is_pure_uint(tex
->format
))
1743 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1744 else if (util_format_is_pure_sint(tex
->format
))
1745 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1747 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1749 if (screen
->is_format_supported(screen
, tex
->format
,
1751 PIPE_BIND_RENDER_TARGET
)) {
1752 pipe
->clear_render_target(pipe
, sf
, &color
,
1754 box
->width
, box
->height
, false);
1756 /* Software fallback - just for R9G9B9E5_FLOAT */
1757 util_clear_render_target(pipe
, sf
, &color
,
1759 box
->width
, box
->height
);
1762 pipe_surface_reference(&sf
, NULL
);
1765 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1767 const struct util_format_description
*desc
= util_format_description(format
);
1769 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1771 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1772 return V_0280A0_SWAP_STD
;
1774 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1777 switch (desc
->nr_channels
) {
1779 if (HAS_SWIZZLE(0,X
))
1780 return V_0280A0_SWAP_STD
; /* X___ */
1781 else if (HAS_SWIZZLE(3,X
))
1782 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1785 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1786 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1787 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1788 return V_0280A0_SWAP_STD
; /* XY__ */
1789 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1790 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1791 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1793 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1794 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1795 return V_0280A0_SWAP_ALT
; /* X__Y */
1796 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1797 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1800 if (HAS_SWIZZLE(0,X
))
1801 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1802 else if (HAS_SWIZZLE(0,Z
))
1803 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1806 /* check the middle channels, the 1st and 4th channel can be NONE */
1807 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1808 return V_0280A0_SWAP_STD
; /* XYZW */
1809 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1810 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1811 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1812 return V_0280A0_SWAP_ALT
; /* ZYXW */
1813 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1816 return V_0280A0_SWAP_ALT_REV
;
1818 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1825 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1827 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1832 if (rctx
->dcc_stats
[slot
].query_active
)
1833 vi_separate_dcc_stop_query(&rctx
->b
,
1834 rctx
->dcc_stats
[slot
].tex
);
1836 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1837 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1838 rctx
->b
.destroy_query(&rctx
->b
,
1839 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1840 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1843 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1847 * Return the per-context slot where DCC statistics queries for the texture live.
1849 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1850 struct r600_texture
*tex
)
1852 int i
, empty_slot
= -1;
1854 /* Remove zombie textures (textures kept alive by this array only). */
1855 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1856 if (rctx
->dcc_stats
[i
].tex
&&
1857 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
1858 vi_dcc_clean_up_context_slot(rctx
, i
);
1860 /* Find the texture. */
1861 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
1862 /* Return if found. */
1863 if (rctx
->dcc_stats
[i
].tex
== tex
) {
1864 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
1868 /* Record the first seen empty slot. */
1869 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
1873 /* Not found. Remove the oldest member to make space in the array. */
1874 if (empty_slot
== -1) {
1875 int oldest_slot
= 0;
1877 /* Find the oldest slot. */
1878 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1879 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
1880 rctx
->dcc_stats
[i
].last_use_timestamp
)
1883 /* Clean up the oldest slot. */
1884 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
1885 empty_slot
= oldest_slot
;
1888 /* Add the texture to the new slot. */
1889 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
1890 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
1894 static struct pipe_query
*
1895 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
1897 struct r600_query_hw
*query
= (struct r600_query_hw
*)
1898 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
1900 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
1901 return (struct pipe_query
*)query
;
1905 * Called when binding a color buffer.
1907 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
1908 struct r600_texture
*tex
)
1910 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1911 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1913 assert(!rctx
->dcc_stats
[i
].query_active
);
1915 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
1916 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
1918 /* begin or resume the query */
1919 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
1920 rctx
->dcc_stats
[i
].query_active
= true;
1924 * Called when unbinding a color buffer.
1926 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
1927 struct r600_texture
*tex
)
1929 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1930 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1932 assert(rctx
->dcc_stats
[i
].query_active
);
1933 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
1935 /* pause or end the query */
1936 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
1937 rctx
->dcc_stats
[i
].query_active
= false;
1940 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
1942 /* The minimum number of fullscreen draws per frame that is required
1944 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
1947 /* Called by fast clear. */
1948 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
1949 struct r600_texture
*tex
)
1951 /* The intent is to use this with shared displayable back buffers,
1952 * but it's not strictly limited only to them.
1954 if (!tex
->resource
.is_shared
||
1955 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
1956 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
1957 tex
->surface
.last_level
> 0 ||
1958 !tex
->surface
.dcc_size
)
1961 if (tex
->dcc_offset
)
1962 return; /* already enabled */
1964 /* Enable the DCC stat gathering. */
1965 if (!tex
->dcc_gather_statistics
) {
1966 tex
->dcc_gather_statistics
= true;
1967 vi_separate_dcc_start_query(&rctx
->b
, tex
);
1970 if (!vi_should_enable_separate_dcc(tex
))
1971 return; /* stats show that DCC decompression is too expensive */
1973 assert(tex
->surface
.level
[0].dcc_enabled
);
1974 assert(!tex
->dcc_separate_buffer
);
1976 r600_texture_discard_cmask(rctx
->screen
, tex
);
1978 /* Get a DCC buffer. */
1979 if (tex
->last_dcc_separate_buffer
) {
1980 assert(tex
->dcc_gather_statistics
);
1981 assert(!tex
->dcc_separate_buffer
);
1982 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
1983 tex
->last_dcc_separate_buffer
= NULL
;
1985 tex
->dcc_separate_buffer
= (struct r600_resource
*)
1986 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
1988 tex
->surface
.dcc_size
,
1989 tex
->surface
.dcc_alignment
);
1990 if (!tex
->dcc_separate_buffer
)
1994 /* dcc_offset is the absolute GPUVM address. */
1995 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
1997 /* no need to flag anything since this is called by fast clear that
1998 * flags framebuffer state
2003 * Called by pipe_context::flush_resource, the place where DCC decompression
2006 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2007 struct r600_texture
*tex
)
2009 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2010 struct pipe_query
*tmp
;
2011 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2012 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2013 bool disable
= false;
2015 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2016 union pipe_query_result result
;
2018 /* Read the results. */
2019 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2021 r600_query_hw_reset_buffers(rctx
,
2022 (struct r600_query_hw
*)
2023 rctx
->dcc_stats
[i
].ps_stats
[2]);
2025 /* Compute the approximate number of fullscreen draws. */
2026 tex
->ps_draw_ratio
=
2027 result
.pipeline_statistics
.ps_invocations
/
2028 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2029 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2031 disable
= tex
->dcc_separate_buffer
&&
2032 !vi_should_enable_separate_dcc(tex
);
2035 tex
->num_slow_clears
= 0;
2037 /* stop the statistics query for ps_stats[0] */
2039 vi_separate_dcc_stop_query(ctx
, tex
);
2041 /* Move the queries in the queue by one. */
2042 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2043 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2044 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2045 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2047 /* create and start a new query as ps_stats[0] */
2049 vi_separate_dcc_start_query(ctx
, tex
);
2052 assert(!tex
->last_dcc_separate_buffer
);
2053 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2054 tex
->dcc_separate_buffer
= NULL
;
2055 tex
->dcc_offset
= 0;
2056 /* no need to flag anything since this is called after
2057 * decompression that re-sets framebuffer state
2062 /* FAST COLOR CLEAR */
2064 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2065 enum pipe_format surface_format
,
2066 const union pipe_color_union
*color
)
2068 union util_color uc
;
2070 memset(&uc
, 0, sizeof(uc
));
2072 if (util_format_is_pure_uint(surface_format
)) {
2073 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2074 } else if (util_format_is_pure_sint(surface_format
)) {
2075 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2077 util_pack_color(color
->f
, surface_format
, &uc
);
2080 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2083 static void vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2084 const union pipe_color_union
*color
,
2085 uint32_t* reset_value
,
2086 bool* clear_words_needed
)
2088 bool values
[4] = {};
2090 bool main_value
= false;
2091 bool extra_value
= false;
2093 const struct util_format_description
*desc
= util_format_description(surface_format
);
2095 *clear_words_needed
= true;
2096 *reset_value
= 0x20202020U
;
2098 /* If we want to clear without needing a fast clear eliminate step, we
2099 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2100 * have two sets of flags, one for the last or first channel(extra) and
2101 * one for the other channels(main).
2104 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2105 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2106 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2108 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2109 if(r600_translate_colorswap(surface_format
, false) <= 1)
2110 extra_channel
= desc
->nr_channels
- 1;
2116 for (i
= 0; i
< 4; ++i
) {
2117 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2119 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2120 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2123 if (util_format_is_pure_sint(surface_format
)) {
2124 values
[i
] = color
->i
[i
] != 0;
2125 if (color
->i
[i
] != 0 && color
->i
[i
] != INT32_MAX
)
2127 } else if (util_format_is_pure_uint(surface_format
)) {
2128 values
[i
] = color
->ui
[i
] != 0U;
2129 if (color
->ui
[i
] != 0U && color
->ui
[i
] != UINT32_MAX
)
2132 values
[i
] = color
->f
[i
] != 0.0F
;
2133 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2137 if (index
== extra_channel
)
2138 extra_value
= values
[i
];
2140 main_value
= values
[i
];
2143 for (int i
= 0; i
< 4; ++i
)
2144 if (values
[i
] != main_value
&&
2145 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2146 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2147 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2150 *clear_words_needed
= false;
2152 *reset_value
|= 0x80808080U
;
2155 *reset_value
|= 0x40404040U
;
2158 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2159 struct r600_texture
*rtex
,
2160 unsigned level
, unsigned clear_value
)
2162 struct pipe_resource
*dcc_buffer
;
2163 uint64_t dcc_offset
;
2165 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2167 if (rtex
->dcc_separate_buffer
) {
2168 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2171 dcc_buffer
= &rtex
->resource
.b
.b
;
2172 dcc_offset
= rtex
->dcc_offset
;
2175 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2177 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2178 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2179 clear_value
, R600_COHERENCY_CB_META
);
2182 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2183 * This allows hitting the MSAA resolve fast path, which requires that both
2184 * src and dst micro tile modes match.
2186 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2187 struct r600_texture
*rtex
)
2189 if (rtex
->resource
.is_shared
||
2190 rtex
->surface
.nsamples
<= 1 ||
2191 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2194 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2195 assert(rtex
->surface
.last_level
== 0);
2197 /* These magic numbers were copied from addrlib. It doesn't use any
2198 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2199 * different bpp and micro tile mode.
2201 if (rscreen
->chip_class
>= CIK
) {
2202 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2203 case 0: /* displayable */
2204 rtex
->surface
.tiling_index
[0] = 10;
2207 rtex
->surface
.tiling_index
[0] = 14;
2209 case 3: /* rotated */
2210 rtex
->surface
.tiling_index
[0] = 28;
2212 default: /* depth, thick */
2213 assert(!"unexpected micro mode");
2217 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2218 case 0: /* displayable */
2219 switch (rtex
->surface
.bpe
) {
2221 rtex
->surface
.tiling_index
[0] = 10;
2224 rtex
->surface
.tiling_index
[0] = 11;
2226 default: /* 32, 64 */
2227 rtex
->surface
.tiling_index
[0] = 12;
2232 switch (rtex
->surface
.bpe
) {
2234 rtex
->surface
.tiling_index
[0] = 14;
2237 rtex
->surface
.tiling_index
[0] = 15;
2240 rtex
->surface
.tiling_index
[0] = 16;
2242 default: /* 64, 128 */
2243 rtex
->surface
.tiling_index
[0] = 17;
2247 default: /* depth, thick */
2248 assert(!"unexpected micro mode");
2253 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2255 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2256 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2259 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2260 struct pipe_framebuffer_state
*fb
,
2261 struct r600_atom
*fb_state
,
2262 unsigned *buffers
, unsigned *dirty_cbufs
,
2263 const union pipe_color_union
*color
)
2267 /* This function is broken in BE, so just disable this path for now */
2268 #ifdef PIPE_ARCH_BIG_ENDIAN
2272 if (rctx
->render_cond
)
2275 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2276 struct r600_texture
*tex
;
2277 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2282 /* if this colorbuffer is not being cleared */
2283 if (!(*buffers
& clear_bit
))
2286 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2288 /* 128-bit formats are unusupported */
2289 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2293 /* the clear is allowed if all layers are bound */
2294 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2295 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2299 /* cannot clear mipmapped textures */
2300 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2304 /* only supported on tiled surfaces */
2305 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2309 /* shared textures can't use fast clear without an explicit flush,
2310 * because there is no way to communicate the clear color among
2313 if (tex
->resource
.is_shared
&&
2314 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2317 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2318 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2319 rctx
->chip_class
>= CIK
&&
2320 rctx
->screen
->info
.drm_major
== 2 &&
2321 rctx
->screen
->info
.drm_minor
< 38) {
2325 /* Fast clear is the most appropriate place to enable DCC for
2326 * displayable surfaces.
2328 if (rctx
->chip_class
>= VI
&&
2329 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2330 vi_separate_dcc_try_enable(rctx
, tex
);
2332 /* Stoney can't do a CMASK-based clear, so all clears are
2333 * considered to be hypothetically slow clears, which
2334 * is weighed when determining to enable separate DCC.
2336 if (tex
->dcc_gather_statistics
&&
2337 rctx
->family
== CHIP_STONEY
)
2338 tex
->num_slow_clears
++;
2341 /* Try to clear DCC first, otherwise try CMASK. */
2342 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2343 uint32_t reset_value
;
2344 bool clear_words_needed
;
2346 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2349 /* We can change the micro tile mode before a full clear. */
2350 if (rctx
->screen
->chip_class
>= SI
)
2351 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2353 vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
, color
, &reset_value
, &clear_words_needed
);
2354 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2356 if (clear_words_needed
)
2357 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2358 tex
->separate_dcc_dirty
= true;
2360 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2361 if (rctx
->family
== CHIP_STONEY
)
2364 /* ensure CMASK is enabled */
2365 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2366 if (tex
->cmask
.size
== 0) {
2370 /* We can change the micro tile mode before a full clear. */
2371 if (rctx
->screen
->chip_class
>= SI
)
2372 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2374 /* Do the fast clear. */
2375 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2376 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2377 R600_COHERENCY_CB_META
);
2379 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2382 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2385 *dirty_cbufs
|= 1 << i
;
2386 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2387 *buffers
&= ~clear_bit
;
2391 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2393 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2394 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2397 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2399 rctx
->b
.create_surface
= r600_create_surface
;
2400 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2401 rctx
->b
.clear_texture
= r600_clear_texture
;