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radeonsi: implement MSAA for CIK
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include <errno.h>
32
33 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
34 static void r600_copy_region_with_blit(struct pipe_context *pipe,
35 struct pipe_resource *dst,
36 unsigned dst_level,
37 unsigned dstx, unsigned dsty, unsigned dstz,
38 struct pipe_resource *src,
39 unsigned src_level,
40 const struct pipe_box *src_box)
41 {
42 struct pipe_blit_info blit;
43
44 memset(&blit, 0, sizeof(blit));
45 blit.src.resource = src;
46 blit.src.format = src->format;
47 blit.src.level = src_level;
48 blit.src.box = *src_box;
49 blit.dst.resource = dst;
50 blit.dst.format = dst->format;
51 blit.dst.level = dst_level;
52 blit.dst.box.x = dstx;
53 blit.dst.box.y = dsty;
54 blit.dst.box.z = dstz;
55 blit.dst.box.width = src_box->width;
56 blit.dst.box.height = src_box->height;
57 blit.dst.box.depth = src_box->depth;
58 blit.mask = util_format_get_mask(src->format) &
59 util_format_get_mask(dst->format);
60 blit.filter = PIPE_TEX_FILTER_NEAREST;
61
62 if (blit.mask) {
63 pipe->blit(pipe, &blit);
64 }
65 }
66
67 /* Copy from a full GPU texture to a transfer's staging one. */
68 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
69 {
70 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
71 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
72 struct pipe_resource *dst = &rtransfer->staging->b.b;
73 struct pipe_resource *src = transfer->resource;
74
75 if (src->nr_samples > 1) {
76 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
77 src, transfer->level, &transfer->box);
78 return;
79 }
80
81 if (!rctx->dma_copy(ctx, dst, 0, 0, 0, 0,
82 src, transfer->level,
83 &transfer->box)) {
84 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
85 src, transfer->level, &transfer->box);
86 }
87 }
88
89 /* Copy from a transfer's staging texture to a full GPU one. */
90 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
91 {
92 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
93 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
94 struct pipe_resource *dst = transfer->resource;
95 struct pipe_resource *src = &rtransfer->staging->b.b;
96 struct pipe_box sbox;
97
98 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
99
100 if (dst->nr_samples > 1) {
101 r600_copy_region_with_blit(ctx, dst, transfer->level,
102 transfer->box.x, transfer->box.y, transfer->box.z,
103 src, 0, &sbox);
104 return;
105 }
106
107 if (!rctx->dma_copy(ctx, dst, transfer->level,
108 transfer->box.x, transfer->box.y, transfer->box.z,
109 src, 0, &sbox)) {
110 ctx->resource_copy_region(ctx, dst, transfer->level,
111 transfer->box.x, transfer->box.y, transfer->box.z,
112 src, 0, &sbox);
113 }
114 }
115
116 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
117 const struct pipe_box *box)
118 {
119 enum pipe_format format = rtex->resource.b.b.format;
120
121 return rtex->surface.level[level].offset +
122 box->z * rtex->surface.level[level].slice_size +
123 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
124 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
125 }
126
127 static int r600_init_surface(struct r600_common_screen *rscreen,
128 struct radeon_surface *surface,
129 const struct pipe_resource *ptex,
130 unsigned array_mode,
131 bool is_flushed_depth)
132 {
133 const struct util_format_description *desc =
134 util_format_description(ptex->format);
135 bool is_depth, is_stencil;
136
137 is_depth = util_format_has_depth(desc);
138 is_stencil = util_format_has_stencil(desc);
139
140 surface->npix_x = ptex->width0;
141 surface->npix_y = ptex->height0;
142 surface->npix_z = ptex->depth0;
143 surface->blk_w = util_format_get_blockwidth(ptex->format);
144 surface->blk_h = util_format_get_blockheight(ptex->format);
145 surface->blk_d = 1;
146 surface->array_size = 1;
147 surface->last_level = ptex->last_level;
148
149 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
150 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
151 surface->bpe = 4; /* stencil is allocated separately on evergreen */
152 } else {
153 surface->bpe = util_format_get_blocksize(ptex->format);
154 /* align byte per element on dword */
155 if (surface->bpe == 3) {
156 surface->bpe = 4;
157 }
158 }
159
160 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
161 surface->flags = RADEON_SURF_SET(array_mode, MODE);
162
163 switch (ptex->target) {
164 case PIPE_TEXTURE_1D:
165 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
166 break;
167 case PIPE_TEXTURE_RECT:
168 case PIPE_TEXTURE_2D:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
170 break;
171 case PIPE_TEXTURE_3D:
172 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
173 break;
174 case PIPE_TEXTURE_1D_ARRAY:
175 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
176 surface->array_size = ptex->array_size;
177 break;
178 case PIPE_TEXTURE_2D_ARRAY:
179 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
180 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
181 surface->array_size = ptex->array_size;
182 break;
183 case PIPE_TEXTURE_CUBE:
184 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
185 break;
186 case PIPE_BUFFER:
187 default:
188 return -EINVAL;
189 }
190 if (ptex->bind & PIPE_BIND_SCANOUT) {
191 surface->flags |= RADEON_SURF_SCANOUT;
192 }
193
194 if (!is_flushed_depth && is_depth) {
195 surface->flags |= RADEON_SURF_ZBUFFER;
196
197 if (is_stencil) {
198 surface->flags |= RADEON_SURF_SBUFFER |
199 RADEON_SURF_HAS_SBUFFER_MIPTREE;
200 }
201 }
202 if (rscreen->chip_class >= SI) {
203 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
204 }
205 return 0;
206 }
207
208 static int r600_setup_surface(struct pipe_screen *screen,
209 struct r600_texture *rtex,
210 unsigned pitch_in_bytes_override)
211 {
212 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
213 int r;
214
215 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
216 if (r) {
217 return r;
218 }
219
220 rtex->size = rtex->surface.bo_size;
221
222 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
223 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
224 * for those
225 */
226 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
227 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
228 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
229 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
230 rtex->surface.stencil_offset =
231 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
232 }
233 }
234 return 0;
235 }
236
237 static boolean r600_texture_get_handle(struct pipe_screen* screen,
238 struct pipe_resource *ptex,
239 struct winsys_handle *whandle)
240 {
241 struct r600_texture *rtex = (struct r600_texture*)ptex;
242 struct r600_resource *resource = &rtex->resource;
243 struct radeon_surface *surface = &rtex->surface;
244 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
245
246 rscreen->ws->buffer_set_tiling(resource->buf,
247 NULL,
248 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
249 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
250 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
251 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
252 surface->bankw, surface->bankh,
253 surface->tile_split,
254 surface->stencil_tile_split,
255 surface->mtilea,
256 surface->level[0].pitch_bytes);
257
258 return rscreen->ws->buffer_get_handle(resource->buf,
259 surface->level[0].pitch_bytes, whandle);
260 }
261
262 static void r600_texture_destroy(struct pipe_screen *screen,
263 struct pipe_resource *ptex)
264 {
265 struct r600_texture *rtex = (struct r600_texture*)ptex;
266 struct r600_resource *resource = &rtex->resource;
267
268 if (rtex->flushed_depth_texture)
269 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
270
271 pipe_resource_reference((struct pipe_resource**)&rtex->htile, NULL);
272 if (rtex->cmask_buffer != &rtex->resource) {
273 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
274 }
275 pb_reference(&resource->buf, NULL);
276 FREE(rtex);
277 }
278
279 static const struct u_resource_vtbl r600_texture_vtbl;
280
281 /* The number of samples can be specified independently of the texture. */
282 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
283 struct r600_texture *rtex,
284 unsigned nr_samples,
285 struct r600_fmask_info *out)
286 {
287 /* FMASK is allocated like an ordinary texture. */
288 struct radeon_surface fmask = rtex->surface;
289
290 memset(out, 0, sizeof(*out));
291
292 fmask.bo_alignment = 0;
293 fmask.bo_size = 0;
294 fmask.nsamples = 1;
295 fmask.flags |= RADEON_SURF_FMASK;
296
297 if (rscreen->chip_class >= SI) {
298 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
299 }
300
301 switch (nr_samples) {
302 case 2:
303 case 4:
304 fmask.bpe = 1;
305 if (rscreen->chip_class <= CAYMAN) {
306 fmask.bankh = 4;
307 }
308 break;
309 case 8:
310 fmask.bpe = 4;
311 break;
312 default:
313 R600_ERR("Invalid sample count for FMASK allocation.\n");
314 return;
315 }
316
317 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
318 * This can be fixed by writing a separate FMASK allocator specifically
319 * for R600-R700 asics. */
320 if (rscreen->chip_class <= R700) {
321 fmask.bpe *= 2;
322 }
323
324 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
325 R600_ERR("Got error in surface_init while allocating FMASK.\n");
326 return;
327 }
328
329 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
330
331 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
332 if (out->slice_tile_max)
333 out->slice_tile_max -= 1;
334
335 out->tile_mode_index = fmask.tiling_index[0];
336 out->pitch = fmask.level[0].nblk_x;
337 out->bank_height = fmask.bankh;
338 out->alignment = MAX2(256, fmask.bo_alignment);
339 out->size = fmask.bo_size;
340 }
341
342 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
343 struct r600_texture *rtex)
344 {
345 r600_texture_get_fmask_info(rscreen, rtex,
346 rtex->resource.b.b.nr_samples, &rtex->fmask);
347
348 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
349 rtex->size = rtex->fmask.offset + rtex->fmask.size;
350 }
351
352 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
353 struct r600_texture *rtex,
354 struct r600_cmask_info *out)
355 {
356 unsigned cmask_tile_width = 8;
357 unsigned cmask_tile_height = 8;
358 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
359 unsigned element_bits = 4;
360 unsigned cmask_cache_bits = 1024;
361 unsigned num_pipes = rscreen->tiling_info.num_channels;
362 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
363
364 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
365 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
366 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
367 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
368 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
369
370 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
371 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
372
373 unsigned base_align = num_pipes * pipe_interleave_bytes;
374 unsigned slice_bytes =
375 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
376
377 assert(macro_tile_width % 128 == 0);
378 assert(macro_tile_height % 128 == 0);
379
380 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
381 out->alignment = MAX2(256, base_align);
382 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
383 }
384
385 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
386 struct r600_texture *rtex,
387 struct r600_cmask_info *out)
388 {
389 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
390 unsigned num_pipes = rscreen->tiling_info.num_channels;
391 unsigned cl_width, cl_height;
392
393 switch (num_pipes) {
394 case 2:
395 cl_width = 32;
396 cl_height = 16;
397 break;
398 case 4:
399 cl_width = 32;
400 cl_height = 32;
401 break;
402 case 8:
403 cl_width = 64;
404 cl_height = 32;
405 break;
406 case 16: /* Hawaii */
407 cl_width = 64;
408 cl_height = 64;
409 break;
410 default:
411 assert(0);
412 return;
413 }
414
415 unsigned base_align = num_pipes * pipe_interleave_bytes;
416
417 unsigned width = align(rtex->surface.npix_x, cl_width*8);
418 unsigned height = align(rtex->surface.npix_y, cl_height*8);
419 unsigned slice_elements = (width * height) / (8*8);
420
421 /* Each element of CMASK is a nibble. */
422 unsigned slice_bytes = slice_elements / 2;
423
424 out->slice_tile_max = (width * height) / (128*128);
425 if (out->slice_tile_max)
426 out->slice_tile_max -= 1;
427
428 out->alignment = MAX2(256, base_align);
429 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
430 }
431
432 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
433 struct r600_texture *rtex)
434 {
435 if (rscreen->chip_class >= SI) {
436 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
437 } else {
438 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
439 }
440
441 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
442 rtex->size = rtex->cmask.offset + rtex->cmask.size;
443 }
444
445 void r600_texture_init_cmask(struct r600_common_screen *rscreen,
446 struct r600_texture *rtex)
447 {
448 assert(rtex->cmask.size == 0);
449
450 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
451
452 rtex->cmask_buffer = (struct r600_resource *)
453 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
454 PIPE_USAGE_STATIC, rtex->cmask.size);
455 if (rtex->cmask_buffer == NULL) {
456 rtex->cmask.size = 0;
457 }
458 }
459
460 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
461 struct r600_texture *rtex)
462 {
463 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
464 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
465 unsigned htile_size;
466 unsigned npipes = rscreen->info.r600_num_tile_pipes;
467
468 /* XXX also use it for other texture targets */
469 if (rscreen->info.drm_minor < 26 ||
470 rtex->resource.b.b.target != PIPE_TEXTURE_2D ||
471 rtex->surface.level[0].nblk_x < 32 ||
472 rtex->surface.level[0].nblk_y < 32) {
473 return;
474 }
475
476 /* this alignment and htile size only apply to linear htile buffer */
477 sw = align(sw, 16 << 3);
478 sh = align(sh, npipes << 3);
479 htile_size = (sw >> 3) * (sh >> 3) * 4;
480 /* must be aligned with 2K * npipes */
481 htile_size = align(htile_size, (2 << 10) * npipes);
482
483 /* XXX don't allocate it separately */
484 rtex->htile = (struct r600_resource*)pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
485 PIPE_USAGE_STATIC, htile_size);
486 if (rtex->htile == NULL) {
487 /* this is not a fatal error as we can still keep rendering
488 * without htile buffer
489 */
490 R600_ERR("r600: failed to create bo for htile buffers\n");
491 } else {
492 r600_screen_clear_buffer(rscreen, &rtex->htile->b.b, 0, htile_size, 0);
493 }
494 }
495
496 static struct r600_texture *
497 r600_texture_create_object(struct pipe_screen *screen,
498 const struct pipe_resource *base,
499 unsigned pitch_in_bytes_override,
500 struct pb_buffer *buf,
501 struct radeon_surface *surface)
502 {
503 struct r600_texture *rtex;
504 struct r600_resource *resource;
505 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
506 int r;
507
508 rtex = CALLOC_STRUCT(r600_texture);
509 if (rtex == NULL)
510 return NULL;
511
512 resource = &rtex->resource;
513 resource->b.b = *base;
514 resource->b.vtbl = &r600_texture_vtbl;
515 pipe_reference_init(&resource->b.b.reference, 1);
516 resource->b.b.screen = screen;
517 rtex->pitch_override = pitch_in_bytes_override;
518
519 /* don't include stencil-only formats which we don't support for rendering */
520 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
521
522 rtex->surface = *surface;
523 r = r600_setup_surface(screen, rtex, pitch_in_bytes_override);
524 if (r) {
525 FREE(rtex);
526 return NULL;
527 }
528
529 /* Tiled depth textures utilize the non-displayable tile order.
530 * This must be done after r600_setup_surface.
531 * Applies to R600-Cayman. */
532 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
533
534 if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
535 r600_texture_allocate_fmask(rscreen, rtex);
536 r600_texture_allocate_cmask(rscreen, rtex);
537 rtex->cmask_buffer = &rtex->resource;
538 }
539
540 if (!rtex->is_depth && base->nr_samples > 1 &&
541 (!rtex->fmask.size || !rtex->cmask.size)) {
542 FREE(rtex);
543 return NULL;
544 }
545
546 if (rtex->is_depth &&
547 !(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
548 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
549 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
550 if (rscreen->chip_class >= SI) {
551 /* XXX implement Hyper-Z for SI.
552 * Reuse the CMASK allocator, which is almost the same as HTILE. */
553 } else {
554 r600_texture_allocate_htile(rscreen, rtex);
555 }
556 }
557
558 /* Now create the backing buffer. */
559 if (!buf) {
560 unsigned base_align = rtex->surface.bo_alignment;
561 unsigned usage = rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D ?
562 PIPE_USAGE_STATIC : base->usage;
563
564 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
565 FREE(rtex);
566 return NULL;
567 }
568 } else {
569 resource->buf = buf;
570 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
571 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
572 }
573
574 if (rtex->cmask.size) {
575 /* Initialize the cmask to 0xCC (= compressed state). */
576 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
577 rtex->cmask.offset, rtex->cmask.size, 0xCCCCCCCC);
578 }
579
580 if (rscreen->debug_flags & DBG_VM) {
581 fprintf(stderr, "VM start=0x%llX end=0x%llX | Texture %ix%ix%i, %i levels, %i samples, %s\n",
582 r600_resource_va(screen, &rtex->resource.b.b),
583 r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
584 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
585 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
586 }
587
588 if (rscreen->debug_flags & DBG_TEX ||
589 (rtex->resource.b.b.last_level > 0 && rscreen->debug_flags & DBG_TEXMIP)) {
590 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
591 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
592 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
593 rtex->surface.npix_x, rtex->surface.npix_y,
594 rtex->surface.npix_z, rtex->surface.blk_w,
595 rtex->surface.blk_h, rtex->surface.blk_d,
596 rtex->surface.array_size, rtex->surface.last_level,
597 rtex->surface.bpe, rtex->surface.nsamples,
598 rtex->surface.flags, util_format_short_name(base->format));
599 for (int i = 0; i <= rtex->surface.last_level; i++) {
600 printf(" L %i: offset=%llu, slice_size=%llu, npix_x=%u, "
601 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
602 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
603 i, rtex->surface.level[i].offset,
604 rtex->surface.level[i].slice_size,
605 u_minify(rtex->resource.b.b.width0, i),
606 u_minify(rtex->resource.b.b.height0, i),
607 u_minify(rtex->resource.b.b.depth0, i),
608 rtex->surface.level[i].nblk_x,
609 rtex->surface.level[i].nblk_y,
610 rtex->surface.level[i].nblk_z,
611 rtex->surface.level[i].pitch_bytes,
612 rtex->surface.level[i].mode);
613 }
614 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
615 for (int i = 0; i <= rtex->surface.last_level; i++) {
616 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
617 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
618 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
619 i, rtex->surface.stencil_level[i].offset,
620 rtex->surface.stencil_level[i].slice_size,
621 u_minify(rtex->resource.b.b.width0, i),
622 u_minify(rtex->resource.b.b.height0, i),
623 u_minify(rtex->resource.b.b.depth0, i),
624 rtex->surface.stencil_level[i].nblk_x,
625 rtex->surface.stencil_level[i].nblk_y,
626 rtex->surface.stencil_level[i].nblk_z,
627 rtex->surface.stencil_level[i].pitch_bytes,
628 rtex->surface.stencil_level[i].mode);
629 }
630 }
631 }
632 return rtex;
633 }
634
635 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
636 const struct pipe_resource *templ)
637 {
638 const struct util_format_description *desc = util_format_description(templ->format);
639
640 /* MSAA resources must be 2D tiled. */
641 if (templ->nr_samples > 1)
642 return RADEON_SURF_MODE_2D;
643
644 /* Transfer resources should be linear. */
645 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
646 return RADEON_SURF_MODE_LINEAR_ALIGNED;
647
648 /* Handle common candidates for the linear mode.
649 * Compressed textures must always be tiled. */
650 if (!(templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) &&
651 !util_format_is_compressed(templ->format)) {
652 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600-Cayman. */
653 if (rscreen->chip_class <= CAYMAN &&
654 desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
655 return RADEON_SURF_MODE_LINEAR_ALIGNED;
656
657 /* Cursors are linear on SI.
658 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
659 if (rscreen->chip_class >= SI &&
660 (templ->bind & PIPE_BIND_CURSOR))
661 return RADEON_SURF_MODE_LINEAR_ALIGNED;
662
663 if (templ->bind & PIPE_BIND_LINEAR)
664 return RADEON_SURF_MODE_LINEAR_ALIGNED;
665
666 /* Textures with a very small height are recommended to be linear. */
667 if (templ->target == PIPE_TEXTURE_1D ||
668 templ->target == PIPE_TEXTURE_1D_ARRAY ||
669 templ->height0 <= 4)
670 return RADEON_SURF_MODE_LINEAR_ALIGNED;
671
672 /* Textures likely to be mapped often. */
673 if (templ->usage == PIPE_USAGE_STAGING ||
674 templ->usage == PIPE_USAGE_STREAM)
675 return RADEON_SURF_MODE_LINEAR_ALIGNED;
676 }
677
678 /* Make small textures 1D tiled. */
679 if (templ->width0 <= 16 || templ->height0 <= 16)
680 return RADEON_SURF_MODE_1D;
681
682 /* The allocator will switch to 1D if needed. */
683 return RADEON_SURF_MODE_2D;
684 }
685
686 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
687 const struct pipe_resource *templ)
688 {
689 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
690 struct radeon_surface surface = {0};
691 int r;
692
693 r = r600_init_surface(rscreen, &surface, templ,
694 r600_choose_tiling(rscreen, templ),
695 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
696 if (r) {
697 return NULL;
698 }
699 r = rscreen->ws->surface_best(rscreen->ws, &surface);
700 if (r) {
701 return NULL;
702 }
703 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
704 0, NULL, &surface);
705 }
706
707 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
708 const struct pipe_resource *templ,
709 struct winsys_handle *whandle)
710 {
711 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
712 struct pb_buffer *buf = NULL;
713 unsigned stride = 0;
714 unsigned array_mode;
715 enum radeon_bo_layout micro, macro;
716 struct radeon_surface surface;
717 int r;
718
719 /* Support only 2D textures without mipmaps */
720 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
721 templ->depth0 != 1 || templ->last_level != 0)
722 return NULL;
723
724 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
725 if (!buf)
726 return NULL;
727
728 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
729 &surface.bankw, &surface.bankh,
730 &surface.tile_split,
731 &surface.stencil_tile_split,
732 &surface.mtilea);
733
734 if (macro == RADEON_LAYOUT_TILED)
735 array_mode = RADEON_SURF_MODE_2D;
736 else if (micro == RADEON_LAYOUT_TILED)
737 array_mode = RADEON_SURF_MODE_1D;
738 else
739 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
740
741 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
742 if (r) {
743 return NULL;
744 }
745
746 /* always set the scanout flags on SI */
747 if (rscreen->chip_class >= SI)
748 surface.flags |= RADEON_SURF_SCANOUT;
749
750 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
751 stride, buf, &surface);
752 }
753
754 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
755 struct pipe_resource *texture,
756 struct r600_texture **staging)
757 {
758 struct r600_texture *rtex = (struct r600_texture*)texture;
759 struct pipe_resource resource;
760 struct r600_texture **flushed_depth_texture = staging ?
761 staging : &rtex->flushed_depth_texture;
762
763 if (!staging && rtex->flushed_depth_texture)
764 return true; /* it's ready */
765
766 resource.target = texture->target;
767 resource.format = texture->format;
768 resource.width0 = texture->width0;
769 resource.height0 = texture->height0;
770 resource.depth0 = texture->depth0;
771 resource.array_size = texture->array_size;
772 resource.last_level = texture->last_level;
773 resource.nr_samples = texture->nr_samples;
774 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
775 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
776 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
777
778 if (staging)
779 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
780
781 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
782 if (*flushed_depth_texture == NULL) {
783 R600_ERR("failed to create temporary texture to hold flushed depth\n");
784 return false;
785 }
786
787 (*flushed_depth_texture)->is_flushing_texture = TRUE;
788 (*flushed_depth_texture)->non_disp_tiling = false;
789 return true;
790 }
791
792 /**
793 * Initialize the pipe_resource descriptor to be of the same size as the box,
794 * which is supposed to hold a subregion of the texture "orig" at the given
795 * mipmap level.
796 */
797 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
798 struct pipe_resource *orig,
799 const struct pipe_box *box,
800 unsigned level, unsigned flags)
801 {
802 memset(res, 0, sizeof(*res));
803 res->format = orig->format;
804 res->width0 = box->width;
805 res->height0 = box->height;
806 res->depth0 = 1;
807 res->array_size = 1;
808 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
809 res->flags = flags;
810
811 /* We must set the correct texture target and dimensions for a 3D box. */
812 if (box->depth > 1 && util_max_layer(orig, level) > 0)
813 res->target = orig->target;
814 else
815 res->target = PIPE_TEXTURE_2D;
816
817 switch (res->target) {
818 case PIPE_TEXTURE_1D_ARRAY:
819 case PIPE_TEXTURE_2D_ARRAY:
820 case PIPE_TEXTURE_CUBE_ARRAY:
821 res->array_size = box->depth;
822 break;
823 case PIPE_TEXTURE_3D:
824 res->depth0 = box->depth;
825 break;
826 default:;
827 }
828 }
829
830 static void *r600_texture_transfer_map(struct pipe_context *ctx,
831 struct pipe_resource *texture,
832 unsigned level,
833 unsigned usage,
834 const struct pipe_box *box,
835 struct pipe_transfer **ptransfer)
836 {
837 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
838 struct r600_texture *rtex = (struct r600_texture*)texture;
839 struct r600_transfer *trans;
840 boolean use_staging_texture = FALSE;
841 struct r600_resource *buf;
842 unsigned offset = 0;
843 char *map;
844
845 /* We cannot map a tiled texture directly because the data is
846 * in a different order, therefore we do detiling using a blit.
847 *
848 * Also, use a temporary in GTT memory for read transfers, as
849 * the CPU is much happier reading out of cached system memory
850 * than uncached VRAM.
851 */
852 if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D)
853 use_staging_texture = TRUE;
854
855 /* Untiled buffers in VRAM, which is slow for CPU reads */
856 if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
857 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
858 use_staging_texture = TRUE;
859 }
860
861 /* Use a staging texture for uploads if the underlying BO is busy. */
862 if (!(usage & PIPE_TRANSFER_READ) &&
863 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
864 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
865 use_staging_texture = TRUE;
866 }
867
868 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
869 use_staging_texture = FALSE;
870 }
871
872 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
873 return NULL;
874 }
875
876 trans = CALLOC_STRUCT(r600_transfer);
877 if (trans == NULL)
878 return NULL;
879 trans->transfer.resource = texture;
880 trans->transfer.level = level;
881 trans->transfer.usage = usage;
882 trans->transfer.box = *box;
883
884 if (rtex->is_depth) {
885 struct r600_texture *staging_depth;
886
887 if (rtex->resource.b.b.nr_samples > 1) {
888 /* MSAA depth buffers need to be converted to single sample buffers.
889 *
890 * Mapping MSAA depth buffers can occur if ReadPixels is called
891 * with a multisample GLX visual.
892 *
893 * First downsample the depth buffer to a temporary texture,
894 * then decompress the temporary one to staging.
895 *
896 * Only the region being mapped is transfered.
897 */
898 struct pipe_resource resource;
899
900 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
901
902 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
903 R600_ERR("failed to create temporary texture to hold untiled copy\n");
904 FREE(trans);
905 return NULL;
906 }
907
908 if (usage & PIPE_TRANSFER_READ) {
909 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
910
911 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
912 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
913 0, 0, 0, box->depth, 0, 0);
914 pipe_resource_reference((struct pipe_resource**)&temp, NULL);
915 }
916 }
917 else {
918 /* XXX: only readback the rectangle which is being mapped? */
919 /* XXX: when discard is true, no need to read back from depth texture */
920 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
921 R600_ERR("failed to create temporary texture to hold untiled copy\n");
922 FREE(trans);
923 return NULL;
924 }
925
926 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
927 level, level,
928 box->z, box->z + box->depth - 1,
929 0, 0);
930
931 offset = r600_texture_get_offset(staging_depth, level, box);
932 }
933
934 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
935 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
936 trans->staging = (struct r600_resource*)staging_depth;
937 } else if (use_staging_texture) {
938 struct pipe_resource resource;
939 struct r600_texture *staging;
940
941 r600_init_temp_resource_from_box(&resource, texture, box, level,
942 R600_RESOURCE_FLAG_TRANSFER);
943
944 /* Create the temporary texture. */
945 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
946 if (staging == NULL) {
947 R600_ERR("failed to create temporary texture to hold untiled copy\n");
948 FREE(trans);
949 return NULL;
950 }
951 trans->staging = &staging->resource;
952 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
953 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
954 if (usage & PIPE_TRANSFER_READ) {
955 r600_copy_to_staging_texture(ctx, trans);
956 }
957 } else {
958 /* the resource is mapped directly */
959 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
960 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
961 offset = r600_texture_get_offset(rtex, level, box);
962 }
963
964 if (trans->staging) {
965 buf = trans->staging;
966 } else {
967 buf = &rtex->resource;
968 }
969
970 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
971 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
972 FREE(trans);
973 return NULL;
974 }
975
976 *ptransfer = &trans->transfer;
977 return map + offset;
978 }
979
980 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
981 struct pipe_transfer* transfer)
982 {
983 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
984 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
985 struct radeon_winsys_cs_handle *buf;
986 struct pipe_resource *texture = transfer->resource;
987 struct r600_texture *rtex = (struct r600_texture*)texture;
988
989 if (rtransfer->staging) {
990 buf = rtransfer->staging->cs_buf;
991 } else {
992 buf = r600_resource(transfer->resource)->cs_buf;
993 }
994 rctx->ws->buffer_unmap(buf);
995
996 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
997 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
998 ctx->resource_copy_region(ctx, texture, transfer->level,
999 transfer->box.x, transfer->box.y, transfer->box.z,
1000 &rtransfer->staging->b.b, transfer->level,
1001 &transfer->box);
1002 } else {
1003 r600_copy_from_staging_texture(ctx, rtransfer);
1004 }
1005 }
1006
1007 if (rtransfer->staging)
1008 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1009
1010 FREE(transfer);
1011 }
1012
1013 static const struct u_resource_vtbl r600_texture_vtbl =
1014 {
1015 r600_texture_get_handle, /* get_handle */
1016 r600_texture_destroy, /* resource_destroy */
1017 r600_texture_transfer_map, /* transfer_map */
1018 NULL, /* transfer_flush_region */
1019 r600_texture_transfer_unmap, /* transfer_unmap */
1020 NULL /* transfer_inline_write */
1021 };