2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe_common.h"
25 #include "r600_query.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_memory.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31 #include "util/os_time.h"
34 #include "state_tracker/drm_driver.h"
35 #include "amd/common/sid.h"
37 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
38 struct r600_texture
*rtex
);
39 static enum radeon_surf_mode
40 r600_choose_tiling(struct r600_common_screen
*rscreen
,
41 const struct pipe_resource
*templ
);
44 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
58 /* MSAA: Blits don't exist in the real world. */
59 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
60 rdst
->resource
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (rsrc
->is_depth
|| rdst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(rsrc
, src_level
) ||
75 vi_dcc_enabled(rdst
, dst_level
))
79 * src: Both texture and SDMA paths need decompression. Use SDMA.
80 * dst: If overwriting the whole texture, discard CMASK and use
81 * SDMA. Otherwise, use the 3D path.
83 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
84 /* The CMASK clear is only enabled for the first level. */
85 assert(dst_level
== 0);
86 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
87 dstx
, dsty
, dstz
, src_box
->width
,
88 src_box
->height
, src_box
->depth
))
91 r600_texture_discard_cmask(rctx
->screen
, rdst
);
94 /* All requirements are met. Prepare textures for SDMA. */
95 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
96 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
98 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
99 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
104 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
105 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
106 struct pipe_resource
*dst
,
108 unsigned dstx
, unsigned dsty
, unsigned dstz
,
109 struct pipe_resource
*src
,
111 const struct pipe_box
*src_box
)
113 struct pipe_blit_info blit
;
115 memset(&blit
, 0, sizeof(blit
));
116 blit
.src
.resource
= src
;
117 blit
.src
.format
= src
->format
;
118 blit
.src
.level
= src_level
;
119 blit
.src
.box
= *src_box
;
120 blit
.dst
.resource
= dst
;
121 blit
.dst
.format
= dst
->format
;
122 blit
.dst
.level
= dst_level
;
123 blit
.dst
.box
.x
= dstx
;
124 blit
.dst
.box
.y
= dsty
;
125 blit
.dst
.box
.z
= dstz
;
126 blit
.dst
.box
.width
= src_box
->width
;
127 blit
.dst
.box
.height
= src_box
->height
;
128 blit
.dst
.box
.depth
= src_box
->depth
;
129 blit
.mask
= util_format_get_mask(src
->format
) &
130 util_format_get_mask(dst
->format
);
131 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
134 pipe
->blit(pipe
, &blit
);
138 /* Copy from a full GPU texture to a transfer's staging one. */
139 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
141 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
142 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
143 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
144 struct pipe_resource
*src
= transfer
->resource
;
146 if (src
->nr_samples
> 1) {
147 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
148 src
, transfer
->level
, &transfer
->box
);
152 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
156 /* Copy from a transfer's staging texture to a full GPU one. */
157 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
159 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
160 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
161 struct pipe_resource
*dst
= transfer
->resource
;
162 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
163 struct pipe_box sbox
;
165 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
167 if (dst
->nr_samples
> 1) {
168 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
169 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
174 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
175 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
179 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
180 struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
,
183 unsigned *layer_stride
)
185 if (rscreen
->chip_class
>= GFX9
) {
186 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
187 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
192 /* Each texture is an array of slices. Each slice is an array
193 * of mipmap levels. */
194 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
195 rtex
->surface
.u
.gfx9
.offset
[level
] +
196 (box
->y
/ rtex
->surface
.blk_h
*
197 rtex
->surface
.u
.gfx9
.surf_pitch
+
198 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
200 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
202 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
203 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
206 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
208 /* Each texture is an array of mipmap levels. Each level is
209 * an array of slices. */
210 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
211 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
212 (box
->y
/ rtex
->surface
.blk_h
*
213 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
214 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
218 static int r600_init_surface(struct r600_common_screen
*rscreen
,
219 struct radeon_surf
*surface
,
220 const struct pipe_resource
*ptex
,
221 enum radeon_surf_mode array_mode
,
222 unsigned pitch_in_bytes_override
,
226 bool is_flushed_depth
,
227 bool tc_compatible_htile
)
229 const struct util_format_description
*desc
=
230 util_format_description(ptex
->format
);
231 bool is_depth
, is_stencil
;
233 unsigned i
, bpe
, flags
= 0;
235 is_depth
= util_format_has_depth(desc
);
236 is_stencil
= util_format_has_stencil(desc
);
238 if (!is_flushed_depth
&&
239 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
240 bpe
= 4; /* stencil is allocated separately on evergreen */
242 bpe
= util_format_get_blocksize(ptex
->format
);
243 assert(util_is_power_of_two(bpe
));
246 if (!is_flushed_depth
&& is_depth
) {
247 flags
|= RADEON_SURF_ZBUFFER
;
249 if (tc_compatible_htile
&&
250 (rscreen
->chip_class
>= GFX9
||
251 array_mode
== RADEON_SURF_MODE_2D
)) {
252 /* TC-compatible HTILE only supports Z32_FLOAT.
253 * GFX9 also supports Z16_UNORM.
254 * On VI, promote Z16 to Z32. DB->CB copies will convert
255 * the format for transfers.
257 if (rscreen
->chip_class
== VI
)
260 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
264 flags
|= RADEON_SURF_SBUFFER
;
267 if (rscreen
->chip_class
>= VI
&&
268 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
269 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
270 /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
271 (ptex
->nr_samples
>= 2 &&
272 (!rscreen
->dcc_msaa_allowed
|| ptex
->array_size
> 1))))
273 flags
|= RADEON_SURF_DISABLE_DCC
;
275 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
276 /* This should catch bugs in gallium users setting incorrect flags. */
277 assert(ptex
->nr_samples
<= 1 &&
278 ptex
->array_size
== 1 &&
280 ptex
->last_level
== 0 &&
281 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
283 flags
|= RADEON_SURF_SCANOUT
;
286 if (ptex
->bind
& PIPE_BIND_SHARED
)
287 flags
|= RADEON_SURF_SHAREABLE
;
289 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
290 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
291 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
293 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
294 array_mode
, surface
);
299 if (rscreen
->chip_class
>= GFX9
) {
300 assert(!pitch_in_bytes_override
||
301 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
302 surface
->u
.gfx9
.surf_offset
= offset
;
305 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
306 surface
->u
.legacy
.level
[i
].offset
+= offset
;
312 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
313 struct r600_texture
*rtex
,
314 struct radeon_bo_metadata
*metadata
)
316 struct radeon_surf
*surface
= &rtex
->surface
;
318 memset(metadata
, 0, sizeof(*metadata
));
320 if (rscreen
->chip_class
>= GFX9
) {
321 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
323 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
324 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
325 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
326 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
327 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
328 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
329 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
330 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
331 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
332 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
333 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
334 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
338 static void r600_surface_import_metadata(struct r600_common_screen
*rscreen
,
339 struct radeon_surf
*surf
,
340 struct radeon_bo_metadata
*metadata
,
341 enum radeon_surf_mode
*array_mode
,
344 if (rscreen
->chip_class
>= GFX9
) {
345 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
346 *array_mode
= RADEON_SURF_MODE_2D
;
348 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
350 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
351 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
353 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
355 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
356 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
357 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
358 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
359 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
360 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
362 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
363 *array_mode
= RADEON_SURF_MODE_2D
;
364 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
365 *array_mode
= RADEON_SURF_MODE_1D
;
367 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
369 *is_scanout
= metadata
->u
.legacy
.scanout
;
373 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
374 struct r600_texture
*rtex
)
376 struct r600_common_screen
*rscreen
= rctx
->screen
;
377 struct pipe_context
*ctx
= &rctx
->b
;
379 if (ctx
== rscreen
->aux_context
)
380 mtx_lock(&rscreen
->aux_context_lock
);
382 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
383 ctx
->flush(ctx
, NULL
, 0);
385 if (ctx
== rscreen
->aux_context
)
386 mtx_unlock(&rscreen
->aux_context_lock
);
389 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
390 struct r600_texture
*rtex
)
392 if (!rtex
->cmask
.size
)
395 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
398 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
399 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
400 rtex
->dirty_level_mask
= 0;
402 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
404 if (rtex
->cmask_buffer
!= &rtex
->resource
)
405 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
407 /* Notify all contexts about the change. */
408 p_atomic_inc(&rscreen
->dirty_tex_counter
);
409 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
412 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
414 /* We can't disable DCC if it can be written by another process. */
415 return rtex
->dcc_offset
&&
416 (!rtex
->resource
.b
.is_shared
||
417 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
420 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
421 struct r600_texture
*rtex
)
423 if (!r600_can_disable_dcc(rtex
))
426 assert(rtex
->dcc_separate_buffer
== NULL
);
429 rtex
->dcc_offset
= 0;
431 /* Notify all contexts about the change. */
432 p_atomic_inc(&rscreen
->dirty_tex_counter
);
437 * Disable DCC for the texture. (first decompress, then discard metadata).
439 * There is unresolved multi-context synchronization issue between
440 * screen::aux_context and the current context. If applications do this with
441 * multiple contexts, it's already undefined behavior for them and we don't
442 * have to worry about that. The scenario is:
444 * If context 1 disables DCC and context 2 has queued commands that write
445 * to the texture via CB with DCC enabled, and the order of operations is
447 * context 2 queues draw calls rendering to the texture, but doesn't flush
448 * context 1 disables DCC and flushes
449 * context 1 & 2 reset descriptors and FB state
450 * context 2 flushes (new compressed tiles written by the draw calls)
451 * context 1 & 2 read garbage, because DCC is disabled, yet there are
454 * \param rctx the current context if you have one, or rscreen->aux_context
457 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
458 struct r600_texture
*rtex
)
460 struct r600_common_screen
*rscreen
= rctx
->screen
;
462 if (!r600_can_disable_dcc(rtex
))
465 if (&rctx
->b
== rscreen
->aux_context
)
466 mtx_lock(&rscreen
->aux_context_lock
);
468 /* Decompress DCC. */
469 rctx
->decompress_dcc(&rctx
->b
, rtex
);
470 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
472 if (&rctx
->b
== rscreen
->aux_context
)
473 mtx_unlock(&rscreen
->aux_context_lock
);
475 return r600_texture_discard_dcc(rscreen
, rtex
);
478 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
479 struct r600_texture
*rtex
,
480 unsigned new_bind_flag
,
481 bool invalidate_storage
)
483 struct pipe_screen
*screen
= rctx
->b
.screen
;
484 struct r600_texture
*new_tex
;
485 struct pipe_resource templ
= rtex
->resource
.b
.b
;
488 templ
.bind
|= new_bind_flag
;
490 if (rtex
->resource
.b
.is_shared
)
493 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
494 if (rtex
->surface
.is_linear
)
497 /* This fails with MSAA, depth, and compressed textures. */
498 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
499 RADEON_SURF_MODE_LINEAR_ALIGNED
)
503 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
507 /* Copy the pixels to the new texture. */
508 if (!invalidate_storage
) {
509 for (i
= 0; i
<= templ
.last_level
; i
++) {
513 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
514 util_max_layer(&templ
, i
) + 1, &box
);
516 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
517 &rtex
->resource
.b
.b
, i
, &box
);
521 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
522 r600_texture_discard_cmask(rctx
->screen
, rtex
);
523 r600_texture_discard_dcc(rctx
->screen
, rtex
);
526 /* Replace the structure fields of rtex. */
527 rtex
->resource
.b
.b
.bind
= templ
.bind
;
528 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
529 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
530 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
531 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
532 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
533 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
534 rtex
->resource
.domains
= new_tex
->resource
.domains
;
535 rtex
->resource
.flags
= new_tex
->resource
.flags
;
536 rtex
->size
= new_tex
->size
;
537 rtex
->db_render_format
= new_tex
->db_render_format
;
538 rtex
->db_compatible
= new_tex
->db_compatible
;
539 rtex
->can_sample_z
= new_tex
->can_sample_z
;
540 rtex
->can_sample_s
= new_tex
->can_sample_s
;
541 rtex
->surface
= new_tex
->surface
;
542 rtex
->fmask
= new_tex
->fmask
;
543 rtex
->cmask
= new_tex
->cmask
;
544 rtex
->cb_color_info
= new_tex
->cb_color_info
;
545 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
546 rtex
->htile_offset
= new_tex
->htile_offset
;
547 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
548 rtex
->depth_cleared
= new_tex
->depth_cleared
;
549 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
550 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
551 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
553 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
554 assert(!rtex
->htile_offset
);
555 assert(!rtex
->cmask
.size
);
556 assert(!rtex
->fmask
.size
);
557 assert(!rtex
->dcc_offset
);
558 assert(!rtex
->is_depth
);
561 r600_texture_reference(&new_tex
, NULL
);
563 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
566 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
567 struct pipe_context
*ctx
,
568 struct pipe_resource
*resource
,
569 struct winsys_handle
*whandle
,
572 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
573 struct r600_common_context
*rctx
;
574 struct r600_resource
*res
= (struct r600_resource
*)resource
;
575 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
576 struct radeon_bo_metadata metadata
;
577 bool update_metadata
= false;
578 unsigned stride
, offset
, slice_size
;
580 ctx
= threaded_context_unwrap_sync(ctx
);
581 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
583 if (resource
->target
!= PIPE_BUFFER
) {
584 /* This is not supported now, but it might be required for OpenCL
585 * interop in the future.
587 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
590 /* Move a suballocated texture into a non-suballocated allocation. */
591 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
592 rtex
->surface
.tile_swizzle
||
593 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
594 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
595 assert(!res
->b
.is_shared
);
596 r600_reallocate_texture_inplace(rctx
, rtex
,
597 PIPE_BIND_SHARED
, false);
598 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
599 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
600 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
601 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
602 assert(rtex
->surface
.tile_swizzle
== 0);
605 /* Since shader image stores don't support DCC on VI,
606 * disable it for external clients that want write
609 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
610 if (si_texture_disable_dcc(rctx
, rtex
))
611 update_metadata
= true;
614 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
615 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
616 /* Eliminate fast clear (both CMASK and DCC) */
617 r600_eliminate_fast_color_clear(rctx
, rtex
);
619 /* Disable CMASK if flush_resource isn't going
622 if (rtex
->cmask
.size
)
623 r600_texture_discard_cmask(rscreen
, rtex
);
627 if (!res
->b
.is_shared
|| update_metadata
) {
628 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
629 if (rscreen
->query_opaque_metadata
)
630 rscreen
->query_opaque_metadata(rscreen
, rtex
,
633 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
636 if (rscreen
->chip_class
>= GFX9
) {
637 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
638 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
640 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
642 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
643 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
645 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
648 /* Move a suballocated buffer into a non-suballocated allocation. */
649 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
650 assert(!res
->b
.is_shared
);
652 /* Allocate a new buffer with PIPE_BIND_SHARED. */
653 struct pipe_resource templ
= res
->b
.b
;
654 templ
.bind
|= PIPE_BIND_SHARED
;
656 struct pipe_resource
*newb
=
657 screen
->resource_create(screen
, &templ
);
661 /* Copy the old buffer contents to the new one. */
663 u_box_1d(0, newb
->width0
, &box
);
664 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
666 /* Move the new buffer storage to the old pipe_resource. */
667 si_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
668 pipe_resource_reference(&newb
, NULL
);
670 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
671 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
680 if (res
->b
.is_shared
) {
681 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
684 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
685 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
686 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
688 res
->b
.is_shared
= true;
689 res
->external_usage
= usage
;
692 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
693 slice_size
, whandle
);
696 static void r600_texture_destroy(struct pipe_screen
*screen
,
697 struct pipe_resource
*ptex
)
699 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
700 struct r600_resource
*resource
= &rtex
->resource
;
702 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
704 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
705 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
707 pb_reference(&resource
->buf
, NULL
);
708 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
709 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
713 static const struct u_resource_vtbl r600_texture_vtbl
;
715 /* The number of samples can be specified independently of the texture. */
716 void si_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
717 struct r600_texture
*rtex
,
719 struct r600_fmask_info
*out
)
721 /* FMASK is allocated like an ordinary texture. */
722 struct pipe_resource templ
= rtex
->resource
.b
.b
;
723 struct radeon_surf fmask
= {};
726 memset(out
, 0, sizeof(*out
));
728 if (rscreen
->chip_class
>= GFX9
) {
729 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
730 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
734 templ
.nr_samples
= 1;
735 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
737 switch (nr_samples
) {
746 R600_ERR("Invalid sample count for FMASK allocation.\n");
750 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
751 RADEON_SURF_MODE_2D
, &fmask
)) {
752 R600_ERR("Got error in surface_init while allocating FMASK.\n");
756 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
758 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
759 if (out
->slice_tile_max
)
760 out
->slice_tile_max
-= 1;
762 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
763 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
764 out
->bank_height
= fmask
.u
.legacy
.bankh
;
765 out
->tile_swizzle
= fmask
.tile_swizzle
;
766 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
767 out
->size
= fmask
.surf_size
;
770 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
771 struct r600_texture
*rtex
)
773 si_texture_get_fmask_info(rscreen
, rtex
,
774 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
776 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
777 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
780 void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
781 struct r600_texture
*rtex
,
782 struct r600_cmask_info
*out
)
784 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
785 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
786 unsigned cl_width
, cl_height
;
788 if (rscreen
->chip_class
>= GFX9
) {
789 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
790 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
807 case 16: /* Hawaii */
816 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
818 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
819 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
820 unsigned slice_elements
= (width
* height
) / (8*8);
822 /* Each element of CMASK is a nibble. */
823 unsigned slice_bytes
= slice_elements
/ 2;
825 out
->slice_tile_max
= (width
* height
) / (128*128);
826 if (out
->slice_tile_max
)
827 out
->slice_tile_max
-= 1;
829 out
->alignment
= MAX2(256, base_align
);
830 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
831 align(slice_bytes
, base_align
);
834 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
835 struct r600_texture
*rtex
)
837 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
839 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
840 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
842 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
845 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
846 struct r600_texture
*rtex
)
848 unsigned cl_width
, cl_height
, width
, height
;
849 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
850 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
852 assert(rscreen
->chip_class
<= VI
);
854 rtex
->surface
.htile_size
= 0;
856 /* HTILE is broken with 1D tiling on old kernels and CIK. */
857 if (rscreen
->chip_class
>= CIK
&&
858 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
859 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
862 /* Overalign HTILE on P2 configs to work around GPU hangs in
863 * piglit/depthstencil-render-miplevels 585.
865 * This has been confirmed to help Kabini & Stoney, where the hangs
866 * are always reproducible. I think I have seen the test hang
867 * on Carrizo too, though it was very rare there.
869 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
898 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
899 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
901 slice_elements
= (width
* height
) / (8 * 8);
902 slice_bytes
= slice_elements
* 4;
904 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
905 base_align
= num_pipes
* pipe_interleave_bytes
;
907 rtex
->surface
.htile_alignment
= base_align
;
908 rtex
->surface
.htile_size
=
909 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
910 align(slice_bytes
, base_align
);
913 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
914 struct r600_texture
*rtex
)
916 if (rscreen
->chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
917 r600_texture_get_htile_size(rscreen
, rtex
);
919 if (!rtex
->surface
.htile_size
)
922 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
923 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
926 void si_print_texture_info(struct r600_common_screen
*rscreen
,
927 struct r600_texture
*rtex
, struct u_log_context
*log
)
931 /* Common parameters. */
932 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
933 "blk_h=%u, array_size=%u, last_level=%u, "
934 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
935 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
936 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
938 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
939 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
940 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
942 if (rscreen
->chip_class
>= GFX9
) {
943 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
944 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
945 rtex
->surface
.surf_size
,
946 rtex
->surface
.u
.gfx9
.surf_slice_size
,
947 rtex
->surface
.surf_alignment
,
948 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
949 rtex
->surface
.u
.gfx9
.surf
.epitch
,
950 rtex
->surface
.u
.gfx9
.surf_pitch
);
952 if (rtex
->fmask
.size
) {
953 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
954 "alignment=%u, swmode=%u, epitch=%u\n",
956 rtex
->surface
.u
.gfx9
.fmask_size
,
957 rtex
->surface
.u
.gfx9
.fmask_alignment
,
958 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
959 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
962 if (rtex
->cmask
.size
) {
963 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
964 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
966 rtex
->surface
.u
.gfx9
.cmask_size
,
967 rtex
->surface
.u
.gfx9
.cmask_alignment
,
968 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
969 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
972 if (rtex
->htile_offset
) {
973 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
974 "rb_aligned=%u, pipe_aligned=%u\n",
976 rtex
->surface
.htile_size
,
977 rtex
->surface
.htile_alignment
,
978 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
979 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
982 if (rtex
->dcc_offset
) {
983 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
984 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
985 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
986 rtex
->surface
.dcc_alignment
,
987 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
988 rtex
->surface
.num_dcc_levels
);
991 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
992 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
993 rtex
->surface
.u
.gfx9
.stencil_offset
,
994 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
995 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1000 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1001 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1002 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1003 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1004 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1005 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1007 if (rtex
->fmask
.size
)
1008 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1009 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1010 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1011 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1012 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1014 if (rtex
->cmask
.size
)
1015 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1016 "slice_tile_max=%u\n",
1017 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1018 rtex
->cmask
.slice_tile_max
);
1020 if (rtex
->htile_offset
)
1021 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1022 "alignment=%u, TC_compatible = %u\n",
1023 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1024 rtex
->surface
.htile_alignment
,
1025 rtex
->tc_compatible_htile
);
1027 if (rtex
->dcc_offset
) {
1028 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1029 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1030 rtex
->surface
.dcc_alignment
);
1031 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1032 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1033 "fast_clear_size=%u\n",
1034 i
, i
< rtex
->surface
.num_dcc_levels
,
1035 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1036 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1039 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1040 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1041 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1042 "mode=%u, tiling_index = %u\n",
1043 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1044 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1045 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1046 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1047 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1048 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1049 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1050 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1051 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1053 if (rtex
->surface
.has_stencil
) {
1054 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1055 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1056 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1057 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1058 "slice_size=%"PRIu64
", npix_x=%u, "
1059 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1060 "mode=%u, tiling_index = %u\n",
1061 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1062 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1063 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1064 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1065 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1066 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1067 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1068 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1069 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1074 /* Common processing for r600_texture_create and r600_texture_from_handle */
1075 static struct r600_texture
*
1076 r600_texture_create_object(struct pipe_screen
*screen
,
1077 const struct pipe_resource
*base
,
1078 struct pb_buffer
*buf
,
1079 struct radeon_surf
*surface
)
1081 struct r600_texture
*rtex
;
1082 struct r600_resource
*resource
;
1083 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1085 rtex
= CALLOC_STRUCT(r600_texture
);
1089 resource
= &rtex
->resource
;
1090 resource
->b
.b
= *base
;
1091 resource
->b
.b
.next
= NULL
;
1092 resource
->b
.vtbl
= &r600_texture_vtbl
;
1093 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1094 resource
->b
.b
.screen
= screen
;
1096 /* don't include stencil-only formats which we don't support for rendering */
1097 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1099 rtex
->surface
= *surface
;
1100 rtex
->size
= rtex
->surface
.surf_size
;
1102 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1103 (rtex
->surface
.flags
&
1104 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1106 /* TC-compatible HTILE:
1107 * - VI only supports Z32_FLOAT.
1108 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1109 if (rtex
->tc_compatible_htile
) {
1110 if (rscreen
->chip_class
>= GFX9
&&
1111 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1112 rtex
->db_render_format
= base
->format
;
1114 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1115 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1116 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1119 rtex
->db_render_format
= base
->format
;
1122 /* Applies to GCN. */
1123 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1125 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1126 * between frames, so the only thing that can enable separate DCC
1127 * with DRI2 is multiple slow clears within a frame.
1129 rtex
->ps_draw_ratio
= 0;
1131 if (rtex
->is_depth
) {
1132 if (rscreen
->chip_class
>= GFX9
) {
1133 rtex
->can_sample_z
= true;
1134 rtex
->can_sample_s
= true;
1136 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1137 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1140 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1141 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1142 rtex
->db_compatible
= true;
1144 if (!(rscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1145 r600_texture_allocate_htile(rscreen
, rtex
);
1148 if (base
->nr_samples
> 1) {
1150 r600_texture_allocate_fmask(rscreen
, rtex
);
1151 r600_texture_allocate_cmask(rscreen
, rtex
);
1152 rtex
->cmask_buffer
= &rtex
->resource
;
1154 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1160 /* Shared textures must always set up DCC here.
1161 * If it's not present, it will be disabled by
1162 * apply_opaque_metadata later.
1164 if (rtex
->surface
.dcc_size
&&
1165 (buf
|| !(rscreen
->debug_flags
& DBG(NO_DCC
))) &&
1166 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1167 /* Reserve space for the DCC buffer. */
1168 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1169 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1173 /* Now create the backing buffer. */
1175 si_init_resource_fields(rscreen
, resource
, rtex
->size
,
1176 rtex
->surface
.surf_alignment
);
1178 if (!si_alloc_resource(rscreen
, resource
)) {
1183 resource
->buf
= buf
;
1184 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1185 resource
->bo_size
= buf
->size
;
1186 resource
->bo_alignment
= buf
->alignment
;
1187 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1188 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1189 resource
->vram_usage
= buf
->size
;
1190 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1191 resource
->gart_usage
= buf
->size
;
1194 if (rtex
->cmask
.size
) {
1195 /* Initialize the cmask to 0xCC (= compressed state). */
1196 si_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1197 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1200 if (rtex
->htile_offset
) {
1201 uint32_t clear_value
= 0;
1203 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1204 clear_value
= 0x0000030F;
1206 si_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1208 rtex
->surface
.htile_size
,
1212 /* Initialize DCC only if the texture is not being imported. */
1213 if (!buf
&& rtex
->dcc_offset
) {
1214 si_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1216 rtex
->surface
.dcc_size
,
1220 /* Initialize the CMASK base register value. */
1221 rtex
->cmask
.base_address_reg
=
1222 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1224 if (rscreen
->debug_flags
& DBG(VM
)) {
1225 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1226 rtex
->resource
.gpu_address
,
1227 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1228 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1229 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1232 if (rscreen
->debug_flags
& DBG(TEX
)) {
1234 struct u_log_context log
;
1235 u_log_context_init(&log
);
1236 si_print_texture_info(rscreen
, rtex
, &log
);
1237 u_log_new_page_print(&log
, stdout
);
1239 u_log_context_destroy(&log
);
1245 static enum radeon_surf_mode
1246 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1247 const struct pipe_resource
*templ
)
1249 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1250 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1251 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1252 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1254 /* MSAA resources must be 2D tiled. */
1255 if (templ
->nr_samples
> 1)
1256 return RADEON_SURF_MODE_2D
;
1258 /* Transfer resources should be linear. */
1259 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1260 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1262 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1263 * which requires 2D tiling.
1265 if (rscreen
->chip_class
== VI
&&
1267 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1268 return RADEON_SURF_MODE_2D
;
1270 /* Handle common candidates for the linear mode.
1271 * Compressed textures and DB surfaces must always be tiled.
1273 if (!force_tiling
&&
1274 !is_depth_stencil
&&
1275 !util_format_is_compressed(templ
->format
)) {
1276 if (rscreen
->debug_flags
& DBG(NO_TILING
))
1277 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1279 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1280 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1281 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1283 /* Cursors are linear on SI.
1284 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1285 if (templ
->bind
& PIPE_BIND_CURSOR
)
1286 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1288 if (templ
->bind
& PIPE_BIND_LINEAR
)
1289 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1291 /* Textures with a very small height are recommended to be linear. */
1292 if (templ
->target
== PIPE_TEXTURE_1D
||
1293 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1294 /* Only very thin and long 2D textures should benefit from
1295 * linear_aligned. */
1296 (templ
->width0
> 8 && templ
->height0
<= 2))
1297 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1299 /* Textures likely to be mapped often. */
1300 if (templ
->usage
== PIPE_USAGE_STAGING
||
1301 templ
->usage
== PIPE_USAGE_STREAM
)
1302 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1305 /* Make small textures 1D tiled. */
1306 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1307 (rscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1308 return RADEON_SURF_MODE_1D
;
1310 /* The allocator will switch to 1D if needed. */
1311 return RADEON_SURF_MODE_2D
;
1314 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1315 const struct pipe_resource
*templ
)
1317 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1318 struct radeon_surf surface
= {0};
1319 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1320 bool tc_compatible_htile
=
1321 rscreen
->chip_class
>= VI
&&
1322 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1323 !(rscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1324 !is_flushed_depth
&&
1325 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1326 util_format_is_depth_or_stencil(templ
->format
);
1330 r
= r600_init_surface(rscreen
, &surface
, templ
,
1331 r600_choose_tiling(rscreen
, templ
), 0, 0,
1332 false, false, is_flushed_depth
,
1333 tc_compatible_htile
);
1338 return (struct pipe_resource
*)
1339 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1342 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1343 const struct pipe_resource
*templ
,
1344 struct winsys_handle
*whandle
,
1347 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1348 struct pb_buffer
*buf
= NULL
;
1349 unsigned stride
= 0, offset
= 0;
1350 enum radeon_surf_mode array_mode
;
1351 struct radeon_surf surface
= {};
1353 struct radeon_bo_metadata metadata
= {};
1354 struct r600_texture
*rtex
;
1357 /* Support only 2D textures without mipmaps */
1358 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1359 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1362 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1366 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1367 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
1368 &array_mode
, &is_scanout
);
1370 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1371 offset
, true, is_scanout
, false, false);
1376 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1380 rtex
->resource
.b
.is_shared
= true;
1381 rtex
->resource
.external_usage
= usage
;
1383 if (rscreen
->apply_opaque_metadata
)
1384 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1386 assert(rtex
->surface
.tile_swizzle
== 0);
1387 return &rtex
->resource
.b
.b
;
1390 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1391 struct pipe_resource
*texture
,
1392 struct r600_texture
**staging
)
1394 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1395 struct pipe_resource resource
;
1396 struct r600_texture
**flushed_depth_texture
= staging
?
1397 staging
: &rtex
->flushed_depth_texture
;
1398 enum pipe_format pipe_format
= texture
->format
;
1401 if (rtex
->flushed_depth_texture
)
1402 return true; /* it's ready */
1404 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1405 switch (pipe_format
) {
1406 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1407 /* Save memory by not allocating the S plane. */
1408 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1410 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1411 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1412 /* Save memory bandwidth by not copying the
1413 * stencil part during flush.
1415 * This potentially increases memory bandwidth
1416 * if an application uses both Z and S texturing
1417 * simultaneously (a flushed Z24S8 texture
1418 * would be stored compactly), but how often
1419 * does that really happen?
1421 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1425 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1426 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1428 /* DB->CB copies to an 8bpp surface don't work. */
1429 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1433 memset(&resource
, 0, sizeof(resource
));
1434 resource
.target
= texture
->target
;
1435 resource
.format
= pipe_format
;
1436 resource
.width0
= texture
->width0
;
1437 resource
.height0
= texture
->height0
;
1438 resource
.depth0
= texture
->depth0
;
1439 resource
.array_size
= texture
->array_size
;
1440 resource
.last_level
= texture
->last_level
;
1441 resource
.nr_samples
= texture
->nr_samples
;
1442 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1443 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1444 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1447 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1449 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1450 if (*flushed_depth_texture
== NULL
) {
1451 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1458 * Initialize the pipe_resource descriptor to be of the same size as the box,
1459 * which is supposed to hold a subregion of the texture "orig" at the given
1462 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1463 struct pipe_resource
*orig
,
1464 const struct pipe_box
*box
,
1465 unsigned level
, unsigned flags
)
1467 memset(res
, 0, sizeof(*res
));
1468 res
->format
= orig
->format
;
1469 res
->width0
= box
->width
;
1470 res
->height0
= box
->height
;
1472 res
->array_size
= 1;
1473 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1476 /* We must set the correct texture target and dimensions for a 3D box. */
1477 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1478 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1479 res
->array_size
= box
->depth
;
1481 res
->target
= PIPE_TEXTURE_2D
;
1485 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1486 struct r600_texture
*rtex
,
1487 unsigned transfer_usage
,
1488 const struct pipe_box
*box
)
1490 return !rtex
->resource
.b
.is_shared
&&
1491 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1492 rtex
->resource
.b
.b
.last_level
== 0 &&
1493 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1494 box
->x
, box
->y
, box
->z
,
1495 box
->width
, box
->height
,
1499 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1500 struct r600_texture
*rtex
)
1502 struct r600_common_screen
*rscreen
= rctx
->screen
;
1504 /* There is no point in discarding depth and tiled buffers. */
1505 assert(!rtex
->is_depth
);
1506 assert(rtex
->surface
.is_linear
);
1508 /* Reallocate the buffer in the same pipe_resource. */
1509 si_alloc_resource(rscreen
, &rtex
->resource
);
1511 /* Initialize the CMASK base address (needed even without CMASK). */
1512 rtex
->cmask
.base_address_reg
=
1513 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1515 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1517 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1520 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1521 struct pipe_resource
*texture
,
1524 const struct pipe_box
*box
,
1525 struct pipe_transfer
**ptransfer
)
1527 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1528 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1529 struct r600_transfer
*trans
;
1530 struct r600_resource
*buf
;
1531 unsigned offset
= 0;
1533 bool use_staging_texture
= false;
1535 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1536 assert(box
->width
&& box
->height
&& box
->depth
);
1538 /* Depth textures use staging unconditionally. */
1539 if (!rtex
->is_depth
) {
1540 /* Degrade the tile mode if we get too many transfers on APUs.
1541 * On dGPUs, the staging texture is always faster.
1542 * Only count uploads that are at least 4x4 pixels large.
1544 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1546 box
->width
>= 4 && box
->height
>= 4 &&
1547 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1548 bool can_invalidate
=
1549 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1552 r600_reallocate_texture_inplace(rctx
, rtex
,
1557 /* Tiled textures need to be converted into a linear texture for CPU
1558 * access. The staging texture is always linear and is placed in GART.
1560 * Reading from VRAM or GTT WC is slow, always use the staging
1561 * texture in this case.
1563 * Use the staging texture for uploads if the underlying BO
1566 if (!rtex
->surface
.is_linear
)
1567 use_staging_texture
= true;
1568 else if (usage
& PIPE_TRANSFER_READ
)
1569 use_staging_texture
=
1570 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1571 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1572 /* Write & linear only: */
1573 else if (si_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1574 RADEON_USAGE_READWRITE
) ||
1575 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1576 RADEON_USAGE_READWRITE
)) {
1578 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1580 r600_texture_invalidate_storage(rctx
, rtex
);
1582 use_staging_texture
= true;
1586 trans
= CALLOC_STRUCT(r600_transfer
);
1589 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1590 trans
->b
.b
.level
= level
;
1591 trans
->b
.b
.usage
= usage
;
1592 trans
->b
.b
.box
= *box
;
1594 if (rtex
->is_depth
) {
1595 struct r600_texture
*staging_depth
;
1597 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1598 /* MSAA depth buffers need to be converted to single sample buffers.
1600 * Mapping MSAA depth buffers can occur if ReadPixels is called
1601 * with a multisample GLX visual.
1603 * First downsample the depth buffer to a temporary texture,
1604 * then decompress the temporary one to staging.
1606 * Only the region being mapped is transfered.
1608 struct pipe_resource resource
;
1610 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1612 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1613 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1618 if (usage
& PIPE_TRANSFER_READ
) {
1619 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1621 R600_ERR("failed to create a temporary depth texture\n");
1626 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1627 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1628 0, 0, 0, box
->depth
, 0, 0);
1629 pipe_resource_reference(&temp
, NULL
);
1632 /* Just get the strides. */
1633 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1635 &trans
->b
.b
.layer_stride
);
1637 /* XXX: only readback the rectangle which is being mapped? */
1638 /* XXX: when discard is true, no need to read back from depth texture */
1639 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1640 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1645 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1647 box
->z
, box
->z
+ box
->depth
- 1,
1650 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1653 &trans
->b
.b
.layer_stride
);
1656 trans
->staging
= (struct r600_resource
*)staging_depth
;
1657 buf
= trans
->staging
;
1658 } else if (use_staging_texture
) {
1659 struct pipe_resource resource
;
1660 struct r600_texture
*staging
;
1662 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1663 R600_RESOURCE_FLAG_TRANSFER
);
1664 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1665 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1667 /* Create the temporary texture. */
1668 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1670 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1674 trans
->staging
= &staging
->resource
;
1676 /* Just get the strides. */
1677 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1679 &trans
->b
.b
.layer_stride
);
1681 if (usage
& PIPE_TRANSFER_READ
)
1682 r600_copy_to_staging_texture(ctx
, trans
);
1684 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1686 buf
= trans
->staging
;
1688 /* the resource is mapped directly */
1689 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1691 &trans
->b
.b
.layer_stride
);
1692 buf
= &rtex
->resource
;
1695 if (!(map
= si_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1696 r600_resource_reference(&trans
->staging
, NULL
);
1701 *ptransfer
= &trans
->b
.b
;
1702 return map
+ offset
;
1705 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1706 struct pipe_transfer
* transfer
)
1708 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1709 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1710 struct pipe_resource
*texture
= transfer
->resource
;
1711 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1713 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1714 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1715 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1716 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1717 &rtransfer
->staging
->b
.b
, transfer
->level
,
1720 r600_copy_from_staging_texture(ctx
, rtransfer
);
1724 if (rtransfer
->staging
) {
1725 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1726 r600_resource_reference(&rtransfer
->staging
, NULL
);
1729 /* Heuristic for {upload, draw, upload, draw, ..}:
1731 * Flush the gfx IB if we've allocated too much texture storage.
1733 * The idea is that we don't want to build IBs that use too much
1734 * memory and put pressure on the kernel memory manager and we also
1735 * want to make temporary and invalidated buffers go idle ASAP to
1736 * decrease the total memory usage or make them reusable. The memory
1737 * usage will be slightly higher than given here because of the buffer
1738 * cache in the winsys.
1740 * The result is that the kernel memory manager is never a bottleneck.
1742 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1743 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1744 rctx
->num_alloc_tex_transfer_bytes
= 0;
1747 pipe_resource_reference(&transfer
->resource
, NULL
);
1751 static const struct u_resource_vtbl r600_texture_vtbl
=
1753 NULL
, /* get_handle */
1754 r600_texture_destroy
, /* resource_destroy */
1755 r600_texture_transfer_map
, /* transfer_map */
1756 u_default_transfer_flush_region
, /* transfer_flush_region */
1757 r600_texture_transfer_unmap
, /* transfer_unmap */
1760 /* DCC channel type categories within which formats can be reinterpreted
1761 * while keeping the same DCC encoding. The swizzle must also match. */
1762 enum dcc_channel_type
{
1763 dcc_channel_float32
,
1766 dcc_channel_float16
,
1769 dcc_channel_uint_10_10_10_2
,
1772 dcc_channel_incompatible
,
1775 /* Return the type of DCC encoding. */
1776 static enum dcc_channel_type
1777 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1781 /* Find the first non-void channel. */
1782 for (i
= 0; i
< desc
->nr_channels
; i
++)
1783 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1785 if (i
== desc
->nr_channels
)
1786 return dcc_channel_incompatible
;
1788 switch (desc
->channel
[i
].size
) {
1790 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1791 return dcc_channel_float32
;
1792 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1793 return dcc_channel_uint32
;
1794 return dcc_channel_sint32
;
1796 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1797 return dcc_channel_float16
;
1798 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1799 return dcc_channel_uint16
;
1800 return dcc_channel_sint16
;
1802 return dcc_channel_uint_10_10_10_2
;
1804 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1805 return dcc_channel_uint8
;
1806 return dcc_channel_sint8
;
1808 return dcc_channel_incompatible
;
1812 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1813 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1814 enum pipe_format format2
)
1816 const struct util_format_description
*desc1
, *desc2
;
1817 enum dcc_channel_type type1
, type2
;
1820 if (format1
== format2
)
1823 desc1
= util_format_description(format1
);
1824 desc2
= util_format_description(format2
);
1826 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1829 /* Swizzles must be the same. */
1830 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1831 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1832 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1833 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1836 type1
= vi_get_dcc_channel_type(desc1
);
1837 type2
= vi_get_dcc_channel_type(desc2
);
1839 return type1
!= dcc_channel_incompatible
&&
1840 type2
!= dcc_channel_incompatible
&&
1844 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1846 enum pipe_format view_format
)
1848 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1850 return vi_dcc_enabled(rtex
, level
) &&
1851 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1854 /* This can't be merged with the above function, because
1855 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1856 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1857 struct pipe_resource
*tex
,
1859 enum pipe_format view_format
)
1861 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1863 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1864 if (!si_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1865 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1868 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1869 struct pipe_resource
*texture
,
1870 const struct pipe_surface
*templ
,
1871 unsigned width0
, unsigned height0
,
1872 unsigned width
, unsigned height
)
1874 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1879 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1880 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1882 pipe_reference_init(&surface
->base
.reference
, 1);
1883 pipe_resource_reference(&surface
->base
.texture
, texture
);
1884 surface
->base
.context
= pipe
;
1885 surface
->base
.format
= templ
->format
;
1886 surface
->base
.width
= width
;
1887 surface
->base
.height
= height
;
1888 surface
->base
.u
= templ
->u
;
1890 surface
->width0
= width0
;
1891 surface
->height0
= height0
;
1893 surface
->dcc_incompatible
=
1894 texture
->target
!= PIPE_BUFFER
&&
1895 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1897 return &surface
->base
;
1900 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1901 struct pipe_resource
*tex
,
1902 const struct pipe_surface
*templ
)
1904 unsigned level
= templ
->u
.tex
.level
;
1905 unsigned width
= u_minify(tex
->width0
, level
);
1906 unsigned height
= u_minify(tex
->height0
, level
);
1907 unsigned width0
= tex
->width0
;
1908 unsigned height0
= tex
->height0
;
1910 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1911 const struct util_format_description
*tex_desc
1912 = util_format_description(tex
->format
);
1913 const struct util_format_description
*templ_desc
1914 = util_format_description(templ
->format
);
1916 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1918 /* Adjust size of surface if and only if the block width or
1919 * height is changed. */
1920 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1921 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1922 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1923 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1925 width
= nblks_x
* templ_desc
->block
.width
;
1926 height
= nblks_y
* templ_desc
->block
.height
;
1928 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1929 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1933 return si_create_surface_custom(pipe
, tex
, templ
,
1938 static void r600_surface_destroy(struct pipe_context
*pipe
,
1939 struct pipe_surface
*surface
)
1941 pipe_resource_reference(&surface
->texture
, NULL
);
1945 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1947 const struct util_format_description
*desc
= util_format_description(format
);
1949 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1951 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1952 return V_028C70_SWAP_STD
;
1954 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1957 switch (desc
->nr_channels
) {
1959 if (HAS_SWIZZLE(0,X
))
1960 return V_028C70_SWAP_STD
; /* X___ */
1961 else if (HAS_SWIZZLE(3,X
))
1962 return V_028C70_SWAP_ALT_REV
; /* ___X */
1965 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1966 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1967 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1968 return V_028C70_SWAP_STD
; /* XY__ */
1969 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1970 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1971 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1973 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
1974 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1975 return V_028C70_SWAP_ALT
; /* X__Y */
1976 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1977 return V_028C70_SWAP_ALT_REV
; /* Y__X */
1980 if (HAS_SWIZZLE(0,X
))
1981 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
1982 else if (HAS_SWIZZLE(0,Z
))
1983 return V_028C70_SWAP_STD_REV
; /* ZYX */
1986 /* check the middle channels, the 1st and 4th channel can be NONE */
1987 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1988 return V_028C70_SWAP_STD
; /* XYZW */
1989 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1990 return V_028C70_SWAP_STD_REV
; /* WZYX */
1991 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1992 return V_028C70_SWAP_ALT
; /* ZYXW */
1993 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1996 return V_028C70_SWAP_ALT_REV
;
1998 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2005 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2007 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2012 if (rctx
->dcc_stats
[slot
].query_active
)
2013 vi_separate_dcc_stop_query(&rctx
->b
,
2014 rctx
->dcc_stats
[slot
].tex
);
2016 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2017 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2018 rctx
->b
.destroy_query(&rctx
->b
,
2019 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2020 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2023 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2027 * Return the per-context slot where DCC statistics queries for the texture live.
2029 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2030 struct r600_texture
*tex
)
2032 int i
, empty_slot
= -1;
2034 /* Remove zombie textures (textures kept alive by this array only). */
2035 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2036 if (rctx
->dcc_stats
[i
].tex
&&
2037 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2038 vi_dcc_clean_up_context_slot(rctx
, i
);
2040 /* Find the texture. */
2041 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2042 /* Return if found. */
2043 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2044 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2048 /* Record the first seen empty slot. */
2049 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2053 /* Not found. Remove the oldest member to make space in the array. */
2054 if (empty_slot
== -1) {
2055 int oldest_slot
= 0;
2057 /* Find the oldest slot. */
2058 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2059 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2060 rctx
->dcc_stats
[i
].last_use_timestamp
)
2063 /* Clean up the oldest slot. */
2064 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2065 empty_slot
= oldest_slot
;
2068 /* Add the texture to the new slot. */
2069 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2070 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2074 static struct pipe_query
*
2075 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2077 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2078 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2080 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2081 return (struct pipe_query
*)query
;
2085 * Called when binding a color buffer.
2087 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2088 struct r600_texture
*tex
)
2090 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2091 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2093 assert(!rctx
->dcc_stats
[i
].query_active
);
2095 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2096 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2098 /* begin or resume the query */
2099 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2100 rctx
->dcc_stats
[i
].query_active
= true;
2104 * Called when unbinding a color buffer.
2106 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2107 struct r600_texture
*tex
)
2109 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2110 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2112 assert(rctx
->dcc_stats
[i
].query_active
);
2113 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2115 /* pause or end the query */
2116 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2117 rctx
->dcc_stats
[i
].query_active
= false;
2120 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2122 /* The minimum number of fullscreen draws per frame that is required
2124 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2127 /* Called by fast clear. */
2128 void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2129 struct r600_texture
*tex
)
2131 /* The intent is to use this with shared displayable back buffers,
2132 * but it's not strictly limited only to them.
2134 if (!tex
->resource
.b
.is_shared
||
2135 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2136 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2137 tex
->resource
.b
.b
.last_level
> 0 ||
2138 !tex
->surface
.dcc_size
)
2141 if (tex
->dcc_offset
)
2142 return; /* already enabled */
2144 /* Enable the DCC stat gathering. */
2145 if (!tex
->dcc_gather_statistics
) {
2146 tex
->dcc_gather_statistics
= true;
2147 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2150 if (!vi_should_enable_separate_dcc(tex
))
2151 return; /* stats show that DCC decompression is too expensive */
2153 assert(tex
->surface
.num_dcc_levels
);
2154 assert(!tex
->dcc_separate_buffer
);
2156 r600_texture_discard_cmask(rctx
->screen
, tex
);
2158 /* Get a DCC buffer. */
2159 if (tex
->last_dcc_separate_buffer
) {
2160 assert(tex
->dcc_gather_statistics
);
2161 assert(!tex
->dcc_separate_buffer
);
2162 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2163 tex
->last_dcc_separate_buffer
= NULL
;
2165 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2166 si_aligned_buffer_create(rctx
->b
.screen
,
2167 R600_RESOURCE_FLAG_UNMAPPABLE
,
2169 tex
->surface
.dcc_size
,
2170 tex
->surface
.dcc_alignment
);
2171 if (!tex
->dcc_separate_buffer
)
2175 /* dcc_offset is the absolute GPUVM address. */
2176 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2178 /* no need to flag anything since this is called by fast clear that
2179 * flags framebuffer state
2184 * Called by pipe_context::flush_resource, the place where DCC decompression
2187 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2188 struct r600_texture
*tex
)
2190 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2191 struct pipe_query
*tmp
;
2192 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2193 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2194 bool disable
= false;
2196 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2197 union pipe_query_result result
;
2199 /* Read the results. */
2200 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2202 si_query_hw_reset_buffers(rctx
,
2203 (struct r600_query_hw
*)
2204 rctx
->dcc_stats
[i
].ps_stats
[2]);
2206 /* Compute the approximate number of fullscreen draws. */
2207 tex
->ps_draw_ratio
=
2208 result
.pipeline_statistics
.ps_invocations
/
2209 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2210 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2212 disable
= tex
->dcc_separate_buffer
&&
2213 !vi_should_enable_separate_dcc(tex
);
2216 tex
->num_slow_clears
= 0;
2218 /* stop the statistics query for ps_stats[0] */
2220 vi_separate_dcc_stop_query(ctx
, tex
);
2222 /* Move the queries in the queue by one. */
2223 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2224 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2225 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2226 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2228 /* create and start a new query as ps_stats[0] */
2230 vi_separate_dcc_start_query(ctx
, tex
);
2233 assert(!tex
->last_dcc_separate_buffer
);
2234 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2235 tex
->dcc_separate_buffer
= NULL
;
2236 tex
->dcc_offset
= 0;
2237 /* no need to flag anything since this is called after
2238 * decompression that re-sets framebuffer state
2243 static struct pipe_memory_object
*
2244 r600_memobj_from_handle(struct pipe_screen
*screen
,
2245 struct winsys_handle
*whandle
,
2248 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2249 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2250 struct pb_buffer
*buf
= NULL
;
2251 uint32_t stride
, offset
;
2256 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
,
2263 memobj
->b
.dedicated
= dedicated
;
2265 memobj
->stride
= stride
;
2266 memobj
->offset
= offset
;
2268 return (struct pipe_memory_object
*)memobj
;
2273 r600_memobj_destroy(struct pipe_screen
*screen
,
2274 struct pipe_memory_object
*_memobj
)
2276 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2278 pb_reference(&memobj
->buf
, NULL
);
2282 static struct pipe_resource
*
2283 r600_texture_from_memobj(struct pipe_screen
*screen
,
2284 const struct pipe_resource
*templ
,
2285 struct pipe_memory_object
*_memobj
,
2289 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2290 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2291 struct r600_texture
*rtex
;
2292 struct radeon_surf surface
= {};
2293 struct radeon_bo_metadata metadata
= {};
2294 enum radeon_surf_mode array_mode
;
2296 struct pb_buffer
*buf
= NULL
;
2298 if (memobj
->b
.dedicated
) {
2299 rscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2300 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
2301 &array_mode
, &is_scanout
);
2304 * The bo metadata is unset for un-dedicated images. So we fall
2305 * back to linear. See answer to question 5 of the
2306 * VK_KHX_external_memory spec for some details.
2308 * It is possible that this case isn't going to work if the
2309 * surface pitch isn't correctly aligned by default.
2311 * In order to support it correctly we require multi-image
2312 * metadata to be syncrhonized between radv and radeonsi. The
2313 * semantics of associating multiple image metadata to a memory
2314 * object on the vulkan export side are not concretely defined
2317 * All the use cases we are aware of at the moment for memory
2318 * objects use dedicated allocations. So lets keep the initial
2319 * implementation simple.
2321 * A possible alternative is to attempt to reconstruct the
2322 * tiling information when the TexParameter TEXTURE_TILING_EXT
2325 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2330 r
= r600_init_surface(rscreen
, &surface
, templ
,
2331 array_mode
, memobj
->stride
,
2332 offset
, true, is_scanout
,
2337 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2341 /* r600_texture_create_object doesn't increment refcount of
2342 * memobj->buf, so increment it here.
2344 pb_reference(&buf
, memobj
->buf
);
2346 rtex
->resource
.b
.is_shared
= true;
2347 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2349 if (rscreen
->apply_opaque_metadata
)
2350 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
2352 return &rtex
->resource
.b
.b
;
2355 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2356 struct pipe_resource
*resource
,
2359 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2361 /* Buffers only support the linear flag. */
2362 if (resource
->target
== PIPE_BUFFER
)
2363 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2365 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2368 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2371 /* TODO: PIPE_BIND_CURSOR - do we care? */
2375 void si_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2377 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2378 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2379 rscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2380 rscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2381 rscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2382 rscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2385 void si_init_context_texture_functions(struct r600_common_context
*rctx
)
2387 rctx
->b
.create_surface
= r600_create_surface
;
2388 rctx
->b
.surface_destroy
= r600_surface_destroy
;