2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
57 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
62 rdst
->resource
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (rsrc
->is_depth
|| rdst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
77 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 r600_texture_discard_cmask(rctx
->screen
, rdst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
98 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
100 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
143 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
145 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
161 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
182 const struct pipe_box
*box
)
184 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
186 return rtex
->surface
.level
[level
].offset
+
187 box
->z
* rtex
->surface
.level
[level
].slice_size
+
188 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
189 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
192 static int r600_init_surface(struct r600_common_screen
*rscreen
,
193 struct radeon_surf
*surface
,
194 const struct pipe_resource
*ptex
,
195 enum radeon_surf_mode array_mode
,
196 unsigned pitch_in_bytes_override
,
200 bool is_flushed_depth
,
201 bool tc_compatible_htile
)
203 const struct util_format_description
*desc
=
204 util_format_description(ptex
->format
);
205 bool is_depth
, is_stencil
;
207 unsigned i
, bpe
, flags
= 0;
209 is_depth
= util_format_has_depth(desc
);
210 is_stencil
= util_format_has_stencil(desc
);
212 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
213 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
214 bpe
= 4; /* stencil is allocated separately on evergreen */
216 bpe
= util_format_get_blocksize(ptex
->format
);
217 /* align byte per element on dword */
223 if (!is_flushed_depth
&& is_depth
) {
224 flags
|= RADEON_SURF_ZBUFFER
;
226 if (tc_compatible_htile
&&
227 array_mode
== RADEON_SURF_MODE_2D
) {
228 /* TC-compatible HTILE only supports Z32_FLOAT.
229 * Promote Z16 to Z32. DB->CB copies will convert
230 * the format for transfers.
233 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
237 flags
|= RADEON_SURF_SBUFFER
|
238 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
242 if (rscreen
->chip_class
>= SI
) {
243 flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
246 if (rscreen
->chip_class
>= VI
&&
247 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
248 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
249 flags
|= RADEON_SURF_DISABLE_DCC
;
251 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
252 /* This should catch bugs in gallium users setting incorrect flags. */
253 assert(ptex
->nr_samples
<= 1 &&
254 ptex
->array_size
== 1 &&
256 ptex
->last_level
== 0 &&
257 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
259 flags
|= RADEON_SURF_SCANOUT
;
263 flags
|= RADEON_SURF_IMPORTED
;
265 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
266 array_mode
, surface
);
271 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= surface
->level
[0].pitch_bytes
) {
272 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
275 surface
->level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
276 surface
->level
[0].pitch_bytes
= pitch_in_bytes_override
;
277 surface
->level
[0].slice_size
= pitch_in_bytes_override
* surface
->level
[0].nblk_y
;
281 for (i
= 0; i
< ARRAY_SIZE(surface
->level
); ++i
)
282 surface
->level
[i
].offset
+= offset
;
287 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
288 struct radeon_bo_metadata
*metadata
)
290 struct radeon_surf
*surface
= &rtex
->surface
;
292 memset(metadata
, 0, sizeof(*metadata
));
293 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
294 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
295 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
296 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
297 metadata
->pipe_config
= surface
->pipe_config
;
298 metadata
->bankw
= surface
->bankw
;
299 metadata
->bankh
= surface
->bankh
;
300 metadata
->tile_split
= surface
->tile_split
;
301 metadata
->mtilea
= surface
->mtilea
;
302 metadata
->num_banks
= surface
->num_banks
;
303 metadata
->stride
= surface
->level
[0].pitch_bytes
;
304 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
307 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
309 p_atomic_inc(&rscreen
->dirty_fb_counter
);
312 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
313 struct r600_texture
*rtex
)
315 struct r600_common_screen
*rscreen
= rctx
->screen
;
316 struct pipe_context
*ctx
= &rctx
->b
;
318 if (ctx
== rscreen
->aux_context
)
319 pipe_mutex_lock(rscreen
->aux_context_lock
);
321 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
322 ctx
->flush(ctx
, NULL
, 0);
324 if (ctx
== rscreen
->aux_context
)
325 pipe_mutex_unlock(rscreen
->aux_context_lock
);
328 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
329 struct r600_texture
*rtex
)
331 if (!rtex
->cmask
.size
)
334 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
337 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
338 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
339 rtex
->dirty_level_mask
= 0;
341 if (rscreen
->chip_class
>= SI
)
342 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
344 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
346 if (rtex
->cmask_buffer
!= &rtex
->resource
)
347 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
349 /* Notify all contexts about the change. */
350 r600_dirty_all_framebuffer_states(rscreen
);
351 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
354 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
356 /* We can't disable DCC if it can be written by another process. */
357 return rtex
->dcc_offset
&&
358 (!rtex
->resource
.is_shared
||
359 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
362 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
363 struct r600_texture
*rtex
)
365 if (!r600_can_disable_dcc(rtex
))
368 assert(rtex
->dcc_separate_buffer
== NULL
);
371 rtex
->dcc_offset
= 0;
373 /* Notify all contexts about the change. */
374 r600_dirty_all_framebuffer_states(rscreen
);
379 * Disable DCC for the texture. (first decompress, then discard metadata).
381 * There is unresolved multi-context synchronization issue between
382 * screen::aux_context and the current context. If applications do this with
383 * multiple contexts, it's already undefined behavior for them and we don't
384 * have to worry about that. The scenario is:
386 * If context 1 disables DCC and context 2 has queued commands that write
387 * to the texture via CB with DCC enabled, and the order of operations is
389 * context 2 queues draw calls rendering to the texture, but doesn't flush
390 * context 1 disables DCC and flushes
391 * context 1 & 2 reset descriptors and FB state
392 * context 2 flushes (new compressed tiles written by the draw calls)
393 * context 1 & 2 read garbage, because DCC is disabled, yet there are
396 * \param rctx the current context if you have one, or rscreen->aux_context
399 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
400 struct r600_texture
*rtex
)
402 struct r600_common_screen
*rscreen
= rctx
->screen
;
404 if (!r600_can_disable_dcc(rtex
))
407 if (&rctx
->b
== rscreen
->aux_context
)
408 pipe_mutex_lock(rscreen
->aux_context_lock
);
410 /* Decompress DCC. */
411 rctx
->decompress_dcc(&rctx
->b
, rtex
);
412 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
414 if (&rctx
->b
== rscreen
->aux_context
)
415 pipe_mutex_unlock(rscreen
->aux_context_lock
);
417 return r600_texture_discard_dcc(rscreen
, rtex
);
420 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
421 struct r600_texture
*rtex
,
422 bool invalidate_storage
)
424 struct pipe_screen
*screen
= rctx
->b
.screen
;
425 struct r600_texture
*new_tex
;
426 struct pipe_resource templ
= rtex
->resource
.b
.b
;
429 templ
.bind
|= PIPE_BIND_LINEAR
;
431 /* r600g doesn't react to dirty_tex_descriptor_counter */
432 if (rctx
->chip_class
< SI
)
435 if (rtex
->resource
.is_shared
||
436 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
439 /* This fails with MSAA, depth, and compressed textures. */
440 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
441 RADEON_SURF_MODE_LINEAR_ALIGNED
)
444 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
448 /* Copy the pixels to the new texture. */
449 if (!invalidate_storage
) {
450 for (i
= 0; i
<= templ
.last_level
; i
++) {
454 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
455 util_max_layer(&templ
, i
) + 1, &box
);
457 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
458 &rtex
->resource
.b
.b
, i
, &box
);
462 r600_texture_discard_cmask(rctx
->screen
, rtex
);
463 r600_texture_discard_dcc(rctx
->screen
, rtex
);
465 /* Replace the structure fields of rtex. */
466 rtex
->resource
.b
.b
.bind
= templ
.bind
;
467 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
468 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
469 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
470 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
471 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
472 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
473 rtex
->resource
.domains
= new_tex
->resource
.domains
;
474 rtex
->resource
.flags
= new_tex
->resource
.flags
;
475 rtex
->size
= new_tex
->size
;
476 rtex
->surface
= new_tex
->surface
;
477 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
478 rtex
->cb_color_info
= new_tex
->cb_color_info
;
479 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
481 assert(!rtex
->htile_buffer
);
482 assert(!rtex
->cmask
.size
);
483 assert(!rtex
->fmask
.size
);
484 assert(!rtex
->dcc_offset
);
485 assert(!rtex
->is_depth
);
487 r600_texture_reference(&new_tex
, NULL
);
489 r600_dirty_all_framebuffer_states(rctx
->screen
);
490 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
493 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
494 struct pipe_context
*ctx
,
495 struct pipe_resource
*resource
,
496 struct winsys_handle
*whandle
,
499 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
500 struct r600_common_context
*rctx
= (struct r600_common_context
*)
501 (ctx
? ctx
: rscreen
->aux_context
);
502 struct r600_resource
*res
= (struct r600_resource
*)resource
;
503 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
504 struct radeon_bo_metadata metadata
;
505 bool update_metadata
= false;
507 /* This is not supported now, but it might be required for OpenCL
508 * interop in the future.
510 if (resource
->target
!= PIPE_BUFFER
&&
511 (resource
->nr_samples
> 1 || rtex
->is_depth
))
514 if (resource
->target
!= PIPE_BUFFER
) {
515 /* Since shader image stores don't support DCC on VI,
516 * disable it for external clients that want write
519 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
520 if (r600_texture_disable_dcc(rctx
, rtex
))
521 update_metadata
= true;
524 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
525 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
526 /* Eliminate fast clear (both CMASK and DCC) */
527 r600_eliminate_fast_color_clear(rctx
, rtex
);
529 /* Disable CMASK if flush_resource isn't going
532 if (rtex
->cmask
.size
)
533 r600_texture_discard_cmask(rscreen
, rtex
);
537 if (!res
->is_shared
|| update_metadata
) {
538 r600_texture_init_metadata(rtex
, &metadata
);
539 if (rscreen
->query_opaque_metadata
)
540 rscreen
->query_opaque_metadata(rscreen
, rtex
,
543 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
547 if (res
->is_shared
) {
548 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
551 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
552 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
553 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
555 res
->is_shared
= true;
556 res
->external_usage
= usage
;
559 return rscreen
->ws
->buffer_get_handle(res
->buf
,
560 rtex
->surface
.level
[0].pitch_bytes
,
561 rtex
->surface
.level
[0].offset
,
562 rtex
->surface
.level
[0].slice_size
,
566 static void r600_texture_destroy(struct pipe_screen
*screen
,
567 struct pipe_resource
*ptex
)
569 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
570 struct r600_resource
*resource
= &rtex
->resource
;
572 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
574 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
575 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
576 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
578 pb_reference(&resource
->buf
, NULL
);
579 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
580 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
584 static const struct u_resource_vtbl r600_texture_vtbl
;
586 /* The number of samples can be specified independently of the texture. */
587 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
588 struct r600_texture
*rtex
,
590 struct r600_fmask_info
*out
)
592 /* FMASK is allocated like an ordinary texture. */
593 struct pipe_resource templ
= rtex
->resource
.b
.b
;
594 struct radeon_surf fmask
= {};
597 memset(out
, 0, sizeof(*out
));
599 templ
.nr_samples
= 1;
600 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
602 /* Use the same parameters and tile mode. */
603 fmask
.bankw
= rtex
->surface
.bankw
;
604 fmask
.bankh
= rtex
->surface
.bankh
;
605 fmask
.mtilea
= rtex
->surface
.mtilea
;
606 fmask
.tile_split
= rtex
->surface
.tile_split
;
608 if (rscreen
->chip_class
>= SI
) {
609 flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
612 switch (nr_samples
) {
616 if (rscreen
->chip_class
<= CAYMAN
) {
624 R600_ERR("Invalid sample count for FMASK allocation.\n");
628 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
629 * This can be fixed by writing a separate FMASK allocator specifically
630 * for R600-R700 asics. */
631 if (rscreen
->chip_class
<= R700
) {
635 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
636 RADEON_SURF_MODE_2D
, &fmask
)) {
637 R600_ERR("Got error in surface_init while allocating FMASK.\n");
641 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
643 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
644 if (out
->slice_tile_max
)
645 out
->slice_tile_max
-= 1;
647 out
->tile_mode_index
= fmask
.tiling_index
[0];
648 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
649 out
->bank_height
= fmask
.bankh
;
650 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
651 out
->size
= fmask
.bo_size
;
654 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
655 struct r600_texture
*rtex
)
657 r600_texture_get_fmask_info(rscreen
, rtex
,
658 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
660 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
661 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
664 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
665 struct r600_texture
*rtex
,
666 struct r600_cmask_info
*out
)
668 unsigned cmask_tile_width
= 8;
669 unsigned cmask_tile_height
= 8;
670 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
671 unsigned element_bits
= 4;
672 unsigned cmask_cache_bits
= 1024;
673 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
674 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
676 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
677 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
678 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
679 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
680 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
682 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
683 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
685 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
686 unsigned slice_bytes
=
687 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
689 assert(macro_tile_width
% 128 == 0);
690 assert(macro_tile_height
% 128 == 0);
692 out
->pitch
= pitch_elements
;
693 out
->height
= height
;
694 out
->xalign
= macro_tile_width
;
695 out
->yalign
= macro_tile_height
;
696 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
697 out
->alignment
= MAX2(256, base_align
);
698 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
699 align(slice_bytes
, base_align
);
702 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
703 struct r600_texture
*rtex
,
704 struct r600_cmask_info
*out
)
706 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
707 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
708 unsigned cl_width
, cl_height
;
723 case 16: /* Hawaii */
732 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
734 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
735 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
736 unsigned slice_elements
= (width
* height
) / (8*8);
738 /* Each element of CMASK is a nibble. */
739 unsigned slice_bytes
= slice_elements
/ 2;
742 out
->height
= height
;
743 out
->xalign
= cl_width
* 8;
744 out
->yalign
= cl_height
* 8;
745 out
->slice_tile_max
= (width
* height
) / (128*128);
746 if (out
->slice_tile_max
)
747 out
->slice_tile_max
-= 1;
749 out
->alignment
= MAX2(256, base_align
);
750 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
751 align(slice_bytes
, base_align
);
754 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
755 struct r600_texture
*rtex
)
757 if (rscreen
->chip_class
>= SI
) {
758 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
760 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
763 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
764 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
766 if (rscreen
->chip_class
>= SI
)
767 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
769 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
772 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
773 struct r600_texture
*rtex
)
775 if (rtex
->cmask_buffer
)
778 assert(rtex
->cmask
.size
== 0);
780 if (rscreen
->chip_class
>= SI
) {
781 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
783 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
786 rtex
->cmask_buffer
= (struct r600_resource
*)
787 r600_aligned_buffer_create(&rscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
789 rtex
->cmask
.alignment
);
790 if (rtex
->cmask_buffer
== NULL
) {
791 rtex
->cmask
.size
= 0;
795 /* update colorbuffer state bits */
796 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
798 if (rscreen
->chip_class
>= SI
)
799 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
801 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
803 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
806 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
807 struct r600_texture
*rtex
)
809 unsigned cl_width
, cl_height
, width
, height
;
810 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
811 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
813 if (rscreen
->chip_class
<= EVERGREEN
&&
814 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
817 /* HW bug on R6xx. */
818 if (rscreen
->chip_class
== R600
&&
819 (rtex
->resource
.b
.b
.width0
> 7680 ||
820 rtex
->resource
.b
.b
.height0
> 7680))
823 /* HTILE is broken with 1D tiling on old kernels and CIK. */
824 if (rscreen
->chip_class
>= CIK
&&
825 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
826 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
829 /* Overalign HTILE on P2 configs to work around GPU hangs in
830 * piglit/depthstencil-render-miplevels 585.
832 * This has been confirmed to help Kabini & Stoney, where the hangs
833 * are always reproducible. I think I have seen the test hang
834 * on Carrizo too, though it was very rare there.
836 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
865 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
866 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
868 slice_elements
= (width
* height
) / (8 * 8);
869 slice_bytes
= slice_elements
* 4;
871 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
872 base_align
= num_pipes
* pipe_interleave_bytes
;
874 rtex
->htile
.pitch
= width
;
875 rtex
->htile
.height
= height
;
876 rtex
->htile
.xalign
= cl_width
* 8;
877 rtex
->htile
.yalign
= cl_height
* 8;
878 rtex
->htile
.alignment
= base_align
;
880 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
881 align(slice_bytes
, base_align
);
884 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
885 struct r600_texture
*rtex
)
887 uint64_t htile_size
, alignment
;
888 uint32_t clear_value
;
890 if (rtex
->tc_compatible_htile
) {
891 htile_size
= rtex
->surface
.htile_size
;
892 alignment
= rtex
->surface
.htile_alignment
;
893 clear_value
= 0x0000030F;
895 htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
896 alignment
= rtex
->htile
.alignment
;
903 rtex
->htile_buffer
= (struct r600_resource
*)
904 r600_aligned_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
906 htile_size
, alignment
);
907 if (rtex
->htile_buffer
== NULL
) {
908 /* this is not a fatal error as we can still keep rendering
909 * without htile buffer */
910 R600_ERR("Failed to create buffer object for htile buffer.\n");
912 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
913 0, htile_size
, clear_value
,
914 R600_COHERENCY_NONE
);
918 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
922 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
923 "blk_h=%u, array_size=%u, last_level=%u, "
924 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
925 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
926 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
928 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
929 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
930 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
932 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
933 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
934 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
935 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
936 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
937 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
939 if (rtex
->fmask
.size
)
940 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
941 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
942 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
943 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
944 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
946 if (rtex
->cmask
.size
)
947 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
948 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
949 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
950 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
951 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
953 if (rtex
->htile_buffer
)
954 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
955 "xalign=%u, yalign=%u, TC_compatible = %u\n",
956 rtex
->htile_buffer
->b
.b
.width0
,
957 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
958 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
,
959 rtex
->tc_compatible_htile
);
961 if (rtex
->dcc_offset
) {
962 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
963 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
964 rtex
->surface
.dcc_alignment
);
965 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
966 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
967 "fast_clear_size=%"PRIu64
"\n",
968 i
, rtex
->surface
.level
[i
].dcc_enabled
,
969 rtex
->surface
.level
[i
].dcc_offset
,
970 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
973 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
974 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
975 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
976 "pitch_bytes=%u, mode=%u\n",
977 i
, rtex
->surface
.level
[i
].offset
,
978 rtex
->surface
.level
[i
].slice_size
,
979 u_minify(rtex
->resource
.b
.b
.width0
, i
),
980 u_minify(rtex
->resource
.b
.b
.height0
, i
),
981 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
982 rtex
->surface
.level
[i
].nblk_x
,
983 rtex
->surface
.level
[i
].nblk_y
,
984 rtex
->surface
.level
[i
].pitch_bytes
,
985 rtex
->surface
.level
[i
].mode
);
987 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
988 fprintf(f
, " StencilLayout: tilesplit=%u\n",
989 rtex
->surface
.stencil_tile_split
);
990 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
991 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
992 "slice_size=%"PRIu64
", npix_x=%u, "
993 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
994 "pitch_bytes=%u, mode=%u\n",
995 i
, rtex
->surface
.stencil_level
[i
].offset
,
996 rtex
->surface
.stencil_level
[i
].slice_size
,
997 u_minify(rtex
->resource
.b
.b
.width0
, i
),
998 u_minify(rtex
->resource
.b
.b
.height0
, i
),
999 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1000 rtex
->surface
.stencil_level
[i
].nblk_x
,
1001 rtex
->surface
.stencil_level
[i
].nblk_y
,
1002 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
1003 rtex
->surface
.stencil_level
[i
].mode
);
1008 /* Common processing for r600_texture_create and r600_texture_from_handle */
1009 static struct r600_texture
*
1010 r600_texture_create_object(struct pipe_screen
*screen
,
1011 const struct pipe_resource
*base
,
1012 struct pb_buffer
*buf
,
1013 struct radeon_surf
*surface
)
1015 struct r600_texture
*rtex
;
1016 struct r600_resource
*resource
;
1017 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1019 rtex
= CALLOC_STRUCT(r600_texture
);
1023 resource
= &rtex
->resource
;
1024 resource
->b
.b
= *base
;
1025 resource
->b
.b
.next
= NULL
;
1026 resource
->b
.vtbl
= &r600_texture_vtbl
;
1027 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1028 resource
->b
.b
.screen
= screen
;
1030 /* don't include stencil-only formats which we don't support for rendering */
1031 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1033 rtex
->surface
= *surface
;
1034 rtex
->size
= rtex
->surface
.bo_size
;
1036 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0;
1037 assert(!!(rtex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) ==
1038 rtex
->tc_compatible_htile
);
1040 /* TC-compatible HTILE only supports Z32_FLOAT. */
1041 if (rtex
->tc_compatible_htile
)
1042 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1044 rtex
->db_render_format
= base
->format
;
1046 /* Tiled depth textures utilize the non-displayable tile order.
1047 * This must be done after r600_setup_surface.
1048 * Applies to R600-Cayman. */
1049 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1050 /* Applies to GCN. */
1051 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1053 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1054 * between frames, so the only thing that can enable separate DCC
1055 * with DRI2 is multiple slow clears within a frame.
1057 rtex
->ps_draw_ratio
= 0;
1059 if (rtex
->is_depth
) {
1060 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1061 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1062 rscreen
->chip_class
>= EVERGREEN
) {
1063 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1064 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1066 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1067 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1068 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1069 rtex
->can_sample_z
= true;
1072 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1073 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1074 rtex
->db_compatible
= true;
1076 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1077 r600_texture_allocate_htile(rscreen
, rtex
);
1080 if (base
->nr_samples
> 1) {
1082 r600_texture_allocate_fmask(rscreen
, rtex
);
1083 r600_texture_allocate_cmask(rscreen
, rtex
);
1084 rtex
->cmask_buffer
= &rtex
->resource
;
1086 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1092 /* Shared textures must always set up DCC here.
1093 * If it's not present, it will be disabled by
1094 * apply_opaque_metadata later.
1096 if (rtex
->surface
.dcc_size
&&
1097 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1098 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1099 /* Reserve space for the DCC buffer. */
1100 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1101 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1105 /* Now create the backing buffer. */
1107 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1108 rtex
->surface
.bo_alignment
);
1110 resource
->flags
|= RADEON_FLAG_HANDLE
;
1112 if (!r600_alloc_resource(rscreen
, resource
)) {
1117 resource
->buf
= buf
;
1118 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1119 resource
->bo_size
= buf
->size
;
1120 resource
->bo_alignment
= buf
->alignment
;
1121 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1122 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1123 resource
->vram_usage
= buf
->size
;
1124 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1125 resource
->gart_usage
= buf
->size
;
1128 if (rtex
->cmask
.size
) {
1129 /* Initialize the cmask to 0xCC (= compressed state). */
1130 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1131 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1132 0xCCCCCCCC, R600_COHERENCY_NONE
);
1135 /* Initialize DCC only if the texture is not being imported. */
1136 if (!buf
&& rtex
->dcc_offset
) {
1137 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1139 rtex
->surface
.dcc_size
,
1140 0xFFFFFFFF, R600_COHERENCY_NONE
);
1143 /* Initialize the CMASK base register value. */
1144 rtex
->cmask
.base_address_reg
=
1145 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1147 if (rscreen
->debug_flags
& DBG_VM
) {
1148 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1149 rtex
->resource
.gpu_address
,
1150 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1151 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1152 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1155 if (rscreen
->debug_flags
& DBG_TEX
) {
1157 r600_print_texture_info(rtex
, stdout
);
1164 static enum radeon_surf_mode
1165 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1166 const struct pipe_resource
*templ
)
1168 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1169 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1171 /* MSAA resources must be 2D tiled. */
1172 if (templ
->nr_samples
> 1)
1173 return RADEON_SURF_MODE_2D
;
1175 /* Transfer resources should be linear. */
1176 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1177 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1179 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1180 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1181 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1182 (templ
->target
== PIPE_TEXTURE_2D
||
1183 templ
->target
== PIPE_TEXTURE_3D
))
1184 force_tiling
= true;
1186 /* Handle common candidates for the linear mode.
1187 * Compressed textures and DB surfaces must always be tiled.
1189 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1190 (!util_format_is_depth_or_stencil(templ
->format
) ||
1191 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1192 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1193 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1195 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1196 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1197 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1199 /* Cursors are linear on SI.
1200 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1201 if (rscreen
->chip_class
>= SI
&&
1202 (templ
->bind
& PIPE_BIND_CURSOR
))
1203 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1205 if (templ
->bind
& PIPE_BIND_LINEAR
)
1206 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1208 /* Textures with a very small height are recommended to be linear. */
1209 if (templ
->target
== PIPE_TEXTURE_1D
||
1210 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1211 templ
->height0
<= 4)
1212 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1214 /* Textures likely to be mapped often. */
1215 if (templ
->usage
== PIPE_USAGE_STAGING
||
1216 templ
->usage
== PIPE_USAGE_STREAM
)
1217 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1220 /* Make small textures 1D tiled. */
1221 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1222 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1223 return RADEON_SURF_MODE_1D
;
1225 /* The allocator will switch to 1D if needed. */
1226 return RADEON_SURF_MODE_2D
;
1229 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1230 const struct pipe_resource
*templ
)
1232 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1233 struct radeon_surf surface
= {0};
1234 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1235 bool tc_compatible_htile
=
1236 rscreen
->chip_class
>= VI
&&
1237 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1238 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1239 !is_flushed_depth
&&
1240 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1241 util_format_is_depth_or_stencil(templ
->format
);
1245 r
= r600_init_surface(rscreen
, &surface
, templ
,
1246 r600_choose_tiling(rscreen
, templ
), 0, 0,
1247 false, false, is_flushed_depth
,
1248 tc_compatible_htile
);
1253 return (struct pipe_resource
*)
1254 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1257 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1258 const struct pipe_resource
*templ
,
1259 struct winsys_handle
*whandle
,
1262 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1263 struct pb_buffer
*buf
= NULL
;
1264 unsigned stride
= 0, offset
= 0;
1265 unsigned array_mode
;
1266 struct radeon_surf surface
;
1268 struct radeon_bo_metadata metadata
= {};
1269 struct r600_texture
*rtex
;
1271 /* Support only 2D textures without mipmaps */
1272 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1273 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1276 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1280 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1282 surface
.pipe_config
= metadata
.pipe_config
;
1283 surface
.bankw
= metadata
.bankw
;
1284 surface
.bankh
= metadata
.bankh
;
1285 surface
.tile_split
= metadata
.tile_split
;
1286 surface
.mtilea
= metadata
.mtilea
;
1287 surface
.num_banks
= metadata
.num_banks
;
1289 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1290 array_mode
= RADEON_SURF_MODE_2D
;
1291 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1292 array_mode
= RADEON_SURF_MODE_1D
;
1294 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1296 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1297 offset
, true, metadata
.scanout
, false, false);
1302 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1306 rtex
->resource
.is_shared
= true;
1307 rtex
->resource
.external_usage
= usage
;
1309 if (rscreen
->apply_opaque_metadata
)
1310 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1312 return &rtex
->resource
.b
.b
;
1315 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1316 struct pipe_resource
*texture
,
1317 struct r600_texture
**staging
)
1319 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1320 struct pipe_resource resource
;
1321 struct r600_texture
**flushed_depth_texture
= staging
?
1322 staging
: &rtex
->flushed_depth_texture
;
1323 enum pipe_format pipe_format
= texture
->format
;
1326 if (rtex
->flushed_depth_texture
)
1327 return true; /* it's ready */
1329 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1330 switch (pipe_format
) {
1331 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1332 /* Save memory by not allocating the S plane. */
1333 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1335 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1336 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1337 /* Save memory bandwidth by not copying the
1338 * stencil part during flush.
1340 * This potentially increases memory bandwidth
1341 * if an application uses both Z and S texturing
1342 * simultaneously (a flushed Z24S8 texture
1343 * would be stored compactly), but how often
1344 * does that really happen?
1346 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1350 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1351 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1353 /* DB->CB copies to an 8bpp surface don't work. */
1354 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1358 memset(&resource
, 0, sizeof(resource
));
1359 resource
.target
= texture
->target
;
1360 resource
.format
= pipe_format
;
1361 resource
.width0
= texture
->width0
;
1362 resource
.height0
= texture
->height0
;
1363 resource
.depth0
= texture
->depth0
;
1364 resource
.array_size
= texture
->array_size
;
1365 resource
.last_level
= texture
->last_level
;
1366 resource
.nr_samples
= texture
->nr_samples
;
1367 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1368 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1369 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1372 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1374 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1375 if (*flushed_depth_texture
== NULL
) {
1376 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1380 (*flushed_depth_texture
)->non_disp_tiling
= false;
1385 * Initialize the pipe_resource descriptor to be of the same size as the box,
1386 * which is supposed to hold a subregion of the texture "orig" at the given
1389 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1390 struct pipe_resource
*orig
,
1391 const struct pipe_box
*box
,
1392 unsigned level
, unsigned flags
)
1394 memset(res
, 0, sizeof(*res
));
1395 res
->format
= orig
->format
;
1396 res
->width0
= box
->width
;
1397 res
->height0
= box
->height
;
1399 res
->array_size
= 1;
1400 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1403 /* We must set the correct texture target and dimensions for a 3D box. */
1404 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1405 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1406 res
->array_size
= box
->depth
;
1408 res
->target
= PIPE_TEXTURE_2D
;
1412 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1413 struct r600_texture
*rtex
,
1414 unsigned transfer_usage
,
1415 const struct pipe_box
*box
)
1417 /* r600g doesn't react to dirty_tex_descriptor_counter */
1418 return rscreen
->chip_class
>= SI
&&
1419 !rtex
->resource
.is_shared
&&
1420 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1421 rtex
->resource
.b
.b
.last_level
== 0 &&
1422 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1423 box
->x
, box
->y
, box
->z
,
1424 box
->width
, box
->height
,
1428 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1429 struct r600_texture
*rtex
)
1431 struct r600_common_screen
*rscreen
= rctx
->screen
;
1433 /* There is no point in discarding depth and tiled buffers. */
1434 assert(!rtex
->is_depth
);
1435 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1437 /* Reallocate the buffer in the same pipe_resource. */
1438 r600_alloc_resource(rscreen
, &rtex
->resource
);
1440 /* Initialize the CMASK base address (needed even without CMASK). */
1441 rtex
->cmask
.base_address_reg
=
1442 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1444 r600_dirty_all_framebuffer_states(rscreen
);
1445 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1447 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1450 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1451 struct pipe_resource
*texture
,
1454 const struct pipe_box
*box
,
1455 struct pipe_transfer
**ptransfer
)
1457 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1458 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1459 struct r600_transfer
*trans
;
1460 struct r600_resource
*buf
;
1461 unsigned offset
= 0;
1463 bool use_staging_texture
= false;
1465 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1467 /* Depth textures use staging unconditionally. */
1468 if (!rtex
->is_depth
) {
1469 /* Degrade the tile mode if we get too many transfers on APUs.
1470 * On dGPUs, the staging texture is always faster.
1471 * Only count uploads that are at least 4x4 pixels large.
1473 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1475 box
->width
>= 4 && box
->height
>= 4 &&
1476 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1477 bool can_invalidate
=
1478 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1481 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1485 /* Tiled textures need to be converted into a linear texture for CPU
1486 * access. The staging texture is always linear and is placed in GART.
1488 * Reading from VRAM is slow, always use the staging texture in
1491 * Use the staging texture for uploads if the underlying BO
1494 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1495 use_staging_texture
= true;
1496 else if (usage
& PIPE_TRANSFER_READ
)
1497 use_staging_texture
= (rtex
->resource
.domains
&
1498 RADEON_DOMAIN_VRAM
) != 0;
1499 /* Write & linear only: */
1500 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1501 RADEON_USAGE_READWRITE
) ||
1502 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1503 RADEON_USAGE_READWRITE
)) {
1505 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1507 r600_texture_invalidate_storage(rctx
, rtex
);
1509 use_staging_texture
= true;
1513 trans
= CALLOC_STRUCT(r600_transfer
);
1516 trans
->transfer
.resource
= texture
;
1517 trans
->transfer
.level
= level
;
1518 trans
->transfer
.usage
= usage
;
1519 trans
->transfer
.box
= *box
;
1521 if (rtex
->is_depth
) {
1522 struct r600_texture
*staging_depth
;
1524 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1525 /* MSAA depth buffers need to be converted to single sample buffers.
1527 * Mapping MSAA depth buffers can occur if ReadPixels is called
1528 * with a multisample GLX visual.
1530 * First downsample the depth buffer to a temporary texture,
1531 * then decompress the temporary one to staging.
1533 * Only the region being mapped is transfered.
1535 struct pipe_resource resource
;
1537 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1539 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1540 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1545 if (usage
& PIPE_TRANSFER_READ
) {
1546 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1548 R600_ERR("failed to create a temporary depth texture\n");
1553 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1554 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1555 0, 0, 0, box
->depth
, 0, 0);
1556 pipe_resource_reference(&temp
, NULL
);
1560 /* XXX: only readback the rectangle which is being mapped? */
1561 /* XXX: when discard is true, no need to read back from depth texture */
1562 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1563 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1568 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1570 box
->z
, box
->z
+ box
->depth
- 1,
1573 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1576 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1577 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1578 trans
->staging
= (struct r600_resource
*)staging_depth
;
1579 buf
= trans
->staging
;
1580 } else if (use_staging_texture
) {
1581 struct pipe_resource resource
;
1582 struct r600_texture
*staging
;
1584 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1585 R600_RESOURCE_FLAG_TRANSFER
);
1586 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1587 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1589 /* Create the temporary texture. */
1590 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1592 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1596 trans
->staging
= &staging
->resource
;
1597 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1598 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1600 if (usage
& PIPE_TRANSFER_READ
)
1601 r600_copy_to_staging_texture(ctx
, trans
);
1603 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1605 buf
= trans
->staging
;
1607 /* the resource is mapped directly */
1608 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1609 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1610 offset
= r600_texture_get_offset(rtex
, level
, box
);
1611 buf
= &rtex
->resource
;
1614 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1615 r600_resource_reference(&trans
->staging
, NULL
);
1620 *ptransfer
= &trans
->transfer
;
1621 return map
+ offset
;
1624 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1625 struct pipe_transfer
* transfer
)
1627 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1628 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1629 struct pipe_resource
*texture
= transfer
->resource
;
1630 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1632 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1633 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1634 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1635 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1636 &rtransfer
->staging
->b
.b
, transfer
->level
,
1639 r600_copy_from_staging_texture(ctx
, rtransfer
);
1643 if (rtransfer
->staging
) {
1644 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1645 r600_resource_reference(&rtransfer
->staging
, NULL
);
1648 /* Heuristic for {upload, draw, upload, draw, ..}:
1650 * Flush the gfx IB if we've allocated too much texture storage.
1652 * The idea is that we don't want to build IBs that use too much
1653 * memory and put pressure on the kernel memory manager and we also
1654 * want to make temporary and invalidated buffers go idle ASAP to
1655 * decrease the total memory usage or make them reusable. The memory
1656 * usage will be slightly higher than given here because of the buffer
1657 * cache in the winsys.
1659 * The result is that the kernel memory manager is never a bottleneck.
1661 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1662 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1663 rctx
->num_alloc_tex_transfer_bytes
= 0;
1669 static const struct u_resource_vtbl r600_texture_vtbl
=
1671 NULL
, /* get_handle */
1672 r600_texture_destroy
, /* resource_destroy */
1673 r600_texture_transfer_map
, /* transfer_map */
1674 u_default_transfer_flush_region
, /* transfer_flush_region */
1675 r600_texture_transfer_unmap
, /* transfer_unmap */
1678 /* DCC channel type categories within which formats can be reinterpreted
1679 * while keeping the same DCC encoding. The swizzle must also match. */
1680 enum dcc_channel_type
{
1681 dcc_channel_float32
,
1684 dcc_channel_float16
,
1687 dcc_channel_uint_10_10_10_2
,
1690 dcc_channel_incompatible
,
1693 /* Return the type of DCC encoding. */
1694 static enum dcc_channel_type
1695 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1699 /* Find the first non-void channel. */
1700 for (i
= 0; i
< desc
->nr_channels
; i
++)
1701 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1703 if (i
== desc
->nr_channels
)
1704 return dcc_channel_incompatible
;
1706 switch (desc
->channel
[i
].size
) {
1708 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1709 return dcc_channel_float32
;
1710 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1711 return dcc_channel_uint32
;
1712 return dcc_channel_sint32
;
1714 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1715 return dcc_channel_float16
;
1716 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1717 return dcc_channel_uint16
;
1718 return dcc_channel_sint16
;
1720 return dcc_channel_uint_10_10_10_2
;
1722 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1723 return dcc_channel_uint8
;
1724 return dcc_channel_sint8
;
1726 return dcc_channel_incompatible
;
1730 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1731 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1732 enum pipe_format format2
)
1734 const struct util_format_description
*desc1
, *desc2
;
1735 enum dcc_channel_type type1
, type2
;
1738 if (format1
== format2
)
1741 desc1
= util_format_description(format1
);
1742 desc2
= util_format_description(format2
);
1744 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1747 /* Swizzles must be the same. */
1748 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1749 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1750 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1751 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1754 type1
= vi_get_dcc_channel_type(desc1
);
1755 type2
= vi_get_dcc_channel_type(desc2
);
1757 return type1
!= dcc_channel_incompatible
&&
1758 type2
!= dcc_channel_incompatible
&&
1762 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1763 struct pipe_resource
*tex
,
1765 enum pipe_format view_format
)
1767 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1769 if (rtex
->dcc_offset
&&
1770 rtex
->surface
.level
[level
].dcc_enabled
&&
1771 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1772 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1773 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1776 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1777 struct pipe_resource
*texture
,
1778 const struct pipe_surface
*templ
,
1779 unsigned width
, unsigned height
)
1781 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1782 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1783 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1788 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1789 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1791 pipe_reference_init(&surface
->base
.reference
, 1);
1792 pipe_resource_reference(&surface
->base
.texture
, texture
);
1793 surface
->base
.context
= pipe
;
1794 surface
->base
.format
= templ
->format
;
1795 surface
->base
.width
= width
;
1796 surface
->base
.height
= height
;
1797 surface
->base
.u
= templ
->u
;
1798 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1800 if (texture
->target
!= PIPE_BUFFER
)
1801 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1805 return &surface
->base
;
1808 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1809 struct pipe_resource
*tex
,
1810 const struct pipe_surface
*templ
)
1812 unsigned level
= templ
->u
.tex
.level
;
1813 unsigned width
= u_minify(tex
->width0
, level
);
1814 unsigned height
= u_minify(tex
->height0
, level
);
1816 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1817 const struct util_format_description
*tex_desc
1818 = util_format_description(tex
->format
);
1819 const struct util_format_description
*templ_desc
1820 = util_format_description(templ
->format
);
1822 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1824 /* Adjust size of surface if and only if the block width or
1825 * height is changed. */
1826 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1827 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1828 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1829 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1831 width
= nblks_x
* templ_desc
->block
.width
;
1832 height
= nblks_y
* templ_desc
->block
.height
;
1836 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1839 static void r600_surface_destroy(struct pipe_context
*pipe
,
1840 struct pipe_surface
*surface
)
1842 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1843 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1844 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1845 pipe_resource_reference(&surface
->texture
, NULL
);
1849 static void r600_clear_texture(struct pipe_context
*pipe
,
1850 struct pipe_resource
*tex
,
1852 const struct pipe_box
*box
,
1855 struct pipe_screen
*screen
= pipe
->screen
;
1856 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1857 struct pipe_surface tmpl
= {{0}};
1858 struct pipe_surface
*sf
;
1859 const struct util_format_description
*desc
=
1860 util_format_description(tex
->format
);
1862 tmpl
.format
= tex
->format
;
1863 tmpl
.u
.tex
.first_layer
= box
->z
;
1864 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1865 tmpl
.u
.tex
.level
= level
;
1866 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1870 if (rtex
->is_depth
) {
1873 uint8_t stencil
= 0;
1875 /* Depth is always present. */
1876 clear
= PIPE_CLEAR_DEPTH
;
1877 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1879 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1880 clear
|= PIPE_CLEAR_STENCIL
;
1881 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1884 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1886 box
->width
, box
->height
, false);
1888 union pipe_color_union color
;
1890 /* pipe_color_union requires the full vec4 representation. */
1891 if (util_format_is_pure_uint(tex
->format
))
1892 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1893 else if (util_format_is_pure_sint(tex
->format
))
1894 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1896 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1898 if (screen
->is_format_supported(screen
, tex
->format
,
1900 PIPE_BIND_RENDER_TARGET
)) {
1901 pipe
->clear_render_target(pipe
, sf
, &color
,
1903 box
->width
, box
->height
, false);
1905 /* Software fallback - just for R9G9B9E5_FLOAT */
1906 util_clear_render_target(pipe
, sf
, &color
,
1908 box
->width
, box
->height
);
1911 pipe_surface_reference(&sf
, NULL
);
1914 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1916 const struct util_format_description
*desc
= util_format_description(format
);
1918 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1920 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1921 return V_0280A0_SWAP_STD
;
1923 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1926 switch (desc
->nr_channels
) {
1928 if (HAS_SWIZZLE(0,X
))
1929 return V_0280A0_SWAP_STD
; /* X___ */
1930 else if (HAS_SWIZZLE(3,X
))
1931 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1934 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1935 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1936 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1937 return V_0280A0_SWAP_STD
; /* XY__ */
1938 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1939 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1940 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1942 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1943 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1944 return V_0280A0_SWAP_ALT
; /* X__Y */
1945 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1946 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1949 if (HAS_SWIZZLE(0,X
))
1950 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1951 else if (HAS_SWIZZLE(0,Z
))
1952 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1955 /* check the middle channels, the 1st and 4th channel can be NONE */
1956 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1957 return V_0280A0_SWAP_STD
; /* XYZW */
1958 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1959 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1960 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1961 return V_0280A0_SWAP_ALT
; /* ZYXW */
1962 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1965 return V_0280A0_SWAP_ALT_REV
;
1967 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1974 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1976 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1981 if (rctx
->dcc_stats
[slot
].query_active
)
1982 vi_separate_dcc_stop_query(&rctx
->b
,
1983 rctx
->dcc_stats
[slot
].tex
);
1985 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1986 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1987 rctx
->b
.destroy_query(&rctx
->b
,
1988 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1989 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1992 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1996 * Return the per-context slot where DCC statistics queries for the texture live.
1998 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1999 struct r600_texture
*tex
)
2001 int i
, empty_slot
= -1;
2003 /* Remove zombie textures (textures kept alive by this array only). */
2004 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2005 if (rctx
->dcc_stats
[i
].tex
&&
2006 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2007 vi_dcc_clean_up_context_slot(rctx
, i
);
2009 /* Find the texture. */
2010 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2011 /* Return if found. */
2012 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2013 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2017 /* Record the first seen empty slot. */
2018 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2022 /* Not found. Remove the oldest member to make space in the array. */
2023 if (empty_slot
== -1) {
2024 int oldest_slot
= 0;
2026 /* Find the oldest slot. */
2027 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2028 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2029 rctx
->dcc_stats
[i
].last_use_timestamp
)
2032 /* Clean up the oldest slot. */
2033 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2034 empty_slot
= oldest_slot
;
2037 /* Add the texture to the new slot. */
2038 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2039 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2043 static struct pipe_query
*
2044 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2046 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2047 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2049 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2050 return (struct pipe_query
*)query
;
2054 * Called when binding a color buffer.
2056 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2057 struct r600_texture
*tex
)
2059 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2060 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2062 assert(!rctx
->dcc_stats
[i
].query_active
);
2064 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2065 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2067 /* begin or resume the query */
2068 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2069 rctx
->dcc_stats
[i
].query_active
= true;
2073 * Called when unbinding a color buffer.
2075 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2076 struct r600_texture
*tex
)
2078 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2079 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2081 assert(rctx
->dcc_stats
[i
].query_active
);
2082 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2084 /* pause or end the query */
2085 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2086 rctx
->dcc_stats
[i
].query_active
= false;
2089 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2091 /* The minimum number of fullscreen draws per frame that is required
2093 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2096 /* Called by fast clear. */
2097 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2098 struct r600_texture
*tex
)
2100 /* The intent is to use this with shared displayable back buffers,
2101 * but it's not strictly limited only to them.
2103 if (!tex
->resource
.is_shared
||
2104 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2105 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2106 tex
->resource
.b
.b
.last_level
> 0 ||
2107 !tex
->surface
.dcc_size
)
2110 if (tex
->dcc_offset
)
2111 return; /* already enabled */
2113 /* Enable the DCC stat gathering. */
2114 if (!tex
->dcc_gather_statistics
) {
2115 tex
->dcc_gather_statistics
= true;
2116 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2119 if (!vi_should_enable_separate_dcc(tex
))
2120 return; /* stats show that DCC decompression is too expensive */
2122 assert(tex
->surface
.level
[0].dcc_enabled
);
2123 assert(!tex
->dcc_separate_buffer
);
2125 r600_texture_discard_cmask(rctx
->screen
, tex
);
2127 /* Get a DCC buffer. */
2128 if (tex
->last_dcc_separate_buffer
) {
2129 assert(tex
->dcc_gather_statistics
);
2130 assert(!tex
->dcc_separate_buffer
);
2131 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2132 tex
->last_dcc_separate_buffer
= NULL
;
2134 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2135 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
2137 tex
->surface
.dcc_size
,
2138 tex
->surface
.dcc_alignment
);
2139 if (!tex
->dcc_separate_buffer
)
2143 /* dcc_offset is the absolute GPUVM address. */
2144 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2146 /* no need to flag anything since this is called by fast clear that
2147 * flags framebuffer state
2152 * Called by pipe_context::flush_resource, the place where DCC decompression
2155 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2156 struct r600_texture
*tex
)
2158 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2159 struct pipe_query
*tmp
;
2160 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2161 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2162 bool disable
= false;
2164 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2165 union pipe_query_result result
;
2167 /* Read the results. */
2168 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2170 r600_query_hw_reset_buffers(rctx
,
2171 (struct r600_query_hw
*)
2172 rctx
->dcc_stats
[i
].ps_stats
[2]);
2174 /* Compute the approximate number of fullscreen draws. */
2175 tex
->ps_draw_ratio
=
2176 result
.pipeline_statistics
.ps_invocations
/
2177 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2178 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2180 disable
= tex
->dcc_separate_buffer
&&
2181 !vi_should_enable_separate_dcc(tex
);
2184 tex
->num_slow_clears
= 0;
2186 /* stop the statistics query for ps_stats[0] */
2188 vi_separate_dcc_stop_query(ctx
, tex
);
2190 /* Move the queries in the queue by one. */
2191 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2192 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2193 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2194 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2196 /* create and start a new query as ps_stats[0] */
2198 vi_separate_dcc_start_query(ctx
, tex
);
2201 assert(!tex
->last_dcc_separate_buffer
);
2202 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2203 tex
->dcc_separate_buffer
= NULL
;
2204 tex
->dcc_offset
= 0;
2205 /* no need to flag anything since this is called after
2206 * decompression that re-sets framebuffer state
2211 /* FAST COLOR CLEAR */
2213 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2214 enum pipe_format surface_format
,
2215 const union pipe_color_union
*color
)
2217 union util_color uc
;
2219 memset(&uc
, 0, sizeof(uc
));
2221 if (util_format_get_blocksizebits(surface_format
) == 128) {
2222 /* DCC fast clear only:
2223 * CLEAR_WORD0 = R = G = B
2226 assert(color
->ui
[0] == color
->ui
[1] &&
2227 color
->ui
[0] == color
->ui
[2]);
2228 uc
.ui
[0] = color
->ui
[0];
2229 uc
.ui
[1] = color
->ui
[3];
2230 } else if (util_format_is_pure_uint(surface_format
)) {
2231 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2232 } else if (util_format_is_pure_sint(surface_format
)) {
2233 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2235 util_pack_color(color
->f
, surface_format
, &uc
);
2238 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2241 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2242 const union pipe_color_union
*color
,
2243 uint32_t* reset_value
,
2244 bool* clear_words_needed
)
2246 bool values
[4] = {};
2248 bool main_value
= false;
2249 bool extra_value
= false;
2251 const struct util_format_description
*desc
= util_format_description(surface_format
);
2253 if (desc
->block
.bits
== 128 &&
2254 (color
->ui
[0] != color
->ui
[1] ||
2255 color
->ui
[0] != color
->ui
[2]))
2258 *clear_words_needed
= true;
2259 *reset_value
= 0x20202020U
;
2261 /* If we want to clear without needing a fast clear eliminate step, we
2262 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2263 * have two sets of flags, one for the last or first channel(extra) and
2264 * one for the other channels(main).
2267 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2268 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2269 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2271 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2272 if(r600_translate_colorswap(surface_format
, false) <= 1)
2273 extra_channel
= desc
->nr_channels
- 1;
2279 for (i
= 0; i
< 4; ++i
) {
2280 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2282 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2283 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2286 if (desc
->channel
[i
].pure_integer
&&
2287 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2288 /* Use the maximum value for clamping the clear color. */
2289 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2291 values
[i
] = color
->i
[i
] != 0;
2292 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2294 } else if (desc
->channel
[i
].pure_integer
&&
2295 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2296 /* Use the maximum value for clamping the clear color. */
2297 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2299 values
[i
] = color
->ui
[i
] != 0U;
2300 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2303 values
[i
] = color
->f
[i
] != 0.0F
;
2304 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2308 if (index
== extra_channel
)
2309 extra_value
= values
[i
];
2311 main_value
= values
[i
];
2314 for (int i
= 0; i
< 4; ++i
)
2315 if (values
[i
] != main_value
&&
2316 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2317 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2318 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2321 *clear_words_needed
= false;
2323 *reset_value
|= 0x80808080U
;
2326 *reset_value
|= 0x40404040U
;
2330 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2331 struct r600_texture
*rtex
,
2332 unsigned level
, unsigned clear_value
)
2334 struct pipe_resource
*dcc_buffer
;
2335 uint64_t dcc_offset
;
2337 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2339 if (rtex
->dcc_separate_buffer
) {
2340 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2343 dcc_buffer
= &rtex
->resource
.b
.b
;
2344 dcc_offset
= rtex
->dcc_offset
;
2347 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2349 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2350 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2351 clear_value
, R600_COHERENCY_CB_META
);
2354 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2355 * This allows hitting the MSAA resolve fast path, which requires that both
2356 * src and dst micro tile modes match.
2358 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2359 struct r600_texture
*rtex
)
2361 if (rtex
->resource
.is_shared
||
2362 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2363 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2366 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2367 assert(rtex
->resource
.b
.b
.last_level
== 0);
2369 /* These magic numbers were copied from addrlib. It doesn't use any
2370 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2371 * different bpp and micro tile mode.
2373 if (rscreen
->chip_class
>= CIK
) {
2374 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2375 case 0: /* displayable */
2376 rtex
->surface
.tiling_index
[0] = 10;
2379 rtex
->surface
.tiling_index
[0] = 14;
2381 case 3: /* rotated */
2382 rtex
->surface
.tiling_index
[0] = 28;
2384 default: /* depth, thick */
2385 assert(!"unexpected micro mode");
2389 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2390 case 0: /* displayable */
2391 switch (rtex
->surface
.bpe
) {
2393 rtex
->surface
.tiling_index
[0] = 10;
2396 rtex
->surface
.tiling_index
[0] = 11;
2399 rtex
->surface
.tiling_index
[0] = 12;
2404 switch (rtex
->surface
.bpe
) {
2406 rtex
->surface
.tiling_index
[0] = 14;
2409 rtex
->surface
.tiling_index
[0] = 15;
2412 rtex
->surface
.tiling_index
[0] = 16;
2414 default: /* 8, 16 */
2415 rtex
->surface
.tiling_index
[0] = 17;
2419 default: /* depth, thick */
2420 assert(!"unexpected micro mode");
2425 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2427 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2428 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2431 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2432 struct pipe_framebuffer_state
*fb
,
2433 struct r600_atom
*fb_state
,
2434 unsigned *buffers
, unsigned *dirty_cbufs
,
2435 const union pipe_color_union
*color
)
2439 /* This function is broken in BE, so just disable this path for now */
2440 #ifdef PIPE_ARCH_BIG_ENDIAN
2444 if (rctx
->render_cond
)
2447 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2448 struct r600_texture
*tex
;
2449 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2454 /* if this colorbuffer is not being cleared */
2455 if (!(*buffers
& clear_bit
))
2458 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2460 /* the clear is allowed if all layers are bound */
2461 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2462 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2466 /* cannot clear mipmapped textures */
2467 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2471 /* only supported on tiled surfaces */
2472 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2476 /* shared textures can't use fast clear without an explicit flush,
2477 * because there is no way to communicate the clear color among
2480 if (tex
->resource
.is_shared
&&
2481 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2484 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2485 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2486 rctx
->chip_class
>= CIK
&&
2487 rctx
->screen
->info
.drm_major
== 2 &&
2488 rctx
->screen
->info
.drm_minor
< 38) {
2492 /* Fast clear is the most appropriate place to enable DCC for
2493 * displayable surfaces.
2495 if (rctx
->chip_class
>= VI
&&
2496 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2497 vi_separate_dcc_try_enable(rctx
, tex
);
2499 /* Stoney can't do a CMASK-based clear, so all clears are
2500 * considered to be hypothetically slow clears, which
2501 * is weighed when determining to enable separate DCC.
2503 if (tex
->dcc_gather_statistics
&&
2504 rctx
->family
== CHIP_STONEY
)
2505 tex
->num_slow_clears
++;
2508 /* Try to clear DCC first, otherwise try CMASK. */
2509 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2510 uint32_t reset_value
;
2511 bool clear_words_needed
;
2513 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2516 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2517 color
, &reset_value
,
2518 &clear_words_needed
))
2521 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2523 if (clear_words_needed
)
2524 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2525 tex
->separate_dcc_dirty
= true;
2527 /* 128-bit formats are unusupported */
2528 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2532 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2533 if (rctx
->family
== CHIP_STONEY
)
2536 /* ensure CMASK is enabled */
2537 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2538 if (tex
->cmask
.size
== 0) {
2542 /* Do the fast clear. */
2543 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2544 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2545 R600_COHERENCY_CB_META
);
2547 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2550 /* We can change the micro tile mode before a full clear. */
2551 if (rctx
->screen
->chip_class
>= SI
)
2552 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2554 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2557 *dirty_cbufs
|= 1 << i
;
2558 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2559 *buffers
&= ~clear_bit
;
2563 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2565 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2566 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2569 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2571 rctx
->b
.create_surface
= r600_create_surface
;
2572 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2573 rctx
->b
.clear_texture
= r600_clear_texture
;