2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if (vi_dcc_enabled(rsrc
, src_level
) ||
76 vi_dcc_enabled(rdst
, dst_level
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
181 struct r600_texture
*rtex
, unsigned level
,
182 const struct pipe_box
*box
,
184 unsigned *layer_stride
)
186 if (rscreen
->chip_class
>= GFX9
) {
187 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
188 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
193 /* Each texture is an array of slices. Each slice is an array
194 * of mipmap levels. */
195 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
196 ((rtex
->surface
.u
.gfx9
.surf_ymip_offset
[level
] +
197 box
->y
/ rtex
->surface
.blk_h
) *
198 rtex
->surface
.u
.gfx9
.surf_pitch
+
199 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
201 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
203 *layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
206 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
208 /* Each texture is an array of mipmap levels. Each level is
209 * an array of slices. */
210 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
211 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
212 (box
->y
/ rtex
->surface
.blk_h
*
213 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
214 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
218 static int r600_init_surface(struct r600_common_screen
*rscreen
,
219 struct radeon_surf
*surface
,
220 const struct pipe_resource
*ptex
,
221 enum radeon_surf_mode array_mode
,
222 unsigned pitch_in_bytes_override
,
226 bool is_flushed_depth
,
227 bool tc_compatible_htile
)
229 const struct util_format_description
*desc
=
230 util_format_description(ptex
->format
);
231 bool is_depth
, is_stencil
;
233 unsigned i
, bpe
, flags
= 0;
235 is_depth
= util_format_has_depth(desc
);
236 is_stencil
= util_format_has_stencil(desc
);
238 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
239 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
240 bpe
= 4; /* stencil is allocated separately on evergreen */
242 bpe
= util_format_get_blocksize(ptex
->format
);
243 /* align byte per element on dword */
249 if (!is_flushed_depth
&& is_depth
) {
250 flags
|= RADEON_SURF_ZBUFFER
;
252 if (tc_compatible_htile
&&
253 (rscreen
->chip_class
>= GFX9
||
254 array_mode
== RADEON_SURF_MODE_2D
)) {
255 /* TC-compatible HTILE only supports Z32_FLOAT.
256 * GFX9 also supports Z16_UNORM.
257 * On VI, promote Z16 to Z32. DB->CB copies will convert
258 * the format for transfers.
260 if (rscreen
->chip_class
== VI
)
263 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
267 flags
|= RADEON_SURF_SBUFFER
;
270 if (rscreen
->chip_class
>= VI
&&
271 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
272 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
273 flags
|= RADEON_SURF_DISABLE_DCC
;
275 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
276 /* This should catch bugs in gallium users setting incorrect flags. */
277 assert(ptex
->nr_samples
<= 1 &&
278 ptex
->array_size
== 1 &&
280 ptex
->last_level
== 0 &&
281 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
283 flags
|= RADEON_SURF_SCANOUT
;
287 flags
|= RADEON_SURF_IMPORTED
;
288 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
289 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
291 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
292 array_mode
, surface
);
297 if (rscreen
->chip_class
>= GFX9
) {
298 assert(!pitch_in_bytes_override
||
299 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
300 surface
->u
.gfx9
.surf_offset
= offset
;
302 if (pitch_in_bytes_override
&&
303 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
304 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
307 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
308 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
*
309 surface
->u
.legacy
.level
[0].nblk_y
;
313 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
314 surface
->u
.legacy
.level
[i
].offset
+= offset
;
320 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
321 struct r600_texture
*rtex
,
322 struct radeon_bo_metadata
*metadata
)
324 struct radeon_surf
*surface
= &rtex
->surface
;
326 memset(metadata
, 0, sizeof(*metadata
));
328 if (rscreen
->chip_class
>= GFX9
) {
329 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
331 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
332 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
333 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
334 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
335 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
336 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
337 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
338 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
339 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
340 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
341 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
342 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
346 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
347 struct r600_texture
*rtex
)
349 struct r600_common_screen
*rscreen
= rctx
->screen
;
350 struct pipe_context
*ctx
= &rctx
->b
;
352 if (ctx
== rscreen
->aux_context
)
353 mtx_lock(&rscreen
->aux_context_lock
);
355 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
356 ctx
->flush(ctx
, NULL
, 0);
358 if (ctx
== rscreen
->aux_context
)
359 mtx_unlock(&rscreen
->aux_context_lock
);
362 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
363 struct r600_texture
*rtex
)
365 if (!rtex
->cmask
.size
)
368 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
371 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
372 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
373 rtex
->dirty_level_mask
= 0;
375 if (rscreen
->chip_class
>= SI
)
376 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
378 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
380 if (rtex
->cmask_buffer
!= &rtex
->resource
)
381 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
383 /* Notify all contexts about the change. */
384 p_atomic_inc(&rscreen
->dirty_tex_counter
);
385 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
388 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
390 /* We can't disable DCC if it can be written by another process. */
391 return rtex
->dcc_offset
&&
392 (!rtex
->resource
.is_shared
||
393 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
396 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
397 struct r600_texture
*rtex
)
399 if (!r600_can_disable_dcc(rtex
))
402 assert(rtex
->dcc_separate_buffer
== NULL
);
405 rtex
->dcc_offset
= 0;
407 /* Notify all contexts about the change. */
408 p_atomic_inc(&rscreen
->dirty_tex_counter
);
413 * Disable DCC for the texture. (first decompress, then discard metadata).
415 * There is unresolved multi-context synchronization issue between
416 * screen::aux_context and the current context. If applications do this with
417 * multiple contexts, it's already undefined behavior for them and we don't
418 * have to worry about that. The scenario is:
420 * If context 1 disables DCC and context 2 has queued commands that write
421 * to the texture via CB with DCC enabled, and the order of operations is
423 * context 2 queues draw calls rendering to the texture, but doesn't flush
424 * context 1 disables DCC and flushes
425 * context 1 & 2 reset descriptors and FB state
426 * context 2 flushes (new compressed tiles written by the draw calls)
427 * context 1 & 2 read garbage, because DCC is disabled, yet there are
430 * \param rctx the current context if you have one, or rscreen->aux_context
433 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
434 struct r600_texture
*rtex
)
436 struct r600_common_screen
*rscreen
= rctx
->screen
;
438 if (!r600_can_disable_dcc(rtex
))
441 if (&rctx
->b
== rscreen
->aux_context
)
442 mtx_lock(&rscreen
->aux_context_lock
);
444 /* Decompress DCC. */
445 rctx
->decompress_dcc(&rctx
->b
, rtex
);
446 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
448 if (&rctx
->b
== rscreen
->aux_context
)
449 mtx_unlock(&rscreen
->aux_context_lock
);
451 return r600_texture_discard_dcc(rscreen
, rtex
);
454 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
455 struct r600_texture
*rtex
,
456 bool invalidate_storage
)
458 struct pipe_screen
*screen
= rctx
->b
.screen
;
459 struct r600_texture
*new_tex
;
460 struct pipe_resource templ
= rtex
->resource
.b
.b
;
463 templ
.bind
|= PIPE_BIND_LINEAR
;
465 /* r600g doesn't react to dirty_tex_descriptor_counter */
466 if (rctx
->chip_class
< SI
)
469 if (rtex
->resource
.is_shared
||
470 rtex
->surface
.is_linear
)
473 /* This fails with MSAA, depth, and compressed textures. */
474 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
475 RADEON_SURF_MODE_LINEAR_ALIGNED
)
478 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
482 /* Copy the pixels to the new texture. */
483 if (!invalidate_storage
) {
484 for (i
= 0; i
<= templ
.last_level
; i
++) {
488 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
489 util_max_layer(&templ
, i
) + 1, &box
);
491 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
492 &rtex
->resource
.b
.b
, i
, &box
);
496 r600_texture_discard_cmask(rctx
->screen
, rtex
);
497 r600_texture_discard_dcc(rctx
->screen
, rtex
);
499 /* Replace the structure fields of rtex. */
500 rtex
->resource
.b
.b
.bind
= templ
.bind
;
501 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
502 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
503 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
504 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
505 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
506 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
507 rtex
->resource
.domains
= new_tex
->resource
.domains
;
508 rtex
->resource
.flags
= new_tex
->resource
.flags
;
509 rtex
->size
= new_tex
->size
;
510 rtex
->surface
= new_tex
->surface
;
511 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
512 rtex
->cb_color_info
= new_tex
->cb_color_info
;
513 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
515 assert(!rtex
->htile_buffer
);
516 assert(!rtex
->cmask
.size
);
517 assert(!rtex
->fmask
.size
);
518 assert(!rtex
->dcc_offset
);
519 assert(!rtex
->is_depth
);
521 r600_texture_reference(&new_tex
, NULL
);
523 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
526 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
527 struct pipe_context
*ctx
,
528 struct pipe_resource
*resource
,
529 struct winsys_handle
*whandle
,
532 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
533 struct r600_common_context
*rctx
= (struct r600_common_context
*)
534 (ctx
? ctx
: rscreen
->aux_context
);
535 struct r600_resource
*res
= (struct r600_resource
*)resource
;
536 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
537 struct radeon_bo_metadata metadata
;
538 bool update_metadata
= false;
539 unsigned stride
, offset
, slice_size
;
541 /* This is not supported now, but it might be required for OpenCL
542 * interop in the future.
544 if (resource
->target
!= PIPE_BUFFER
&&
545 (resource
->nr_samples
> 1 || rtex
->is_depth
))
548 if (resource
->target
!= PIPE_BUFFER
) {
549 /* Since shader image stores don't support DCC on VI,
550 * disable it for external clients that want write
553 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
554 if (r600_texture_disable_dcc(rctx
, rtex
))
555 update_metadata
= true;
558 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
559 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
560 /* Eliminate fast clear (both CMASK and DCC) */
561 r600_eliminate_fast_color_clear(rctx
, rtex
);
563 /* Disable CMASK if flush_resource isn't going
566 if (rtex
->cmask
.size
)
567 r600_texture_discard_cmask(rscreen
, rtex
);
571 if (!res
->is_shared
|| update_metadata
) {
572 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
573 if (rscreen
->query_opaque_metadata
)
574 rscreen
->query_opaque_metadata(rscreen
, rtex
,
577 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
581 if (res
->is_shared
) {
582 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
585 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
586 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
587 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
589 res
->is_shared
= true;
590 res
->external_usage
= usage
;
593 if (rscreen
->chip_class
>= GFX9
) {
594 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
595 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
597 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
599 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
600 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
602 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
604 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
605 slice_size
, whandle
);
608 static void r600_texture_destroy(struct pipe_screen
*screen
,
609 struct pipe_resource
*ptex
)
611 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
612 struct r600_resource
*resource
= &rtex
->resource
;
614 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
616 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
617 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
618 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
620 pb_reference(&resource
->buf
, NULL
);
621 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
622 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
626 static const struct u_resource_vtbl r600_texture_vtbl
;
628 /* The number of samples can be specified independently of the texture. */
629 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
630 struct r600_texture
*rtex
,
632 struct r600_fmask_info
*out
)
634 /* FMASK is allocated like an ordinary texture. */
635 struct pipe_resource templ
= rtex
->resource
.b
.b
;
636 struct radeon_surf fmask
= {};
639 memset(out
, 0, sizeof(*out
));
641 if (rscreen
->chip_class
>= GFX9
) {
642 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
643 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
647 templ
.nr_samples
= 1;
648 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
650 if (rscreen
->chip_class
<= CAYMAN
) {
651 /* Use the same parameters and tile mode. */
652 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
653 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
654 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
655 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
658 fmask
.u
.legacy
.bankh
= 4;
661 switch (nr_samples
) {
670 R600_ERR("Invalid sample count for FMASK allocation.\n");
674 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
675 * This can be fixed by writing a separate FMASK allocator specifically
676 * for R600-R700 asics. */
677 if (rscreen
->chip_class
<= R700
) {
681 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
682 RADEON_SURF_MODE_2D
, &fmask
)) {
683 R600_ERR("Got error in surface_init while allocating FMASK.\n");
687 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
689 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
690 if (out
->slice_tile_max
)
691 out
->slice_tile_max
-= 1;
693 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
694 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
695 out
->bank_height
= fmask
.u
.legacy
.bankh
;
696 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
697 out
->size
= fmask
.surf_size
;
700 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
701 struct r600_texture
*rtex
)
703 r600_texture_get_fmask_info(rscreen
, rtex
,
704 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
706 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
707 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
710 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
711 struct r600_texture
*rtex
,
712 struct r600_cmask_info
*out
)
714 unsigned cmask_tile_width
= 8;
715 unsigned cmask_tile_height
= 8;
716 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
717 unsigned element_bits
= 4;
718 unsigned cmask_cache_bits
= 1024;
719 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
720 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
722 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
723 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
724 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
725 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
726 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
728 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
729 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
731 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
732 unsigned slice_bytes
=
733 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
735 assert(macro_tile_width
% 128 == 0);
736 assert(macro_tile_height
% 128 == 0);
738 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
739 out
->alignment
= MAX2(256, base_align
);
740 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
741 align(slice_bytes
, base_align
);
744 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
745 struct r600_texture
*rtex
,
746 struct r600_cmask_info
*out
)
748 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
749 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
750 unsigned cl_width
, cl_height
;
752 if (rscreen
->chip_class
>= GFX9
) {
753 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
754 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
771 case 16: /* Hawaii */
780 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
782 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
783 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
784 unsigned slice_elements
= (width
* height
) / (8*8);
786 /* Each element of CMASK is a nibble. */
787 unsigned slice_bytes
= slice_elements
/ 2;
789 out
->slice_tile_max
= (width
* height
) / (128*128);
790 if (out
->slice_tile_max
)
791 out
->slice_tile_max
-= 1;
793 out
->alignment
= MAX2(256, base_align
);
794 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
795 align(slice_bytes
, base_align
);
798 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
799 struct r600_texture
*rtex
)
801 if (rscreen
->chip_class
>= SI
) {
802 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
804 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
807 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
808 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
810 if (rscreen
->chip_class
>= SI
)
811 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
813 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
816 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
817 struct r600_texture
*rtex
)
819 if (rtex
->cmask_buffer
)
822 assert(rtex
->cmask
.size
== 0);
824 if (rscreen
->chip_class
>= SI
) {
825 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
827 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
830 rtex
->cmask_buffer
= (struct r600_resource
*)
831 r600_aligned_buffer_create(&rscreen
->b
,
832 R600_RESOURCE_FLAG_UNMAPPABLE
,
835 rtex
->cmask
.alignment
);
836 if (rtex
->cmask_buffer
== NULL
) {
837 rtex
->cmask
.size
= 0;
841 /* update colorbuffer state bits */
842 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
844 if (rscreen
->chip_class
>= SI
)
845 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
847 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
849 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
852 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
853 struct r600_texture
*rtex
)
855 unsigned cl_width
, cl_height
, width
, height
;
856 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
857 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
859 assert(rscreen
->chip_class
<= VI
);
861 rtex
->surface
.htile_size
= 0;
863 if (rscreen
->chip_class
<= EVERGREEN
&&
864 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
867 /* HW bug on R6xx. */
868 if (rscreen
->chip_class
== R600
&&
869 (rtex
->resource
.b
.b
.width0
> 7680 ||
870 rtex
->resource
.b
.b
.height0
> 7680))
873 /* HTILE is broken with 1D tiling on old kernels and CIK. */
874 if (rscreen
->chip_class
>= CIK
&&
875 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
876 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
879 /* Overalign HTILE on P2 configs to work around GPU hangs in
880 * piglit/depthstencil-render-miplevels 585.
882 * This has been confirmed to help Kabini & Stoney, where the hangs
883 * are always reproducible. I think I have seen the test hang
884 * on Carrizo too, though it was very rare there.
886 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
915 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
916 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
918 slice_elements
= (width
* height
) / (8 * 8);
919 slice_bytes
= slice_elements
* 4;
921 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
922 base_align
= num_pipes
* pipe_interleave_bytes
;
924 rtex
->surface
.htile_alignment
= base_align
;
925 rtex
->surface
.htile_size
=
926 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
927 align(slice_bytes
, base_align
);
930 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
931 struct r600_texture
*rtex
)
933 uint32_t clear_value
;
935 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
) {
936 clear_value
= 0x0000030F;
938 r600_texture_get_htile_size(rscreen
, rtex
);
942 if (!rtex
->surface
.htile_size
)
945 rtex
->htile_buffer
= (struct r600_resource
*)
946 r600_aligned_buffer_create(&rscreen
->b
,
947 R600_RESOURCE_FLAG_UNMAPPABLE
,
949 rtex
->surface
.htile_size
,
950 rtex
->surface
.htile_alignment
);
951 if (rtex
->htile_buffer
== NULL
) {
952 /* this is not a fatal error as we can still keep rendering
953 * without htile buffer */
954 R600_ERR("Failed to create buffer object for htile buffer.\n");
956 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
957 0, rtex
->surface
.htile_size
,
962 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
963 struct r600_texture
*rtex
, FILE *f
)
967 /* Common parameters. */
968 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
969 "blk_h=%u, array_size=%u, last_level=%u, "
970 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
971 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
972 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
974 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
975 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
976 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
978 if (rscreen
->chip_class
>= GFX9
) {
979 fprintf(f
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
980 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
981 rtex
->surface
.surf_size
,
982 rtex
->surface
.u
.gfx9
.surf_slice_size
,
983 rtex
->surface
.surf_alignment
,
984 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
985 rtex
->surface
.u
.gfx9
.surf
.epitch
,
986 rtex
->surface
.u
.gfx9
.surf_pitch
);
988 if (rtex
->fmask
.size
) {
989 fprintf(f
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
990 "alignment=%u, swmode=%u, epitch=%u\n",
992 rtex
->surface
.u
.gfx9
.fmask_size
,
993 rtex
->surface
.u
.gfx9
.fmask_alignment
,
994 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
995 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
998 if (rtex
->cmask
.size
) {
999 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1000 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1002 rtex
->surface
.u
.gfx9
.cmask_size
,
1003 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1004 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1005 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1008 if (rtex
->htile_buffer
) {
1009 fprintf(f
, " HTile: size=%u, alignment=%u, "
1010 "rb_aligned=%u, pipe_aligned=%u\n",
1011 rtex
->htile_buffer
->b
.b
.width0
,
1012 rtex
->htile_buffer
->buf
->alignment
,
1013 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1014 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1017 if (rtex
->dcc_offset
) {
1018 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
1019 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1020 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1021 rtex
->surface
.dcc_alignment
,
1022 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1023 rtex
->surface
.num_dcc_levels
);
1026 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1027 fprintf(f
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1028 rtex
->surface
.u
.gfx9
.stencil_offset
,
1029 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1030 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1035 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1036 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1037 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1038 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1039 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1040 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1042 if (rtex
->fmask
.size
)
1043 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1044 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1045 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1046 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1047 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1049 if (rtex
->cmask
.size
)
1050 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1051 "slice_tile_max=%u\n",
1052 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1053 rtex
->cmask
.slice_tile_max
);
1055 if (rtex
->htile_buffer
)
1056 fprintf(f
, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
1057 rtex
->htile_buffer
->b
.b
.width0
,
1058 rtex
->htile_buffer
->buf
->alignment
,
1059 rtex
->tc_compatible_htile
);
1061 if (rtex
->dcc_offset
) {
1062 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1063 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1064 rtex
->surface
.dcc_alignment
);
1065 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1066 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1067 "fast_clear_size=%"PRIu64
"\n",
1068 i
, i
< rtex
->surface
.num_dcc_levels
,
1069 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1070 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1073 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1074 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1075 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1076 "mode=%u, tiling_index = %u\n",
1077 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1078 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1079 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1080 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1081 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1082 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1083 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1084 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1085 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1087 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1088 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1089 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1090 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1091 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1092 "slice_size=%"PRIu64
", npix_x=%u, "
1093 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1094 "mode=%u, tiling_index = %u\n",
1095 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1096 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1097 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1098 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1099 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1100 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1101 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1102 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1103 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1108 /* Common processing for r600_texture_create and r600_texture_from_handle */
1109 static struct r600_texture
*
1110 r600_texture_create_object(struct pipe_screen
*screen
,
1111 const struct pipe_resource
*base
,
1112 struct pb_buffer
*buf
,
1113 struct radeon_surf
*surface
)
1115 struct r600_texture
*rtex
;
1116 struct r600_resource
*resource
;
1117 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1119 rtex
= CALLOC_STRUCT(r600_texture
);
1123 resource
= &rtex
->resource
;
1124 resource
->b
.b
= *base
;
1125 resource
->b
.b
.next
= NULL
;
1126 resource
->b
.vtbl
= &r600_texture_vtbl
;
1127 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1128 resource
->b
.b
.screen
= screen
;
1130 /* don't include stencil-only formats which we don't support for rendering */
1131 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1133 rtex
->surface
= *surface
;
1134 rtex
->size
= rtex
->surface
.surf_size
;
1136 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1137 (rtex
->surface
.flags
&
1138 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1140 /* TC-compatible HTILE:
1141 * - VI only supports Z32_FLOAT.
1142 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1143 if (rtex
->tc_compatible_htile
) {
1144 if (rscreen
->chip_class
>= GFX9
&&
1145 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1146 rtex
->db_render_format
= base
->format
;
1148 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1150 rtex
->db_render_format
= base
->format
;
1153 /* Tiled depth textures utilize the non-displayable tile order.
1154 * This must be done after r600_setup_surface.
1155 * Applies to R600-Cayman. */
1156 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1157 /* Applies to GCN. */
1158 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1160 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1161 * between frames, so the only thing that can enable separate DCC
1162 * with DRI2 is multiple slow clears within a frame.
1164 rtex
->ps_draw_ratio
= 0;
1166 if (rtex
->is_depth
) {
1167 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1168 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1169 rscreen
->chip_class
>= EVERGREEN
) {
1170 if (rscreen
->chip_class
>= GFX9
) {
1171 rtex
->can_sample_z
= true;
1172 rtex
->can_sample_s
= true;
1174 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1175 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1178 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1179 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1180 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1181 rtex
->can_sample_z
= true;
1184 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1185 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1186 rtex
->db_compatible
= true;
1188 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1189 r600_texture_allocate_htile(rscreen
, rtex
);
1192 if (base
->nr_samples
> 1) {
1194 r600_texture_allocate_fmask(rscreen
, rtex
);
1195 r600_texture_allocate_cmask(rscreen
, rtex
);
1196 rtex
->cmask_buffer
= &rtex
->resource
;
1198 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1204 /* Shared textures must always set up DCC here.
1205 * If it's not present, it will be disabled by
1206 * apply_opaque_metadata later.
1208 if (rtex
->surface
.dcc_size
&&
1209 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1210 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1211 /* Reserve space for the DCC buffer. */
1212 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1213 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1217 /* Now create the backing buffer. */
1219 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1220 rtex
->surface
.surf_alignment
);
1222 resource
->flags
|= RADEON_FLAG_HANDLE
;
1224 if (!r600_alloc_resource(rscreen
, resource
)) {
1229 resource
->buf
= buf
;
1230 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1231 resource
->bo_size
= buf
->size
;
1232 resource
->bo_alignment
= buf
->alignment
;
1233 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1234 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1235 resource
->vram_usage
= buf
->size
;
1236 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1237 resource
->gart_usage
= buf
->size
;
1240 if (rtex
->cmask
.size
) {
1241 /* Initialize the cmask to 0xCC (= compressed state). */
1242 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1243 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1247 /* Initialize DCC only if the texture is not being imported. */
1248 if (!buf
&& rtex
->dcc_offset
) {
1249 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1251 rtex
->surface
.dcc_size
,
1255 /* Initialize the CMASK base register value. */
1256 rtex
->cmask
.base_address_reg
=
1257 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1259 if (rscreen
->debug_flags
& DBG_VM
) {
1260 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1261 rtex
->resource
.gpu_address
,
1262 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1263 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1264 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1267 if (rscreen
->debug_flags
& DBG_TEX
) {
1269 r600_print_texture_info(rscreen
, rtex
, stdout
);
1276 static enum radeon_surf_mode
1277 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1278 const struct pipe_resource
*templ
)
1280 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1281 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1283 /* MSAA resources must be 2D tiled. */
1284 if (templ
->nr_samples
> 1)
1285 return RADEON_SURF_MODE_2D
;
1287 /* Transfer resources should be linear. */
1288 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1289 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1291 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1292 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1293 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1294 (templ
->target
== PIPE_TEXTURE_2D
||
1295 templ
->target
== PIPE_TEXTURE_3D
))
1296 force_tiling
= true;
1298 /* Handle common candidates for the linear mode.
1299 * Compressed textures and DB surfaces must always be tiled.
1301 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1302 (!util_format_is_depth_or_stencil(templ
->format
) ||
1303 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1304 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1305 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1307 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1308 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1309 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1311 /* Cursors are linear on SI.
1312 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1313 if (rscreen
->chip_class
>= SI
&&
1314 (templ
->bind
& PIPE_BIND_CURSOR
))
1315 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1317 if (templ
->bind
& PIPE_BIND_LINEAR
)
1318 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1320 /* Textures with a very small height are recommended to be linear. */
1321 if (templ
->target
== PIPE_TEXTURE_1D
||
1322 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1323 /* Only very thin and long 2D textures should benefit from
1324 * linear_aligned. */
1325 (templ
->width0
> 8 && templ
->height0
<= 2))
1326 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1328 /* Textures likely to be mapped often. */
1329 if (templ
->usage
== PIPE_USAGE_STAGING
||
1330 templ
->usage
== PIPE_USAGE_STREAM
)
1331 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1334 /* Make small textures 1D tiled. */
1335 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1336 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1337 return RADEON_SURF_MODE_1D
;
1339 /* The allocator will switch to 1D if needed. */
1340 return RADEON_SURF_MODE_2D
;
1343 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1344 const struct pipe_resource
*templ
)
1346 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1347 struct radeon_surf surface
= {0};
1348 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1349 bool tc_compatible_htile
=
1350 rscreen
->chip_class
>= VI
&&
1351 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1352 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1353 !is_flushed_depth
&&
1354 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1355 util_format_is_depth_or_stencil(templ
->format
);
1359 r
= r600_init_surface(rscreen
, &surface
, templ
,
1360 r600_choose_tiling(rscreen
, templ
), 0, 0,
1361 false, false, is_flushed_depth
,
1362 tc_compatible_htile
);
1367 return (struct pipe_resource
*)
1368 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1371 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1372 const struct pipe_resource
*templ
,
1373 struct winsys_handle
*whandle
,
1376 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1377 struct pb_buffer
*buf
= NULL
;
1378 unsigned stride
= 0, offset
= 0;
1379 unsigned array_mode
;
1380 struct radeon_surf surface
;
1382 struct radeon_bo_metadata metadata
= {};
1383 struct r600_texture
*rtex
;
1386 /* Support only 2D textures without mipmaps */
1387 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1388 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1391 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1395 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1397 if (rscreen
->chip_class
>= GFX9
) {
1398 if (metadata
.u
.gfx9
.swizzle_mode
> 0)
1399 array_mode
= RADEON_SURF_MODE_2D
;
1401 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1403 is_scanout
= metadata
.u
.gfx9
.swizzle_mode
== 0 ||
1404 metadata
.u
.gfx9
.swizzle_mode
% 4 == 2;
1406 surface
.u
.legacy
.pipe_config
= metadata
.u
.legacy
.pipe_config
;
1407 surface
.u
.legacy
.bankw
= metadata
.u
.legacy
.bankw
;
1408 surface
.u
.legacy
.bankh
= metadata
.u
.legacy
.bankh
;
1409 surface
.u
.legacy
.tile_split
= metadata
.u
.legacy
.tile_split
;
1410 surface
.u
.legacy
.mtilea
= metadata
.u
.legacy
.mtilea
;
1411 surface
.u
.legacy
.num_banks
= metadata
.u
.legacy
.num_banks
;
1413 if (metadata
.u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1414 array_mode
= RADEON_SURF_MODE_2D
;
1415 else if (metadata
.u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1416 array_mode
= RADEON_SURF_MODE_1D
;
1418 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1420 is_scanout
= metadata
.u
.legacy
.scanout
;
1423 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1424 offset
, true, is_scanout
, false, false);
1429 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1433 rtex
->resource
.is_shared
= true;
1434 rtex
->resource
.external_usage
= usage
;
1436 if (rscreen
->apply_opaque_metadata
)
1437 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1439 /* Validate that addrlib arrived at the same surface parameters. */
1440 if (rscreen
->chip_class
>= GFX9
) {
1441 assert(metadata
.u
.gfx9
.swizzle_mode
== surface
.u
.gfx9
.surf
.swizzle_mode
);
1444 return &rtex
->resource
.b
.b
;
1447 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1448 struct pipe_resource
*texture
,
1449 struct r600_texture
**staging
)
1451 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1452 struct pipe_resource resource
;
1453 struct r600_texture
**flushed_depth_texture
= staging
?
1454 staging
: &rtex
->flushed_depth_texture
;
1455 enum pipe_format pipe_format
= texture
->format
;
1458 if (rtex
->flushed_depth_texture
)
1459 return true; /* it's ready */
1461 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1462 switch (pipe_format
) {
1463 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1464 /* Save memory by not allocating the S plane. */
1465 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1467 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1468 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1469 /* Save memory bandwidth by not copying the
1470 * stencil part during flush.
1472 * This potentially increases memory bandwidth
1473 * if an application uses both Z and S texturing
1474 * simultaneously (a flushed Z24S8 texture
1475 * would be stored compactly), but how often
1476 * does that really happen?
1478 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1482 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1483 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1485 /* DB->CB copies to an 8bpp surface don't work. */
1486 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1490 memset(&resource
, 0, sizeof(resource
));
1491 resource
.target
= texture
->target
;
1492 resource
.format
= pipe_format
;
1493 resource
.width0
= texture
->width0
;
1494 resource
.height0
= texture
->height0
;
1495 resource
.depth0
= texture
->depth0
;
1496 resource
.array_size
= texture
->array_size
;
1497 resource
.last_level
= texture
->last_level
;
1498 resource
.nr_samples
= texture
->nr_samples
;
1499 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1500 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1501 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1504 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1506 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1507 if (*flushed_depth_texture
== NULL
) {
1508 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1512 (*flushed_depth_texture
)->non_disp_tiling
= false;
1517 * Initialize the pipe_resource descriptor to be of the same size as the box,
1518 * which is supposed to hold a subregion of the texture "orig" at the given
1521 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1522 struct pipe_resource
*orig
,
1523 const struct pipe_box
*box
,
1524 unsigned level
, unsigned flags
)
1526 memset(res
, 0, sizeof(*res
));
1527 res
->format
= orig
->format
;
1528 res
->width0
= box
->width
;
1529 res
->height0
= box
->height
;
1531 res
->array_size
= 1;
1532 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1535 /* We must set the correct texture target and dimensions for a 3D box. */
1536 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1537 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1538 res
->array_size
= box
->depth
;
1540 res
->target
= PIPE_TEXTURE_2D
;
1544 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1545 struct r600_texture
*rtex
,
1546 unsigned transfer_usage
,
1547 const struct pipe_box
*box
)
1549 /* r600g doesn't react to dirty_tex_descriptor_counter */
1550 return rscreen
->chip_class
>= SI
&&
1551 !rtex
->resource
.is_shared
&&
1552 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1553 rtex
->resource
.b
.b
.last_level
== 0 &&
1554 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1555 box
->x
, box
->y
, box
->z
,
1556 box
->width
, box
->height
,
1560 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1561 struct r600_texture
*rtex
)
1563 struct r600_common_screen
*rscreen
= rctx
->screen
;
1565 /* There is no point in discarding depth and tiled buffers. */
1566 assert(!rtex
->is_depth
);
1567 assert(rtex
->surface
.is_linear
);
1569 /* Reallocate the buffer in the same pipe_resource. */
1570 r600_alloc_resource(rscreen
, &rtex
->resource
);
1572 /* Initialize the CMASK base address (needed even without CMASK). */
1573 rtex
->cmask
.base_address_reg
=
1574 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1576 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1578 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1581 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1582 struct pipe_resource
*texture
,
1585 const struct pipe_box
*box
,
1586 struct pipe_transfer
**ptransfer
)
1588 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1589 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1590 struct r600_transfer
*trans
;
1591 struct r600_resource
*buf
;
1592 unsigned offset
= 0;
1594 bool use_staging_texture
= false;
1596 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1597 assert(box
->width
&& box
->height
&& box
->depth
);
1599 /* Depth textures use staging unconditionally. */
1600 if (!rtex
->is_depth
) {
1601 /* Degrade the tile mode if we get too many transfers on APUs.
1602 * On dGPUs, the staging texture is always faster.
1603 * Only count uploads that are at least 4x4 pixels large.
1605 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1607 box
->width
>= 4 && box
->height
>= 4 &&
1608 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1609 bool can_invalidate
=
1610 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1613 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1617 /* Tiled textures need to be converted into a linear texture for CPU
1618 * access. The staging texture is always linear and is placed in GART.
1620 * Reading from VRAM or GTT WC is slow, always use the staging
1621 * texture in this case.
1623 * Use the staging texture for uploads if the underlying BO
1626 /* TODO: Linear CPU mipmap addressing is broken on GFX9: */
1627 if (!rtex
->surface
.is_linear
||
1628 (rctx
->chip_class
== GFX9
&& level
))
1629 use_staging_texture
= true;
1630 else if (usage
& PIPE_TRANSFER_READ
)
1631 use_staging_texture
=
1632 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1633 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1634 /* Write & linear only: */
1635 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1636 RADEON_USAGE_READWRITE
) ||
1637 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1638 RADEON_USAGE_READWRITE
)) {
1640 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1642 r600_texture_invalidate_storage(rctx
, rtex
);
1644 use_staging_texture
= true;
1648 trans
= CALLOC_STRUCT(r600_transfer
);
1651 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
1652 trans
->transfer
.level
= level
;
1653 trans
->transfer
.usage
= usage
;
1654 trans
->transfer
.box
= *box
;
1656 if (rtex
->is_depth
) {
1657 struct r600_texture
*staging_depth
;
1659 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1660 /* MSAA depth buffers need to be converted to single sample buffers.
1662 * Mapping MSAA depth buffers can occur if ReadPixels is called
1663 * with a multisample GLX visual.
1665 * First downsample the depth buffer to a temporary texture,
1666 * then decompress the temporary one to staging.
1668 * Only the region being mapped is transfered.
1670 struct pipe_resource resource
;
1672 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1674 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1675 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1680 if (usage
& PIPE_TRANSFER_READ
) {
1681 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1683 R600_ERR("failed to create a temporary depth texture\n");
1688 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1689 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1690 0, 0, 0, box
->depth
, 0, 0);
1691 pipe_resource_reference(&temp
, NULL
);
1694 /* Just get the strides. */
1695 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1696 &trans
->transfer
.stride
,
1697 &trans
->transfer
.layer_stride
);
1699 /* XXX: only readback the rectangle which is being mapped? */
1700 /* XXX: when discard is true, no need to read back from depth texture */
1701 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1702 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1707 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1709 box
->z
, box
->z
+ box
->depth
- 1,
1712 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1714 &trans
->transfer
.stride
,
1715 &trans
->transfer
.layer_stride
);
1718 trans
->staging
= (struct r600_resource
*)staging_depth
;
1719 buf
= trans
->staging
;
1720 } else if (use_staging_texture
) {
1721 struct pipe_resource resource
;
1722 struct r600_texture
*staging
;
1724 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1725 R600_RESOURCE_FLAG_TRANSFER
);
1726 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1727 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1729 /* Create the temporary texture. */
1730 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1732 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1736 trans
->staging
= &staging
->resource
;
1738 /* Just get the strides. */
1739 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1740 &trans
->transfer
.stride
,
1741 &trans
->transfer
.layer_stride
);
1743 if (usage
& PIPE_TRANSFER_READ
)
1744 r600_copy_to_staging_texture(ctx
, trans
);
1746 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1748 buf
= trans
->staging
;
1750 /* the resource is mapped directly */
1751 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1752 &trans
->transfer
.stride
,
1753 &trans
->transfer
.layer_stride
);
1754 buf
= &rtex
->resource
;
1757 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1758 r600_resource_reference(&trans
->staging
, NULL
);
1763 *ptransfer
= &trans
->transfer
;
1764 return map
+ offset
;
1767 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1768 struct pipe_transfer
* transfer
)
1770 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1771 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1772 struct pipe_resource
*texture
= transfer
->resource
;
1773 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1775 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1776 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1777 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1778 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1779 &rtransfer
->staging
->b
.b
, transfer
->level
,
1782 r600_copy_from_staging_texture(ctx
, rtransfer
);
1786 if (rtransfer
->staging
) {
1787 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1788 r600_resource_reference(&rtransfer
->staging
, NULL
);
1791 /* Heuristic for {upload, draw, upload, draw, ..}:
1793 * Flush the gfx IB if we've allocated too much texture storage.
1795 * The idea is that we don't want to build IBs that use too much
1796 * memory and put pressure on the kernel memory manager and we also
1797 * want to make temporary and invalidated buffers go idle ASAP to
1798 * decrease the total memory usage or make them reusable. The memory
1799 * usage will be slightly higher than given here because of the buffer
1800 * cache in the winsys.
1802 * The result is that the kernel memory manager is never a bottleneck.
1804 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1805 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1806 rctx
->num_alloc_tex_transfer_bytes
= 0;
1809 pipe_resource_reference(&transfer
->resource
, NULL
);
1813 static const struct u_resource_vtbl r600_texture_vtbl
=
1815 NULL
, /* get_handle */
1816 r600_texture_destroy
, /* resource_destroy */
1817 r600_texture_transfer_map
, /* transfer_map */
1818 u_default_transfer_flush_region
, /* transfer_flush_region */
1819 r600_texture_transfer_unmap
, /* transfer_unmap */
1822 /* DCC channel type categories within which formats can be reinterpreted
1823 * while keeping the same DCC encoding. The swizzle must also match. */
1824 enum dcc_channel_type
{
1825 dcc_channel_float32
,
1828 dcc_channel_float16
,
1831 dcc_channel_uint_10_10_10_2
,
1834 dcc_channel_incompatible
,
1837 /* Return the type of DCC encoding. */
1838 static enum dcc_channel_type
1839 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1843 /* Find the first non-void channel. */
1844 for (i
= 0; i
< desc
->nr_channels
; i
++)
1845 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1847 if (i
== desc
->nr_channels
)
1848 return dcc_channel_incompatible
;
1850 switch (desc
->channel
[i
].size
) {
1852 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1853 return dcc_channel_float32
;
1854 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1855 return dcc_channel_uint32
;
1856 return dcc_channel_sint32
;
1858 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1859 return dcc_channel_float16
;
1860 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1861 return dcc_channel_uint16
;
1862 return dcc_channel_sint16
;
1864 return dcc_channel_uint_10_10_10_2
;
1866 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1867 return dcc_channel_uint8
;
1868 return dcc_channel_sint8
;
1870 return dcc_channel_incompatible
;
1874 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1875 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1876 enum pipe_format format2
)
1878 const struct util_format_description
*desc1
, *desc2
;
1879 enum dcc_channel_type type1
, type2
;
1882 if (format1
== format2
)
1885 desc1
= util_format_description(format1
);
1886 desc2
= util_format_description(format2
);
1888 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1891 /* Swizzles must be the same. */
1892 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1893 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1894 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1895 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1898 type1
= vi_get_dcc_channel_type(desc1
);
1899 type2
= vi_get_dcc_channel_type(desc2
);
1901 return type1
!= dcc_channel_incompatible
&&
1902 type2
!= dcc_channel_incompatible
&&
1906 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1907 struct pipe_resource
*tex
,
1909 enum pipe_format view_format
)
1911 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1913 if (vi_dcc_enabled(rtex
, level
) &&
1914 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1915 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1916 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1919 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1920 struct pipe_resource
*texture
,
1921 const struct pipe_surface
*templ
,
1922 unsigned width0
, unsigned height0
,
1923 unsigned width
, unsigned height
)
1925 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1926 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1931 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1932 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1934 pipe_reference_init(&surface
->base
.reference
, 1);
1935 pipe_resource_reference(&surface
->base
.texture
, texture
);
1936 surface
->base
.context
= pipe
;
1937 surface
->base
.format
= templ
->format
;
1938 surface
->base
.width
= width
;
1939 surface
->base
.height
= height
;
1940 surface
->base
.u
= templ
->u
;
1942 surface
->width0
= width0
;
1943 surface
->height0
= height0
;
1945 if (texture
->target
!= PIPE_BUFFER
)
1946 vi_disable_dcc_if_incompatible_format(rctx
, texture
,
1950 return &surface
->base
;
1953 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1954 struct pipe_resource
*tex
,
1955 const struct pipe_surface
*templ
)
1957 unsigned level
= templ
->u
.tex
.level
;
1958 unsigned width
= u_minify(tex
->width0
, level
);
1959 unsigned height
= u_minify(tex
->height0
, level
);
1961 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1962 const struct util_format_description
*tex_desc
1963 = util_format_description(tex
->format
);
1964 const struct util_format_description
*templ_desc
1965 = util_format_description(templ
->format
);
1967 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1969 /* Adjust size of surface if and only if the block width or
1970 * height is changed. */
1971 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1972 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1973 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1974 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1976 width
= nblks_x
* templ_desc
->block
.width
;
1977 height
= nblks_y
* templ_desc
->block
.height
;
1981 return r600_create_surface_custom(pipe
, tex
, templ
,
1982 tex
->width0
, tex
->height0
,
1986 static void r600_surface_destroy(struct pipe_context
*pipe
,
1987 struct pipe_surface
*surface
)
1989 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1990 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1991 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1992 pipe_resource_reference(&surface
->texture
, NULL
);
1996 static void r600_clear_texture(struct pipe_context
*pipe
,
1997 struct pipe_resource
*tex
,
1999 const struct pipe_box
*box
,
2002 struct pipe_screen
*screen
= pipe
->screen
;
2003 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
2004 struct pipe_surface tmpl
= {{0}};
2005 struct pipe_surface
*sf
;
2006 const struct util_format_description
*desc
=
2007 util_format_description(tex
->format
);
2009 tmpl
.format
= tex
->format
;
2010 tmpl
.u
.tex
.first_layer
= box
->z
;
2011 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
2012 tmpl
.u
.tex
.level
= level
;
2013 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
2017 if (rtex
->is_depth
) {
2020 uint8_t stencil
= 0;
2022 /* Depth is always present. */
2023 clear
= PIPE_CLEAR_DEPTH
;
2024 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
2026 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2027 clear
|= PIPE_CLEAR_STENCIL
;
2028 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
2031 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
2033 box
->width
, box
->height
, false);
2035 union pipe_color_union color
;
2037 /* pipe_color_union requires the full vec4 representation. */
2038 if (util_format_is_pure_uint(tex
->format
))
2039 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2040 else if (util_format_is_pure_sint(tex
->format
))
2041 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2043 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2045 if (screen
->is_format_supported(screen
, tex
->format
,
2047 PIPE_BIND_RENDER_TARGET
)) {
2048 pipe
->clear_render_target(pipe
, sf
, &color
,
2050 box
->width
, box
->height
, false);
2052 /* Software fallback - just for R9G9B9E5_FLOAT */
2053 util_clear_render_target(pipe
, sf
, &color
,
2055 box
->width
, box
->height
);
2058 pipe_surface_reference(&sf
, NULL
);
2061 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2063 const struct util_format_description
*desc
= util_format_description(format
);
2065 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2067 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2068 return V_0280A0_SWAP_STD
;
2070 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2073 switch (desc
->nr_channels
) {
2075 if (HAS_SWIZZLE(0,X
))
2076 return V_0280A0_SWAP_STD
; /* X___ */
2077 else if (HAS_SWIZZLE(3,X
))
2078 return V_0280A0_SWAP_ALT_REV
; /* ___X */
2081 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2082 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2083 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2084 return V_0280A0_SWAP_STD
; /* XY__ */
2085 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2086 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2087 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2089 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
2090 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2091 return V_0280A0_SWAP_ALT
; /* X__Y */
2092 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2093 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2096 if (HAS_SWIZZLE(0,X
))
2097 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2098 else if (HAS_SWIZZLE(0,Z
))
2099 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2102 /* check the middle channels, the 1st and 4th channel can be NONE */
2103 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2104 return V_0280A0_SWAP_STD
; /* XYZW */
2105 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2106 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2107 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2108 return V_0280A0_SWAP_ALT
; /* ZYXW */
2109 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2112 return V_0280A0_SWAP_ALT_REV
;
2114 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2121 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2123 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2128 if (rctx
->dcc_stats
[slot
].query_active
)
2129 vi_separate_dcc_stop_query(&rctx
->b
,
2130 rctx
->dcc_stats
[slot
].tex
);
2132 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2133 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2134 rctx
->b
.destroy_query(&rctx
->b
,
2135 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2136 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2139 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2143 * Return the per-context slot where DCC statistics queries for the texture live.
2145 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2146 struct r600_texture
*tex
)
2148 int i
, empty_slot
= -1;
2150 /* Remove zombie textures (textures kept alive by this array only). */
2151 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2152 if (rctx
->dcc_stats
[i
].tex
&&
2153 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2154 vi_dcc_clean_up_context_slot(rctx
, i
);
2156 /* Find the texture. */
2157 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2158 /* Return if found. */
2159 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2160 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2164 /* Record the first seen empty slot. */
2165 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2169 /* Not found. Remove the oldest member to make space in the array. */
2170 if (empty_slot
== -1) {
2171 int oldest_slot
= 0;
2173 /* Find the oldest slot. */
2174 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2175 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2176 rctx
->dcc_stats
[i
].last_use_timestamp
)
2179 /* Clean up the oldest slot. */
2180 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2181 empty_slot
= oldest_slot
;
2184 /* Add the texture to the new slot. */
2185 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2186 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2190 static struct pipe_query
*
2191 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2193 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2194 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2196 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2197 return (struct pipe_query
*)query
;
2201 * Called when binding a color buffer.
2203 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2204 struct r600_texture
*tex
)
2206 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2207 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2209 assert(!rctx
->dcc_stats
[i
].query_active
);
2211 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2212 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2214 /* begin or resume the query */
2215 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2216 rctx
->dcc_stats
[i
].query_active
= true;
2220 * Called when unbinding a color buffer.
2222 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2223 struct r600_texture
*tex
)
2225 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2226 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2228 assert(rctx
->dcc_stats
[i
].query_active
);
2229 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2231 /* pause or end the query */
2232 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2233 rctx
->dcc_stats
[i
].query_active
= false;
2236 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2238 /* The minimum number of fullscreen draws per frame that is required
2240 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2243 /* Called by fast clear. */
2244 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2245 struct r600_texture
*tex
)
2247 /* The intent is to use this with shared displayable back buffers,
2248 * but it's not strictly limited only to them.
2250 if (!tex
->resource
.is_shared
||
2251 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2252 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2253 tex
->resource
.b
.b
.last_level
> 0 ||
2254 !tex
->surface
.dcc_size
)
2257 if (tex
->dcc_offset
)
2258 return; /* already enabled */
2260 /* Enable the DCC stat gathering. */
2261 if (!tex
->dcc_gather_statistics
) {
2262 tex
->dcc_gather_statistics
= true;
2263 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2266 if (!vi_should_enable_separate_dcc(tex
))
2267 return; /* stats show that DCC decompression is too expensive */
2269 assert(tex
->surface
.num_dcc_levels
);
2270 assert(!tex
->dcc_separate_buffer
);
2272 r600_texture_discard_cmask(rctx
->screen
, tex
);
2274 /* Get a DCC buffer. */
2275 if (tex
->last_dcc_separate_buffer
) {
2276 assert(tex
->dcc_gather_statistics
);
2277 assert(!tex
->dcc_separate_buffer
);
2278 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2279 tex
->last_dcc_separate_buffer
= NULL
;
2281 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2282 r600_aligned_buffer_create(rctx
->b
.screen
,
2283 R600_RESOURCE_FLAG_UNMAPPABLE
,
2285 tex
->surface
.dcc_size
,
2286 tex
->surface
.dcc_alignment
);
2287 if (!tex
->dcc_separate_buffer
)
2291 /* dcc_offset is the absolute GPUVM address. */
2292 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2294 /* no need to flag anything since this is called by fast clear that
2295 * flags framebuffer state
2300 * Called by pipe_context::flush_resource, the place where DCC decompression
2303 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2304 struct r600_texture
*tex
)
2306 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2307 struct pipe_query
*tmp
;
2308 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2309 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2310 bool disable
= false;
2312 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2313 union pipe_query_result result
;
2315 /* Read the results. */
2316 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2318 r600_query_hw_reset_buffers(rctx
,
2319 (struct r600_query_hw
*)
2320 rctx
->dcc_stats
[i
].ps_stats
[2]);
2322 /* Compute the approximate number of fullscreen draws. */
2323 tex
->ps_draw_ratio
=
2324 result
.pipeline_statistics
.ps_invocations
/
2325 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2326 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2328 disable
= tex
->dcc_separate_buffer
&&
2329 !vi_should_enable_separate_dcc(tex
);
2332 tex
->num_slow_clears
= 0;
2334 /* stop the statistics query for ps_stats[0] */
2336 vi_separate_dcc_stop_query(ctx
, tex
);
2338 /* Move the queries in the queue by one. */
2339 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2340 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2341 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2342 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2344 /* create and start a new query as ps_stats[0] */
2346 vi_separate_dcc_start_query(ctx
, tex
);
2349 assert(!tex
->last_dcc_separate_buffer
);
2350 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2351 tex
->dcc_separate_buffer
= NULL
;
2352 tex
->dcc_offset
= 0;
2353 /* no need to flag anything since this is called after
2354 * decompression that re-sets framebuffer state
2359 /* FAST COLOR CLEAR */
2361 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2362 enum pipe_format surface_format
,
2363 const union pipe_color_union
*color
)
2365 union util_color uc
;
2367 memset(&uc
, 0, sizeof(uc
));
2369 if (rtex
->surface
.bpe
== 16) {
2370 /* DCC fast clear only:
2371 * CLEAR_WORD0 = R = G = B
2374 assert(color
->ui
[0] == color
->ui
[1] &&
2375 color
->ui
[0] == color
->ui
[2]);
2376 uc
.ui
[0] = color
->ui
[0];
2377 uc
.ui
[1] = color
->ui
[3];
2378 } else if (util_format_is_pure_uint(surface_format
)) {
2379 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2380 } else if (util_format_is_pure_sint(surface_format
)) {
2381 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2383 util_pack_color(color
->f
, surface_format
, &uc
);
2386 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2389 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2390 const union pipe_color_union
*color
,
2391 uint32_t* reset_value
,
2392 bool* clear_words_needed
)
2394 bool values
[4] = {};
2396 bool main_value
= false;
2397 bool extra_value
= false;
2399 const struct util_format_description
*desc
= util_format_description(surface_format
);
2401 if (desc
->block
.bits
== 128 &&
2402 (color
->ui
[0] != color
->ui
[1] ||
2403 color
->ui
[0] != color
->ui
[2]))
2406 *clear_words_needed
= true;
2407 *reset_value
= 0x20202020U
;
2409 /* If we want to clear without needing a fast clear eliminate step, we
2410 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2411 * have two sets of flags, one for the last or first channel(extra) and
2412 * one for the other channels(main).
2415 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2416 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2417 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2419 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2420 if(r600_translate_colorswap(surface_format
, false) <= 1)
2421 extra_channel
= desc
->nr_channels
- 1;
2427 for (i
= 0; i
< 4; ++i
) {
2428 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2430 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2431 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2434 if (desc
->channel
[i
].pure_integer
&&
2435 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2436 /* Use the maximum value for clamping the clear color. */
2437 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2439 values
[i
] = color
->i
[i
] != 0;
2440 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2442 } else if (desc
->channel
[i
].pure_integer
&&
2443 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2444 /* Use the maximum value for clamping the clear color. */
2445 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2447 values
[i
] = color
->ui
[i
] != 0U;
2448 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2451 values
[i
] = color
->f
[i
] != 0.0F
;
2452 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2456 if (index
== extra_channel
)
2457 extra_value
= values
[i
];
2459 main_value
= values
[i
];
2462 for (int i
= 0; i
< 4; ++i
)
2463 if (values
[i
] != main_value
&&
2464 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2465 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2466 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2469 *clear_words_needed
= false;
2471 *reset_value
|= 0x80808080U
;
2474 *reset_value
|= 0x40404040U
;
2478 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2479 struct r600_texture
*rtex
,
2480 unsigned level
, unsigned clear_value
)
2482 struct pipe_resource
*dcc_buffer
;
2483 uint64_t dcc_offset
, clear_size
;
2485 assert(vi_dcc_enabled(rtex
, level
));
2487 if (rtex
->dcc_separate_buffer
) {
2488 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2491 dcc_buffer
= &rtex
->resource
.b
.b
;
2492 dcc_offset
= rtex
->dcc_offset
;
2495 if (rctx
->chip_class
>= GFX9
) {
2496 /* Mipmap level clears aren't implemented. */
2497 assert(rtex
->resource
.b
.b
.last_level
== 0);
2498 /* MSAA needs a different clear size. */
2499 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2500 clear_size
= rtex
->surface
.dcc_size
;
2502 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2503 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2506 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2507 clear_value
, R600_COHERENCY_CB_META
);
2510 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2511 * This allows hitting the MSAA resolve fast path, which requires that both
2512 * src and dst micro tile modes match.
2514 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2515 struct r600_texture
*rtex
)
2517 if (rtex
->resource
.is_shared
||
2518 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2519 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2522 assert(rscreen
->chip_class
>= GFX9
||
2523 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2524 assert(rtex
->resource
.b
.b
.last_level
== 0);
2526 if (rscreen
->chip_class
>= GFX9
) {
2527 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2528 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2530 /* If you do swizzle_mode % 4, you'll get:
2536 * Depth-sample order isn't allowed:
2538 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2540 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2541 case RADEON_MICRO_MODE_DISPLAY
:
2542 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2543 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2545 case RADEON_MICRO_MODE_THIN
:
2546 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2547 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2549 case RADEON_MICRO_MODE_ROTATED
:
2550 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2551 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2553 default: /* depth */
2554 assert(!"unexpected micro mode");
2557 } else if (rscreen
->chip_class
>= CIK
) {
2558 /* These magic numbers were copied from addrlib. It doesn't use
2559 * any definitions for them either. They are all 2D_TILED_THIN1
2560 * modes with different bpp and micro tile mode.
2562 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2563 case RADEON_MICRO_MODE_DISPLAY
:
2564 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2566 case RADEON_MICRO_MODE_THIN
:
2567 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2569 case RADEON_MICRO_MODE_ROTATED
:
2570 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2572 default: /* depth, thick */
2573 assert(!"unexpected micro mode");
2577 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2578 case RADEON_MICRO_MODE_DISPLAY
:
2579 switch (rtex
->surface
.bpe
) {
2581 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2584 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2587 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2591 case RADEON_MICRO_MODE_THIN
:
2592 switch (rtex
->surface
.bpe
) {
2594 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2597 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2600 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2602 default: /* 8, 16 */
2603 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2607 default: /* depth, thick */
2608 assert(!"unexpected micro mode");
2613 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2615 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2618 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2619 struct pipe_framebuffer_state
*fb
,
2620 struct r600_atom
*fb_state
,
2621 unsigned *buffers
, unsigned *dirty_cbufs
,
2622 const union pipe_color_union
*color
)
2626 /* This function is broken in BE, so just disable this path for now */
2627 #ifdef PIPE_ARCH_BIG_ENDIAN
2631 if (rctx
->render_cond
)
2634 /* TODO: fix CMASK and DCC fast clear */
2635 if (rctx
->chip_class
>= GFX9
)
2638 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2639 struct r600_texture
*tex
;
2640 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2645 /* if this colorbuffer is not being cleared */
2646 if (!(*buffers
& clear_bit
))
2649 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2651 /* the clear is allowed if all layers are bound */
2652 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2653 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2657 /* cannot clear mipmapped textures */
2658 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2662 /* only supported on tiled surfaces */
2663 if (tex
->surface
.is_linear
) {
2667 /* shared textures can't use fast clear without an explicit flush,
2668 * because there is no way to communicate the clear color among
2671 if (tex
->resource
.is_shared
&&
2672 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2675 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2676 if (rctx
->chip_class
== CIK
&&
2677 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2678 rctx
->screen
->info
.drm_major
== 2 &&
2679 rctx
->screen
->info
.drm_minor
< 38) {
2683 /* Fast clear is the most appropriate place to enable DCC for
2684 * displayable surfaces.
2686 if (rctx
->chip_class
>= VI
&&
2687 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2688 vi_separate_dcc_try_enable(rctx
, tex
);
2690 /* RB+ isn't supported with a CMASK-based clear, so all
2691 * clears are considered to be hypothetically slow
2692 * clears, which is weighed when determining whether to
2693 * enable separate DCC.
2695 if (tex
->dcc_gather_statistics
&&
2696 rctx
->screen
->rbplus_allowed
)
2697 tex
->num_slow_clears
++;
2700 /* Try to clear DCC first, otherwise try CMASK. */
2701 if (vi_dcc_enabled(tex
, 0)) {
2702 uint32_t reset_value
;
2703 bool clear_words_needed
;
2705 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2708 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2709 color
, &reset_value
,
2710 &clear_words_needed
))
2713 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2715 if (clear_words_needed
)
2716 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2717 tex
->separate_dcc_dirty
= true;
2719 /* 128-bit formats are unusupported */
2720 if (tex
->surface
.bpe
> 8) {
2724 /* RB+ doesn't work with CMASK fast clear. */
2725 if (rctx
->screen
->rbplus_allowed
)
2728 /* ensure CMASK is enabled */
2729 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2730 if (tex
->cmask
.size
== 0) {
2734 /* Do the fast clear. */
2735 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2736 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2737 R600_COHERENCY_CB_META
);
2739 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2742 /* We can change the micro tile mode before a full clear. */
2743 if (rctx
->screen
->chip_class
>= SI
)
2744 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2746 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2749 *dirty_cbufs
|= 1 << i
;
2750 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2751 *buffers
&= ~clear_bit
;
2755 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2757 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2758 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2761 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2763 rctx
->b
.create_surface
= r600_create_surface
;
2764 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2765 rctx
->b
.clear_texture
= r600_clear_texture
;