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radeonsi: fix Hyper-Z on Stoney
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static boolean r600_texture_get_handle(struct pipe_screen* screen,
232 struct pipe_resource *ptex,
233 struct winsys_handle *whandle)
234 {
235 struct r600_texture *rtex = (struct r600_texture*)ptex;
236 struct r600_resource *resource = &rtex->resource;
237 struct radeon_surf *surface = &rtex->surface;
238 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
239
240 rscreen->ws->buffer_set_tiling(resource->buf,
241 NULL,
242 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
243 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
244 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
245 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
246 surface->pipe_config,
247 surface->bankw, surface->bankh,
248 surface->tile_split,
249 surface->stencil_tile_split,
250 surface->mtilea, surface->num_banks,
251 surface->level[0].pitch_bytes,
252 (surface->flags & RADEON_SURF_SCANOUT) != 0);
253
254 return rscreen->ws->buffer_get_handle(resource->buf,
255 surface->level[0].pitch_bytes, whandle);
256 }
257
258 static void r600_texture_destroy(struct pipe_screen *screen,
259 struct pipe_resource *ptex)
260 {
261 struct r600_texture *rtex = (struct r600_texture*)ptex;
262 struct r600_resource *resource = &rtex->resource;
263
264 if (rtex->flushed_depth_texture)
265 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
266
267 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
268 if (rtex->cmask_buffer != &rtex->resource) {
269 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
270 }
271 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
272 pb_reference(&resource->buf, NULL);
273 FREE(rtex);
274 }
275
276 static const struct u_resource_vtbl r600_texture_vtbl;
277
278 /* The number of samples can be specified independently of the texture. */
279 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
280 struct r600_texture *rtex,
281 unsigned nr_samples,
282 struct r600_fmask_info *out)
283 {
284 /* FMASK is allocated like an ordinary texture. */
285 struct radeon_surf fmask = rtex->surface;
286
287 memset(out, 0, sizeof(*out));
288
289 fmask.bo_alignment = 0;
290 fmask.bo_size = 0;
291 fmask.nsamples = 1;
292 fmask.flags |= RADEON_SURF_FMASK;
293
294 /* Force 2D tiling if it wasn't set. This may occur when creating
295 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
296 * destination buffer must have an FMASK too. */
297 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
298 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
299
300 if (rscreen->chip_class >= SI) {
301 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
302 }
303
304 switch (nr_samples) {
305 case 2:
306 case 4:
307 fmask.bpe = 1;
308 if (rscreen->chip_class <= CAYMAN) {
309 fmask.bankh = 4;
310 }
311 break;
312 case 8:
313 fmask.bpe = 4;
314 break;
315 default:
316 R600_ERR("Invalid sample count for FMASK allocation.\n");
317 return;
318 }
319
320 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
321 * This can be fixed by writing a separate FMASK allocator specifically
322 * for R600-R700 asics. */
323 if (rscreen->chip_class <= R700) {
324 fmask.bpe *= 2;
325 }
326
327 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
328 R600_ERR("Got error in surface_init while allocating FMASK.\n");
329 return;
330 }
331
332 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
333
334 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
335 if (out->slice_tile_max)
336 out->slice_tile_max -= 1;
337
338 out->tile_mode_index = fmask.tiling_index[0];
339 out->pitch_in_pixels = fmask.level[0].nblk_x;
340 out->bank_height = fmask.bankh;
341 out->alignment = MAX2(256, fmask.bo_alignment);
342 out->size = fmask.bo_size;
343 }
344
345 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
346 struct r600_texture *rtex)
347 {
348 r600_texture_get_fmask_info(rscreen, rtex,
349 rtex->resource.b.b.nr_samples, &rtex->fmask);
350
351 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
352 rtex->size = rtex->fmask.offset + rtex->fmask.size;
353 }
354
355 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
356 struct r600_texture *rtex,
357 struct r600_cmask_info *out)
358 {
359 unsigned cmask_tile_width = 8;
360 unsigned cmask_tile_height = 8;
361 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
362 unsigned element_bits = 4;
363 unsigned cmask_cache_bits = 1024;
364 unsigned num_pipes = rscreen->tiling_info.num_channels;
365 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
366
367 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
368 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
369 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
370 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
371 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
372
373 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
374 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
375
376 unsigned base_align = num_pipes * pipe_interleave_bytes;
377 unsigned slice_bytes =
378 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
379
380 assert(macro_tile_width % 128 == 0);
381 assert(macro_tile_height % 128 == 0);
382
383 out->pitch = pitch_elements;
384 out->height = height;
385 out->xalign = macro_tile_width;
386 out->yalign = macro_tile_height;
387 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
388 out->alignment = MAX2(256, base_align);
389 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
390 align(slice_bytes, base_align);
391 }
392
393 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
394 struct r600_texture *rtex,
395 struct r600_cmask_info *out)
396 {
397 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
398 unsigned num_pipes = rscreen->tiling_info.num_channels;
399 unsigned cl_width, cl_height;
400
401 switch (num_pipes) {
402 case 2:
403 cl_width = 32;
404 cl_height = 16;
405 break;
406 case 4:
407 cl_width = 32;
408 cl_height = 32;
409 break;
410 case 8:
411 cl_width = 64;
412 cl_height = 32;
413 break;
414 case 16: /* Hawaii */
415 cl_width = 64;
416 cl_height = 64;
417 break;
418 default:
419 assert(0);
420 return;
421 }
422
423 unsigned base_align = num_pipes * pipe_interleave_bytes;
424
425 unsigned width = align(rtex->surface.npix_x, cl_width*8);
426 unsigned height = align(rtex->surface.npix_y, cl_height*8);
427 unsigned slice_elements = (width * height) / (8*8);
428
429 /* Each element of CMASK is a nibble. */
430 unsigned slice_bytes = slice_elements / 2;
431
432 out->pitch = width;
433 out->height = height;
434 out->xalign = cl_width * 8;
435 out->yalign = cl_height * 8;
436 out->slice_tile_max = (width * height) / (128*128);
437 if (out->slice_tile_max)
438 out->slice_tile_max -= 1;
439
440 out->alignment = MAX2(256, base_align);
441 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
442 align(slice_bytes, base_align);
443 }
444
445 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
446 struct r600_texture *rtex)
447 {
448 if (rscreen->chip_class >= SI) {
449 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
450 } else {
451 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
452 }
453
454 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
455 rtex->size = rtex->cmask.offset + rtex->cmask.size;
456
457 if (rscreen->chip_class >= SI)
458 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
459 else
460 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
461 }
462
463 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
464 struct r600_texture *rtex)
465 {
466 if (rtex->cmask_buffer)
467 return;
468
469 assert(rtex->cmask.size == 0);
470
471 if (rscreen->chip_class >= SI) {
472 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
473 } else {
474 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
475 }
476
477 rtex->cmask_buffer = (struct r600_resource *)
478 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
479 PIPE_USAGE_DEFAULT, rtex->cmask.size);
480 if (rtex->cmask_buffer == NULL) {
481 rtex->cmask.size = 0;
482 return;
483 }
484
485 /* update colorbuffer state bits */
486 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
487
488 if (rscreen->chip_class >= SI)
489 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
490 else
491 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
492 }
493
494 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
495 struct r600_texture *rtex)
496 {
497 if (rscreen->debug_flags & DBG_NO_DCC)
498 return;
499
500 rtex->dcc_buffer = (struct r600_resource *)
501 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
502 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
503 if (rtex->dcc_buffer == NULL) {
504 return;
505 }
506
507 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
508 0xFFFFFFFF, true);
509
510 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
511 }
512
513 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
514 struct r600_texture *rtex)
515 {
516 unsigned cl_width, cl_height, width, height;
517 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
518 unsigned num_pipes = rscreen->tiling_info.num_channels;
519
520 if (rscreen->chip_class <= EVERGREEN &&
521 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
522 return 0;
523
524 /* HW bug on R6xx. */
525 if (rscreen->chip_class == R600 &&
526 (rtex->surface.level[0].npix_x > 7680 ||
527 rtex->surface.level[0].npix_y > 7680))
528 return 0;
529
530 /* HTILE is broken with 1D tiling on old kernels and CIK. */
531 if (rscreen->chip_class >= CIK &&
532 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
533 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
534 return 0;
535
536 /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
537 if (rscreen->family == CHIP_STONEY)
538 num_pipes = 4;
539
540 switch (num_pipes) {
541 case 1:
542 cl_width = 32;
543 cl_height = 16;
544 break;
545 case 2:
546 cl_width = 32;
547 cl_height = 32;
548 break;
549 case 4:
550 cl_width = 64;
551 cl_height = 32;
552 break;
553 case 8:
554 cl_width = 64;
555 cl_height = 64;
556 break;
557 case 16:
558 cl_width = 128;
559 cl_height = 64;
560 break;
561 default:
562 assert(0);
563 return 0;
564 }
565
566 width = align(rtex->surface.npix_x, cl_width * 8);
567 height = align(rtex->surface.npix_y, cl_height * 8);
568
569 slice_elements = (width * height) / (8 * 8);
570 slice_bytes = slice_elements * 4;
571
572 pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
573 base_align = num_pipes * pipe_interleave_bytes;
574
575 rtex->htile.pitch = width;
576 rtex->htile.height = height;
577 rtex->htile.xalign = cl_width * 8;
578 rtex->htile.yalign = cl_height * 8;
579
580 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
581 align(slice_bytes, base_align);
582 }
583
584 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
585 struct r600_texture *rtex)
586 {
587 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
588
589 if (!htile_size)
590 return;
591
592 rtex->htile_buffer = (struct r600_resource*)
593 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
594 PIPE_USAGE_DEFAULT, htile_size);
595 if (rtex->htile_buffer == NULL) {
596 /* this is not a fatal error as we can still keep rendering
597 * without htile buffer */
598 R600_ERR("Failed to create buffer object for htile buffer.\n");
599 } else {
600 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
601 htile_size, 0, true);
602 }
603 }
604
605 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
606 {
607 int i;
608
609 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
610 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
611 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
612 rtex->surface.npix_x, rtex->surface.npix_y,
613 rtex->surface.npix_z, rtex->surface.blk_w,
614 rtex->surface.blk_h, rtex->surface.blk_d,
615 rtex->surface.array_size, rtex->surface.last_level,
616 rtex->surface.bpe, rtex->surface.nsamples,
617 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
618
619 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
620 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
621 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
622 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
623 rtex->surface.tile_split, rtex->surface.pipe_config,
624 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
625
626 if (rtex->fmask.size)
627 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
628 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
629 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
630 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
631 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
632
633 if (rtex->cmask.size)
634 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
635 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
636 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
637 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
638 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
639
640 if (rtex->htile_buffer)
641 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
642 "xalign=%u, yalign=%u\n",
643 rtex->htile_buffer->b.b.width0,
644 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
645 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
646
647 if (rtex->dcc_buffer) {
648 fprintf(f, " DCC: size=%u, alignment=%u\n",
649 rtex->dcc_buffer->b.b.width0,
650 rtex->dcc_buffer->buf->alignment);
651 for (i = 0; i <= rtex->surface.last_level; i++)
652 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
653 i, rtex->surface.level[i].dcc_offset);
654 }
655
656 for (i = 0; i <= rtex->surface.last_level; i++)
657 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
658 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
659 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
660 i, rtex->surface.level[i].offset,
661 rtex->surface.level[i].slice_size,
662 u_minify(rtex->resource.b.b.width0, i),
663 u_minify(rtex->resource.b.b.height0, i),
664 u_minify(rtex->resource.b.b.depth0, i),
665 rtex->surface.level[i].nblk_x,
666 rtex->surface.level[i].nblk_y,
667 rtex->surface.level[i].nblk_z,
668 rtex->surface.level[i].pitch_bytes,
669 rtex->surface.level[i].mode);
670
671 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
672 for (i = 0; i <= rtex->surface.last_level; i++) {
673 fprintf(f, " StencilLayout: tilesplit=%u\n",
674 rtex->surface.stencil_tile_split);
675 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
676 "slice_size=%"PRIu64", npix_x=%u, "
677 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
678 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
679 i, rtex->surface.stencil_level[i].offset,
680 rtex->surface.stencil_level[i].slice_size,
681 u_minify(rtex->resource.b.b.width0, i),
682 u_minify(rtex->resource.b.b.height0, i),
683 u_minify(rtex->resource.b.b.depth0, i),
684 rtex->surface.stencil_level[i].nblk_x,
685 rtex->surface.stencil_level[i].nblk_y,
686 rtex->surface.stencil_level[i].nblk_z,
687 rtex->surface.stencil_level[i].pitch_bytes,
688 rtex->surface.stencil_level[i].mode);
689 }
690 }
691 }
692
693 /* Common processing for r600_texture_create and r600_texture_from_handle */
694 static struct r600_texture *
695 r600_texture_create_object(struct pipe_screen *screen,
696 const struct pipe_resource *base,
697 unsigned pitch_in_bytes_override,
698 struct pb_buffer *buf,
699 struct radeon_surf *surface)
700 {
701 struct r600_texture *rtex;
702 struct r600_resource *resource;
703 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
704
705 rtex = CALLOC_STRUCT(r600_texture);
706 if (!rtex)
707 return NULL;
708
709 resource = &rtex->resource;
710 resource->b.b = *base;
711 resource->b.vtbl = &r600_texture_vtbl;
712 pipe_reference_init(&resource->b.b.reference, 1);
713 resource->b.b.screen = screen;
714
715 /* don't include stencil-only formats which we don't support for rendering */
716 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
717
718 rtex->surface = *surface;
719 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
720 FREE(rtex);
721 return NULL;
722 }
723
724 /* Tiled depth textures utilize the non-displayable tile order.
725 * This must be done after r600_setup_surface.
726 * Applies to R600-Cayman. */
727 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
728
729 if (rtex->is_depth) {
730 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
731 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
732 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
733
734 r600_texture_allocate_htile(rscreen, rtex);
735 }
736 } else {
737 if (base->nr_samples > 1) {
738 if (!buf) {
739 r600_texture_allocate_fmask(rscreen, rtex);
740 r600_texture_allocate_cmask(rscreen, rtex);
741 rtex->cmask_buffer = &rtex->resource;
742 }
743 if (!rtex->fmask.size || !rtex->cmask.size) {
744 FREE(rtex);
745 return NULL;
746 }
747 }
748 if (rtex->surface.dcc_size)
749 vi_texture_alloc_dcc_separate(rscreen, rtex);
750 }
751
752 /* Now create the backing buffer. */
753 if (!buf) {
754 if (!r600_init_resource(rscreen, resource, rtex->size,
755 rtex->surface.bo_alignment, TRUE)) {
756 FREE(rtex);
757 return NULL;
758 }
759 } else {
760 resource->buf = buf;
761 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
762 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
763 }
764
765 if (rtex->cmask.size) {
766 /* Initialize the cmask to 0xCC (= compressed state). */
767 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
768 rtex->cmask.offset, rtex->cmask.size,
769 0xCCCCCCCC, true);
770 }
771
772 /* Initialize the CMASK base register value. */
773 rtex->cmask.base_address_reg =
774 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
775
776 if (rscreen->debug_flags & DBG_VM) {
777 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
778 rtex->resource.gpu_address,
779 rtex->resource.gpu_address + rtex->resource.buf->size,
780 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
781 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
782 }
783
784 if (rscreen->debug_flags & DBG_TEX) {
785 puts("Texture:");
786 r600_print_texture_info(rtex, stdout);
787 }
788
789 return rtex;
790 }
791
792 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
793 const struct pipe_resource *templ)
794 {
795 const struct util_format_description *desc = util_format_description(templ->format);
796 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
797
798 /* MSAA resources must be 2D tiled. */
799 if (templ->nr_samples > 1)
800 return RADEON_SURF_MODE_2D;
801
802 /* Transfer resources should be linear. */
803 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
804 return RADEON_SURF_MODE_LINEAR_ALIGNED;
805
806 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
807 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
808 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
809 (templ->target == PIPE_TEXTURE_2D ||
810 templ->target == PIPE_TEXTURE_3D))
811 force_tiling = true;
812
813 /* Handle common candidates for the linear mode.
814 * Compressed textures must always be tiled. */
815 if (!force_tiling && !util_format_is_compressed(templ->format)) {
816 /* Not everything can be linear, so we cannot enforce it
817 * for all textures. */
818 if ((rscreen->debug_flags & DBG_NO_TILING) &&
819 (!util_format_is_depth_or_stencil(templ->format) ||
820 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
821 return RADEON_SURF_MODE_LINEAR_ALIGNED;
822
823 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
824 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
825 return RADEON_SURF_MODE_LINEAR_ALIGNED;
826
827 /* Cursors are linear on SI.
828 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
829 if (rscreen->chip_class >= SI &&
830 (templ->bind & PIPE_BIND_CURSOR))
831 return RADEON_SURF_MODE_LINEAR_ALIGNED;
832
833 if (templ->bind & PIPE_BIND_LINEAR)
834 return RADEON_SURF_MODE_LINEAR_ALIGNED;
835
836 /* Textures with a very small height are recommended to be linear. */
837 if (templ->target == PIPE_TEXTURE_1D ||
838 templ->target == PIPE_TEXTURE_1D_ARRAY ||
839 templ->height0 <= 4)
840 return RADEON_SURF_MODE_LINEAR_ALIGNED;
841
842 /* Textures likely to be mapped often. */
843 if (templ->usage == PIPE_USAGE_STAGING ||
844 templ->usage == PIPE_USAGE_STREAM)
845 return RADEON_SURF_MODE_LINEAR_ALIGNED;
846 }
847
848 /* Make small textures 1D tiled. */
849 if (templ->width0 <= 16 || templ->height0 <= 16 ||
850 (rscreen->debug_flags & DBG_NO_2D_TILING))
851 return RADEON_SURF_MODE_1D;
852
853 /* The allocator will switch to 1D if needed. */
854 return RADEON_SURF_MODE_2D;
855 }
856
857 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
858 const struct pipe_resource *templ)
859 {
860 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
861 struct radeon_surf surface = {0};
862 int r;
863
864 r = r600_init_surface(rscreen, &surface, templ,
865 r600_choose_tiling(rscreen, templ),
866 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
867 if (r) {
868 return NULL;
869 }
870 r = rscreen->ws->surface_best(rscreen->ws, &surface);
871 if (r) {
872 return NULL;
873 }
874 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
875 0, NULL, &surface);
876 }
877
878 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
879 const struct pipe_resource *templ,
880 struct winsys_handle *whandle)
881 {
882 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
883 struct pb_buffer *buf = NULL;
884 unsigned stride = 0;
885 unsigned array_mode;
886 enum radeon_bo_layout micro, macro;
887 struct radeon_surf surface;
888 bool scanout;
889 int r;
890
891 /* Support only 2D textures without mipmaps */
892 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
893 templ->depth0 != 1 || templ->last_level != 0)
894 return NULL;
895
896 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
897 if (!buf)
898 return NULL;
899
900 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
901 &surface.bankw, &surface.bankh,
902 &surface.tile_split,
903 &surface.stencil_tile_split,
904 &surface.mtilea, &scanout);
905
906 if (macro == RADEON_LAYOUT_TILED)
907 array_mode = RADEON_SURF_MODE_2D;
908 else if (micro == RADEON_LAYOUT_TILED)
909 array_mode = RADEON_SURF_MODE_1D;
910 else
911 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
912
913 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
914 if (r) {
915 return NULL;
916 }
917
918 if (scanout)
919 surface.flags |= RADEON_SURF_SCANOUT;
920
921 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
922 stride, buf, &surface);
923 }
924
925 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
926 struct pipe_resource *texture,
927 struct r600_texture **staging)
928 {
929 struct r600_texture *rtex = (struct r600_texture*)texture;
930 struct pipe_resource resource;
931 struct r600_texture **flushed_depth_texture = staging ?
932 staging : &rtex->flushed_depth_texture;
933
934 if (!staging && rtex->flushed_depth_texture)
935 return true; /* it's ready */
936
937 resource.target = texture->target;
938 resource.format = texture->format;
939 resource.width0 = texture->width0;
940 resource.height0 = texture->height0;
941 resource.depth0 = texture->depth0;
942 resource.array_size = texture->array_size;
943 resource.last_level = texture->last_level;
944 resource.nr_samples = texture->nr_samples;
945 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
946 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
947 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
948
949 if (staging)
950 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
951
952 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
953 if (*flushed_depth_texture == NULL) {
954 R600_ERR("failed to create temporary texture to hold flushed depth\n");
955 return false;
956 }
957
958 (*flushed_depth_texture)->is_flushing_texture = TRUE;
959 (*flushed_depth_texture)->non_disp_tiling = false;
960 return true;
961 }
962
963 /**
964 * Initialize the pipe_resource descriptor to be of the same size as the box,
965 * which is supposed to hold a subregion of the texture "orig" at the given
966 * mipmap level.
967 */
968 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
969 struct pipe_resource *orig,
970 const struct pipe_box *box,
971 unsigned level, unsigned flags)
972 {
973 memset(res, 0, sizeof(*res));
974 res->format = orig->format;
975 res->width0 = box->width;
976 res->height0 = box->height;
977 res->depth0 = 1;
978 res->array_size = 1;
979 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
980 res->flags = flags;
981
982 /* We must set the correct texture target and dimensions for a 3D box. */
983 if (box->depth > 1 && util_max_layer(orig, level) > 0)
984 res->target = orig->target;
985 else
986 res->target = PIPE_TEXTURE_2D;
987
988 switch (res->target) {
989 case PIPE_TEXTURE_1D_ARRAY:
990 case PIPE_TEXTURE_2D_ARRAY:
991 case PIPE_TEXTURE_CUBE_ARRAY:
992 res->array_size = box->depth;
993 break;
994 case PIPE_TEXTURE_3D:
995 res->depth0 = box->depth;
996 break;
997 default:;
998 }
999 }
1000
1001 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1002 struct pipe_resource *texture,
1003 unsigned level,
1004 unsigned usage,
1005 const struct pipe_box *box,
1006 struct pipe_transfer **ptransfer)
1007 {
1008 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1009 struct r600_texture *rtex = (struct r600_texture*)texture;
1010 struct r600_transfer *trans;
1011 boolean use_staging_texture = FALSE;
1012 struct r600_resource *buf;
1013 unsigned offset = 0;
1014 char *map;
1015
1016 /* We cannot map a tiled texture directly because the data is
1017 * in a different order, therefore we do detiling using a blit.
1018 *
1019 * Also, use a temporary in GTT memory for read transfers, as
1020 * the CPU is much happier reading out of cached system memory
1021 * than uncached VRAM.
1022 */
1023 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1024 use_staging_texture = TRUE;
1025 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1026 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1027 /* Untiled buffers in VRAM, which is slow for CPU reads */
1028 use_staging_texture = TRUE;
1029 } else if (!(usage & PIPE_TRANSFER_READ) &&
1030 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1031 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1032 /* Use a staging texture for uploads if the underlying BO is busy. */
1033 use_staging_texture = TRUE;
1034 }
1035
1036 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1037 use_staging_texture = FALSE;
1038 }
1039
1040 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1041 return NULL;
1042 }
1043
1044 trans = CALLOC_STRUCT(r600_transfer);
1045 if (!trans)
1046 return NULL;
1047 trans->transfer.resource = texture;
1048 trans->transfer.level = level;
1049 trans->transfer.usage = usage;
1050 trans->transfer.box = *box;
1051
1052 if (rtex->is_depth) {
1053 struct r600_texture *staging_depth;
1054
1055 if (rtex->resource.b.b.nr_samples > 1) {
1056 /* MSAA depth buffers need to be converted to single sample buffers.
1057 *
1058 * Mapping MSAA depth buffers can occur if ReadPixels is called
1059 * with a multisample GLX visual.
1060 *
1061 * First downsample the depth buffer to a temporary texture,
1062 * then decompress the temporary one to staging.
1063 *
1064 * Only the region being mapped is transfered.
1065 */
1066 struct pipe_resource resource;
1067
1068 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1069
1070 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1071 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1072 FREE(trans);
1073 return NULL;
1074 }
1075
1076 if (usage & PIPE_TRANSFER_READ) {
1077 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1078 if (!temp) {
1079 R600_ERR("failed to create a temporary depth texture\n");
1080 FREE(trans);
1081 return NULL;
1082 }
1083
1084 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1085 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1086 0, 0, 0, box->depth, 0, 0);
1087 pipe_resource_reference(&temp, NULL);
1088 }
1089 }
1090 else {
1091 /* XXX: only readback the rectangle which is being mapped? */
1092 /* XXX: when discard is true, no need to read back from depth texture */
1093 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1094 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1095 FREE(trans);
1096 return NULL;
1097 }
1098
1099 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1100 level, level,
1101 box->z, box->z + box->depth - 1,
1102 0, 0);
1103
1104 offset = r600_texture_get_offset(staging_depth, level, box);
1105 }
1106
1107 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1108 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1109 trans->staging = (struct r600_resource*)staging_depth;
1110 } else if (use_staging_texture) {
1111 struct pipe_resource resource;
1112 struct r600_texture *staging;
1113
1114 r600_init_temp_resource_from_box(&resource, texture, box, level,
1115 R600_RESOURCE_FLAG_TRANSFER);
1116 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1117 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1118
1119 /* Create the temporary texture. */
1120 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1121 if (!staging) {
1122 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1123 FREE(trans);
1124 return NULL;
1125 }
1126 trans->staging = &staging->resource;
1127 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1128 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1129 if (usage & PIPE_TRANSFER_READ) {
1130 r600_copy_to_staging_texture(ctx, trans);
1131 }
1132 } else {
1133 /* the resource is mapped directly */
1134 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1135 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1136 offset = r600_texture_get_offset(rtex, level, box);
1137 }
1138
1139 if (trans->staging) {
1140 buf = trans->staging;
1141 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1142 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1143 } else {
1144 buf = &rtex->resource;
1145 }
1146
1147 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1148 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1149 FREE(trans);
1150 return NULL;
1151 }
1152
1153 *ptransfer = &trans->transfer;
1154 return map + offset;
1155 }
1156
1157 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1158 struct pipe_transfer* transfer)
1159 {
1160 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1161 struct pipe_resource *texture = transfer->resource;
1162 struct r600_texture *rtex = (struct r600_texture*)texture;
1163
1164 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1165 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1166 ctx->resource_copy_region(ctx, texture, transfer->level,
1167 transfer->box.x, transfer->box.y, transfer->box.z,
1168 &rtransfer->staging->b.b, transfer->level,
1169 &transfer->box);
1170 } else {
1171 r600_copy_from_staging_texture(ctx, rtransfer);
1172 }
1173 }
1174
1175 if (rtransfer->staging)
1176 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1177
1178 FREE(transfer);
1179 }
1180
1181 static const struct u_resource_vtbl r600_texture_vtbl =
1182 {
1183 NULL, /* get_handle */
1184 r600_texture_destroy, /* resource_destroy */
1185 r600_texture_transfer_map, /* transfer_map */
1186 u_default_transfer_flush_region, /* transfer_flush_region */
1187 r600_texture_transfer_unmap, /* transfer_unmap */
1188 NULL /* transfer_inline_write */
1189 };
1190
1191 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1192 struct pipe_resource *texture,
1193 const struct pipe_surface *templ,
1194 unsigned width, unsigned height)
1195 {
1196 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1197
1198 if (!surface)
1199 return NULL;
1200
1201 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1202 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1203
1204 pipe_reference_init(&surface->base.reference, 1);
1205 pipe_resource_reference(&surface->base.texture, texture);
1206 surface->base.context = pipe;
1207 surface->base.format = templ->format;
1208 surface->base.width = width;
1209 surface->base.height = height;
1210 surface->base.u = templ->u;
1211 return &surface->base;
1212 }
1213
1214 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1215 struct pipe_resource *tex,
1216 const struct pipe_surface *templ)
1217 {
1218 unsigned level = templ->u.tex.level;
1219 unsigned width = u_minify(tex->width0, level);
1220 unsigned height = u_minify(tex->height0, level);
1221
1222 if (templ->format != tex->format) {
1223 const struct util_format_description *tex_desc
1224 = util_format_description(tex->format);
1225 const struct util_format_description *templ_desc
1226 = util_format_description(templ->format);
1227
1228 assert(tex_desc->block.bits == templ_desc->block.bits);
1229
1230 /* Adjust size of surface if and only if the block width or
1231 * height is changed. */
1232 if (tex_desc->block.width != templ_desc->block.width ||
1233 tex_desc->block.height != templ_desc->block.height) {
1234 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1235 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1236
1237 width = nblks_x * templ_desc->block.width;
1238 height = nblks_y * templ_desc->block.height;
1239 }
1240 }
1241
1242 return r600_create_surface_custom(pipe, tex, templ, width, height);
1243 }
1244
1245 static void r600_surface_destroy(struct pipe_context *pipe,
1246 struct pipe_surface *surface)
1247 {
1248 struct r600_surface *surf = (struct r600_surface*)surface;
1249 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1250 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1251 pipe_resource_reference(&surface->texture, NULL);
1252 FREE(surface);
1253 }
1254
1255 unsigned r600_translate_colorswap(enum pipe_format format)
1256 {
1257 const struct util_format_description *desc = util_format_description(format);
1258
1259 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1260
1261 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1262 return V_0280A0_SWAP_STD;
1263
1264 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1265 return ~0U;
1266
1267 switch (desc->nr_channels) {
1268 case 1:
1269 if (HAS_SWIZZLE(0,X))
1270 return V_0280A0_SWAP_STD; /* X___ */
1271 else if (HAS_SWIZZLE(3,X))
1272 return V_0280A0_SWAP_ALT_REV; /* ___X */
1273 break;
1274 case 2:
1275 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1276 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1277 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1278 return V_0280A0_SWAP_STD; /* XY__ */
1279 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1280 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1281 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1282 return V_0280A0_SWAP_STD_REV; /* YX__ */
1283 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1284 return V_0280A0_SWAP_ALT; /* X__Y */
1285 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1286 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1287 break;
1288 case 3:
1289 if (HAS_SWIZZLE(0,X))
1290 return V_0280A0_SWAP_STD; /* XYZ */
1291 else if (HAS_SWIZZLE(0,Z))
1292 return V_0280A0_SWAP_STD_REV; /* ZYX */
1293 break;
1294 case 4:
1295 /* check the middle channels, the 1st and 4th channel can be NONE */
1296 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1297 return V_0280A0_SWAP_STD; /* XYZW */
1298 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1299 return V_0280A0_SWAP_STD_REV; /* WZYX */
1300 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1301 return V_0280A0_SWAP_ALT; /* ZYXW */
1302 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
1303 return V_0280A0_SWAP_ALT_REV; /* WXYZ */
1304 break;
1305 }
1306 return ~0U;
1307 }
1308
1309 static void evergreen_set_clear_color(struct r600_texture *rtex,
1310 enum pipe_format surface_format,
1311 const union pipe_color_union *color)
1312 {
1313 union util_color uc;
1314
1315 memset(&uc, 0, sizeof(uc));
1316
1317 if (util_format_is_pure_uint(surface_format)) {
1318 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1319 } else if (util_format_is_pure_sint(surface_format)) {
1320 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1321 } else {
1322 util_pack_color(color->f, surface_format, &uc);
1323 }
1324
1325 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1326 }
1327
1328 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1329 const union pipe_color_union *color,
1330 uint32_t* reset_value,
1331 bool* clear_words_needed)
1332 {
1333 bool values[4] = {};
1334 int i;
1335 bool main_value = false;
1336 bool extra_value = false;
1337 int extra_channel;
1338 const struct util_format_description *desc = util_format_description(surface_format);
1339
1340 *clear_words_needed = true;
1341 *reset_value = 0x20202020U;
1342
1343 /* If we want to clear without needing a fast clear eliminate step, we
1344 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1345 * have two sets of flags, one for the last or first channel(extra) and
1346 * one for the other channels(main).
1347 */
1348
1349 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1350 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1351 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1352 extra_channel = -1;
1353 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1354 if(r600_translate_colorswap(surface_format) <= 1)
1355 extra_channel = desc->nr_channels - 1;
1356 else
1357 extra_channel = 0;
1358 } else
1359 return;
1360
1361 for (i = 0; i < 4; ++i) {
1362 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1363
1364 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1365 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1366 continue;
1367
1368 if (util_format_is_pure_sint(surface_format)) {
1369 values[i] = color->i[i] != 0;
1370 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1371 return;
1372 } else if (util_format_is_pure_uint(surface_format)) {
1373 values[i] = color->ui[i] != 0U;
1374 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1375 return;
1376 } else {
1377 values[i] = color->f[i] != 0.0F;
1378 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1379 return;
1380 }
1381
1382 if (index == extra_channel)
1383 extra_value = values[i];
1384 else
1385 main_value = values[i];
1386 }
1387
1388 for (int i = 0; i < 4; ++i)
1389 if (values[i] != main_value &&
1390 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1391 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1392 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1393 return;
1394
1395 *clear_words_needed = false;
1396 if (main_value)
1397 *reset_value |= 0x80808080U;
1398
1399 if (extra_value)
1400 *reset_value |= 0x40404040U;
1401 }
1402
1403 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1404 struct pipe_framebuffer_state *fb,
1405 struct r600_atom *fb_state,
1406 unsigned *buffers, unsigned *dirty_cbufs,
1407 const union pipe_color_union *color)
1408 {
1409 int i;
1410
1411 if (rctx->render_cond)
1412 return;
1413
1414 for (i = 0; i < fb->nr_cbufs; i++) {
1415 struct r600_texture *tex;
1416 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1417
1418 if (!fb->cbufs[i])
1419 continue;
1420
1421 /* if this colorbuffer is not being cleared */
1422 if (!(*buffers & clear_bit))
1423 continue;
1424
1425 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1426
1427 /* 128-bit formats are unusupported */
1428 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1429 continue;
1430 }
1431
1432 /* the clear is allowed if all layers are bound */
1433 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1434 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1435 continue;
1436 }
1437
1438 /* cannot clear mipmapped textures */
1439 if (fb->cbufs[i]->texture->last_level != 0) {
1440 continue;
1441 }
1442
1443 /* only supported on tiled surfaces */
1444 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1445 continue;
1446 }
1447
1448 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1449 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1450 rctx->chip_class >= CIK &&
1451 rctx->screen->info.drm_major == 2 &&
1452 rctx->screen->info.drm_minor < 38) {
1453 continue;
1454 }
1455
1456 if (tex->dcc_buffer) {
1457 uint32_t reset_value;
1458 bool clear_words_needed;
1459
1460 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1461 continue;
1462
1463 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1464
1465 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1466 0, tex->surface.dcc_size, reset_value, true);
1467
1468 if (clear_words_needed)
1469 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1470 } else {
1471 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1472 if (rctx->family == CHIP_STONEY)
1473 continue;
1474
1475 /* ensure CMASK is enabled */
1476 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1477 if (tex->cmask.size == 0) {
1478 continue;
1479 }
1480
1481 /* Do the fast clear. */
1482 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1483 tex->cmask.offset, tex->cmask.size, 0, true);
1484
1485 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1486 }
1487
1488 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1489
1490 if (dirty_cbufs)
1491 *dirty_cbufs |= 1 << i;
1492 rctx->set_atom_dirty(rctx, fb_state, true);
1493 *buffers &= ~clear_bit;
1494 }
1495 }
1496
1497 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1498 {
1499 rscreen->b.resource_from_handle = r600_texture_from_handle;
1500 rscreen->b.resource_get_handle = r600_texture_get_handle;
1501 }
1502
1503 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1504 {
1505 rctx->b.create_surface = r600_create_surface;
1506 rctx->b.surface_destroy = r600_surface_destroy;
1507 }