2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe_common.h"
25 #include "r600_query.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_memory.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31 #include "util/os_time.h"
34 #include "state_tracker/drm_driver.h"
35 #include "amd/common/sid.h"
37 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
38 struct r600_texture
*rtex
);
39 static enum radeon_surf_mode
40 r600_choose_tiling(struct r600_common_screen
*rscreen
,
41 const struct pipe_resource
*templ
);
44 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
58 /* MSAA: Blits don't exist in the real world. */
59 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
60 rdst
->resource
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (rsrc
->is_depth
|| rdst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(rsrc
, src_level
) ||
75 vi_dcc_enabled(rdst
, dst_level
))
79 * src: Both texture and SDMA paths need decompression. Use SDMA.
80 * dst: If overwriting the whole texture, discard CMASK and use
81 * SDMA. Otherwise, use the 3D path.
83 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
84 /* The CMASK clear is only enabled for the first level. */
85 assert(dst_level
== 0);
86 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
87 dstx
, dsty
, dstz
, src_box
->width
,
88 src_box
->height
, src_box
->depth
))
91 r600_texture_discard_cmask(rctx
->screen
, rdst
);
94 /* All requirements are met. Prepare textures for SDMA. */
95 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
96 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
98 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
99 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
104 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
105 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
106 struct pipe_resource
*dst
,
108 unsigned dstx
, unsigned dsty
, unsigned dstz
,
109 struct pipe_resource
*src
,
111 const struct pipe_box
*src_box
)
113 struct pipe_blit_info blit
;
115 memset(&blit
, 0, sizeof(blit
));
116 blit
.src
.resource
= src
;
117 blit
.src
.format
= src
->format
;
118 blit
.src
.level
= src_level
;
119 blit
.src
.box
= *src_box
;
120 blit
.dst
.resource
= dst
;
121 blit
.dst
.format
= dst
->format
;
122 blit
.dst
.level
= dst_level
;
123 blit
.dst
.box
.x
= dstx
;
124 blit
.dst
.box
.y
= dsty
;
125 blit
.dst
.box
.z
= dstz
;
126 blit
.dst
.box
.width
= src_box
->width
;
127 blit
.dst
.box
.height
= src_box
->height
;
128 blit
.dst
.box
.depth
= src_box
->depth
;
129 blit
.mask
= util_format_get_mask(src
->format
) &
130 util_format_get_mask(dst
->format
);
131 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
134 pipe
->blit(pipe
, &blit
);
138 /* Copy from a full GPU texture to a transfer's staging one. */
139 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
141 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
142 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
143 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
144 struct pipe_resource
*src
= transfer
->resource
;
146 if (src
->nr_samples
> 1) {
147 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
148 src
, transfer
->level
, &transfer
->box
);
152 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
156 /* Copy from a transfer's staging texture to a full GPU one. */
157 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
159 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
160 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
161 struct pipe_resource
*dst
= transfer
->resource
;
162 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
163 struct pipe_box sbox
;
165 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
167 if (dst
->nr_samples
> 1) {
168 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
169 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
174 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
175 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
179 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
180 struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
,
183 unsigned *layer_stride
)
185 if (rscreen
->chip_class
>= GFX9
) {
186 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
187 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
192 /* Each texture is an array of slices. Each slice is an array
193 * of mipmap levels. */
194 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
195 rtex
->surface
.u
.gfx9
.offset
[level
] +
196 (box
->y
/ rtex
->surface
.blk_h
*
197 rtex
->surface
.u
.gfx9
.surf_pitch
+
198 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
200 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
202 *layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
205 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
207 /* Each texture is an array of mipmap levels. Each level is
208 * an array of slices. */
209 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
210 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
211 (box
->y
/ rtex
->surface
.blk_h
*
212 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
213 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
217 static int r600_init_surface(struct r600_common_screen
*rscreen
,
218 struct radeon_surf
*surface
,
219 const struct pipe_resource
*ptex
,
220 enum radeon_surf_mode array_mode
,
221 unsigned pitch_in_bytes_override
,
225 bool is_flushed_depth
,
226 bool tc_compatible_htile
)
228 const struct util_format_description
*desc
=
229 util_format_description(ptex
->format
);
230 bool is_depth
, is_stencil
;
232 unsigned i
, bpe
, flags
= 0;
234 is_depth
= util_format_has_depth(desc
);
235 is_stencil
= util_format_has_stencil(desc
);
237 if (!is_flushed_depth
&&
238 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
239 bpe
= 4; /* stencil is allocated separately on evergreen */
241 bpe
= util_format_get_blocksize(ptex
->format
);
242 assert(util_is_power_of_two(bpe
));
245 if (!is_flushed_depth
&& is_depth
) {
246 flags
|= RADEON_SURF_ZBUFFER
;
248 if (tc_compatible_htile
&&
249 (rscreen
->chip_class
>= GFX9
||
250 array_mode
== RADEON_SURF_MODE_2D
)) {
251 /* TC-compatible HTILE only supports Z32_FLOAT.
252 * GFX9 also supports Z16_UNORM.
253 * On VI, promote Z16 to Z32. DB->CB copies will convert
254 * the format for transfers.
256 if (rscreen
->chip_class
== VI
)
259 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
263 flags
|= RADEON_SURF_SBUFFER
;
266 if (rscreen
->chip_class
>= VI
&&
267 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
268 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
269 flags
|= RADEON_SURF_DISABLE_DCC
;
271 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
272 /* This should catch bugs in gallium users setting incorrect flags. */
273 assert(ptex
->nr_samples
<= 1 &&
274 ptex
->array_size
== 1 &&
276 ptex
->last_level
== 0 &&
277 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
279 flags
|= RADEON_SURF_SCANOUT
;
282 if (ptex
->bind
& PIPE_BIND_SHARED
)
283 flags
|= RADEON_SURF_SHAREABLE
;
285 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
286 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
287 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
289 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
290 array_mode
, surface
);
295 if (rscreen
->chip_class
>= GFX9
) {
296 assert(!pitch_in_bytes_override
||
297 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
298 surface
->u
.gfx9
.surf_offset
= offset
;
301 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
302 surface
->u
.legacy
.level
[i
].offset
+= offset
;
308 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
309 struct r600_texture
*rtex
,
310 struct radeon_bo_metadata
*metadata
)
312 struct radeon_surf
*surface
= &rtex
->surface
;
314 memset(metadata
, 0, sizeof(*metadata
));
316 if (rscreen
->chip_class
>= GFX9
) {
317 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
319 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
320 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
321 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
322 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
323 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
324 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
325 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
326 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
327 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
328 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
329 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
330 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
334 static void r600_surface_import_metadata(struct r600_common_screen
*rscreen
,
335 struct radeon_surf
*surf
,
336 struct radeon_bo_metadata
*metadata
,
337 enum radeon_surf_mode
*array_mode
,
340 if (rscreen
->chip_class
>= GFX9
) {
341 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
342 *array_mode
= RADEON_SURF_MODE_2D
;
344 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
346 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
347 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
349 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
351 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
352 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
353 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
354 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
355 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
356 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
358 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
359 *array_mode
= RADEON_SURF_MODE_2D
;
360 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
361 *array_mode
= RADEON_SURF_MODE_1D
;
363 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
365 *is_scanout
= metadata
->u
.legacy
.scanout
;
369 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
370 struct r600_texture
*rtex
)
372 struct r600_common_screen
*rscreen
= rctx
->screen
;
373 struct pipe_context
*ctx
= &rctx
->b
;
375 if (ctx
== rscreen
->aux_context
)
376 mtx_lock(&rscreen
->aux_context_lock
);
378 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
379 ctx
->flush(ctx
, NULL
, 0);
381 if (ctx
== rscreen
->aux_context
)
382 mtx_unlock(&rscreen
->aux_context_lock
);
385 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
386 struct r600_texture
*rtex
)
388 if (!rtex
->cmask
.size
)
391 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
394 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
395 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
396 rtex
->dirty_level_mask
= 0;
398 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
400 if (rtex
->cmask_buffer
!= &rtex
->resource
)
401 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
403 /* Notify all contexts about the change. */
404 p_atomic_inc(&rscreen
->dirty_tex_counter
);
405 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
408 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
410 /* We can't disable DCC if it can be written by another process. */
411 return rtex
->dcc_offset
&&
412 (!rtex
->resource
.b
.is_shared
||
413 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
416 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
417 struct r600_texture
*rtex
)
419 if (!r600_can_disable_dcc(rtex
))
422 assert(rtex
->dcc_separate_buffer
== NULL
);
425 rtex
->dcc_offset
= 0;
427 /* Notify all contexts about the change. */
428 p_atomic_inc(&rscreen
->dirty_tex_counter
);
433 * Disable DCC for the texture. (first decompress, then discard metadata).
435 * There is unresolved multi-context synchronization issue between
436 * screen::aux_context and the current context. If applications do this with
437 * multiple contexts, it's already undefined behavior for them and we don't
438 * have to worry about that. The scenario is:
440 * If context 1 disables DCC and context 2 has queued commands that write
441 * to the texture via CB with DCC enabled, and the order of operations is
443 * context 2 queues draw calls rendering to the texture, but doesn't flush
444 * context 1 disables DCC and flushes
445 * context 1 & 2 reset descriptors and FB state
446 * context 2 flushes (new compressed tiles written by the draw calls)
447 * context 1 & 2 read garbage, because DCC is disabled, yet there are
450 * \param rctx the current context if you have one, or rscreen->aux_context
453 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
454 struct r600_texture
*rtex
)
456 struct r600_common_screen
*rscreen
= rctx
->screen
;
458 if (!r600_can_disable_dcc(rtex
))
461 if (&rctx
->b
== rscreen
->aux_context
)
462 mtx_lock(&rscreen
->aux_context_lock
);
464 /* Decompress DCC. */
465 rctx
->decompress_dcc(&rctx
->b
, rtex
);
466 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
468 if (&rctx
->b
== rscreen
->aux_context
)
469 mtx_unlock(&rscreen
->aux_context_lock
);
471 return r600_texture_discard_dcc(rscreen
, rtex
);
474 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
475 struct r600_texture
*rtex
,
476 unsigned new_bind_flag
,
477 bool invalidate_storage
)
479 struct pipe_screen
*screen
= rctx
->b
.screen
;
480 struct r600_texture
*new_tex
;
481 struct pipe_resource templ
= rtex
->resource
.b
.b
;
484 templ
.bind
|= new_bind_flag
;
486 if (rtex
->resource
.b
.is_shared
)
489 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
490 if (rtex
->surface
.is_linear
)
493 /* This fails with MSAA, depth, and compressed textures. */
494 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
495 RADEON_SURF_MODE_LINEAR_ALIGNED
)
499 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
503 /* Copy the pixels to the new texture. */
504 if (!invalidate_storage
) {
505 for (i
= 0; i
<= templ
.last_level
; i
++) {
509 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
510 util_max_layer(&templ
, i
) + 1, &box
);
512 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
513 &rtex
->resource
.b
.b
, i
, &box
);
517 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
518 r600_texture_discard_cmask(rctx
->screen
, rtex
);
519 r600_texture_discard_dcc(rctx
->screen
, rtex
);
522 /* Replace the structure fields of rtex. */
523 rtex
->resource
.b
.b
.bind
= templ
.bind
;
524 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
525 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
526 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
527 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
528 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
529 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
530 rtex
->resource
.domains
= new_tex
->resource
.domains
;
531 rtex
->resource
.flags
= new_tex
->resource
.flags
;
532 rtex
->size
= new_tex
->size
;
533 rtex
->db_render_format
= new_tex
->db_render_format
;
534 rtex
->db_compatible
= new_tex
->db_compatible
;
535 rtex
->can_sample_z
= new_tex
->can_sample_z
;
536 rtex
->can_sample_s
= new_tex
->can_sample_s
;
537 rtex
->surface
= new_tex
->surface
;
538 rtex
->fmask
= new_tex
->fmask
;
539 rtex
->cmask
= new_tex
->cmask
;
540 rtex
->cb_color_info
= new_tex
->cb_color_info
;
541 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
542 rtex
->htile_offset
= new_tex
->htile_offset
;
543 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
544 rtex
->depth_cleared
= new_tex
->depth_cleared
;
545 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
546 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
547 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
549 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
550 assert(!rtex
->htile_offset
);
551 assert(!rtex
->cmask
.size
);
552 assert(!rtex
->fmask
.size
);
553 assert(!rtex
->dcc_offset
);
554 assert(!rtex
->is_depth
);
557 r600_texture_reference(&new_tex
, NULL
);
559 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
562 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
563 struct pipe_context
*ctx
,
564 struct pipe_resource
*resource
,
565 struct winsys_handle
*whandle
,
568 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
569 struct r600_common_context
*rctx
;
570 struct r600_resource
*res
= (struct r600_resource
*)resource
;
571 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
572 struct radeon_bo_metadata metadata
;
573 bool update_metadata
= false;
574 unsigned stride
, offset
, slice_size
;
576 ctx
= threaded_context_unwrap_sync(ctx
);
577 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
579 if (resource
->target
!= PIPE_BUFFER
) {
580 /* This is not supported now, but it might be required for OpenCL
581 * interop in the future.
583 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
586 /* Move a suballocated texture into a non-suballocated allocation. */
587 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
588 rtex
->surface
.tile_swizzle
||
589 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
590 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
591 assert(!res
->b
.is_shared
);
592 r600_reallocate_texture_inplace(rctx
, rtex
,
593 PIPE_BIND_SHARED
, false);
594 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
595 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
596 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
597 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
598 assert(rtex
->surface
.tile_swizzle
== 0);
601 /* Since shader image stores don't support DCC on VI,
602 * disable it for external clients that want write
605 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
606 if (si_texture_disable_dcc(rctx
, rtex
))
607 update_metadata
= true;
610 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
611 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
612 /* Eliminate fast clear (both CMASK and DCC) */
613 r600_eliminate_fast_color_clear(rctx
, rtex
);
615 /* Disable CMASK if flush_resource isn't going
618 if (rtex
->cmask
.size
)
619 r600_texture_discard_cmask(rscreen
, rtex
);
623 if (!res
->b
.is_shared
|| update_metadata
) {
624 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
625 if (rscreen
->query_opaque_metadata
)
626 rscreen
->query_opaque_metadata(rscreen
, rtex
,
629 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
632 if (rscreen
->chip_class
>= GFX9
) {
633 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
634 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
636 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
638 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
639 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
641 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
644 /* Move a suballocated buffer into a non-suballocated allocation. */
645 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
646 assert(!res
->b
.is_shared
);
648 /* Allocate a new buffer with PIPE_BIND_SHARED. */
649 struct pipe_resource templ
= res
->b
.b
;
650 templ
.bind
|= PIPE_BIND_SHARED
;
652 struct pipe_resource
*newb
=
653 screen
->resource_create(screen
, &templ
);
657 /* Copy the old buffer contents to the new one. */
659 u_box_1d(0, newb
->width0
, &box
);
660 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
662 /* Move the new buffer storage to the old pipe_resource. */
663 si_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
664 pipe_resource_reference(&newb
, NULL
);
666 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
667 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
676 if (res
->b
.is_shared
) {
677 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
680 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
681 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
682 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
684 res
->b
.is_shared
= true;
685 res
->external_usage
= usage
;
688 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
689 slice_size
, whandle
);
692 static void r600_texture_destroy(struct pipe_screen
*screen
,
693 struct pipe_resource
*ptex
)
695 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
696 struct r600_resource
*resource
= &rtex
->resource
;
698 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
700 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
701 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
703 pb_reference(&resource
->buf
, NULL
);
704 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
705 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
709 static const struct u_resource_vtbl r600_texture_vtbl
;
711 /* The number of samples can be specified independently of the texture. */
712 void si_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
713 struct r600_texture
*rtex
,
715 struct r600_fmask_info
*out
)
717 /* FMASK is allocated like an ordinary texture. */
718 struct pipe_resource templ
= rtex
->resource
.b
.b
;
719 struct radeon_surf fmask
= {};
722 memset(out
, 0, sizeof(*out
));
724 if (rscreen
->chip_class
>= GFX9
) {
725 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
726 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
730 templ
.nr_samples
= 1;
731 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
733 switch (nr_samples
) {
742 R600_ERR("Invalid sample count for FMASK allocation.\n");
746 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
747 RADEON_SURF_MODE_2D
, &fmask
)) {
748 R600_ERR("Got error in surface_init while allocating FMASK.\n");
752 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
754 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
755 if (out
->slice_tile_max
)
756 out
->slice_tile_max
-= 1;
758 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
759 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
760 out
->bank_height
= fmask
.u
.legacy
.bankh
;
761 out
->tile_swizzle
= fmask
.tile_swizzle
;
762 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
763 out
->size
= fmask
.surf_size
;
766 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
767 struct r600_texture
*rtex
)
769 si_texture_get_fmask_info(rscreen
, rtex
,
770 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
772 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
773 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
776 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
777 struct r600_texture
*rtex
,
778 struct r600_cmask_info
*out
)
780 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
781 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
782 unsigned cl_width
, cl_height
;
784 if (rscreen
->chip_class
>= GFX9
) {
785 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
786 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
803 case 16: /* Hawaii */
812 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
814 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
815 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
816 unsigned slice_elements
= (width
* height
) / (8*8);
818 /* Each element of CMASK is a nibble. */
819 unsigned slice_bytes
= slice_elements
/ 2;
821 out
->slice_tile_max
= (width
* height
) / (128*128);
822 if (out
->slice_tile_max
)
823 out
->slice_tile_max
-= 1;
825 out
->alignment
= MAX2(256, base_align
);
826 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
827 align(slice_bytes
, base_align
);
830 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
831 struct r600_texture
*rtex
)
833 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
835 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
836 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
838 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
841 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
842 struct r600_texture
*rtex
)
844 if (rtex
->cmask_buffer
)
847 assert(rtex
->cmask
.size
== 0);
849 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
851 rtex
->cmask_buffer
= (struct r600_resource
*)
852 si_aligned_buffer_create(&rscreen
->b
,
853 R600_RESOURCE_FLAG_UNMAPPABLE
,
856 rtex
->cmask
.alignment
);
857 if (rtex
->cmask_buffer
== NULL
) {
858 rtex
->cmask
.size
= 0;
862 /* update colorbuffer state bits */
863 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
865 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
867 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
870 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
871 struct r600_texture
*rtex
)
873 unsigned cl_width
, cl_height
, width
, height
;
874 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
875 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
877 assert(rscreen
->chip_class
<= VI
);
879 rtex
->surface
.htile_size
= 0;
881 /* HTILE is broken with 1D tiling on old kernels and CIK. */
882 if (rscreen
->chip_class
>= CIK
&&
883 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
884 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
887 /* Overalign HTILE on P2 configs to work around GPU hangs in
888 * piglit/depthstencil-render-miplevels 585.
890 * This has been confirmed to help Kabini & Stoney, where the hangs
891 * are always reproducible. I think I have seen the test hang
892 * on Carrizo too, though it was very rare there.
894 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
923 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
924 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
926 slice_elements
= (width
* height
) / (8 * 8);
927 slice_bytes
= slice_elements
* 4;
929 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
930 base_align
= num_pipes
* pipe_interleave_bytes
;
932 rtex
->surface
.htile_alignment
= base_align
;
933 rtex
->surface
.htile_size
=
934 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
935 align(slice_bytes
, base_align
);
938 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
939 struct r600_texture
*rtex
)
941 if (rscreen
->chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
942 r600_texture_get_htile_size(rscreen
, rtex
);
944 if (!rtex
->surface
.htile_size
)
947 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
948 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
951 void si_print_texture_info(struct r600_common_screen
*rscreen
,
952 struct r600_texture
*rtex
, struct u_log_context
*log
)
956 /* Common parameters. */
957 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
958 "blk_h=%u, array_size=%u, last_level=%u, "
959 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
960 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
961 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
963 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
964 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
965 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
967 if (rscreen
->chip_class
>= GFX9
) {
968 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
969 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
970 rtex
->surface
.surf_size
,
971 rtex
->surface
.u
.gfx9
.surf_slice_size
,
972 rtex
->surface
.surf_alignment
,
973 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
974 rtex
->surface
.u
.gfx9
.surf
.epitch
,
975 rtex
->surface
.u
.gfx9
.surf_pitch
);
977 if (rtex
->fmask
.size
) {
978 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
979 "alignment=%u, swmode=%u, epitch=%u\n",
981 rtex
->surface
.u
.gfx9
.fmask_size
,
982 rtex
->surface
.u
.gfx9
.fmask_alignment
,
983 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
984 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
987 if (rtex
->cmask
.size
) {
988 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
989 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
991 rtex
->surface
.u
.gfx9
.cmask_size
,
992 rtex
->surface
.u
.gfx9
.cmask_alignment
,
993 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
994 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
997 if (rtex
->htile_offset
) {
998 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
999 "rb_aligned=%u, pipe_aligned=%u\n",
1001 rtex
->surface
.htile_size
,
1002 rtex
->surface
.htile_alignment
,
1003 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1004 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1007 if (rtex
->dcc_offset
) {
1008 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
1009 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1010 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1011 rtex
->surface
.dcc_alignment
,
1012 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1013 rtex
->surface
.num_dcc_levels
);
1016 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1017 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1018 rtex
->surface
.u
.gfx9
.stencil_offset
,
1019 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1020 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1025 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1026 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1027 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1028 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1029 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1030 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1032 if (rtex
->fmask
.size
)
1033 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1034 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1035 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1036 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1037 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1039 if (rtex
->cmask
.size
)
1040 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1041 "slice_tile_max=%u\n",
1042 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1043 rtex
->cmask
.slice_tile_max
);
1045 if (rtex
->htile_offset
)
1046 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", "
1047 "alignment=%u, TC_compatible = %u\n",
1048 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1049 rtex
->surface
.htile_alignment
,
1050 rtex
->tc_compatible_htile
);
1052 if (rtex
->dcc_offset
) {
1053 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1054 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1055 rtex
->surface
.dcc_alignment
);
1056 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1057 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1058 "fast_clear_size=%"PRIu64
"\n",
1059 i
, i
< rtex
->surface
.num_dcc_levels
,
1060 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1061 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1064 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1065 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1066 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1067 "mode=%u, tiling_index = %u\n",
1068 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1069 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1070 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1071 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1072 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1073 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1074 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1075 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1076 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1078 if (rtex
->surface
.has_stencil
) {
1079 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1080 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1081 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1082 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1083 "slice_size=%"PRIu64
", npix_x=%u, "
1084 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1085 "mode=%u, tiling_index = %u\n",
1086 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1087 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1088 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1089 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1090 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1091 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1092 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1093 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1094 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1099 /* Common processing for r600_texture_create and r600_texture_from_handle */
1100 static struct r600_texture
*
1101 r600_texture_create_object(struct pipe_screen
*screen
,
1102 const struct pipe_resource
*base
,
1103 struct pb_buffer
*buf
,
1104 struct radeon_surf
*surface
)
1106 struct r600_texture
*rtex
;
1107 struct r600_resource
*resource
;
1108 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1110 rtex
= CALLOC_STRUCT(r600_texture
);
1114 resource
= &rtex
->resource
;
1115 resource
->b
.b
= *base
;
1116 resource
->b
.b
.next
= NULL
;
1117 resource
->b
.vtbl
= &r600_texture_vtbl
;
1118 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1119 resource
->b
.b
.screen
= screen
;
1121 /* don't include stencil-only formats which we don't support for rendering */
1122 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1124 rtex
->surface
= *surface
;
1125 rtex
->size
= rtex
->surface
.surf_size
;
1127 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1128 (rtex
->surface
.flags
&
1129 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1131 /* TC-compatible HTILE:
1132 * - VI only supports Z32_FLOAT.
1133 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1134 if (rtex
->tc_compatible_htile
) {
1135 if (rscreen
->chip_class
>= GFX9
&&
1136 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1137 rtex
->db_render_format
= base
->format
;
1139 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1140 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1141 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1144 rtex
->db_render_format
= base
->format
;
1147 /* Applies to GCN. */
1148 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1150 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1151 * between frames, so the only thing that can enable separate DCC
1152 * with DRI2 is multiple slow clears within a frame.
1154 rtex
->ps_draw_ratio
= 0;
1156 if (rtex
->is_depth
) {
1157 if (rscreen
->chip_class
>= GFX9
) {
1158 rtex
->can_sample_z
= true;
1159 rtex
->can_sample_s
= true;
1161 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1162 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1165 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1166 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1167 rtex
->db_compatible
= true;
1169 if (!(rscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1170 r600_texture_allocate_htile(rscreen
, rtex
);
1173 if (base
->nr_samples
> 1) {
1175 r600_texture_allocate_fmask(rscreen
, rtex
);
1176 r600_texture_allocate_cmask(rscreen
, rtex
);
1177 rtex
->cmask_buffer
= &rtex
->resource
;
1179 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1185 /* Shared textures must always set up DCC here.
1186 * If it's not present, it will be disabled by
1187 * apply_opaque_metadata later.
1189 if (rtex
->surface
.dcc_size
&&
1190 (buf
|| !(rscreen
->debug_flags
& DBG(NO_DCC
))) &&
1191 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1192 /* Reserve space for the DCC buffer. */
1193 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1194 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1198 /* Now create the backing buffer. */
1200 si_init_resource_fields(rscreen
, resource
, rtex
->size
,
1201 rtex
->surface
.surf_alignment
);
1203 if (!si_alloc_resource(rscreen
, resource
)) {
1208 resource
->buf
= buf
;
1209 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1210 resource
->bo_size
= buf
->size
;
1211 resource
->bo_alignment
= buf
->alignment
;
1212 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1213 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1214 resource
->vram_usage
= buf
->size
;
1215 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1216 resource
->gart_usage
= buf
->size
;
1219 if (rtex
->cmask
.size
) {
1220 /* Initialize the cmask to 0xCC (= compressed state). */
1221 si_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1222 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1225 if (rtex
->htile_offset
) {
1226 uint32_t clear_value
= 0;
1228 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1229 clear_value
= 0x0000030F;
1231 si_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1233 rtex
->surface
.htile_size
,
1237 /* Initialize DCC only if the texture is not being imported. */
1238 if (!buf
&& rtex
->dcc_offset
) {
1239 si_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1241 rtex
->surface
.dcc_size
,
1245 /* Initialize the CMASK base register value. */
1246 rtex
->cmask
.base_address_reg
=
1247 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1249 if (rscreen
->debug_flags
& DBG(VM
)) {
1250 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1251 rtex
->resource
.gpu_address
,
1252 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1253 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1254 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1257 if (rscreen
->debug_flags
& DBG(TEX
)) {
1259 struct u_log_context log
;
1260 u_log_context_init(&log
);
1261 si_print_texture_info(rscreen
, rtex
, &log
);
1262 u_log_new_page_print(&log
, stdout
);
1264 u_log_context_destroy(&log
);
1270 static enum radeon_surf_mode
1271 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1272 const struct pipe_resource
*templ
)
1274 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1275 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1276 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1277 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1279 /* MSAA resources must be 2D tiled. */
1280 if (templ
->nr_samples
> 1)
1281 return RADEON_SURF_MODE_2D
;
1283 /* Transfer resources should be linear. */
1284 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1285 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1287 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1288 * which requires 2D tiling.
1290 if (rscreen
->chip_class
== VI
&&
1292 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1293 return RADEON_SURF_MODE_2D
;
1295 /* Handle common candidates for the linear mode.
1296 * Compressed textures and DB surfaces must always be tiled.
1298 if (!force_tiling
&&
1299 !is_depth_stencil
&&
1300 !util_format_is_compressed(templ
->format
)) {
1301 if (rscreen
->debug_flags
& DBG(NO_TILING
))
1302 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1304 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1305 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1306 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1308 /* Cursors are linear on SI.
1309 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1310 if (templ
->bind
& PIPE_BIND_CURSOR
)
1311 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1313 if (templ
->bind
& PIPE_BIND_LINEAR
)
1314 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1316 /* Textures with a very small height are recommended to be linear. */
1317 if (templ
->target
== PIPE_TEXTURE_1D
||
1318 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1319 /* Only very thin and long 2D textures should benefit from
1320 * linear_aligned. */
1321 (templ
->width0
> 8 && templ
->height0
<= 2))
1322 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1324 /* Textures likely to be mapped often. */
1325 if (templ
->usage
== PIPE_USAGE_STAGING
||
1326 templ
->usage
== PIPE_USAGE_STREAM
)
1327 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1330 /* Make small textures 1D tiled. */
1331 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1332 (rscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1333 return RADEON_SURF_MODE_1D
;
1335 /* The allocator will switch to 1D if needed. */
1336 return RADEON_SURF_MODE_2D
;
1339 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1340 const struct pipe_resource
*templ
)
1342 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1343 struct radeon_surf surface
= {0};
1344 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1345 bool tc_compatible_htile
=
1346 rscreen
->chip_class
>= VI
&&
1347 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1348 !(rscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1349 !is_flushed_depth
&&
1350 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1351 util_format_is_depth_or_stencil(templ
->format
);
1355 r
= r600_init_surface(rscreen
, &surface
, templ
,
1356 r600_choose_tiling(rscreen
, templ
), 0, 0,
1357 false, false, is_flushed_depth
,
1358 tc_compatible_htile
);
1363 return (struct pipe_resource
*)
1364 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1367 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1368 const struct pipe_resource
*templ
,
1369 struct winsys_handle
*whandle
,
1372 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1373 struct pb_buffer
*buf
= NULL
;
1374 unsigned stride
= 0, offset
= 0;
1375 enum radeon_surf_mode array_mode
;
1376 struct radeon_surf surface
= {};
1378 struct radeon_bo_metadata metadata
= {};
1379 struct r600_texture
*rtex
;
1382 /* Support only 2D textures without mipmaps */
1383 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1384 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1387 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1391 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1392 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
1393 &array_mode
, &is_scanout
);
1395 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1396 offset
, true, is_scanout
, false, false);
1401 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1405 rtex
->resource
.b
.is_shared
= true;
1406 rtex
->resource
.external_usage
= usage
;
1408 if (rscreen
->apply_opaque_metadata
)
1409 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1411 assert(rtex
->surface
.tile_swizzle
== 0);
1412 return &rtex
->resource
.b
.b
;
1415 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1416 struct pipe_resource
*texture
,
1417 struct r600_texture
**staging
)
1419 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1420 struct pipe_resource resource
;
1421 struct r600_texture
**flushed_depth_texture
= staging
?
1422 staging
: &rtex
->flushed_depth_texture
;
1423 enum pipe_format pipe_format
= texture
->format
;
1426 if (rtex
->flushed_depth_texture
)
1427 return true; /* it's ready */
1429 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1430 switch (pipe_format
) {
1431 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1432 /* Save memory by not allocating the S plane. */
1433 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1435 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1436 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1437 /* Save memory bandwidth by not copying the
1438 * stencil part during flush.
1440 * This potentially increases memory bandwidth
1441 * if an application uses both Z and S texturing
1442 * simultaneously (a flushed Z24S8 texture
1443 * would be stored compactly), but how often
1444 * does that really happen?
1446 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1450 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1451 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1453 /* DB->CB copies to an 8bpp surface don't work. */
1454 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1458 memset(&resource
, 0, sizeof(resource
));
1459 resource
.target
= texture
->target
;
1460 resource
.format
= pipe_format
;
1461 resource
.width0
= texture
->width0
;
1462 resource
.height0
= texture
->height0
;
1463 resource
.depth0
= texture
->depth0
;
1464 resource
.array_size
= texture
->array_size
;
1465 resource
.last_level
= texture
->last_level
;
1466 resource
.nr_samples
= texture
->nr_samples
;
1467 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1468 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1469 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1472 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1474 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1475 if (*flushed_depth_texture
== NULL
) {
1476 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1483 * Initialize the pipe_resource descriptor to be of the same size as the box,
1484 * which is supposed to hold a subregion of the texture "orig" at the given
1487 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1488 struct pipe_resource
*orig
,
1489 const struct pipe_box
*box
,
1490 unsigned level
, unsigned flags
)
1492 memset(res
, 0, sizeof(*res
));
1493 res
->format
= orig
->format
;
1494 res
->width0
= box
->width
;
1495 res
->height0
= box
->height
;
1497 res
->array_size
= 1;
1498 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1501 /* We must set the correct texture target and dimensions for a 3D box. */
1502 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1503 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1504 res
->array_size
= box
->depth
;
1506 res
->target
= PIPE_TEXTURE_2D
;
1510 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1511 struct r600_texture
*rtex
,
1512 unsigned transfer_usage
,
1513 const struct pipe_box
*box
)
1515 return !rtex
->resource
.b
.is_shared
&&
1516 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1517 rtex
->resource
.b
.b
.last_level
== 0 &&
1518 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1519 box
->x
, box
->y
, box
->z
,
1520 box
->width
, box
->height
,
1524 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1525 struct r600_texture
*rtex
)
1527 struct r600_common_screen
*rscreen
= rctx
->screen
;
1529 /* There is no point in discarding depth and tiled buffers. */
1530 assert(!rtex
->is_depth
);
1531 assert(rtex
->surface
.is_linear
);
1533 /* Reallocate the buffer in the same pipe_resource. */
1534 si_alloc_resource(rscreen
, &rtex
->resource
);
1536 /* Initialize the CMASK base address (needed even without CMASK). */
1537 rtex
->cmask
.base_address_reg
=
1538 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1540 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1542 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1545 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1546 struct pipe_resource
*texture
,
1549 const struct pipe_box
*box
,
1550 struct pipe_transfer
**ptransfer
)
1552 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1553 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1554 struct r600_transfer
*trans
;
1555 struct r600_resource
*buf
;
1556 unsigned offset
= 0;
1558 bool use_staging_texture
= false;
1560 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1561 assert(box
->width
&& box
->height
&& box
->depth
);
1563 /* Depth textures use staging unconditionally. */
1564 if (!rtex
->is_depth
) {
1565 /* Degrade the tile mode if we get too many transfers on APUs.
1566 * On dGPUs, the staging texture is always faster.
1567 * Only count uploads that are at least 4x4 pixels large.
1569 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1571 box
->width
>= 4 && box
->height
>= 4 &&
1572 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1573 bool can_invalidate
=
1574 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1577 r600_reallocate_texture_inplace(rctx
, rtex
,
1582 /* Tiled textures need to be converted into a linear texture for CPU
1583 * access. The staging texture is always linear and is placed in GART.
1585 * Reading from VRAM or GTT WC is slow, always use the staging
1586 * texture in this case.
1588 * Use the staging texture for uploads if the underlying BO
1591 if (!rtex
->surface
.is_linear
)
1592 use_staging_texture
= true;
1593 else if (usage
& PIPE_TRANSFER_READ
)
1594 use_staging_texture
=
1595 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1596 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1597 /* Write & linear only: */
1598 else if (si_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1599 RADEON_USAGE_READWRITE
) ||
1600 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1601 RADEON_USAGE_READWRITE
)) {
1603 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1605 r600_texture_invalidate_storage(rctx
, rtex
);
1607 use_staging_texture
= true;
1611 trans
= CALLOC_STRUCT(r600_transfer
);
1614 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1615 trans
->b
.b
.level
= level
;
1616 trans
->b
.b
.usage
= usage
;
1617 trans
->b
.b
.box
= *box
;
1619 if (rtex
->is_depth
) {
1620 struct r600_texture
*staging_depth
;
1622 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1623 /* MSAA depth buffers need to be converted to single sample buffers.
1625 * Mapping MSAA depth buffers can occur if ReadPixels is called
1626 * with a multisample GLX visual.
1628 * First downsample the depth buffer to a temporary texture,
1629 * then decompress the temporary one to staging.
1631 * Only the region being mapped is transfered.
1633 struct pipe_resource resource
;
1635 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1637 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1638 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1643 if (usage
& PIPE_TRANSFER_READ
) {
1644 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1646 R600_ERR("failed to create a temporary depth texture\n");
1651 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1652 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1653 0, 0, 0, box
->depth
, 0, 0);
1654 pipe_resource_reference(&temp
, NULL
);
1657 /* Just get the strides. */
1658 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1660 &trans
->b
.b
.layer_stride
);
1662 /* XXX: only readback the rectangle which is being mapped? */
1663 /* XXX: when discard is true, no need to read back from depth texture */
1664 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1665 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1670 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1672 box
->z
, box
->z
+ box
->depth
- 1,
1675 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1678 &trans
->b
.b
.layer_stride
);
1681 trans
->staging
= (struct r600_resource
*)staging_depth
;
1682 buf
= trans
->staging
;
1683 } else if (use_staging_texture
) {
1684 struct pipe_resource resource
;
1685 struct r600_texture
*staging
;
1687 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1688 R600_RESOURCE_FLAG_TRANSFER
);
1689 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1690 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1692 /* Create the temporary texture. */
1693 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1695 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1699 trans
->staging
= &staging
->resource
;
1701 /* Just get the strides. */
1702 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1704 &trans
->b
.b
.layer_stride
);
1706 if (usage
& PIPE_TRANSFER_READ
)
1707 r600_copy_to_staging_texture(ctx
, trans
);
1709 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1711 buf
= trans
->staging
;
1713 /* the resource is mapped directly */
1714 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1716 &trans
->b
.b
.layer_stride
);
1717 buf
= &rtex
->resource
;
1720 if (!(map
= si_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1721 r600_resource_reference(&trans
->staging
, NULL
);
1726 *ptransfer
= &trans
->b
.b
;
1727 return map
+ offset
;
1730 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1731 struct pipe_transfer
* transfer
)
1733 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1734 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1735 struct pipe_resource
*texture
= transfer
->resource
;
1736 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1738 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1739 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1740 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1741 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1742 &rtransfer
->staging
->b
.b
, transfer
->level
,
1745 r600_copy_from_staging_texture(ctx
, rtransfer
);
1749 if (rtransfer
->staging
) {
1750 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1751 r600_resource_reference(&rtransfer
->staging
, NULL
);
1754 /* Heuristic for {upload, draw, upload, draw, ..}:
1756 * Flush the gfx IB if we've allocated too much texture storage.
1758 * The idea is that we don't want to build IBs that use too much
1759 * memory and put pressure on the kernel memory manager and we also
1760 * want to make temporary and invalidated buffers go idle ASAP to
1761 * decrease the total memory usage or make them reusable. The memory
1762 * usage will be slightly higher than given here because of the buffer
1763 * cache in the winsys.
1765 * The result is that the kernel memory manager is never a bottleneck.
1767 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1768 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1769 rctx
->num_alloc_tex_transfer_bytes
= 0;
1772 pipe_resource_reference(&transfer
->resource
, NULL
);
1776 static const struct u_resource_vtbl r600_texture_vtbl
=
1778 NULL
, /* get_handle */
1779 r600_texture_destroy
, /* resource_destroy */
1780 r600_texture_transfer_map
, /* transfer_map */
1781 u_default_transfer_flush_region
, /* transfer_flush_region */
1782 r600_texture_transfer_unmap
, /* transfer_unmap */
1785 /* DCC channel type categories within which formats can be reinterpreted
1786 * while keeping the same DCC encoding. The swizzle must also match. */
1787 enum dcc_channel_type
{
1788 dcc_channel_float32
,
1791 dcc_channel_float16
,
1794 dcc_channel_uint_10_10_10_2
,
1797 dcc_channel_incompatible
,
1800 /* Return the type of DCC encoding. */
1801 static enum dcc_channel_type
1802 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1806 /* Find the first non-void channel. */
1807 for (i
= 0; i
< desc
->nr_channels
; i
++)
1808 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1810 if (i
== desc
->nr_channels
)
1811 return dcc_channel_incompatible
;
1813 switch (desc
->channel
[i
].size
) {
1815 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1816 return dcc_channel_float32
;
1817 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1818 return dcc_channel_uint32
;
1819 return dcc_channel_sint32
;
1821 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1822 return dcc_channel_float16
;
1823 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1824 return dcc_channel_uint16
;
1825 return dcc_channel_sint16
;
1827 return dcc_channel_uint_10_10_10_2
;
1829 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1830 return dcc_channel_uint8
;
1831 return dcc_channel_sint8
;
1833 return dcc_channel_incompatible
;
1837 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1838 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1839 enum pipe_format format2
)
1841 const struct util_format_description
*desc1
, *desc2
;
1842 enum dcc_channel_type type1
, type2
;
1845 if (format1
== format2
)
1848 desc1
= util_format_description(format1
);
1849 desc2
= util_format_description(format2
);
1851 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1854 /* Swizzles must be the same. */
1855 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1856 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1857 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1858 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1861 type1
= vi_get_dcc_channel_type(desc1
);
1862 type2
= vi_get_dcc_channel_type(desc2
);
1864 return type1
!= dcc_channel_incompatible
&&
1865 type2
!= dcc_channel_incompatible
&&
1869 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1871 enum pipe_format view_format
)
1873 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1875 return vi_dcc_enabled(rtex
, level
) &&
1876 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1879 /* This can't be merged with the above function, because
1880 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1881 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1882 struct pipe_resource
*tex
,
1884 enum pipe_format view_format
)
1886 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1888 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1889 if (!si_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1890 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1893 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1894 struct pipe_resource
*texture
,
1895 const struct pipe_surface
*templ
,
1896 unsigned width0
, unsigned height0
,
1897 unsigned width
, unsigned height
)
1899 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1904 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1905 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1907 pipe_reference_init(&surface
->base
.reference
, 1);
1908 pipe_resource_reference(&surface
->base
.texture
, texture
);
1909 surface
->base
.context
= pipe
;
1910 surface
->base
.format
= templ
->format
;
1911 surface
->base
.width
= width
;
1912 surface
->base
.height
= height
;
1913 surface
->base
.u
= templ
->u
;
1915 surface
->width0
= width0
;
1916 surface
->height0
= height0
;
1918 surface
->dcc_incompatible
=
1919 texture
->target
!= PIPE_BUFFER
&&
1920 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1922 return &surface
->base
;
1925 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1926 struct pipe_resource
*tex
,
1927 const struct pipe_surface
*templ
)
1929 unsigned level
= templ
->u
.tex
.level
;
1930 unsigned width
= u_minify(tex
->width0
, level
);
1931 unsigned height
= u_minify(tex
->height0
, level
);
1932 unsigned width0
= tex
->width0
;
1933 unsigned height0
= tex
->height0
;
1935 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1936 const struct util_format_description
*tex_desc
1937 = util_format_description(tex
->format
);
1938 const struct util_format_description
*templ_desc
1939 = util_format_description(templ
->format
);
1941 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1943 /* Adjust size of surface if and only if the block width or
1944 * height is changed. */
1945 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1946 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1947 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1948 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1950 width
= nblks_x
* templ_desc
->block
.width
;
1951 height
= nblks_y
* templ_desc
->block
.height
;
1953 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1954 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1958 return si_create_surface_custom(pipe
, tex
, templ
,
1963 static void r600_surface_destroy(struct pipe_context
*pipe
,
1964 struct pipe_surface
*surface
)
1966 pipe_resource_reference(&surface
->texture
, NULL
);
1970 static void r600_clear_texture(struct pipe_context
*pipe
,
1971 struct pipe_resource
*tex
,
1973 const struct pipe_box
*box
,
1976 struct pipe_screen
*screen
= pipe
->screen
;
1977 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1978 struct pipe_surface tmpl
= {{0}};
1979 struct pipe_surface
*sf
;
1980 const struct util_format_description
*desc
=
1981 util_format_description(tex
->format
);
1983 tmpl
.format
= tex
->format
;
1984 tmpl
.u
.tex
.first_layer
= box
->z
;
1985 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1986 tmpl
.u
.tex
.level
= level
;
1987 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1991 if (rtex
->is_depth
) {
1994 uint8_t stencil
= 0;
1996 /* Depth is always present. */
1997 clear
= PIPE_CLEAR_DEPTH
;
1998 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
2000 if (rtex
->surface
.has_stencil
) {
2001 clear
|= PIPE_CLEAR_STENCIL
;
2002 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
2005 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
2007 box
->width
, box
->height
, false);
2009 union pipe_color_union color
;
2011 /* pipe_color_union requires the full vec4 representation. */
2012 if (util_format_is_pure_uint(tex
->format
))
2013 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2014 else if (util_format_is_pure_sint(tex
->format
))
2015 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2017 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2019 if (screen
->is_format_supported(screen
, tex
->format
,
2021 PIPE_BIND_RENDER_TARGET
)) {
2022 pipe
->clear_render_target(pipe
, sf
, &color
,
2024 box
->width
, box
->height
, false);
2026 /* Software fallback - just for R9G9B9E5_FLOAT */
2027 util_clear_render_target(pipe
, sf
, &color
,
2029 box
->width
, box
->height
);
2032 pipe_surface_reference(&sf
, NULL
);
2035 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2037 const struct util_format_description
*desc
= util_format_description(format
);
2039 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2041 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2042 return V_028C70_SWAP_STD
;
2044 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2047 switch (desc
->nr_channels
) {
2049 if (HAS_SWIZZLE(0,X
))
2050 return V_028C70_SWAP_STD
; /* X___ */
2051 else if (HAS_SWIZZLE(3,X
))
2052 return V_028C70_SWAP_ALT_REV
; /* ___X */
2055 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2056 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2057 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2058 return V_028C70_SWAP_STD
; /* XY__ */
2059 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2060 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2061 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2063 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2064 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2065 return V_028C70_SWAP_ALT
; /* X__Y */
2066 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2067 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2070 if (HAS_SWIZZLE(0,X
))
2071 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2072 else if (HAS_SWIZZLE(0,Z
))
2073 return V_028C70_SWAP_STD_REV
; /* ZYX */
2076 /* check the middle channels, the 1st and 4th channel can be NONE */
2077 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2078 return V_028C70_SWAP_STD
; /* XYZW */
2079 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2080 return V_028C70_SWAP_STD_REV
; /* WZYX */
2081 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2082 return V_028C70_SWAP_ALT
; /* ZYXW */
2083 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2086 return V_028C70_SWAP_ALT_REV
;
2088 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2095 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2097 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2102 if (rctx
->dcc_stats
[slot
].query_active
)
2103 vi_separate_dcc_stop_query(&rctx
->b
,
2104 rctx
->dcc_stats
[slot
].tex
);
2106 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2107 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2108 rctx
->b
.destroy_query(&rctx
->b
,
2109 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2110 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2113 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2117 * Return the per-context slot where DCC statistics queries for the texture live.
2119 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2120 struct r600_texture
*tex
)
2122 int i
, empty_slot
= -1;
2124 /* Remove zombie textures (textures kept alive by this array only). */
2125 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2126 if (rctx
->dcc_stats
[i
].tex
&&
2127 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2128 vi_dcc_clean_up_context_slot(rctx
, i
);
2130 /* Find the texture. */
2131 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2132 /* Return if found. */
2133 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2134 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2138 /* Record the first seen empty slot. */
2139 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2143 /* Not found. Remove the oldest member to make space in the array. */
2144 if (empty_slot
== -1) {
2145 int oldest_slot
= 0;
2147 /* Find the oldest slot. */
2148 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2149 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2150 rctx
->dcc_stats
[i
].last_use_timestamp
)
2153 /* Clean up the oldest slot. */
2154 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2155 empty_slot
= oldest_slot
;
2158 /* Add the texture to the new slot. */
2159 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2160 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2164 static struct pipe_query
*
2165 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2167 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2168 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2170 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2171 return (struct pipe_query
*)query
;
2175 * Called when binding a color buffer.
2177 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2178 struct r600_texture
*tex
)
2180 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2181 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2183 assert(!rctx
->dcc_stats
[i
].query_active
);
2185 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2186 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2188 /* begin or resume the query */
2189 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2190 rctx
->dcc_stats
[i
].query_active
= true;
2194 * Called when unbinding a color buffer.
2196 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2197 struct r600_texture
*tex
)
2199 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2200 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2202 assert(rctx
->dcc_stats
[i
].query_active
);
2203 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2205 /* pause or end the query */
2206 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2207 rctx
->dcc_stats
[i
].query_active
= false;
2210 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2212 /* The minimum number of fullscreen draws per frame that is required
2214 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2217 /* Called by fast clear. */
2218 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2219 struct r600_texture
*tex
)
2221 /* The intent is to use this with shared displayable back buffers,
2222 * but it's not strictly limited only to them.
2224 if (!tex
->resource
.b
.is_shared
||
2225 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2226 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2227 tex
->resource
.b
.b
.last_level
> 0 ||
2228 !tex
->surface
.dcc_size
)
2231 if (tex
->dcc_offset
)
2232 return; /* already enabled */
2234 /* Enable the DCC stat gathering. */
2235 if (!tex
->dcc_gather_statistics
) {
2236 tex
->dcc_gather_statistics
= true;
2237 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2240 if (!vi_should_enable_separate_dcc(tex
))
2241 return; /* stats show that DCC decompression is too expensive */
2243 assert(tex
->surface
.num_dcc_levels
);
2244 assert(!tex
->dcc_separate_buffer
);
2246 r600_texture_discard_cmask(rctx
->screen
, tex
);
2248 /* Get a DCC buffer. */
2249 if (tex
->last_dcc_separate_buffer
) {
2250 assert(tex
->dcc_gather_statistics
);
2251 assert(!tex
->dcc_separate_buffer
);
2252 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2253 tex
->last_dcc_separate_buffer
= NULL
;
2255 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2256 si_aligned_buffer_create(rctx
->b
.screen
,
2257 R600_RESOURCE_FLAG_UNMAPPABLE
,
2259 tex
->surface
.dcc_size
,
2260 tex
->surface
.dcc_alignment
);
2261 if (!tex
->dcc_separate_buffer
)
2265 /* dcc_offset is the absolute GPUVM address. */
2266 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2268 /* no need to flag anything since this is called by fast clear that
2269 * flags framebuffer state
2274 * Called by pipe_context::flush_resource, the place where DCC decompression
2277 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2278 struct r600_texture
*tex
)
2280 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2281 struct pipe_query
*tmp
;
2282 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2283 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2284 bool disable
= false;
2286 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2287 union pipe_query_result result
;
2289 /* Read the results. */
2290 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2292 si_query_hw_reset_buffers(rctx
,
2293 (struct r600_query_hw
*)
2294 rctx
->dcc_stats
[i
].ps_stats
[2]);
2296 /* Compute the approximate number of fullscreen draws. */
2297 tex
->ps_draw_ratio
=
2298 result
.pipeline_statistics
.ps_invocations
/
2299 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2300 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2302 disable
= tex
->dcc_separate_buffer
&&
2303 !vi_should_enable_separate_dcc(tex
);
2306 tex
->num_slow_clears
= 0;
2308 /* stop the statistics query for ps_stats[0] */
2310 vi_separate_dcc_stop_query(ctx
, tex
);
2312 /* Move the queries in the queue by one. */
2313 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2314 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2315 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2316 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2318 /* create and start a new query as ps_stats[0] */
2320 vi_separate_dcc_start_query(ctx
, tex
);
2323 assert(!tex
->last_dcc_separate_buffer
);
2324 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2325 tex
->dcc_separate_buffer
= NULL
;
2326 tex
->dcc_offset
= 0;
2327 /* no need to flag anything since this is called after
2328 * decompression that re-sets framebuffer state
2333 /* FAST COLOR CLEAR */
2335 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2336 enum pipe_format surface_format
,
2337 const union pipe_color_union
*color
)
2339 union util_color uc
;
2341 memset(&uc
, 0, sizeof(uc
));
2343 if (rtex
->surface
.bpe
== 16) {
2344 /* DCC fast clear only:
2345 * CLEAR_WORD0 = R = G = B
2348 assert(color
->ui
[0] == color
->ui
[1] &&
2349 color
->ui
[0] == color
->ui
[2]);
2350 uc
.ui
[0] = color
->ui
[0];
2351 uc
.ui
[1] = color
->ui
[3];
2352 } else if (util_format_is_pure_uint(surface_format
)) {
2353 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2354 } else if (util_format_is_pure_sint(surface_format
)) {
2355 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2357 util_pack_color(color
->f
, surface_format
, &uc
);
2360 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2363 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2364 const union pipe_color_union
*color
,
2365 uint32_t* reset_value
,
2366 bool* clear_words_needed
)
2368 bool values
[4] = {};
2370 bool main_value
= false;
2371 bool extra_value
= false;
2374 /* This is needed to get the correct DCC clear value for luminance formats.
2375 * 1) Get the linear format (because the next step can't handle L8_SRGB).
2376 * 2) Convert luminance to red. (the real hw format for luminance)
2378 surface_format
= util_format_linear(surface_format
);
2379 surface_format
= util_format_luminance_to_red(surface_format
);
2381 const struct util_format_description
*desc
= util_format_description(surface_format
);
2383 if (desc
->block
.bits
== 128 &&
2384 (color
->ui
[0] != color
->ui
[1] ||
2385 color
->ui
[0] != color
->ui
[2]))
2388 *clear_words_needed
= true;
2389 *reset_value
= 0x20202020U
;
2391 /* If we want to clear without needing a fast clear eliminate step, we
2392 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2393 * have two sets of flags, one for the last or first channel(extra) and
2394 * one for the other channels(main).
2397 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2398 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2399 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
||
2400 util_format_is_alpha(surface_format
)) {
2402 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2403 if(si_translate_colorswap(surface_format
, false) <= 1)
2404 extra_channel
= desc
->nr_channels
- 1;
2410 for (i
= 0; i
< 4; ++i
) {
2411 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2413 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2414 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2417 if (desc
->channel
[i
].pure_integer
&&
2418 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2419 /* Use the maximum value for clamping the clear color. */
2420 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2422 values
[i
] = color
->i
[i
] != 0;
2423 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2425 } else if (desc
->channel
[i
].pure_integer
&&
2426 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2427 /* Use the maximum value for clamping the clear color. */
2428 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2430 values
[i
] = color
->ui
[i
] != 0U;
2431 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2434 values
[i
] = color
->f
[i
] != 0.0F
;
2435 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2439 if (index
== extra_channel
)
2440 extra_value
= values
[i
];
2442 main_value
= values
[i
];
2445 for (int i
= 0; i
< 4; ++i
)
2446 if (values
[i
] != main_value
&&
2447 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2448 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2449 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2452 *clear_words_needed
= false;
2454 *reset_value
|= 0x80808080U
;
2457 *reset_value
|= 0x40404040U
;
2461 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2462 struct r600_texture
*rtex
,
2463 unsigned level
, unsigned clear_value
)
2465 struct pipe_resource
*dcc_buffer
;
2466 uint64_t dcc_offset
, clear_size
;
2468 assert(vi_dcc_enabled(rtex
, level
));
2470 if (rtex
->dcc_separate_buffer
) {
2471 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2474 dcc_buffer
= &rtex
->resource
.b
.b
;
2475 dcc_offset
= rtex
->dcc_offset
;
2478 if (rctx
->chip_class
>= GFX9
) {
2479 /* Mipmap level clears aren't implemented. */
2480 assert(rtex
->resource
.b
.b
.last_level
== 0);
2481 /* MSAA needs a different clear size. */
2482 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2483 clear_size
= rtex
->surface
.dcc_size
;
2485 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2486 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2489 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2490 clear_value
, R600_COHERENCY_CB_META
);
2493 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2494 * This allows hitting the MSAA resolve fast path, which requires that both
2495 * src and dst micro tile modes match.
2497 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2498 struct r600_texture
*rtex
)
2500 if (rtex
->resource
.b
.is_shared
||
2501 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2502 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2505 assert(rscreen
->chip_class
>= GFX9
||
2506 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2507 assert(rtex
->resource
.b
.b
.last_level
== 0);
2509 if (rscreen
->chip_class
>= GFX9
) {
2510 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2511 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2513 /* If you do swizzle_mode % 4, you'll get:
2519 * Depth-sample order isn't allowed:
2521 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2523 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2524 case RADEON_MICRO_MODE_DISPLAY
:
2525 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2526 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2528 case RADEON_MICRO_MODE_THIN
:
2529 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2530 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2532 case RADEON_MICRO_MODE_ROTATED
:
2533 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2534 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2536 default: /* depth */
2537 assert(!"unexpected micro mode");
2540 } else if (rscreen
->chip_class
>= CIK
) {
2541 /* These magic numbers were copied from addrlib. It doesn't use
2542 * any definitions for them either. They are all 2D_TILED_THIN1
2543 * modes with different bpp and micro tile mode.
2545 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2546 case RADEON_MICRO_MODE_DISPLAY
:
2547 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2549 case RADEON_MICRO_MODE_THIN
:
2550 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2552 case RADEON_MICRO_MODE_ROTATED
:
2553 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2555 default: /* depth, thick */
2556 assert(!"unexpected micro mode");
2560 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2561 case RADEON_MICRO_MODE_DISPLAY
:
2562 switch (rtex
->surface
.bpe
) {
2564 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2567 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2570 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2574 case RADEON_MICRO_MODE_THIN
:
2575 switch (rtex
->surface
.bpe
) {
2577 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2580 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2583 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2585 default: /* 8, 16 */
2586 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2590 default: /* depth, thick */
2591 assert(!"unexpected micro mode");
2596 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2598 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2601 void si_do_fast_color_clear(struct r600_common_context
*rctx
,
2602 struct pipe_framebuffer_state
*fb
,
2603 struct r600_atom
*fb_state
,
2604 unsigned *buffers
, ubyte
*dirty_cbufs
,
2605 const union pipe_color_union
*color
)
2609 /* This function is broken in BE, so just disable this path for now */
2610 #ifdef PIPE_ARCH_BIG_ENDIAN
2614 if (rctx
->render_cond
)
2617 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2618 struct r600_texture
*tex
;
2619 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2624 /* if this colorbuffer is not being cleared */
2625 if (!(*buffers
& clear_bit
))
2628 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2630 /* the clear is allowed if all layers are bound */
2631 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2632 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2636 /* cannot clear mipmapped textures */
2637 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2641 /* only supported on tiled surfaces */
2642 if (tex
->surface
.is_linear
) {
2646 /* shared textures can't use fast clear without an explicit flush,
2647 * because there is no way to communicate the clear color among
2650 if (tex
->resource
.b
.is_shared
&&
2651 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2654 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2655 if (rctx
->chip_class
== CIK
&&
2656 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2657 rctx
->screen
->info
.drm_major
== 2 &&
2658 rctx
->screen
->info
.drm_minor
< 38) {
2662 /* Fast clear is the most appropriate place to enable DCC for
2663 * displayable surfaces.
2665 if (rctx
->chip_class
>= VI
&&
2666 !(rctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))) {
2667 vi_separate_dcc_try_enable(rctx
, tex
);
2669 /* RB+ isn't supported with a CMASK clear only on Stoney,
2670 * so all clears are considered to be hypothetically slow
2671 * clears, which is weighed when determining whether to
2672 * enable separate DCC.
2674 if (tex
->dcc_gather_statistics
&&
2675 rctx
->family
== CHIP_STONEY
)
2676 tex
->num_slow_clears
++;
2679 /* Try to clear DCC first, otherwise try CMASK. */
2680 if (vi_dcc_enabled(tex
, 0)) {
2681 uint32_t reset_value
;
2682 bool clear_words_needed
;
2684 if (rctx
->screen
->debug_flags
& DBG(NO_DCC_CLEAR
))
2687 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2688 color
, &reset_value
,
2689 &clear_words_needed
))
2692 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2694 unsigned level_bit
= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2695 if (clear_words_needed
) {
2696 bool need_compressed_update
= !tex
->dirty_level_mask
;
2698 tex
->dirty_level_mask
|= level_bit
;
2700 if (need_compressed_update
)
2701 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2703 tex
->separate_dcc_dirty
= true;
2705 /* 128-bit formats are unusupported */
2706 if (tex
->surface
.bpe
> 8) {
2710 /* RB+ doesn't work with CMASK fast clear on Stoney. */
2711 if (rctx
->family
== CHIP_STONEY
)
2714 /* ensure CMASK is enabled */
2715 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2716 if (tex
->cmask
.size
== 0) {
2720 /* Do the fast clear. */
2721 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2722 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2723 R600_COHERENCY_CB_META
);
2725 bool need_compressed_update
= !tex
->dirty_level_mask
;
2727 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2729 if (need_compressed_update
)
2730 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2733 /* We can change the micro tile mode before a full clear. */
2734 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2736 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2739 *dirty_cbufs
|= 1 << i
;
2740 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2741 *buffers
&= ~clear_bit
;
2745 static struct pipe_memory_object
*
2746 r600_memobj_from_handle(struct pipe_screen
*screen
,
2747 struct winsys_handle
*whandle
,
2750 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2751 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2752 struct pb_buffer
*buf
= NULL
;
2753 uint32_t stride
, offset
;
2758 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
,
2765 memobj
->b
.dedicated
= dedicated
;
2767 memobj
->stride
= stride
;
2768 memobj
->offset
= offset
;
2770 return (struct pipe_memory_object
*)memobj
;
2775 r600_memobj_destroy(struct pipe_screen
*screen
,
2776 struct pipe_memory_object
*_memobj
)
2778 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2780 pb_reference(&memobj
->buf
, NULL
);
2784 static struct pipe_resource
*
2785 r600_texture_from_memobj(struct pipe_screen
*screen
,
2786 const struct pipe_resource
*templ
,
2787 struct pipe_memory_object
*_memobj
,
2791 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2792 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2793 struct r600_texture
*rtex
;
2794 struct radeon_surf surface
= {};
2795 struct radeon_bo_metadata metadata
= {};
2796 enum radeon_surf_mode array_mode
;
2798 struct pb_buffer
*buf
= NULL
;
2800 if (memobj
->b
.dedicated
) {
2801 rscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2802 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
2803 &array_mode
, &is_scanout
);
2806 * The bo metadata is unset for un-dedicated images. So we fall
2807 * back to linear. See answer to question 5 of the
2808 * VK_KHX_external_memory spec for some details.
2810 * It is possible that this case isn't going to work if the
2811 * surface pitch isn't correctly aligned by default.
2813 * In order to support it correctly we require multi-image
2814 * metadata to be syncrhonized between radv and radeonsi. The
2815 * semantics of associating multiple image metadata to a memory
2816 * object on the vulkan export side are not concretely defined
2819 * All the use cases we are aware of at the moment for memory
2820 * objects use dedicated allocations. So lets keep the initial
2821 * implementation simple.
2823 * A possible alternative is to attempt to reconstruct the
2824 * tiling information when the TexParameter TEXTURE_TILING_EXT
2827 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2832 r
= r600_init_surface(rscreen
, &surface
, templ
,
2833 array_mode
, memobj
->stride
,
2834 offset
, true, is_scanout
,
2839 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2843 /* r600_texture_create_object doesn't increment refcount of
2844 * memobj->buf, so increment it here.
2846 pb_reference(&buf
, memobj
->buf
);
2848 rtex
->resource
.b
.is_shared
= true;
2849 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2851 if (rscreen
->apply_opaque_metadata
)
2852 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
2854 return &rtex
->resource
.b
.b
;
2857 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2858 struct pipe_resource
*resource
,
2861 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2863 /* Buffers only support the linear flag. */
2864 if (resource
->target
== PIPE_BUFFER
)
2865 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2867 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2870 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2873 /* TODO: PIPE_BIND_CURSOR - do we care? */
2877 void si_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2879 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2880 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2881 rscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2882 rscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2883 rscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2884 rscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2887 void si_init_context_texture_functions(struct r600_common_context
*rctx
)
2889 rctx
->b
.create_surface
= r600_create_surface
;
2890 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2891 rctx
->b
.clear_texture
= r600_clear_texture
;