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gallium/radeon: eliminate fast color clear before sharing
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static void r600_texture_init_metadata(struct r600_texture *rtex,
232 struct radeon_bo_metadata *metadata)
233 {
234 struct radeon_surf *surface = &rtex->surface;
235
236 memset(metadata, 0, sizeof(*metadata));
237 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
238 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
239 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
240 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
241 metadata->pipe_config = surface->pipe_config;
242 metadata->bankw = surface->bankw;
243 metadata->bankh = surface->bankh;
244 metadata->tile_split = surface->tile_split;
245 metadata->stencil_tile_split = surface->stencil_tile_split;
246 metadata->mtilea = surface->mtilea;
247 metadata->num_banks = surface->num_banks;
248 metadata->stride = surface->level[0].pitch_bytes;
249 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
250 }
251
252 static void r600_eliminate_fast_color_clear(struct r600_common_screen *rscreen,
253 struct r600_texture *rtex)
254 {
255 struct pipe_context *ctx = rscreen->aux_context;
256
257 pipe_mutex_lock(rscreen->aux_context_lock);
258 ctx->flush_resource(ctx, &rtex->resource.b.b);
259 ctx->flush(ctx, NULL, 0);
260 pipe_mutex_unlock(rscreen->aux_context_lock);
261 }
262
263 static boolean r600_texture_get_handle(struct pipe_screen* screen,
264 struct pipe_resource *resource,
265 struct winsys_handle *whandle,
266 unsigned usage)
267 {
268 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
269 struct r600_resource *res = (struct r600_resource*)resource;
270 struct r600_texture *rtex = (struct r600_texture*)resource;
271 struct radeon_bo_metadata metadata;
272
273 /* This is not supported now, but it might be required for OpenCL
274 * interop in the future.
275 */
276 if (resource->target != PIPE_BUFFER &&
277 (resource->nr_samples > 1 || rtex->is_depth))
278 return NULL;
279
280 if (!res->is_shared) {
281 res->is_shared = true;
282 res->external_usage = usage;
283
284 if (resource->target != PIPE_BUFFER) {
285 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
286 /* Eliminate fast clear (both CMASK and DCC) */
287 r600_eliminate_fast_color_clear(rscreen, rtex);
288 }
289
290 r600_texture_init_metadata(rtex, &metadata);
291 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
292 }
293 } else {
294 assert(res->external_usage == usage);
295 }
296
297 return rscreen->ws->buffer_get_handle(res->buf,
298 rtex->surface.level[0].pitch_bytes,
299 whandle);
300 }
301
302 static void r600_texture_destroy(struct pipe_screen *screen,
303 struct pipe_resource *ptex)
304 {
305 struct r600_texture *rtex = (struct r600_texture*)ptex;
306 struct r600_resource *resource = &rtex->resource;
307
308 if (rtex->flushed_depth_texture)
309 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
310
311 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
312 if (rtex->cmask_buffer != &rtex->resource) {
313 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
314 }
315 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
316 pb_reference(&resource->buf, NULL);
317 FREE(rtex);
318 }
319
320 static const struct u_resource_vtbl r600_texture_vtbl;
321
322 /* The number of samples can be specified independently of the texture. */
323 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
324 struct r600_texture *rtex,
325 unsigned nr_samples,
326 struct r600_fmask_info *out)
327 {
328 /* FMASK is allocated like an ordinary texture. */
329 struct radeon_surf fmask = rtex->surface;
330
331 memset(out, 0, sizeof(*out));
332
333 fmask.bo_alignment = 0;
334 fmask.bo_size = 0;
335 fmask.nsamples = 1;
336 fmask.flags |= RADEON_SURF_FMASK;
337
338 /* Force 2D tiling if it wasn't set. This may occur when creating
339 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
340 * destination buffer must have an FMASK too. */
341 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
342 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
343
344 if (rscreen->chip_class >= SI) {
345 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
346 }
347
348 switch (nr_samples) {
349 case 2:
350 case 4:
351 fmask.bpe = 1;
352 if (rscreen->chip_class <= CAYMAN) {
353 fmask.bankh = 4;
354 }
355 break;
356 case 8:
357 fmask.bpe = 4;
358 break;
359 default:
360 R600_ERR("Invalid sample count for FMASK allocation.\n");
361 return;
362 }
363
364 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
365 * This can be fixed by writing a separate FMASK allocator specifically
366 * for R600-R700 asics. */
367 if (rscreen->chip_class <= R700) {
368 fmask.bpe *= 2;
369 }
370
371 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
372 R600_ERR("Got error in surface_init while allocating FMASK.\n");
373 return;
374 }
375
376 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
377
378 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
379 if (out->slice_tile_max)
380 out->slice_tile_max -= 1;
381
382 out->tile_mode_index = fmask.tiling_index[0];
383 out->pitch_in_pixels = fmask.level[0].nblk_x;
384 out->bank_height = fmask.bankh;
385 out->alignment = MAX2(256, fmask.bo_alignment);
386 out->size = fmask.bo_size;
387 }
388
389 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
390 struct r600_texture *rtex)
391 {
392 r600_texture_get_fmask_info(rscreen, rtex,
393 rtex->resource.b.b.nr_samples, &rtex->fmask);
394
395 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
396 rtex->size = rtex->fmask.offset + rtex->fmask.size;
397 }
398
399 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
400 struct r600_texture *rtex,
401 struct r600_cmask_info *out)
402 {
403 unsigned cmask_tile_width = 8;
404 unsigned cmask_tile_height = 8;
405 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
406 unsigned element_bits = 4;
407 unsigned cmask_cache_bits = 1024;
408 unsigned num_pipes = rscreen->info.num_tile_pipes;
409 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
410
411 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
412 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
413 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
414 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
415 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
416
417 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
418 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
419
420 unsigned base_align = num_pipes * pipe_interleave_bytes;
421 unsigned slice_bytes =
422 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
423
424 assert(macro_tile_width % 128 == 0);
425 assert(macro_tile_height % 128 == 0);
426
427 out->pitch = pitch_elements;
428 out->height = height;
429 out->xalign = macro_tile_width;
430 out->yalign = macro_tile_height;
431 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
432 out->alignment = MAX2(256, base_align);
433 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
434 align(slice_bytes, base_align);
435 }
436
437 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
438 struct r600_texture *rtex,
439 struct r600_cmask_info *out)
440 {
441 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
442 unsigned num_pipes = rscreen->info.num_tile_pipes;
443 unsigned cl_width, cl_height;
444
445 switch (num_pipes) {
446 case 2:
447 cl_width = 32;
448 cl_height = 16;
449 break;
450 case 4:
451 cl_width = 32;
452 cl_height = 32;
453 break;
454 case 8:
455 cl_width = 64;
456 cl_height = 32;
457 break;
458 case 16: /* Hawaii */
459 cl_width = 64;
460 cl_height = 64;
461 break;
462 default:
463 assert(0);
464 return;
465 }
466
467 unsigned base_align = num_pipes * pipe_interleave_bytes;
468
469 unsigned width = align(rtex->surface.npix_x, cl_width*8);
470 unsigned height = align(rtex->surface.npix_y, cl_height*8);
471 unsigned slice_elements = (width * height) / (8*8);
472
473 /* Each element of CMASK is a nibble. */
474 unsigned slice_bytes = slice_elements / 2;
475
476 out->pitch = width;
477 out->height = height;
478 out->xalign = cl_width * 8;
479 out->yalign = cl_height * 8;
480 out->slice_tile_max = (width * height) / (128*128);
481 if (out->slice_tile_max)
482 out->slice_tile_max -= 1;
483
484 out->alignment = MAX2(256, base_align);
485 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
486 align(slice_bytes, base_align);
487 }
488
489 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
490 struct r600_texture *rtex)
491 {
492 if (rscreen->chip_class >= SI) {
493 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
494 } else {
495 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
496 }
497
498 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
499 rtex->size = rtex->cmask.offset + rtex->cmask.size;
500
501 if (rscreen->chip_class >= SI)
502 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
503 else
504 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
505 }
506
507 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
508 struct r600_texture *rtex)
509 {
510 if (rtex->cmask_buffer)
511 return;
512
513 assert(rtex->cmask.size == 0);
514
515 if (rscreen->chip_class >= SI) {
516 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
517 } else {
518 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
519 }
520
521 rtex->cmask_buffer = (struct r600_resource *)
522 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
523 PIPE_USAGE_DEFAULT, rtex->cmask.size);
524 if (rtex->cmask_buffer == NULL) {
525 rtex->cmask.size = 0;
526 return;
527 }
528
529 /* update colorbuffer state bits */
530 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
531
532 if (rscreen->chip_class >= SI)
533 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
534 else
535 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
536 }
537
538 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
539 struct r600_texture *rtex)
540 {
541 if (rscreen->debug_flags & DBG_NO_DCC)
542 return;
543
544 rtex->dcc_buffer = (struct r600_resource *)
545 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
546 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
547 if (rtex->dcc_buffer == NULL) {
548 return;
549 }
550
551 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
552 0xFFFFFFFF, true);
553
554 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
555 }
556
557 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
558 struct r600_texture *rtex)
559 {
560 unsigned cl_width, cl_height, width, height;
561 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
562 unsigned num_pipes = rscreen->info.num_tile_pipes;
563
564 if (rscreen->chip_class <= EVERGREEN &&
565 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
566 return 0;
567
568 /* HW bug on R6xx. */
569 if (rscreen->chip_class == R600 &&
570 (rtex->surface.level[0].npix_x > 7680 ||
571 rtex->surface.level[0].npix_y > 7680))
572 return 0;
573
574 /* HTILE is broken with 1D tiling on old kernels and CIK. */
575 if (rscreen->chip_class >= CIK &&
576 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
577 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
578 return 0;
579
580 /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
581 if (rscreen->family == CHIP_STONEY)
582 num_pipes = 4;
583
584 switch (num_pipes) {
585 case 1:
586 cl_width = 32;
587 cl_height = 16;
588 break;
589 case 2:
590 cl_width = 32;
591 cl_height = 32;
592 break;
593 case 4:
594 cl_width = 64;
595 cl_height = 32;
596 break;
597 case 8:
598 cl_width = 64;
599 cl_height = 64;
600 break;
601 case 16:
602 cl_width = 128;
603 cl_height = 64;
604 break;
605 default:
606 assert(0);
607 return 0;
608 }
609
610 width = align(rtex->surface.npix_x, cl_width * 8);
611 height = align(rtex->surface.npix_y, cl_height * 8);
612
613 slice_elements = (width * height) / (8 * 8);
614 slice_bytes = slice_elements * 4;
615
616 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
617 base_align = num_pipes * pipe_interleave_bytes;
618
619 rtex->htile.pitch = width;
620 rtex->htile.height = height;
621 rtex->htile.xalign = cl_width * 8;
622 rtex->htile.yalign = cl_height * 8;
623
624 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
625 align(slice_bytes, base_align);
626 }
627
628 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
629 struct r600_texture *rtex)
630 {
631 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
632
633 if (!htile_size)
634 return;
635
636 rtex->htile_buffer = (struct r600_resource*)
637 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
638 PIPE_USAGE_DEFAULT, htile_size);
639 if (rtex->htile_buffer == NULL) {
640 /* this is not a fatal error as we can still keep rendering
641 * without htile buffer */
642 R600_ERR("Failed to create buffer object for htile buffer.\n");
643 } else {
644 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
645 htile_size, 0, true);
646 }
647 }
648
649 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
650 {
651 int i;
652
653 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
654 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
655 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
656 rtex->surface.npix_x, rtex->surface.npix_y,
657 rtex->surface.npix_z, rtex->surface.blk_w,
658 rtex->surface.blk_h, rtex->surface.blk_d,
659 rtex->surface.array_size, rtex->surface.last_level,
660 rtex->surface.bpe, rtex->surface.nsamples,
661 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
662
663 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
664 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
665 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
666 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
667 rtex->surface.tile_split, rtex->surface.pipe_config,
668 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
669
670 if (rtex->fmask.size)
671 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
672 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
673 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
674 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
675 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
676
677 if (rtex->cmask.size)
678 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
679 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
680 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
681 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
682 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
683
684 if (rtex->htile_buffer)
685 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
686 "xalign=%u, yalign=%u\n",
687 rtex->htile_buffer->b.b.width0,
688 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
689 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
690
691 if (rtex->dcc_buffer) {
692 fprintf(f, " DCC: size=%u, alignment=%u\n",
693 rtex->dcc_buffer->b.b.width0,
694 rtex->dcc_buffer->buf->alignment);
695 for (i = 0; i <= rtex->surface.last_level; i++)
696 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
697 i, rtex->surface.level[i].dcc_offset);
698 }
699
700 for (i = 0; i <= rtex->surface.last_level; i++)
701 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
702 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
703 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
704 i, rtex->surface.level[i].offset,
705 rtex->surface.level[i].slice_size,
706 u_minify(rtex->resource.b.b.width0, i),
707 u_minify(rtex->resource.b.b.height0, i),
708 u_minify(rtex->resource.b.b.depth0, i),
709 rtex->surface.level[i].nblk_x,
710 rtex->surface.level[i].nblk_y,
711 rtex->surface.level[i].nblk_z,
712 rtex->surface.level[i].pitch_bytes,
713 rtex->surface.level[i].mode);
714
715 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
716 for (i = 0; i <= rtex->surface.last_level; i++) {
717 fprintf(f, " StencilLayout: tilesplit=%u\n",
718 rtex->surface.stencil_tile_split);
719 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
720 "slice_size=%"PRIu64", npix_x=%u, "
721 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
722 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
723 i, rtex->surface.stencil_level[i].offset,
724 rtex->surface.stencil_level[i].slice_size,
725 u_minify(rtex->resource.b.b.width0, i),
726 u_minify(rtex->resource.b.b.height0, i),
727 u_minify(rtex->resource.b.b.depth0, i),
728 rtex->surface.stencil_level[i].nblk_x,
729 rtex->surface.stencil_level[i].nblk_y,
730 rtex->surface.stencil_level[i].nblk_z,
731 rtex->surface.stencil_level[i].pitch_bytes,
732 rtex->surface.stencil_level[i].mode);
733 }
734 }
735 }
736
737 /* Common processing for r600_texture_create and r600_texture_from_handle */
738 static struct r600_texture *
739 r600_texture_create_object(struct pipe_screen *screen,
740 const struct pipe_resource *base,
741 unsigned pitch_in_bytes_override,
742 struct pb_buffer *buf,
743 struct radeon_surf *surface)
744 {
745 struct r600_texture *rtex;
746 struct r600_resource *resource;
747 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
748
749 rtex = CALLOC_STRUCT(r600_texture);
750 if (!rtex)
751 return NULL;
752
753 resource = &rtex->resource;
754 resource->b.b = *base;
755 resource->b.vtbl = &r600_texture_vtbl;
756 pipe_reference_init(&resource->b.b.reference, 1);
757 resource->b.b.screen = screen;
758
759 /* don't include stencil-only formats which we don't support for rendering */
760 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
761
762 rtex->surface = *surface;
763 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
764 FREE(rtex);
765 return NULL;
766 }
767
768 /* Tiled depth textures utilize the non-displayable tile order.
769 * This must be done after r600_setup_surface.
770 * Applies to R600-Cayman. */
771 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
772
773 if (rtex->is_depth) {
774 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
775 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
776 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
777
778 r600_texture_allocate_htile(rscreen, rtex);
779 }
780 } else {
781 if (base->nr_samples > 1) {
782 if (!buf) {
783 r600_texture_allocate_fmask(rscreen, rtex);
784 r600_texture_allocate_cmask(rscreen, rtex);
785 rtex->cmask_buffer = &rtex->resource;
786 }
787 if (!rtex->fmask.size || !rtex->cmask.size) {
788 FREE(rtex);
789 return NULL;
790 }
791 }
792 if (rtex->surface.dcc_size)
793 vi_texture_alloc_dcc_separate(rscreen, rtex);
794 }
795
796 /* Now create the backing buffer. */
797 if (!buf) {
798 if (!r600_init_resource(rscreen, resource, rtex->size,
799 rtex->surface.bo_alignment, TRUE)) {
800 FREE(rtex);
801 return NULL;
802 }
803 } else {
804 resource->buf = buf;
805 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
806 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
807 }
808
809 if (rtex->cmask.size) {
810 /* Initialize the cmask to 0xCC (= compressed state). */
811 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
812 rtex->cmask.offset, rtex->cmask.size,
813 0xCCCCCCCC, true);
814 }
815
816 /* Initialize the CMASK base register value. */
817 rtex->cmask.base_address_reg =
818 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
819
820 if (rscreen->debug_flags & DBG_VM) {
821 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
822 rtex->resource.gpu_address,
823 rtex->resource.gpu_address + rtex->resource.buf->size,
824 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
825 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
826 }
827
828 if (rscreen->debug_flags & DBG_TEX) {
829 puts("Texture:");
830 r600_print_texture_info(rtex, stdout);
831 }
832
833 return rtex;
834 }
835
836 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
837 const struct pipe_resource *templ)
838 {
839 const struct util_format_description *desc = util_format_description(templ->format);
840 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
841
842 /* MSAA resources must be 2D tiled. */
843 if (templ->nr_samples > 1)
844 return RADEON_SURF_MODE_2D;
845
846 /* Transfer resources should be linear. */
847 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
848 return RADEON_SURF_MODE_LINEAR_ALIGNED;
849
850 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
851 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
852 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
853 (templ->target == PIPE_TEXTURE_2D ||
854 templ->target == PIPE_TEXTURE_3D))
855 force_tiling = true;
856
857 /* Handle common candidates for the linear mode.
858 * Compressed textures must always be tiled. */
859 if (!force_tiling && !util_format_is_compressed(templ->format)) {
860 /* Not everything can be linear, so we cannot enforce it
861 * for all textures. */
862 if ((rscreen->debug_flags & DBG_NO_TILING) &&
863 (!util_format_is_depth_or_stencil(templ->format) ||
864 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
865 return RADEON_SURF_MODE_LINEAR_ALIGNED;
866
867 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
868 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
869 return RADEON_SURF_MODE_LINEAR_ALIGNED;
870
871 /* Cursors are linear on SI.
872 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
873 if (rscreen->chip_class >= SI &&
874 (templ->bind & PIPE_BIND_CURSOR))
875 return RADEON_SURF_MODE_LINEAR_ALIGNED;
876
877 if (templ->bind & PIPE_BIND_LINEAR)
878 return RADEON_SURF_MODE_LINEAR_ALIGNED;
879
880 /* Textures with a very small height are recommended to be linear. */
881 if (templ->target == PIPE_TEXTURE_1D ||
882 templ->target == PIPE_TEXTURE_1D_ARRAY ||
883 templ->height0 <= 4)
884 return RADEON_SURF_MODE_LINEAR_ALIGNED;
885
886 /* Textures likely to be mapped often. */
887 if (templ->usage == PIPE_USAGE_STAGING ||
888 templ->usage == PIPE_USAGE_STREAM)
889 return RADEON_SURF_MODE_LINEAR_ALIGNED;
890 }
891
892 /* Make small textures 1D tiled. */
893 if (templ->width0 <= 16 || templ->height0 <= 16 ||
894 (rscreen->debug_flags & DBG_NO_2D_TILING))
895 return RADEON_SURF_MODE_1D;
896
897 /* The allocator will switch to 1D if needed. */
898 return RADEON_SURF_MODE_2D;
899 }
900
901 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
902 const struct pipe_resource *templ)
903 {
904 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
905 struct radeon_surf surface = {0};
906 int r;
907
908 r = r600_init_surface(rscreen, &surface, templ,
909 r600_choose_tiling(rscreen, templ),
910 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
911 if (r) {
912 return NULL;
913 }
914 r = rscreen->ws->surface_best(rscreen->ws, &surface);
915 if (r) {
916 return NULL;
917 }
918 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
919 0, NULL, &surface);
920 }
921
922 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
923 const struct pipe_resource *templ,
924 struct winsys_handle *whandle,
925 unsigned usage)
926 {
927 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
928 struct pb_buffer *buf = NULL;
929 unsigned stride = 0;
930 unsigned array_mode;
931 struct radeon_surf surface;
932 int r;
933 struct radeon_bo_metadata metadata = {};
934 struct r600_texture *rtex;
935
936 /* Support only 2D textures without mipmaps */
937 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
938 templ->depth0 != 1 || templ->last_level != 0)
939 return NULL;
940
941 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
942 if (!buf)
943 return NULL;
944
945 rscreen->ws->buffer_get_metadata(buf, &metadata);
946
947 surface.bankw = metadata.bankw;
948 surface.bankh = metadata.bankh;
949 surface.tile_split = metadata.tile_split;
950 surface.stencil_tile_split = metadata.stencil_tile_split;
951 surface.mtilea = metadata.mtilea;
952
953 if (metadata.macrotile == RADEON_LAYOUT_TILED)
954 array_mode = RADEON_SURF_MODE_2D;
955 else if (metadata.microtile == RADEON_LAYOUT_TILED)
956 array_mode = RADEON_SURF_MODE_1D;
957 else
958 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
959
960 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
961 if (r) {
962 return NULL;
963 }
964
965 if (metadata.scanout)
966 surface.flags |= RADEON_SURF_SCANOUT;
967
968 rtex = r600_texture_create_object(screen, templ,
969 stride, buf, &surface);
970 if (!rtex)
971 return NULL;
972
973 rtex->resource.is_shared = true;
974 rtex->resource.external_usage = usage;
975 return &rtex->resource.b.b;
976 }
977
978 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
979 struct pipe_resource *texture,
980 struct r600_texture **staging)
981 {
982 struct r600_texture *rtex = (struct r600_texture*)texture;
983 struct pipe_resource resource;
984 struct r600_texture **flushed_depth_texture = staging ?
985 staging : &rtex->flushed_depth_texture;
986
987 if (!staging && rtex->flushed_depth_texture)
988 return true; /* it's ready */
989
990 resource.target = texture->target;
991 resource.format = texture->format;
992 resource.width0 = texture->width0;
993 resource.height0 = texture->height0;
994 resource.depth0 = texture->depth0;
995 resource.array_size = texture->array_size;
996 resource.last_level = texture->last_level;
997 resource.nr_samples = texture->nr_samples;
998 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
999 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1000 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1001
1002 if (staging)
1003 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1004
1005 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1006 if (*flushed_depth_texture == NULL) {
1007 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1008 return false;
1009 }
1010
1011 (*flushed_depth_texture)->is_flushing_texture = TRUE;
1012 (*flushed_depth_texture)->non_disp_tiling = false;
1013 return true;
1014 }
1015
1016 /**
1017 * Initialize the pipe_resource descriptor to be of the same size as the box,
1018 * which is supposed to hold a subregion of the texture "orig" at the given
1019 * mipmap level.
1020 */
1021 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1022 struct pipe_resource *orig,
1023 const struct pipe_box *box,
1024 unsigned level, unsigned flags)
1025 {
1026 memset(res, 0, sizeof(*res));
1027 res->format = orig->format;
1028 res->width0 = box->width;
1029 res->height0 = box->height;
1030 res->depth0 = 1;
1031 res->array_size = 1;
1032 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1033 res->flags = flags;
1034
1035 /* We must set the correct texture target and dimensions for a 3D box. */
1036 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1037 res->target = orig->target;
1038 else
1039 res->target = PIPE_TEXTURE_2D;
1040
1041 switch (res->target) {
1042 case PIPE_TEXTURE_1D_ARRAY:
1043 case PIPE_TEXTURE_2D_ARRAY:
1044 case PIPE_TEXTURE_CUBE_ARRAY:
1045 res->array_size = box->depth;
1046 break;
1047 case PIPE_TEXTURE_3D:
1048 res->depth0 = box->depth;
1049 break;
1050 default:;
1051 }
1052 }
1053
1054 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1055 struct pipe_resource *texture,
1056 unsigned level,
1057 unsigned usage,
1058 const struct pipe_box *box,
1059 struct pipe_transfer **ptransfer)
1060 {
1061 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1062 struct r600_texture *rtex = (struct r600_texture*)texture;
1063 struct r600_transfer *trans;
1064 boolean use_staging_texture = FALSE;
1065 struct r600_resource *buf;
1066 unsigned offset = 0;
1067 char *map;
1068
1069 /* We cannot map a tiled texture directly because the data is
1070 * in a different order, therefore we do detiling using a blit.
1071 *
1072 * Also, use a temporary in GTT memory for read transfers, as
1073 * the CPU is much happier reading out of cached system memory
1074 * than uncached VRAM.
1075 */
1076 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1077 use_staging_texture = TRUE;
1078 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1079 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1080 /* Untiled buffers in VRAM, which is slow for CPU reads */
1081 use_staging_texture = TRUE;
1082 } else if (!(usage & PIPE_TRANSFER_READ) &&
1083 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1084 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1085 /* Use a staging texture for uploads if the underlying BO is busy. */
1086 use_staging_texture = TRUE;
1087 }
1088
1089 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1090 use_staging_texture = FALSE;
1091 }
1092
1093 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1094 return NULL;
1095 }
1096
1097 trans = CALLOC_STRUCT(r600_transfer);
1098 if (!trans)
1099 return NULL;
1100 trans->transfer.resource = texture;
1101 trans->transfer.level = level;
1102 trans->transfer.usage = usage;
1103 trans->transfer.box = *box;
1104
1105 if (rtex->is_depth) {
1106 struct r600_texture *staging_depth;
1107
1108 if (rtex->resource.b.b.nr_samples > 1) {
1109 /* MSAA depth buffers need to be converted to single sample buffers.
1110 *
1111 * Mapping MSAA depth buffers can occur if ReadPixels is called
1112 * with a multisample GLX visual.
1113 *
1114 * First downsample the depth buffer to a temporary texture,
1115 * then decompress the temporary one to staging.
1116 *
1117 * Only the region being mapped is transfered.
1118 */
1119 struct pipe_resource resource;
1120
1121 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1122
1123 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1124 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1125 FREE(trans);
1126 return NULL;
1127 }
1128
1129 if (usage & PIPE_TRANSFER_READ) {
1130 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1131 if (!temp) {
1132 R600_ERR("failed to create a temporary depth texture\n");
1133 FREE(trans);
1134 return NULL;
1135 }
1136
1137 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1138 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1139 0, 0, 0, box->depth, 0, 0);
1140 pipe_resource_reference(&temp, NULL);
1141 }
1142 }
1143 else {
1144 /* XXX: only readback the rectangle which is being mapped? */
1145 /* XXX: when discard is true, no need to read back from depth texture */
1146 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1147 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1148 FREE(trans);
1149 return NULL;
1150 }
1151
1152 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1153 level, level,
1154 box->z, box->z + box->depth - 1,
1155 0, 0);
1156
1157 offset = r600_texture_get_offset(staging_depth, level, box);
1158 }
1159
1160 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1161 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1162 trans->staging = (struct r600_resource*)staging_depth;
1163 } else if (use_staging_texture) {
1164 struct pipe_resource resource;
1165 struct r600_texture *staging;
1166
1167 r600_init_temp_resource_from_box(&resource, texture, box, level,
1168 R600_RESOURCE_FLAG_TRANSFER);
1169 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1170 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1171
1172 /* Create the temporary texture. */
1173 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1174 if (!staging) {
1175 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1176 FREE(trans);
1177 return NULL;
1178 }
1179 trans->staging = &staging->resource;
1180 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1181 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1182 if (usage & PIPE_TRANSFER_READ) {
1183 r600_copy_to_staging_texture(ctx, trans);
1184 }
1185 } else {
1186 /* the resource is mapped directly */
1187 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1188 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1189 offset = r600_texture_get_offset(rtex, level, box);
1190 }
1191
1192 if (trans->staging) {
1193 buf = trans->staging;
1194 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1195 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1196 } else {
1197 buf = &rtex->resource;
1198 }
1199
1200 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1201 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1202 FREE(trans);
1203 return NULL;
1204 }
1205
1206 *ptransfer = &trans->transfer;
1207 return map + offset;
1208 }
1209
1210 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1211 struct pipe_transfer* transfer)
1212 {
1213 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1214 struct pipe_resource *texture = transfer->resource;
1215 struct r600_texture *rtex = (struct r600_texture*)texture;
1216
1217 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1218 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1219 ctx->resource_copy_region(ctx, texture, transfer->level,
1220 transfer->box.x, transfer->box.y, transfer->box.z,
1221 &rtransfer->staging->b.b, transfer->level,
1222 &transfer->box);
1223 } else {
1224 r600_copy_from_staging_texture(ctx, rtransfer);
1225 }
1226 }
1227
1228 if (rtransfer->staging)
1229 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1230
1231 FREE(transfer);
1232 }
1233
1234 static const struct u_resource_vtbl r600_texture_vtbl =
1235 {
1236 NULL, /* get_handle */
1237 r600_texture_destroy, /* resource_destroy */
1238 r600_texture_transfer_map, /* transfer_map */
1239 u_default_transfer_flush_region, /* transfer_flush_region */
1240 r600_texture_transfer_unmap, /* transfer_unmap */
1241 NULL /* transfer_inline_write */
1242 };
1243
1244 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1245 struct pipe_resource *texture,
1246 const struct pipe_surface *templ,
1247 unsigned width, unsigned height)
1248 {
1249 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1250
1251 if (!surface)
1252 return NULL;
1253
1254 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1255 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1256
1257 pipe_reference_init(&surface->base.reference, 1);
1258 pipe_resource_reference(&surface->base.texture, texture);
1259 surface->base.context = pipe;
1260 surface->base.format = templ->format;
1261 surface->base.width = width;
1262 surface->base.height = height;
1263 surface->base.u = templ->u;
1264 return &surface->base;
1265 }
1266
1267 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1268 struct pipe_resource *tex,
1269 const struct pipe_surface *templ)
1270 {
1271 unsigned level = templ->u.tex.level;
1272 unsigned width = u_minify(tex->width0, level);
1273 unsigned height = u_minify(tex->height0, level);
1274
1275 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1276 const struct util_format_description *tex_desc
1277 = util_format_description(tex->format);
1278 const struct util_format_description *templ_desc
1279 = util_format_description(templ->format);
1280
1281 assert(tex_desc->block.bits == templ_desc->block.bits);
1282
1283 /* Adjust size of surface if and only if the block width or
1284 * height is changed. */
1285 if (tex_desc->block.width != templ_desc->block.width ||
1286 tex_desc->block.height != templ_desc->block.height) {
1287 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1288 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1289
1290 width = nblks_x * templ_desc->block.width;
1291 height = nblks_y * templ_desc->block.height;
1292 }
1293 }
1294
1295 return r600_create_surface_custom(pipe, tex, templ, width, height);
1296 }
1297
1298 static void r600_surface_destroy(struct pipe_context *pipe,
1299 struct pipe_surface *surface)
1300 {
1301 struct r600_surface *surf = (struct r600_surface*)surface;
1302 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1303 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1304 pipe_resource_reference(&surface->texture, NULL);
1305 FREE(surface);
1306 }
1307
1308 unsigned r600_translate_colorswap(enum pipe_format format)
1309 {
1310 const struct util_format_description *desc = util_format_description(format);
1311
1312 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1313
1314 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1315 return V_0280A0_SWAP_STD;
1316
1317 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1318 return ~0U;
1319
1320 switch (desc->nr_channels) {
1321 case 1:
1322 if (HAS_SWIZZLE(0,X))
1323 return V_0280A0_SWAP_STD; /* X___ */
1324 else if (HAS_SWIZZLE(3,X))
1325 return V_0280A0_SWAP_ALT_REV; /* ___X */
1326 break;
1327 case 2:
1328 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1329 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1330 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1331 return V_0280A0_SWAP_STD; /* XY__ */
1332 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1333 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1334 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1335 return V_0280A0_SWAP_STD_REV; /* YX__ */
1336 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1337 return V_0280A0_SWAP_ALT; /* X__Y */
1338 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1339 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1340 break;
1341 case 3:
1342 if (HAS_SWIZZLE(0,X))
1343 return V_0280A0_SWAP_STD; /* XYZ */
1344 else if (HAS_SWIZZLE(0,Z))
1345 return V_0280A0_SWAP_STD_REV; /* ZYX */
1346 break;
1347 case 4:
1348 /* check the middle channels, the 1st and 4th channel can be NONE */
1349 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1350 return V_0280A0_SWAP_STD; /* XYZW */
1351 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1352 return V_0280A0_SWAP_STD_REV; /* WZYX */
1353 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1354 return V_0280A0_SWAP_ALT; /* ZYXW */
1355 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
1356 return V_0280A0_SWAP_ALT_REV; /* YZWX */
1357 break;
1358 }
1359 return ~0U;
1360 }
1361
1362 static void evergreen_set_clear_color(struct r600_texture *rtex,
1363 enum pipe_format surface_format,
1364 const union pipe_color_union *color)
1365 {
1366 union util_color uc;
1367
1368 memset(&uc, 0, sizeof(uc));
1369
1370 if (util_format_is_pure_uint(surface_format)) {
1371 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1372 } else if (util_format_is_pure_sint(surface_format)) {
1373 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1374 } else {
1375 util_pack_color(color->f, surface_format, &uc);
1376 }
1377
1378 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1379 }
1380
1381 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1382 const union pipe_color_union *color,
1383 uint32_t* reset_value,
1384 bool* clear_words_needed)
1385 {
1386 bool values[4] = {};
1387 int i;
1388 bool main_value = false;
1389 bool extra_value = false;
1390 int extra_channel;
1391 const struct util_format_description *desc = util_format_description(surface_format);
1392
1393 *clear_words_needed = true;
1394 *reset_value = 0x20202020U;
1395
1396 /* If we want to clear without needing a fast clear eliminate step, we
1397 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1398 * have two sets of flags, one for the last or first channel(extra) and
1399 * one for the other channels(main).
1400 */
1401
1402 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1403 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1404 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1405 extra_channel = -1;
1406 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1407 if(r600_translate_colorswap(surface_format) <= 1)
1408 extra_channel = desc->nr_channels - 1;
1409 else
1410 extra_channel = 0;
1411 } else
1412 return;
1413
1414 for (i = 0; i < 4; ++i) {
1415 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1416
1417 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1418 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1419 continue;
1420
1421 if (util_format_is_pure_sint(surface_format)) {
1422 values[i] = color->i[i] != 0;
1423 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1424 return;
1425 } else if (util_format_is_pure_uint(surface_format)) {
1426 values[i] = color->ui[i] != 0U;
1427 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1428 return;
1429 } else {
1430 values[i] = color->f[i] != 0.0F;
1431 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1432 return;
1433 }
1434
1435 if (index == extra_channel)
1436 extra_value = values[i];
1437 else
1438 main_value = values[i];
1439 }
1440
1441 for (int i = 0; i < 4; ++i)
1442 if (values[i] != main_value &&
1443 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1444 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1445 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1446 return;
1447
1448 *clear_words_needed = false;
1449 if (main_value)
1450 *reset_value |= 0x80808080U;
1451
1452 if (extra_value)
1453 *reset_value |= 0x40404040U;
1454 }
1455
1456 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1457 struct pipe_framebuffer_state *fb,
1458 struct r600_atom *fb_state,
1459 unsigned *buffers, unsigned *dirty_cbufs,
1460 const union pipe_color_union *color)
1461 {
1462 int i;
1463
1464 /* This function is broken in BE, so just disable this path for now */
1465 #ifdef PIPE_ARCH_BIG_ENDIAN
1466 return;
1467 #endif
1468
1469 if (rctx->render_cond)
1470 return;
1471
1472 for (i = 0; i < fb->nr_cbufs; i++) {
1473 struct r600_texture *tex;
1474 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1475
1476 if (!fb->cbufs[i])
1477 continue;
1478
1479 /* if this colorbuffer is not being cleared */
1480 if (!(*buffers & clear_bit))
1481 continue;
1482
1483 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1484
1485 /* 128-bit formats are unusupported */
1486 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1487 continue;
1488 }
1489
1490 /* the clear is allowed if all layers are bound */
1491 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1492 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1493 continue;
1494 }
1495
1496 /* cannot clear mipmapped textures */
1497 if (fb->cbufs[i]->texture->last_level != 0) {
1498 continue;
1499 }
1500
1501 /* only supported on tiled surfaces */
1502 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1503 continue;
1504 }
1505
1506 /* shared textures can't use fast clear without an explicit flush,
1507 * because there is no way to communicate the clear color among
1508 * all clients
1509 */
1510 if (tex->resource.is_shared &&
1511 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1512 continue;
1513
1514 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1515 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1516 rctx->chip_class >= CIK &&
1517 rctx->screen->info.drm_major == 2 &&
1518 rctx->screen->info.drm_minor < 38) {
1519 continue;
1520 }
1521
1522 if (tex->dcc_buffer) {
1523 uint32_t reset_value;
1524 bool clear_words_needed;
1525
1526 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1527 continue;
1528
1529 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1530
1531 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1532 0, tex->surface.dcc_size, reset_value, true);
1533
1534 if (clear_words_needed)
1535 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1536 } else {
1537 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1538 if (rctx->family == CHIP_STONEY)
1539 continue;
1540
1541 /* ensure CMASK is enabled */
1542 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1543 if (tex->cmask.size == 0) {
1544 continue;
1545 }
1546
1547 /* Do the fast clear. */
1548 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1549 tex->cmask.offset, tex->cmask.size, 0, true);
1550
1551 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1552 }
1553
1554 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1555
1556 if (dirty_cbufs)
1557 *dirty_cbufs |= 1 << i;
1558 rctx->set_atom_dirty(rctx, fb_state, true);
1559 *buffers &= ~clear_bit;
1560 }
1561 }
1562
1563 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1564 {
1565 rscreen->b.resource_from_handle = r600_texture_from_handle;
1566 rscreen->b.resource_get_handle = r600_texture_get_handle;
1567 }
1568
1569 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1570 {
1571 rctx->b.create_surface = r600_create_surface;
1572 rctx->b.surface_destroy = r600_surface_destroy;
1573 }