2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "radeonsi/si_pipe.h"
26 #include "r600_query.h"
27 #include "util/u_format.h"
28 #include "util/u_log.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/u_resource.h"
32 #include "util/u_surface.h"
33 #include "util/os_time.h"
36 #include "state_tracker/drm_driver.h"
37 #include "amd/common/sid.h"
39 static void r600_texture_discard_cmask(struct si_screen
*sscreen
,
40 struct r600_texture
*rtex
);
41 static enum radeon_surf_mode
42 r600_choose_tiling(struct si_screen
*sscreen
,
43 const struct pipe_resource
*templ
);
46 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
47 struct r600_texture
*rdst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct r600_texture
*rsrc
,
52 const struct pipe_box
*src_box
)
57 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
62 rdst
->resource
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (rsrc
->is_depth
|| rdst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if (vi_dcc_enabled(rsrc
, src_level
) ||
77 vi_dcc_enabled(rdst
, dst_level
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 r600_texture_discard_cmask(rctx
->screen
, rdst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
98 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
100 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
143 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
145 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
161 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned r600_texture_get_offset(struct si_screen
*sscreen
,
182 struct r600_texture
*rtex
, unsigned level
,
183 const struct pipe_box
*box
,
185 unsigned *layer_stride
)
187 if (sscreen
->info
.chip_class
>= GFX9
) {
188 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
189 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
194 /* Each texture is an array of slices. Each slice is an array
195 * of mipmap levels. */
196 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
197 rtex
->surface
.u
.gfx9
.offset
[level
] +
198 (box
->y
/ rtex
->surface
.blk_h
*
199 rtex
->surface
.u
.gfx9
.surf_pitch
+
200 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
202 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
204 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
205 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
208 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
214 (box
->y
/ rtex
->surface
.blk_h
*
215 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
220 static int r600_init_surface(struct si_screen
*sscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 enum radeon_surf_mode array_mode
,
224 unsigned pitch_in_bytes_override
,
228 bool is_flushed_depth
,
229 bool tc_compatible_htile
)
231 const struct util_format_description
*desc
=
232 util_format_description(ptex
->format
);
233 bool is_depth
, is_stencil
;
235 unsigned i
, bpe
, flags
= 0;
237 is_depth
= util_format_has_depth(desc
);
238 is_stencil
= util_format_has_stencil(desc
);
240 if (!is_flushed_depth
&&
241 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
242 bpe
= 4; /* stencil is allocated separately on evergreen */
244 bpe
= util_format_get_blocksize(ptex
->format
);
245 assert(util_is_power_of_two(bpe
));
248 if (!is_flushed_depth
&& is_depth
) {
249 flags
|= RADEON_SURF_ZBUFFER
;
251 if (tc_compatible_htile
&&
252 (sscreen
->info
.chip_class
>= GFX9
||
253 array_mode
== RADEON_SURF_MODE_2D
)) {
254 /* TC-compatible HTILE only supports Z32_FLOAT.
255 * GFX9 also supports Z16_UNORM.
256 * On VI, promote Z16 to Z32. DB->CB copies will convert
257 * the format for transfers.
259 if (sscreen
->info
.chip_class
== VI
)
262 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
266 flags
|= RADEON_SURF_SBUFFER
;
269 if (sscreen
->info
.chip_class
>= VI
&&
270 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
271 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
272 /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
273 (ptex
->nr_samples
>= 2 &&
274 (!sscreen
->dcc_msaa_allowed
|| ptex
->array_size
> 1))))
275 flags
|= RADEON_SURF_DISABLE_DCC
;
277 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
278 /* This should catch bugs in gallium users setting incorrect flags. */
279 assert(ptex
->nr_samples
<= 1 &&
280 ptex
->array_size
== 1 &&
282 ptex
->last_level
== 0 &&
283 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
285 flags
|= RADEON_SURF_SCANOUT
;
288 if (ptex
->bind
& PIPE_BIND_SHARED
)
289 flags
|= RADEON_SURF_SHAREABLE
;
291 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
292 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
293 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
295 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
296 array_mode
, surface
);
301 if (sscreen
->info
.chip_class
>= GFX9
) {
302 assert(!pitch_in_bytes_override
||
303 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
304 surface
->u
.gfx9
.surf_offset
= offset
;
307 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
308 surface
->u
.legacy
.level
[i
].offset
+= offset
;
314 static void r600_texture_init_metadata(struct si_screen
*sscreen
,
315 struct r600_texture
*rtex
,
316 struct radeon_bo_metadata
*metadata
)
318 struct radeon_surf
*surface
= &rtex
->surface
;
320 memset(metadata
, 0, sizeof(*metadata
));
322 if (sscreen
->info
.chip_class
>= GFX9
) {
323 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
325 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
326 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
327 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
328 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
329 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
330 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
331 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
332 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
333 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
334 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
335 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
336 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
340 static void r600_surface_import_metadata(struct si_screen
*sscreen
,
341 struct radeon_surf
*surf
,
342 struct radeon_bo_metadata
*metadata
,
343 enum radeon_surf_mode
*array_mode
,
346 if (sscreen
->info
.chip_class
>= GFX9
) {
347 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
348 *array_mode
= RADEON_SURF_MODE_2D
;
350 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
352 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
353 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
355 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
357 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
358 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
359 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
360 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
361 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
362 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
364 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
365 *array_mode
= RADEON_SURF_MODE_2D
;
366 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
367 *array_mode
= RADEON_SURF_MODE_1D
;
369 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
371 *is_scanout
= metadata
->u
.legacy
.scanout
;
375 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
376 struct r600_texture
*rtex
)
378 struct si_screen
*sscreen
= rctx
->screen
;
379 struct pipe_context
*ctx
= &rctx
->b
;
381 if (ctx
== sscreen
->aux_context
)
382 mtx_lock(&sscreen
->aux_context_lock
);
384 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
385 ctx
->flush(ctx
, NULL
, 0);
387 if (ctx
== sscreen
->aux_context
)
388 mtx_unlock(&sscreen
->aux_context_lock
);
391 static void r600_texture_discard_cmask(struct si_screen
*sscreen
,
392 struct r600_texture
*rtex
)
394 if (!rtex
->cmask
.size
)
397 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
400 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
401 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
402 rtex
->dirty_level_mask
= 0;
404 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
406 if (rtex
->cmask_buffer
!= &rtex
->resource
)
407 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
409 /* Notify all contexts about the change. */
410 p_atomic_inc(&sscreen
->dirty_tex_counter
);
411 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
414 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
416 /* We can't disable DCC if it can be written by another process. */
417 return rtex
->dcc_offset
&&
418 (!rtex
->resource
.b
.is_shared
||
419 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
422 static bool r600_texture_discard_dcc(struct si_screen
*sscreen
,
423 struct r600_texture
*rtex
)
425 if (!r600_can_disable_dcc(rtex
))
428 assert(rtex
->dcc_separate_buffer
== NULL
);
431 rtex
->dcc_offset
= 0;
433 /* Notify all contexts about the change. */
434 p_atomic_inc(&sscreen
->dirty_tex_counter
);
439 * Disable DCC for the texture. (first decompress, then discard metadata).
441 * There is unresolved multi-context synchronization issue between
442 * screen::aux_context and the current context. If applications do this with
443 * multiple contexts, it's already undefined behavior for them and we don't
444 * have to worry about that. The scenario is:
446 * If context 1 disables DCC and context 2 has queued commands that write
447 * to the texture via CB with DCC enabled, and the order of operations is
449 * context 2 queues draw calls rendering to the texture, but doesn't flush
450 * context 1 disables DCC and flushes
451 * context 1 & 2 reset descriptors and FB state
452 * context 2 flushes (new compressed tiles written by the draw calls)
453 * context 1 & 2 read garbage, because DCC is disabled, yet there are
456 * \param rctx the current context if you have one, or rscreen->aux_context
459 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
460 struct r600_texture
*rtex
)
462 struct si_screen
*sscreen
= rctx
->screen
;
464 if (!r600_can_disable_dcc(rtex
))
467 if (&rctx
->b
== sscreen
->aux_context
)
468 mtx_lock(&sscreen
->aux_context_lock
);
470 /* Decompress DCC. */
471 rctx
->decompress_dcc(&rctx
->b
, rtex
);
472 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
474 if (&rctx
->b
== sscreen
->aux_context
)
475 mtx_unlock(&sscreen
->aux_context_lock
);
477 return r600_texture_discard_dcc(sscreen
, rtex
);
480 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
481 struct r600_texture
*rtex
,
482 unsigned new_bind_flag
,
483 bool invalidate_storage
)
485 struct pipe_screen
*screen
= rctx
->b
.screen
;
486 struct r600_texture
*new_tex
;
487 struct pipe_resource templ
= rtex
->resource
.b
.b
;
490 templ
.bind
|= new_bind_flag
;
492 if (rtex
->resource
.b
.is_shared
)
495 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
496 if (rtex
->surface
.is_linear
)
499 /* This fails with MSAA, depth, and compressed textures. */
500 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
501 RADEON_SURF_MODE_LINEAR_ALIGNED
)
505 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
509 /* Copy the pixels to the new texture. */
510 if (!invalidate_storage
) {
511 for (i
= 0; i
<= templ
.last_level
; i
++) {
515 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
516 util_num_layers(&templ
, i
), &box
);
518 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
519 &rtex
->resource
.b
.b
, i
, &box
);
523 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
524 r600_texture_discard_cmask(rctx
->screen
, rtex
);
525 r600_texture_discard_dcc(rctx
->screen
, rtex
);
528 /* Replace the structure fields of rtex. */
529 rtex
->resource
.b
.b
.bind
= templ
.bind
;
530 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
531 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
532 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
533 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
534 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
535 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
536 rtex
->resource
.domains
= new_tex
->resource
.domains
;
537 rtex
->resource
.flags
= new_tex
->resource
.flags
;
538 rtex
->size
= new_tex
->size
;
539 rtex
->db_render_format
= new_tex
->db_render_format
;
540 rtex
->db_compatible
= new_tex
->db_compatible
;
541 rtex
->can_sample_z
= new_tex
->can_sample_z
;
542 rtex
->can_sample_s
= new_tex
->can_sample_s
;
543 rtex
->surface
= new_tex
->surface
;
544 rtex
->fmask
= new_tex
->fmask
;
545 rtex
->cmask
= new_tex
->cmask
;
546 rtex
->cb_color_info
= new_tex
->cb_color_info
;
547 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
548 rtex
->htile_offset
= new_tex
->htile_offset
;
549 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
550 rtex
->depth_cleared
= new_tex
->depth_cleared
;
551 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
552 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
553 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
555 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
556 assert(!rtex
->htile_offset
);
557 assert(!rtex
->cmask
.size
);
558 assert(!rtex
->fmask
.size
);
559 assert(!rtex
->dcc_offset
);
560 assert(!rtex
->is_depth
);
563 r600_texture_reference(&new_tex
, NULL
);
565 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
568 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
570 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
573 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
574 struct r600_texture
*rtex
,
575 struct radeon_bo_metadata
*md
)
577 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
578 static const unsigned char swizzle
[] = {
585 bool is_array
= util_texture_is_array(res
->target
);
587 /* DRM 2.x.x doesn't support this. */
588 if (sscreen
->info
.drm_major
!= 3)
591 assert(rtex
->dcc_separate_buffer
== NULL
);
592 assert(rtex
->fmask
.size
== 0);
594 /* Metadata image format format version 1:
595 * [0] = 1 (metadata format identifier)
596 * [1] = (VENDOR_ID << 16) | PCI_ID
597 * [2:9] = image descriptor for the whole resource
598 * [2] is always 0, because the base address is cleared
599 * [9] is the DCC offset bits [39:8] from the beginning of
601 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
604 md
->metadata
[0] = 1; /* metadata image format version 1 */
606 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
607 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
609 si_make_texture_descriptor(sscreen
, rtex
, true,
610 res
->target
, res
->format
,
611 swizzle
, 0, res
->last_level
, 0,
612 is_array
? res
->array_size
- 1 : 0,
613 res
->width0
, res
->height0
, res
->depth0
,
616 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
617 0, 0, rtex
->surface
.blk_w
, false, desc
);
619 /* Clear the base address and set the relative DCC offset. */
621 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
622 desc
[7] = rtex
->dcc_offset
>> 8;
624 /* Dwords [2:9] contain the image descriptor. */
625 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
626 md
->size_metadata
= 10 * 4;
628 /* Dwords [10:..] contain the mipmap level offsets. */
629 if (sscreen
->info
.chip_class
<= VI
) {
630 for (i
= 0; i
<= res
->last_level
; i
++)
631 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
633 md
->size_metadata
+= (1 + res
->last_level
) * 4;
637 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
638 struct r600_texture
*rtex
,
639 struct radeon_bo_metadata
*md
)
641 uint32_t *desc
= &md
->metadata
[2];
643 if (sscreen
->info
.chip_class
< VI
)
646 /* Return if DCC is enabled. The texture should be set up with it
649 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
650 md
->metadata
[0] != 0 &&
651 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
652 G_008F28_COMPRESSION_EN(desc
[6])) {
653 rtex
->dcc_offset
= (uint64_t)desc
[7] << 8;
657 /* Disable DCC. These are always set by texture_from_handle and must
660 rtex
->dcc_offset
= 0;
663 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
664 struct pipe_context
*ctx
,
665 struct pipe_resource
*resource
,
666 struct winsys_handle
*whandle
,
669 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
670 struct r600_common_context
*rctx
;
671 struct r600_resource
*res
= (struct r600_resource
*)resource
;
672 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
673 struct radeon_bo_metadata metadata
;
674 bool update_metadata
= false;
675 unsigned stride
, offset
, slice_size
;
678 ctx
= threaded_context_unwrap_sync(ctx
);
679 rctx
= (struct r600_common_context
*)(ctx
? ctx
: sscreen
->aux_context
);
681 if (resource
->target
!= PIPE_BUFFER
) {
682 /* This is not supported now, but it might be required for OpenCL
683 * interop in the future.
685 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
688 /* Move a suballocated texture into a non-suballocated allocation. */
689 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
690 rtex
->surface
.tile_swizzle
||
691 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
692 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
693 assert(!res
->b
.is_shared
);
694 r600_reallocate_texture_inplace(rctx
, rtex
,
695 PIPE_BIND_SHARED
, false);
697 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
698 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
699 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
700 assert(rtex
->surface
.tile_swizzle
== 0);
703 /* Since shader image stores don't support DCC on VI,
704 * disable it for external clients that want write
707 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
708 if (si_texture_disable_dcc(rctx
, rtex
)) {
709 update_metadata
= true;
710 /* si_texture_disable_dcc flushes the context */
715 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
716 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
717 /* Eliminate fast clear (both CMASK and DCC) */
718 r600_eliminate_fast_color_clear(rctx
, rtex
);
719 /* eliminate_fast_color_clear flushes the context */
722 /* Disable CMASK if flush_resource isn't going
725 if (rtex
->cmask
.size
)
726 r600_texture_discard_cmask(sscreen
, rtex
);
730 if (!res
->b
.is_shared
|| update_metadata
) {
731 r600_texture_init_metadata(sscreen
, rtex
, &metadata
);
732 si_query_opaque_metadata(sscreen
, rtex
, &metadata
);
734 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
737 if (sscreen
->info
.chip_class
>= GFX9
) {
738 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
739 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
741 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
743 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
744 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
746 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
749 /* Buffer exports are for the OpenCL interop. */
750 /* Move a suballocated buffer into a non-suballocated allocation. */
751 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
752 /* A DMABUF export always fails if the BO is local. */
753 rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
) {
754 assert(!res
->b
.is_shared
);
756 /* Allocate a new buffer with PIPE_BIND_SHARED. */
757 struct pipe_resource templ
= res
->b
.b
;
758 templ
.bind
|= PIPE_BIND_SHARED
;
760 struct pipe_resource
*newb
=
761 screen
->resource_create(screen
, &templ
);
765 /* Copy the old buffer contents to the new one. */
767 u_box_1d(0, newb
->width0
, &box
);
768 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
771 /* Move the new buffer storage to the old pipe_resource. */
772 si_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
773 pipe_resource_reference(&newb
, NULL
);
775 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
776 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
786 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
788 if (res
->b
.is_shared
) {
789 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
792 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
793 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
794 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
796 res
->b
.is_shared
= true;
797 res
->external_usage
= usage
;
800 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
801 slice_size
, whandle
);
804 static void r600_texture_destroy(struct pipe_screen
*screen
,
805 struct pipe_resource
*ptex
)
807 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
808 struct r600_resource
*resource
= &rtex
->resource
;
810 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
812 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
813 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
815 pb_reference(&resource
->buf
, NULL
);
816 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
817 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
821 static const struct u_resource_vtbl r600_texture_vtbl
;
823 /* The number of samples can be specified independently of the texture. */
824 void si_texture_get_fmask_info(struct si_screen
*sscreen
,
825 struct r600_texture
*rtex
,
827 struct r600_fmask_info
*out
)
829 /* FMASK is allocated like an ordinary texture. */
830 struct pipe_resource templ
= rtex
->resource
.b
.b
;
831 struct radeon_surf fmask
= {};
834 memset(out
, 0, sizeof(*out
));
836 if (sscreen
->info
.chip_class
>= GFX9
) {
837 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
838 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
842 templ
.nr_samples
= 1;
843 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
845 switch (nr_samples
) {
854 R600_ERR("Invalid sample count for FMASK allocation.\n");
858 if (sscreen
->ws
->surface_init(sscreen
->ws
, &templ
, flags
, bpe
,
859 RADEON_SURF_MODE_2D
, &fmask
)) {
860 R600_ERR("Got error in surface_init while allocating FMASK.\n");
864 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
866 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
867 if (out
->slice_tile_max
)
868 out
->slice_tile_max
-= 1;
870 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
871 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
872 out
->bank_height
= fmask
.u
.legacy
.bankh
;
873 out
->tile_swizzle
= fmask
.tile_swizzle
;
874 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
875 out
->size
= fmask
.surf_size
;
878 static void r600_texture_allocate_fmask(struct si_screen
*sscreen
,
879 struct r600_texture
*rtex
)
881 si_texture_get_fmask_info(sscreen
, rtex
,
882 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
884 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
885 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
888 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
889 struct r600_texture
*rtex
,
890 struct r600_cmask_info
*out
)
892 unsigned pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
893 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
894 unsigned cl_width
, cl_height
;
896 if (sscreen
->info
.chip_class
>= GFX9
) {
897 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
898 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
915 case 16: /* Hawaii */
924 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
926 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
927 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
928 unsigned slice_elements
= (width
* height
) / (8*8);
930 /* Each element of CMASK is a nibble. */
931 unsigned slice_bytes
= slice_elements
/ 2;
933 out
->slice_tile_max
= (width
* height
) / (128*128);
934 if (out
->slice_tile_max
)
935 out
->slice_tile_max
-= 1;
937 out
->alignment
= MAX2(256, base_align
);
938 out
->size
= util_num_layers(&rtex
->resource
.b
.b
, 0) *
939 align(slice_bytes
, base_align
);
942 static void r600_texture_allocate_cmask(struct si_screen
*sscreen
,
943 struct r600_texture
*rtex
)
945 si_texture_get_cmask_info(sscreen
, rtex
, &rtex
->cmask
);
947 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
948 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
950 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
953 static void r600_texture_get_htile_size(struct si_screen
*sscreen
,
954 struct r600_texture
*rtex
)
956 unsigned cl_width
, cl_height
, width
, height
;
957 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
958 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
960 assert(sscreen
->info
.chip_class
<= VI
);
962 rtex
->surface
.htile_size
= 0;
964 /* HTILE is broken with 1D tiling on old kernels and CIK. */
965 if (sscreen
->info
.chip_class
>= CIK
&&
966 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
967 sscreen
->info
.drm_major
== 2 && sscreen
->info
.drm_minor
< 38)
970 /* Overalign HTILE on P2 configs to work around GPU hangs in
971 * piglit/depthstencil-render-miplevels 585.
973 * This has been confirmed to help Kabini & Stoney, where the hangs
974 * are always reproducible. I think I have seen the test hang
975 * on Carrizo too, though it was very rare there.
977 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
1006 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
1007 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
1009 slice_elements
= (width
* height
) / (8 * 8);
1010 slice_bytes
= slice_elements
* 4;
1012 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1013 base_align
= num_pipes
* pipe_interleave_bytes
;
1015 rtex
->surface
.htile_alignment
= base_align
;
1016 rtex
->surface
.htile_size
=
1017 util_num_layers(&rtex
->resource
.b
.b
, 0) *
1018 align(slice_bytes
, base_align
);
1021 static void r600_texture_allocate_htile(struct si_screen
*sscreen
,
1022 struct r600_texture
*rtex
)
1024 if (sscreen
->info
.chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
1025 r600_texture_get_htile_size(sscreen
, rtex
);
1027 if (!rtex
->surface
.htile_size
)
1030 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
1031 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
1034 void si_print_texture_info(struct si_screen
*sscreen
,
1035 struct r600_texture
*rtex
, struct u_log_context
*log
)
1039 /* Common parameters. */
1040 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1041 "blk_h=%u, array_size=%u, last_level=%u, "
1042 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1043 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
1044 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1045 rtex
->surface
.blk_h
,
1046 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
1047 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
1048 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
1050 if (sscreen
->info
.chip_class
>= GFX9
) {
1051 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1052 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1053 rtex
->surface
.surf_size
,
1054 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1055 rtex
->surface
.surf_alignment
,
1056 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1057 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1058 rtex
->surface
.u
.gfx9
.surf_pitch
);
1060 if (rtex
->fmask
.size
) {
1061 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1062 "alignment=%u, swmode=%u, epitch=%u\n",
1064 rtex
->surface
.u
.gfx9
.fmask_size
,
1065 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1066 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1067 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1070 if (rtex
->cmask
.size
) {
1071 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1072 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1074 rtex
->surface
.u
.gfx9
.cmask_size
,
1075 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1076 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1077 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1080 if (rtex
->htile_offset
) {
1081 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1082 "rb_aligned=%u, pipe_aligned=%u\n",
1084 rtex
->surface
.htile_size
,
1085 rtex
->surface
.htile_alignment
,
1086 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1087 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1090 if (rtex
->dcc_offset
) {
1091 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1092 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1093 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1094 rtex
->surface
.dcc_alignment
,
1095 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1096 rtex
->surface
.num_dcc_levels
);
1099 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1100 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1101 rtex
->surface
.u
.gfx9
.stencil_offset
,
1102 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1103 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1108 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1109 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1110 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1111 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1112 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1113 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1115 if (rtex
->fmask
.size
)
1116 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1117 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1118 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1119 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1120 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1122 if (rtex
->cmask
.size
)
1123 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1124 "slice_tile_max=%u\n",
1125 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1126 rtex
->cmask
.slice_tile_max
);
1128 if (rtex
->htile_offset
)
1129 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1130 "alignment=%u, TC_compatible = %u\n",
1131 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1132 rtex
->surface
.htile_alignment
,
1133 rtex
->tc_compatible_htile
);
1135 if (rtex
->dcc_offset
) {
1136 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1137 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1138 rtex
->surface
.dcc_alignment
);
1139 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1140 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1141 "fast_clear_size=%u\n",
1142 i
, i
< rtex
->surface
.num_dcc_levels
,
1143 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1144 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1147 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1148 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1149 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1150 "mode=%u, tiling_index = %u\n",
1151 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1152 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1153 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1154 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1155 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1156 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1157 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1158 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1159 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1161 if (rtex
->surface
.has_stencil
) {
1162 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1163 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1164 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1165 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1166 "slice_size=%"PRIu64
", npix_x=%u, "
1167 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1168 "mode=%u, tiling_index = %u\n",
1169 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1170 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1171 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1172 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1173 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1174 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1175 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1176 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1177 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1182 /* Common processing for r600_texture_create and r600_texture_from_handle */
1183 static struct r600_texture
*
1184 r600_texture_create_object(struct pipe_screen
*screen
,
1185 const struct pipe_resource
*base
,
1186 struct pb_buffer
*buf
,
1187 struct radeon_surf
*surface
)
1189 struct r600_texture
*rtex
;
1190 struct r600_resource
*resource
;
1191 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1193 rtex
= CALLOC_STRUCT(r600_texture
);
1197 resource
= &rtex
->resource
;
1198 resource
->b
.b
= *base
;
1199 resource
->b
.b
.next
= NULL
;
1200 resource
->b
.vtbl
= &r600_texture_vtbl
;
1201 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1202 resource
->b
.b
.screen
= screen
;
1204 /* don't include stencil-only formats which we don't support for rendering */
1205 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1207 rtex
->surface
= *surface
;
1208 rtex
->size
= rtex
->surface
.surf_size
;
1210 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1211 (rtex
->surface
.flags
&
1212 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1214 /* TC-compatible HTILE:
1215 * - VI only supports Z32_FLOAT.
1216 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1217 if (rtex
->tc_compatible_htile
) {
1218 if (sscreen
->info
.chip_class
>= GFX9
&&
1219 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1220 rtex
->db_render_format
= base
->format
;
1222 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1223 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1224 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1227 rtex
->db_render_format
= base
->format
;
1230 /* Applies to GCN. */
1231 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1233 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1234 * between frames, so the only thing that can enable separate DCC
1235 * with DRI2 is multiple slow clears within a frame.
1237 rtex
->ps_draw_ratio
= 0;
1239 if (rtex
->is_depth
) {
1240 if (sscreen
->info
.chip_class
>= GFX9
) {
1241 rtex
->can_sample_z
= true;
1242 rtex
->can_sample_s
= true;
1244 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1245 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1248 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1249 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1250 rtex
->db_compatible
= true;
1252 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1253 r600_texture_allocate_htile(sscreen
, rtex
);
1256 if (base
->nr_samples
> 1) {
1258 r600_texture_allocate_fmask(sscreen
, rtex
);
1259 r600_texture_allocate_cmask(sscreen
, rtex
);
1260 rtex
->cmask_buffer
= &rtex
->resource
;
1262 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1268 /* Shared textures must always set up DCC here.
1269 * If it's not present, it will be disabled by
1270 * apply_opaque_metadata later.
1272 if (rtex
->surface
.dcc_size
&&
1273 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1274 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1275 /* Reserve space for the DCC buffer. */
1276 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1277 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1281 /* Now create the backing buffer. */
1283 si_init_resource_fields(sscreen
, resource
, rtex
->size
,
1284 rtex
->surface
.surf_alignment
);
1286 if (!si_alloc_resource(sscreen
, resource
)) {
1291 resource
->buf
= buf
;
1292 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1293 resource
->bo_size
= buf
->size
;
1294 resource
->bo_alignment
= buf
->alignment
;
1295 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1296 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1297 resource
->vram_usage
= buf
->size
;
1298 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1299 resource
->gart_usage
= buf
->size
;
1302 if (rtex
->cmask
.size
) {
1303 /* Initialize the cmask to 0xCC (= compressed state). */
1304 si_screen_clear_buffer(sscreen
, &rtex
->cmask_buffer
->b
.b
,
1305 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1308 if (rtex
->htile_offset
) {
1309 uint32_t clear_value
= 0;
1311 if (sscreen
->info
.chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1312 clear_value
= 0x0000030F;
1314 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1316 rtex
->surface
.htile_size
,
1320 /* Initialize DCC only if the texture is not being imported. */
1321 if (!buf
&& rtex
->dcc_offset
) {
1322 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1324 rtex
->surface
.dcc_size
,
1328 /* Initialize the CMASK base register value. */
1329 rtex
->cmask
.base_address_reg
=
1330 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1332 if (sscreen
->debug_flags
& DBG(VM
)) {
1333 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1334 rtex
->resource
.gpu_address
,
1335 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1336 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1337 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1340 if (sscreen
->debug_flags
& DBG(TEX
)) {
1342 struct u_log_context log
;
1343 u_log_context_init(&log
);
1344 si_print_texture_info(sscreen
, rtex
, &log
);
1345 u_log_new_page_print(&log
, stdout
);
1347 u_log_context_destroy(&log
);
1353 static enum radeon_surf_mode
1354 r600_choose_tiling(struct si_screen
*sscreen
,
1355 const struct pipe_resource
*templ
)
1357 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1358 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1359 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1360 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1362 /* MSAA resources must be 2D tiled. */
1363 if (templ
->nr_samples
> 1)
1364 return RADEON_SURF_MODE_2D
;
1366 /* Transfer resources should be linear. */
1367 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1368 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1370 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1371 * which requires 2D tiling.
1373 if (sscreen
->info
.chip_class
== VI
&&
1375 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1376 return RADEON_SURF_MODE_2D
;
1378 /* Handle common candidates for the linear mode.
1379 * Compressed textures and DB surfaces must always be tiled.
1381 if (!force_tiling
&&
1382 !is_depth_stencil
&&
1383 !util_format_is_compressed(templ
->format
)) {
1384 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1385 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1387 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1388 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1389 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1391 /* Cursors are linear on SI.
1392 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1393 if (templ
->bind
& PIPE_BIND_CURSOR
)
1394 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1396 if (templ
->bind
& PIPE_BIND_LINEAR
)
1397 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1399 /* Textures with a very small height are recommended to be linear. */
1400 if (templ
->target
== PIPE_TEXTURE_1D
||
1401 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1402 /* Only very thin and long 2D textures should benefit from
1403 * linear_aligned. */
1404 (templ
->width0
> 8 && templ
->height0
<= 2))
1405 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1407 /* Textures likely to be mapped often. */
1408 if (templ
->usage
== PIPE_USAGE_STAGING
||
1409 templ
->usage
== PIPE_USAGE_STREAM
)
1410 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1413 /* Make small textures 1D tiled. */
1414 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1415 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1416 return RADEON_SURF_MODE_1D
;
1418 /* The allocator will switch to 1D if needed. */
1419 return RADEON_SURF_MODE_2D
;
1422 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1423 const struct pipe_resource
*templ
)
1425 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1426 struct radeon_surf surface
= {0};
1427 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1428 bool tc_compatible_htile
=
1429 sscreen
->info
.chip_class
>= VI
&&
1430 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1431 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1432 !is_flushed_depth
&&
1433 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1434 util_format_is_depth_or_stencil(templ
->format
);
1438 r
= r600_init_surface(sscreen
, &surface
, templ
,
1439 r600_choose_tiling(sscreen
, templ
), 0, 0,
1440 false, false, is_flushed_depth
,
1441 tc_compatible_htile
);
1446 return (struct pipe_resource
*)
1447 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1450 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1451 const struct pipe_resource
*templ
,
1452 struct winsys_handle
*whandle
,
1455 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1456 struct pb_buffer
*buf
= NULL
;
1457 unsigned stride
= 0, offset
= 0;
1458 enum radeon_surf_mode array_mode
;
1459 struct radeon_surf surface
= {};
1461 struct radeon_bo_metadata metadata
= {};
1462 struct r600_texture
*rtex
;
1465 /* Support only 2D textures without mipmaps */
1466 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1467 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1470 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1474 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1475 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
1476 &array_mode
, &is_scanout
);
1478 r
= r600_init_surface(sscreen
, &surface
, templ
, array_mode
, stride
,
1479 offset
, true, is_scanout
, false, false);
1484 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1488 rtex
->resource
.b
.is_shared
= true;
1489 rtex
->resource
.external_usage
= usage
;
1491 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
1493 assert(rtex
->surface
.tile_swizzle
== 0);
1494 return &rtex
->resource
.b
.b
;
1497 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1498 struct pipe_resource
*texture
,
1499 struct r600_texture
**staging
)
1501 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1502 struct pipe_resource resource
;
1503 struct r600_texture
**flushed_depth_texture
= staging
?
1504 staging
: &rtex
->flushed_depth_texture
;
1505 enum pipe_format pipe_format
= texture
->format
;
1508 if (rtex
->flushed_depth_texture
)
1509 return true; /* it's ready */
1511 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1512 switch (pipe_format
) {
1513 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1514 /* Save memory by not allocating the S plane. */
1515 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1517 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1518 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1519 /* Save memory bandwidth by not copying the
1520 * stencil part during flush.
1522 * This potentially increases memory bandwidth
1523 * if an application uses both Z and S texturing
1524 * simultaneously (a flushed Z24S8 texture
1525 * would be stored compactly), but how often
1526 * does that really happen?
1528 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1532 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1533 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1535 /* DB->CB copies to an 8bpp surface don't work. */
1536 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1540 memset(&resource
, 0, sizeof(resource
));
1541 resource
.target
= texture
->target
;
1542 resource
.format
= pipe_format
;
1543 resource
.width0
= texture
->width0
;
1544 resource
.height0
= texture
->height0
;
1545 resource
.depth0
= texture
->depth0
;
1546 resource
.array_size
= texture
->array_size
;
1547 resource
.last_level
= texture
->last_level
;
1548 resource
.nr_samples
= texture
->nr_samples
;
1549 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1550 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1551 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1554 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1556 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1557 if (*flushed_depth_texture
== NULL
) {
1558 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1565 * Initialize the pipe_resource descriptor to be of the same size as the box,
1566 * which is supposed to hold a subregion of the texture "orig" at the given
1569 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1570 struct pipe_resource
*orig
,
1571 const struct pipe_box
*box
,
1572 unsigned level
, unsigned flags
)
1574 memset(res
, 0, sizeof(*res
));
1575 res
->format
= orig
->format
;
1576 res
->width0
= box
->width
;
1577 res
->height0
= box
->height
;
1579 res
->array_size
= 1;
1580 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1583 /* We must set the correct texture target and dimensions for a 3D box. */
1584 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1585 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1586 res
->array_size
= box
->depth
;
1588 res
->target
= PIPE_TEXTURE_2D
;
1592 static bool r600_can_invalidate_texture(struct si_screen
*sscreen
,
1593 struct r600_texture
*rtex
,
1594 unsigned transfer_usage
,
1595 const struct pipe_box
*box
)
1597 return !rtex
->resource
.b
.is_shared
&&
1598 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1599 rtex
->resource
.b
.b
.last_level
== 0 &&
1600 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1601 box
->x
, box
->y
, box
->z
,
1602 box
->width
, box
->height
,
1606 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1607 struct r600_texture
*rtex
)
1609 struct si_screen
*sscreen
= rctx
->screen
;
1611 /* There is no point in discarding depth and tiled buffers. */
1612 assert(!rtex
->is_depth
);
1613 assert(rtex
->surface
.is_linear
);
1615 /* Reallocate the buffer in the same pipe_resource. */
1616 si_alloc_resource(sscreen
, &rtex
->resource
);
1618 /* Initialize the CMASK base address (needed even without CMASK). */
1619 rtex
->cmask
.base_address_reg
=
1620 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1622 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1624 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1627 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1628 struct pipe_resource
*texture
,
1631 const struct pipe_box
*box
,
1632 struct pipe_transfer
**ptransfer
)
1634 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1635 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1636 struct r600_transfer
*trans
;
1637 struct r600_resource
*buf
;
1638 unsigned offset
= 0;
1640 bool use_staging_texture
= false;
1642 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1643 assert(box
->width
&& box
->height
&& box
->depth
);
1645 /* Depth textures use staging unconditionally. */
1646 if (!rtex
->is_depth
) {
1647 /* Degrade the tile mode if we get too many transfers on APUs.
1648 * On dGPUs, the staging texture is always faster.
1649 * Only count uploads that are at least 4x4 pixels large.
1651 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1653 box
->width
>= 4 && box
->height
>= 4 &&
1654 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1655 bool can_invalidate
=
1656 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1659 r600_reallocate_texture_inplace(rctx
, rtex
,
1664 /* Tiled textures need to be converted into a linear texture for CPU
1665 * access. The staging texture is always linear and is placed in GART.
1667 * Reading from VRAM or GTT WC is slow, always use the staging
1668 * texture in this case.
1670 * Use the staging texture for uploads if the underlying BO
1673 if (!rtex
->surface
.is_linear
)
1674 use_staging_texture
= true;
1675 else if (usage
& PIPE_TRANSFER_READ
)
1676 use_staging_texture
=
1677 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1678 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1679 /* Write & linear only: */
1680 else if (si_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1681 RADEON_USAGE_READWRITE
) ||
1682 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1683 RADEON_USAGE_READWRITE
)) {
1685 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1687 r600_texture_invalidate_storage(rctx
, rtex
);
1689 use_staging_texture
= true;
1693 trans
= CALLOC_STRUCT(r600_transfer
);
1696 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1697 trans
->b
.b
.level
= level
;
1698 trans
->b
.b
.usage
= usage
;
1699 trans
->b
.b
.box
= *box
;
1701 if (rtex
->is_depth
) {
1702 struct r600_texture
*staging_depth
;
1704 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1705 /* MSAA depth buffers need to be converted to single sample buffers.
1707 * Mapping MSAA depth buffers can occur if ReadPixels is called
1708 * with a multisample GLX visual.
1710 * First downsample the depth buffer to a temporary texture,
1711 * then decompress the temporary one to staging.
1713 * Only the region being mapped is transfered.
1715 struct pipe_resource resource
;
1717 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1719 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1720 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1725 if (usage
& PIPE_TRANSFER_READ
) {
1726 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1728 R600_ERR("failed to create a temporary depth texture\n");
1733 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1734 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1735 0, 0, 0, box
->depth
, 0, 0);
1736 pipe_resource_reference(&temp
, NULL
);
1739 /* Just get the strides. */
1740 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1742 &trans
->b
.b
.layer_stride
);
1744 /* XXX: only readback the rectangle which is being mapped? */
1745 /* XXX: when discard is true, no need to read back from depth texture */
1746 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1747 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1752 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1754 box
->z
, box
->z
+ box
->depth
- 1,
1757 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1760 &trans
->b
.b
.layer_stride
);
1763 trans
->staging
= (struct r600_resource
*)staging_depth
;
1764 buf
= trans
->staging
;
1765 } else if (use_staging_texture
) {
1766 struct pipe_resource resource
;
1767 struct r600_texture
*staging
;
1769 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1770 R600_RESOURCE_FLAG_TRANSFER
);
1771 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1772 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1774 /* Create the temporary texture. */
1775 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1777 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1781 trans
->staging
= &staging
->resource
;
1783 /* Just get the strides. */
1784 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1786 &trans
->b
.b
.layer_stride
);
1788 if (usage
& PIPE_TRANSFER_READ
)
1789 r600_copy_to_staging_texture(ctx
, trans
);
1791 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1793 buf
= trans
->staging
;
1795 /* the resource is mapped directly */
1796 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1798 &trans
->b
.b
.layer_stride
);
1799 buf
= &rtex
->resource
;
1802 if (!(map
= si_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1803 r600_resource_reference(&trans
->staging
, NULL
);
1808 *ptransfer
= &trans
->b
.b
;
1809 return map
+ offset
;
1812 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1813 struct pipe_transfer
* transfer
)
1815 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1816 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1817 struct pipe_resource
*texture
= transfer
->resource
;
1818 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1820 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1821 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1822 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1823 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1824 &rtransfer
->staging
->b
.b
, transfer
->level
,
1827 r600_copy_from_staging_texture(ctx
, rtransfer
);
1831 if (rtransfer
->staging
) {
1832 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1833 r600_resource_reference(&rtransfer
->staging
, NULL
);
1836 /* Heuristic for {upload, draw, upload, draw, ..}:
1838 * Flush the gfx IB if we've allocated too much texture storage.
1840 * The idea is that we don't want to build IBs that use too much
1841 * memory and put pressure on the kernel memory manager and we also
1842 * want to make temporary and invalidated buffers go idle ASAP to
1843 * decrease the total memory usage or make them reusable. The memory
1844 * usage will be slightly higher than given here because of the buffer
1845 * cache in the winsys.
1847 * The result is that the kernel memory manager is never a bottleneck.
1849 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1850 rctx
->gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
1851 rctx
->num_alloc_tex_transfer_bytes
= 0;
1854 pipe_resource_reference(&transfer
->resource
, NULL
);
1858 static const struct u_resource_vtbl r600_texture_vtbl
=
1860 NULL
, /* get_handle */
1861 r600_texture_destroy
, /* resource_destroy */
1862 r600_texture_transfer_map
, /* transfer_map */
1863 u_default_transfer_flush_region
, /* transfer_flush_region */
1864 r600_texture_transfer_unmap
, /* transfer_unmap */
1867 /* DCC channel type categories within which formats can be reinterpreted
1868 * while keeping the same DCC encoding. The swizzle must also match. */
1869 enum dcc_channel_type
{
1870 dcc_channel_float32
,
1873 dcc_channel_float16
,
1876 dcc_channel_uint_10_10_10_2
,
1879 dcc_channel_incompatible
,
1882 /* Return the type of DCC encoding. */
1883 static enum dcc_channel_type
1884 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1888 /* Find the first non-void channel. */
1889 for (i
= 0; i
< desc
->nr_channels
; i
++)
1890 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1892 if (i
== desc
->nr_channels
)
1893 return dcc_channel_incompatible
;
1895 switch (desc
->channel
[i
].size
) {
1897 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1898 return dcc_channel_float32
;
1899 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1900 return dcc_channel_uint32
;
1901 return dcc_channel_sint32
;
1903 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1904 return dcc_channel_float16
;
1905 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1906 return dcc_channel_uint16
;
1907 return dcc_channel_sint16
;
1909 return dcc_channel_uint_10_10_10_2
;
1911 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1912 return dcc_channel_uint8
;
1913 return dcc_channel_sint8
;
1915 return dcc_channel_incompatible
;
1919 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1920 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1921 enum pipe_format format2
)
1923 const struct util_format_description
*desc1
, *desc2
;
1924 enum dcc_channel_type type1
, type2
;
1927 if (format1
== format2
)
1930 desc1
= util_format_description(format1
);
1931 desc2
= util_format_description(format2
);
1933 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1936 /* Swizzles must be the same. */
1937 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1938 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1939 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1940 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1943 type1
= vi_get_dcc_channel_type(desc1
);
1944 type2
= vi_get_dcc_channel_type(desc2
);
1946 return type1
!= dcc_channel_incompatible
&&
1947 type2
!= dcc_channel_incompatible
&&
1951 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1953 enum pipe_format view_format
)
1955 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1957 return vi_dcc_enabled(rtex
, level
) &&
1958 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1961 /* This can't be merged with the above function, because
1962 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1963 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1964 struct pipe_resource
*tex
,
1966 enum pipe_format view_format
)
1968 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1970 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1971 if (!si_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1972 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1975 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1976 struct pipe_resource
*texture
,
1977 const struct pipe_surface
*templ
,
1978 unsigned width0
, unsigned height0
,
1979 unsigned width
, unsigned height
)
1981 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1986 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1987 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1989 pipe_reference_init(&surface
->base
.reference
, 1);
1990 pipe_resource_reference(&surface
->base
.texture
, texture
);
1991 surface
->base
.context
= pipe
;
1992 surface
->base
.format
= templ
->format
;
1993 surface
->base
.width
= width
;
1994 surface
->base
.height
= height
;
1995 surface
->base
.u
= templ
->u
;
1997 surface
->width0
= width0
;
1998 surface
->height0
= height0
;
2000 surface
->dcc_incompatible
=
2001 texture
->target
!= PIPE_BUFFER
&&
2002 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2004 return &surface
->base
;
2007 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
2008 struct pipe_resource
*tex
,
2009 const struct pipe_surface
*templ
)
2011 unsigned level
= templ
->u
.tex
.level
;
2012 unsigned width
= u_minify(tex
->width0
, level
);
2013 unsigned height
= u_minify(tex
->height0
, level
);
2014 unsigned width0
= tex
->width0
;
2015 unsigned height0
= tex
->height0
;
2017 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2018 const struct util_format_description
*tex_desc
2019 = util_format_description(tex
->format
);
2020 const struct util_format_description
*templ_desc
2021 = util_format_description(templ
->format
);
2023 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2025 /* Adjust size of surface if and only if the block width or
2026 * height is changed. */
2027 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2028 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2029 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2030 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2032 width
= nblks_x
* templ_desc
->block
.width
;
2033 height
= nblks_y
* templ_desc
->block
.height
;
2035 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2036 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2040 return si_create_surface_custom(pipe
, tex
, templ
,
2045 static void r600_surface_destroy(struct pipe_context
*pipe
,
2046 struct pipe_surface
*surface
)
2048 pipe_resource_reference(&surface
->texture
, NULL
);
2052 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2054 const struct util_format_description
*desc
= util_format_description(format
);
2056 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2058 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2059 return V_028C70_SWAP_STD
;
2061 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2064 switch (desc
->nr_channels
) {
2066 if (HAS_SWIZZLE(0,X
))
2067 return V_028C70_SWAP_STD
; /* X___ */
2068 else if (HAS_SWIZZLE(3,X
))
2069 return V_028C70_SWAP_ALT_REV
; /* ___X */
2072 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2073 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2074 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2075 return V_028C70_SWAP_STD
; /* XY__ */
2076 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2077 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2078 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2080 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2081 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2082 return V_028C70_SWAP_ALT
; /* X__Y */
2083 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2084 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2087 if (HAS_SWIZZLE(0,X
))
2088 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2089 else if (HAS_SWIZZLE(0,Z
))
2090 return V_028C70_SWAP_STD_REV
; /* ZYX */
2093 /* check the middle channels, the 1st and 4th channel can be NONE */
2094 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2095 return V_028C70_SWAP_STD
; /* XYZW */
2096 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2097 return V_028C70_SWAP_STD_REV
; /* WZYX */
2098 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2099 return V_028C70_SWAP_ALT
; /* ZYXW */
2100 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2103 return V_028C70_SWAP_ALT_REV
;
2105 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2112 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2114 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2119 if (rctx
->dcc_stats
[slot
].query_active
)
2120 vi_separate_dcc_stop_query(&rctx
->b
,
2121 rctx
->dcc_stats
[slot
].tex
);
2123 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2124 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2125 rctx
->b
.destroy_query(&rctx
->b
,
2126 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2127 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2130 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2134 * Return the per-context slot where DCC statistics queries for the texture live.
2136 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2137 struct r600_texture
*tex
)
2139 int i
, empty_slot
= -1;
2141 /* Remove zombie textures (textures kept alive by this array only). */
2142 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2143 if (rctx
->dcc_stats
[i
].tex
&&
2144 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2145 vi_dcc_clean_up_context_slot(rctx
, i
);
2147 /* Find the texture. */
2148 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2149 /* Return if found. */
2150 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2151 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2155 /* Record the first seen empty slot. */
2156 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2160 /* Not found. Remove the oldest member to make space in the array. */
2161 if (empty_slot
== -1) {
2162 int oldest_slot
= 0;
2164 /* Find the oldest slot. */
2165 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2166 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2167 rctx
->dcc_stats
[i
].last_use_timestamp
)
2170 /* Clean up the oldest slot. */
2171 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2172 empty_slot
= oldest_slot
;
2175 /* Add the texture to the new slot. */
2176 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2177 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2181 static struct pipe_query
*
2182 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2184 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2185 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2187 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2188 return (struct pipe_query
*)query
;
2192 * Called when binding a color buffer.
2194 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2195 struct r600_texture
*tex
)
2197 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2198 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2200 assert(!rctx
->dcc_stats
[i
].query_active
);
2202 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2203 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2205 /* begin or resume the query */
2206 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2207 rctx
->dcc_stats
[i
].query_active
= true;
2211 * Called when unbinding a color buffer.
2213 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2214 struct r600_texture
*tex
)
2216 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2217 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2219 assert(rctx
->dcc_stats
[i
].query_active
);
2220 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2222 /* pause or end the query */
2223 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2224 rctx
->dcc_stats
[i
].query_active
= false;
2227 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2229 /* The minimum number of fullscreen draws per frame that is required
2231 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2234 /* Called by fast clear. */
2235 void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2236 struct r600_texture
*tex
)
2238 /* The intent is to use this with shared displayable back buffers,
2239 * but it's not strictly limited only to them.
2241 if (!tex
->resource
.b
.is_shared
||
2242 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2243 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2244 tex
->resource
.b
.b
.last_level
> 0 ||
2245 !tex
->surface
.dcc_size
)
2248 if (tex
->dcc_offset
)
2249 return; /* already enabled */
2251 /* Enable the DCC stat gathering. */
2252 if (!tex
->dcc_gather_statistics
) {
2253 tex
->dcc_gather_statistics
= true;
2254 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2257 if (!vi_should_enable_separate_dcc(tex
))
2258 return; /* stats show that DCC decompression is too expensive */
2260 assert(tex
->surface
.num_dcc_levels
);
2261 assert(!tex
->dcc_separate_buffer
);
2263 r600_texture_discard_cmask(rctx
->screen
, tex
);
2265 /* Get a DCC buffer. */
2266 if (tex
->last_dcc_separate_buffer
) {
2267 assert(tex
->dcc_gather_statistics
);
2268 assert(!tex
->dcc_separate_buffer
);
2269 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2270 tex
->last_dcc_separate_buffer
= NULL
;
2272 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2273 si_aligned_buffer_create(rctx
->b
.screen
,
2274 R600_RESOURCE_FLAG_UNMAPPABLE
,
2276 tex
->surface
.dcc_size
,
2277 tex
->surface
.dcc_alignment
);
2278 if (!tex
->dcc_separate_buffer
)
2282 /* dcc_offset is the absolute GPUVM address. */
2283 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2285 /* no need to flag anything since this is called by fast clear that
2286 * flags framebuffer state
2291 * Called by pipe_context::flush_resource, the place where DCC decompression
2294 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2295 struct r600_texture
*tex
)
2297 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2298 struct pipe_query
*tmp
;
2299 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2300 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2301 bool disable
= false;
2303 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2304 union pipe_query_result result
;
2306 /* Read the results. */
2307 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2309 si_query_hw_reset_buffers(rctx
,
2310 (struct r600_query_hw
*)
2311 rctx
->dcc_stats
[i
].ps_stats
[2]);
2313 /* Compute the approximate number of fullscreen draws. */
2314 tex
->ps_draw_ratio
=
2315 result
.pipeline_statistics
.ps_invocations
/
2316 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2317 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2319 disable
= tex
->dcc_separate_buffer
&&
2320 !vi_should_enable_separate_dcc(tex
);
2323 tex
->num_slow_clears
= 0;
2325 /* stop the statistics query for ps_stats[0] */
2327 vi_separate_dcc_stop_query(ctx
, tex
);
2329 /* Move the queries in the queue by one. */
2330 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2331 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2332 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2333 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2335 /* create and start a new query as ps_stats[0] */
2337 vi_separate_dcc_start_query(ctx
, tex
);
2340 assert(!tex
->last_dcc_separate_buffer
);
2341 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2342 tex
->dcc_separate_buffer
= NULL
;
2343 tex
->dcc_offset
= 0;
2344 /* no need to flag anything since this is called after
2345 * decompression that re-sets framebuffer state
2350 static struct pipe_memory_object
*
2351 r600_memobj_from_handle(struct pipe_screen
*screen
,
2352 struct winsys_handle
*whandle
,
2355 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2356 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2357 struct pb_buffer
*buf
= NULL
;
2358 uint32_t stride
, offset
;
2363 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2370 memobj
->b
.dedicated
= dedicated
;
2372 memobj
->stride
= stride
;
2373 memobj
->offset
= offset
;
2375 return (struct pipe_memory_object
*)memobj
;
2380 r600_memobj_destroy(struct pipe_screen
*screen
,
2381 struct pipe_memory_object
*_memobj
)
2383 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2385 pb_reference(&memobj
->buf
, NULL
);
2389 static struct pipe_resource
*
2390 r600_texture_from_memobj(struct pipe_screen
*screen
,
2391 const struct pipe_resource
*templ
,
2392 struct pipe_memory_object
*_memobj
,
2396 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2397 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2398 struct r600_texture
*rtex
;
2399 struct radeon_surf surface
= {};
2400 struct radeon_bo_metadata metadata
= {};
2401 enum radeon_surf_mode array_mode
;
2403 struct pb_buffer
*buf
= NULL
;
2405 if (memobj
->b
.dedicated
) {
2406 sscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2407 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
2408 &array_mode
, &is_scanout
);
2411 * The bo metadata is unset for un-dedicated images. So we fall
2412 * back to linear. See answer to question 5 of the
2413 * VK_KHX_external_memory spec for some details.
2415 * It is possible that this case isn't going to work if the
2416 * surface pitch isn't correctly aligned by default.
2418 * In order to support it correctly we require multi-image
2419 * metadata to be syncrhonized between radv and radeonsi. The
2420 * semantics of associating multiple image metadata to a memory
2421 * object on the vulkan export side are not concretely defined
2424 * All the use cases we are aware of at the moment for memory
2425 * objects use dedicated allocations. So lets keep the initial
2426 * implementation simple.
2428 * A possible alternative is to attempt to reconstruct the
2429 * tiling information when the TexParameter TEXTURE_TILING_EXT
2432 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2437 r
= r600_init_surface(sscreen
, &surface
, templ
,
2438 array_mode
, memobj
->stride
,
2439 offset
, true, is_scanout
,
2444 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2448 /* r600_texture_create_object doesn't increment refcount of
2449 * memobj->buf, so increment it here.
2451 pb_reference(&buf
, memobj
->buf
);
2453 rtex
->resource
.b
.is_shared
= true;
2454 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2456 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
2458 return &rtex
->resource
.b
.b
;
2461 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2462 struct pipe_resource
*resource
,
2465 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2467 /* Buffers only support the linear flag. */
2468 if (resource
->target
== PIPE_BUFFER
)
2469 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2471 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2474 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2477 /* TODO: PIPE_BIND_CURSOR - do we care? */
2481 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2483 sscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2484 sscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2485 sscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2486 sscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2487 sscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2488 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2491 void si_init_context_texture_functions(struct r600_common_context
*rctx
)
2493 rctx
->b
.create_surface
= r600_create_surface
;
2494 rctx
->b
.surface_destroy
= r600_surface_destroy
;