2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "os/os_time.h"
37 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
38 struct r600_texture
*rtex
);
39 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
40 const struct pipe_resource
*templ
);
43 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
44 struct r600_texture
*rdst
,
45 unsigned dst_level
, unsigned dstx
,
46 unsigned dsty
, unsigned dstz
,
47 struct r600_texture
*rsrc
,
49 const struct pipe_box
*src_box
)
54 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
55 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
58 /* MSAA: Blits don't exist in the real world. */
59 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
60 rdst
->resource
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (rsrc
->is_depth
|| rdst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
75 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
79 * src: Both texture and SDMA paths need decompression. Use SDMA.
80 * dst: If overwriting the whole texture, discard CMASK and use
81 * SDMA. Otherwise, use the 3D path.
83 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
84 /* The CMASK clear is only enabled for the first level. */
85 assert(dst_level
== 0);
86 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
87 dstx
, dsty
, dstz
, src_box
->width
,
88 src_box
->height
, src_box
->depth
))
91 r600_texture_discard_cmask(rctx
->screen
, rdst
);
94 /* All requirements are met. Prepare textures for SDMA. */
95 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
96 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
98 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
99 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
104 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
105 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
106 struct pipe_resource
*dst
,
108 unsigned dstx
, unsigned dsty
, unsigned dstz
,
109 struct pipe_resource
*src
,
111 const struct pipe_box
*src_box
)
113 struct pipe_blit_info blit
;
115 memset(&blit
, 0, sizeof(blit
));
116 blit
.src
.resource
= src
;
117 blit
.src
.format
= src
->format
;
118 blit
.src
.level
= src_level
;
119 blit
.src
.box
= *src_box
;
120 blit
.dst
.resource
= dst
;
121 blit
.dst
.format
= dst
->format
;
122 blit
.dst
.level
= dst_level
;
123 blit
.dst
.box
.x
= dstx
;
124 blit
.dst
.box
.y
= dsty
;
125 blit
.dst
.box
.z
= dstz
;
126 blit
.dst
.box
.width
= src_box
->width
;
127 blit
.dst
.box
.height
= src_box
->height
;
128 blit
.dst
.box
.depth
= src_box
->depth
;
129 blit
.mask
= util_format_get_mask(src
->format
) &
130 util_format_get_mask(dst
->format
);
131 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
134 pipe
->blit(pipe
, &blit
);
138 /* Copy from a full GPU texture to a transfer's staging one. */
139 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
141 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
142 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
143 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
144 struct pipe_resource
*src
= transfer
->resource
;
146 if (src
->nr_samples
> 1) {
147 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
148 src
, transfer
->level
, &transfer
->box
);
152 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
156 /* Copy from a transfer's staging texture to a full GPU one. */
157 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
159 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
160 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
161 struct pipe_resource
*dst
= transfer
->resource
;
162 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
163 struct pipe_box sbox
;
165 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
167 if (dst
->nr_samples
> 1) {
168 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
169 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
174 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
175 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
179 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
180 const struct pipe_box
*box
)
182 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
184 return rtex
->surface
.level
[level
].offset
+
185 box
->z
* rtex
->surface
.level
[level
].slice_size
+
186 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
187 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
190 static int r600_init_surface(struct r600_common_screen
*rscreen
,
191 struct radeon_surf
*surface
,
192 const struct pipe_resource
*ptex
,
194 bool is_flushed_depth
)
196 const struct util_format_description
*desc
=
197 util_format_description(ptex
->format
);
198 bool is_depth
, is_stencil
;
200 is_depth
= util_format_has_depth(desc
);
201 is_stencil
= util_format_has_stencil(desc
);
203 surface
->npix_x
= ptex
->width0
;
204 surface
->npix_y
= ptex
->height0
;
205 surface
->npix_z
= ptex
->depth0
;
206 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
207 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
209 surface
->array_size
= 1;
210 surface
->last_level
= ptex
->last_level
;
212 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
213 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
214 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
216 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
217 /* align byte per element on dword */
218 if (surface
->bpe
== 3) {
223 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
224 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
226 switch (ptex
->target
) {
227 case PIPE_TEXTURE_1D
:
228 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
230 case PIPE_TEXTURE_RECT
:
231 case PIPE_TEXTURE_2D
:
232 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
234 case PIPE_TEXTURE_3D
:
235 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
237 case PIPE_TEXTURE_1D_ARRAY
:
238 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
239 surface
->array_size
= ptex
->array_size
;
241 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
242 assert(ptex
->array_size
% 6 == 0);
243 case PIPE_TEXTURE_2D_ARRAY
:
244 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
245 surface
->array_size
= ptex
->array_size
;
247 case PIPE_TEXTURE_CUBE
:
248 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
255 if (!is_flushed_depth
&& is_depth
) {
256 surface
->flags
|= RADEON_SURF_ZBUFFER
;
259 surface
->flags
|= RADEON_SURF_SBUFFER
|
260 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
263 if (rscreen
->chip_class
>= SI
) {
264 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
267 if (rscreen
->chip_class
>= VI
&&
268 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
269 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
270 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
272 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
273 /* This should catch bugs in gallium users setting incorrect flags. */
274 assert(surface
->nsamples
== 1 &&
275 surface
->array_size
== 1 &&
276 surface
->npix_z
== 1 &&
277 surface
->last_level
== 0 &&
278 !(surface
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
280 surface
->flags
|= RADEON_SURF_SCANOUT
;
285 static int r600_setup_surface(struct pipe_screen
*screen
,
286 struct r600_texture
*rtex
,
287 unsigned pitch_in_bytes_override
,
290 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
294 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
299 rtex
->size
= rtex
->surface
.bo_size
;
301 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
302 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
305 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
306 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
307 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
311 for (i
= 0; i
< ARRAY_SIZE(rtex
->surface
.level
); ++i
)
312 rtex
->surface
.level
[i
].offset
+= offset
;
317 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
318 struct radeon_bo_metadata
*metadata
)
320 struct radeon_surf
*surface
= &rtex
->surface
;
322 memset(metadata
, 0, sizeof(*metadata
));
323 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
324 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
325 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
326 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
327 metadata
->pipe_config
= surface
->pipe_config
;
328 metadata
->bankw
= surface
->bankw
;
329 metadata
->bankh
= surface
->bankh
;
330 metadata
->tile_split
= surface
->tile_split
;
331 metadata
->mtilea
= surface
->mtilea
;
332 metadata
->num_banks
= surface
->num_banks
;
333 metadata
->stride
= surface
->level
[0].pitch_bytes
;
334 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
337 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
339 p_atomic_inc(&rscreen
->dirty_fb_counter
);
342 static void r600_eliminate_fast_color_clear(struct r600_common_screen
*rscreen
,
343 struct r600_texture
*rtex
)
345 struct pipe_context
*ctx
= rscreen
->aux_context
;
347 pipe_mutex_lock(rscreen
->aux_context_lock
);
348 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
349 ctx
->flush(ctx
, NULL
, 0);
350 pipe_mutex_unlock(rscreen
->aux_context_lock
);
353 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
354 struct r600_texture
*rtex
)
356 if (!rtex
->cmask
.size
)
359 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
362 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
363 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
365 if (rscreen
->chip_class
>= SI
)
366 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
368 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
370 if (rtex
->cmask_buffer
!= &rtex
->resource
)
371 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
373 /* Notify all contexts about the change. */
374 r600_dirty_all_framebuffer_states(rscreen
);
375 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
378 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
380 /* We can't disable DCC if it can be written by another process. */
381 return rtex
->dcc_offset
&&
382 (!rtex
->resource
.is_shared
||
383 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
386 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
387 struct r600_texture
*rtex
)
389 if (!r600_can_disable_dcc(rtex
))
392 assert(rtex
->dcc_separate_buffer
== NULL
);
395 rtex
->dcc_offset
= 0;
397 /* Notify all contexts about the change. */
398 r600_dirty_all_framebuffer_states(rscreen
);
402 bool r600_texture_disable_dcc(struct r600_common_screen
*rscreen
,
403 struct r600_texture
*rtex
)
405 struct r600_common_context
*rctx
=
406 (struct r600_common_context
*)rscreen
->aux_context
;
408 if (!r600_can_disable_dcc(rtex
))
411 /* Decompress DCC. */
412 pipe_mutex_lock(rscreen
->aux_context_lock
);
413 rctx
->decompress_dcc(&rctx
->b
, rtex
);
414 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
415 pipe_mutex_unlock(rscreen
->aux_context_lock
);
417 return r600_texture_discard_dcc(rscreen
, rtex
);
420 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
421 struct r600_texture
*rtex
,
422 bool invalidate_storage
)
424 struct pipe_screen
*screen
= rctx
->b
.screen
;
425 struct r600_texture
*new_tex
;
426 struct pipe_resource templ
= rtex
->resource
.b
.b
;
429 templ
.bind
|= PIPE_BIND_LINEAR
;
431 /* r600g doesn't react to dirty_tex_descriptor_counter */
432 if (rctx
->chip_class
< SI
)
435 if (rtex
->resource
.is_shared
||
436 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
439 /* This fails with MSAA, depth, and compressed textures. */
440 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
441 RADEON_SURF_MODE_LINEAR_ALIGNED
)
444 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
448 /* Copy the pixels to the new texture. */
449 if (!invalidate_storage
) {
450 for (i
= 0; i
<= templ
.last_level
; i
++) {
454 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
455 util_max_layer(&templ
, i
) + 1, &box
);
457 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
458 &rtex
->resource
.b
.b
, i
, &box
);
462 r600_texture_discard_cmask(rctx
->screen
, rtex
);
463 r600_texture_discard_dcc(rctx
->screen
, rtex
);
465 /* Replace the structure fields of rtex. */
466 rtex
->resource
.b
.b
.bind
= templ
.bind
;
467 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
468 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
469 rtex
->resource
.domains
= new_tex
->resource
.domains
;
470 rtex
->size
= new_tex
->size
;
471 rtex
->surface
= new_tex
->surface
;
472 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
473 rtex
->cb_color_info
= new_tex
->cb_color_info
;
474 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
476 assert(!rtex
->htile_buffer
);
477 assert(!rtex
->cmask
.size
);
478 assert(!rtex
->fmask
.size
);
479 assert(!rtex
->dcc_offset
);
480 assert(!rtex
->is_depth
);
482 r600_texture_reference(&new_tex
, NULL
);
484 r600_dirty_all_framebuffer_states(rctx
->screen
);
485 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
488 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
489 struct pipe_resource
*resource
,
490 struct winsys_handle
*whandle
,
493 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
494 struct r600_resource
*res
= (struct r600_resource
*)resource
;
495 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
496 struct radeon_bo_metadata metadata
;
497 bool update_metadata
= false;
499 /* This is not supported now, but it might be required for OpenCL
500 * interop in the future.
502 if (resource
->target
!= PIPE_BUFFER
&&
503 (resource
->nr_samples
> 1 || rtex
->is_depth
))
506 if (resource
->target
!= PIPE_BUFFER
) {
507 /* Since shader image stores don't support DCC on VI,
508 * disable it for external clients that want write
511 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
512 if (r600_texture_disable_dcc(rscreen
, rtex
))
513 update_metadata
= true;
516 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
518 /* Eliminate fast clear (both CMASK and DCC) */
519 r600_eliminate_fast_color_clear(rscreen
, rtex
);
521 /* Disable CMASK if flush_resource isn't going
524 r600_texture_discard_cmask(rscreen
, rtex
);
528 if (!res
->is_shared
|| update_metadata
) {
529 r600_texture_init_metadata(rtex
, &metadata
);
530 if (rscreen
->query_opaque_metadata
)
531 rscreen
->query_opaque_metadata(rscreen
, rtex
,
534 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
538 if (res
->is_shared
) {
539 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
542 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
543 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
544 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
546 res
->is_shared
= true;
547 res
->external_usage
= usage
;
550 return rscreen
->ws
->buffer_get_handle(res
->buf
,
551 rtex
->surface
.level
[0].pitch_bytes
,
552 rtex
->surface
.level
[0].offset
,
553 rtex
->surface
.level
[0].slice_size
,
557 static void r600_texture_destroy(struct pipe_screen
*screen
,
558 struct pipe_resource
*ptex
)
560 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
561 struct r600_resource
*resource
= &rtex
->resource
;
563 if (rtex
->flushed_depth_texture
)
564 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
566 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
567 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
568 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
570 pb_reference(&resource
->buf
, NULL
);
571 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
572 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
576 static const struct u_resource_vtbl r600_texture_vtbl
;
578 /* The number of samples can be specified independently of the texture. */
579 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
580 struct r600_texture
*rtex
,
582 struct r600_fmask_info
*out
)
584 /* FMASK is allocated like an ordinary texture. */
585 struct radeon_surf fmask
= rtex
->surface
;
587 memset(out
, 0, sizeof(*out
));
589 fmask
.bo_alignment
= 0;
592 fmask
.flags
|= RADEON_SURF_FMASK
;
594 /* Force 2D tiling if it wasn't set. This may occur when creating
595 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
596 * destination buffer must have an FMASK too. */
597 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
598 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
600 if (rscreen
->chip_class
>= SI
) {
601 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
604 switch (nr_samples
) {
608 if (rscreen
->chip_class
<= CAYMAN
) {
616 R600_ERR("Invalid sample count for FMASK allocation.\n");
620 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
621 * This can be fixed by writing a separate FMASK allocator specifically
622 * for R600-R700 asics. */
623 if (rscreen
->chip_class
<= R700
) {
627 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
628 R600_ERR("Got error in surface_init while allocating FMASK.\n");
632 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
634 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
635 if (out
->slice_tile_max
)
636 out
->slice_tile_max
-= 1;
638 out
->tile_mode_index
= fmask
.tiling_index
[0];
639 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
640 out
->bank_height
= fmask
.bankh
;
641 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
642 out
->size
= fmask
.bo_size
;
645 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
646 struct r600_texture
*rtex
)
648 r600_texture_get_fmask_info(rscreen
, rtex
,
649 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
651 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
652 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
655 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
656 struct r600_texture
*rtex
,
657 struct r600_cmask_info
*out
)
659 unsigned cmask_tile_width
= 8;
660 unsigned cmask_tile_height
= 8;
661 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
662 unsigned element_bits
= 4;
663 unsigned cmask_cache_bits
= 1024;
664 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
665 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
667 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
668 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
669 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
670 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
671 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
673 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
674 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
676 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
677 unsigned slice_bytes
=
678 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
680 assert(macro_tile_width
% 128 == 0);
681 assert(macro_tile_height
% 128 == 0);
683 out
->pitch
= pitch_elements
;
684 out
->height
= height
;
685 out
->xalign
= macro_tile_width
;
686 out
->yalign
= macro_tile_height
;
687 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
688 out
->alignment
= MAX2(256, base_align
);
689 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
690 align(slice_bytes
, base_align
);
693 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
694 struct r600_texture
*rtex
,
695 struct r600_cmask_info
*out
)
697 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
698 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
699 unsigned cl_width
, cl_height
;
714 case 16: /* Hawaii */
723 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
725 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
726 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
727 unsigned slice_elements
= (width
* height
) / (8*8);
729 /* Each element of CMASK is a nibble. */
730 unsigned slice_bytes
= slice_elements
/ 2;
733 out
->height
= height
;
734 out
->xalign
= cl_width
* 8;
735 out
->yalign
= cl_height
* 8;
736 out
->slice_tile_max
= (width
* height
) / (128*128);
737 if (out
->slice_tile_max
)
738 out
->slice_tile_max
-= 1;
740 out
->alignment
= MAX2(256, base_align
);
741 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
742 align(slice_bytes
, base_align
);
745 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
746 struct r600_texture
*rtex
)
748 if (rscreen
->chip_class
>= SI
) {
749 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
751 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
754 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
755 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
757 if (rscreen
->chip_class
>= SI
)
758 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
760 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
763 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
764 struct r600_texture
*rtex
)
766 if (rtex
->cmask_buffer
)
769 assert(rtex
->cmask
.size
== 0);
771 if (rscreen
->chip_class
>= SI
) {
772 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
774 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
777 rtex
->cmask_buffer
= (struct r600_resource
*)
778 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
779 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
780 if (rtex
->cmask_buffer
== NULL
) {
781 rtex
->cmask
.size
= 0;
785 /* update colorbuffer state bits */
786 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
788 if (rscreen
->chip_class
>= SI
)
789 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
791 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
793 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
796 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
797 struct r600_texture
*rtex
)
799 unsigned cl_width
, cl_height
, width
, height
;
800 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
801 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
803 if (rscreen
->chip_class
<= EVERGREEN
&&
804 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
807 /* HW bug on R6xx. */
808 if (rscreen
->chip_class
== R600
&&
809 (rtex
->surface
.level
[0].npix_x
> 7680 ||
810 rtex
->surface
.level
[0].npix_y
> 7680))
813 /* HTILE is broken with 1D tiling on old kernels and CIK. */
814 if (rscreen
->chip_class
>= CIK
&&
815 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
816 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
819 /* Overalign HTILE on P2 configs to work around GPU hangs in
820 * piglit/depthstencil-render-miplevels 585.
822 * This has been confirmed to help Kabini & Stoney, where the hangs
823 * are always reproducible. I think I have seen the test hang
824 * on Carrizo too, though it was very rare there.
826 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
855 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
856 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
858 slice_elements
= (width
* height
) / (8 * 8);
859 slice_bytes
= slice_elements
* 4;
861 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
862 base_align
= num_pipes
* pipe_interleave_bytes
;
864 rtex
->htile
.pitch
= width
;
865 rtex
->htile
.height
= height
;
866 rtex
->htile
.xalign
= cl_width
* 8;
867 rtex
->htile
.yalign
= cl_height
* 8;
869 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
870 align(slice_bytes
, base_align
);
873 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
874 struct r600_texture
*rtex
)
876 unsigned htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
881 rtex
->htile_buffer
= (struct r600_resource
*)
882 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
883 PIPE_USAGE_DEFAULT
, htile_size
);
884 if (rtex
->htile_buffer
== NULL
) {
885 /* this is not a fatal error as we can still keep rendering
886 * without htile buffer */
887 R600_ERR("Failed to create buffer object for htile buffer.\n");
889 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0,
890 htile_size
, 0, R600_COHERENCY_NONE
);
894 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
898 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
899 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
900 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
901 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
902 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
903 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
904 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
905 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
906 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
908 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
909 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
910 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
911 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
912 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
913 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
915 if (rtex
->fmask
.size
)
916 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
917 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
918 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
919 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
920 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
922 if (rtex
->cmask
.size
)
923 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
924 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
925 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
926 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
927 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
929 if (rtex
->htile_buffer
)
930 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
931 "xalign=%u, yalign=%u\n",
932 rtex
->htile_buffer
->b
.b
.width0
,
933 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
934 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
);
936 if (rtex
->dcc_offset
) {
937 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
938 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
939 rtex
->surface
.dcc_alignment
);
940 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
941 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
942 "fast_clear_size=%"PRIu64
"\n",
943 i
, rtex
->surface
.level
[i
].dcc_enabled
,
944 rtex
->surface
.level
[i
].dcc_offset
,
945 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
948 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
949 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
950 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
951 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
952 i
, rtex
->surface
.level
[i
].offset
,
953 rtex
->surface
.level
[i
].slice_size
,
954 u_minify(rtex
->resource
.b
.b
.width0
, i
),
955 u_minify(rtex
->resource
.b
.b
.height0
, i
),
956 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
957 rtex
->surface
.level
[i
].nblk_x
,
958 rtex
->surface
.level
[i
].nblk_y
,
959 rtex
->surface
.level
[i
].nblk_z
,
960 rtex
->surface
.level
[i
].pitch_bytes
,
961 rtex
->surface
.level
[i
].mode
);
963 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
964 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
965 fprintf(f
, " StencilLayout: tilesplit=%u\n",
966 rtex
->surface
.stencil_tile_split
);
967 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
968 "slice_size=%"PRIu64
", npix_x=%u, "
969 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
970 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
971 i
, rtex
->surface
.stencil_level
[i
].offset
,
972 rtex
->surface
.stencil_level
[i
].slice_size
,
973 u_minify(rtex
->resource
.b
.b
.width0
, i
),
974 u_minify(rtex
->resource
.b
.b
.height0
, i
),
975 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
976 rtex
->surface
.stencil_level
[i
].nblk_x
,
977 rtex
->surface
.stencil_level
[i
].nblk_y
,
978 rtex
->surface
.stencil_level
[i
].nblk_z
,
979 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
980 rtex
->surface
.stencil_level
[i
].mode
);
985 /* Common processing for r600_texture_create and r600_texture_from_handle */
986 static struct r600_texture
*
987 r600_texture_create_object(struct pipe_screen
*screen
,
988 const struct pipe_resource
*base
,
989 unsigned pitch_in_bytes_override
,
991 struct pb_buffer
*buf
,
992 struct radeon_surf
*surface
)
994 struct r600_texture
*rtex
;
995 struct r600_resource
*resource
;
996 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
998 rtex
= CALLOC_STRUCT(r600_texture
);
1002 resource
= &rtex
->resource
;
1003 resource
->b
.b
= *base
;
1004 resource
->b
.vtbl
= &r600_texture_vtbl
;
1005 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1006 resource
->b
.b
.screen
= screen
;
1008 /* don't include stencil-only formats which we don't support for rendering */
1009 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1011 rtex
->surface
= *surface
;
1012 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
, offset
)) {
1017 /* Tiled depth textures utilize the non-displayable tile order.
1018 * This must be done after r600_setup_surface.
1019 * Applies to R600-Cayman. */
1020 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1021 /* Applies to GCN. */
1022 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1024 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1025 * between frames, so the only thing that can enable separate DCC
1026 * with DRI2 is multiple slow clears within a frame.
1028 rtex
->ps_draw_ratio
= 0;
1030 if (rtex
->is_depth
) {
1031 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1032 R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
1033 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
)) {
1035 r600_texture_allocate_htile(rscreen
, rtex
);
1038 if (base
->nr_samples
> 1) {
1040 r600_texture_allocate_fmask(rscreen
, rtex
);
1041 r600_texture_allocate_cmask(rscreen
, rtex
);
1042 rtex
->cmask_buffer
= &rtex
->resource
;
1044 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1050 /* Shared textures must always set up DCC here.
1051 * If it's not present, it will be disabled by
1052 * apply_opaque_metadata later.
1054 if (rtex
->surface
.dcc_size
&&
1055 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1056 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1057 /* Reserve space for the DCC buffer. */
1058 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1059 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1063 /* Now create the backing buffer. */
1065 if (!r600_init_resource(rscreen
, resource
, rtex
->size
,
1066 rtex
->surface
.bo_alignment
)) {
1071 resource
->buf
= buf
;
1072 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1073 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1076 if (rtex
->cmask
.size
) {
1077 /* Initialize the cmask to 0xCC (= compressed state). */
1078 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1079 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1080 0xCCCCCCCC, R600_COHERENCY_NONE
);
1083 /* Initialize DCC only if the texture is not being imported. */
1084 if (!buf
&& rtex
->dcc_offset
) {
1085 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1087 rtex
->surface
.dcc_size
,
1088 0xFFFFFFFF, R600_COHERENCY_NONE
);
1091 /* Initialize the CMASK base register value. */
1092 rtex
->cmask
.base_address_reg
=
1093 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1095 if (rscreen
->debug_flags
& DBG_VM
) {
1096 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1097 rtex
->resource
.gpu_address
,
1098 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1099 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1100 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1103 if (rscreen
->debug_flags
& DBG_TEX
) {
1105 r600_print_texture_info(rtex
, stdout
);
1111 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
1112 const struct pipe_resource
*templ
)
1114 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1115 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1117 /* MSAA resources must be 2D tiled. */
1118 if (templ
->nr_samples
> 1)
1119 return RADEON_SURF_MODE_2D
;
1121 /* Transfer resources should be linear. */
1122 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1123 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1125 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1126 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1127 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1128 (templ
->target
== PIPE_TEXTURE_2D
||
1129 templ
->target
== PIPE_TEXTURE_3D
))
1130 force_tiling
= true;
1132 /* Handle common candidates for the linear mode.
1133 * Compressed textures and DB surfaces must always be tiled.
1135 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1136 (!util_format_is_depth_or_stencil(templ
->format
) ||
1137 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1138 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1139 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1141 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1142 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1143 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1145 /* Cursors are linear on SI.
1146 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1147 if (rscreen
->chip_class
>= SI
&&
1148 (templ
->bind
& PIPE_BIND_CURSOR
))
1149 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1151 if (templ
->bind
& PIPE_BIND_LINEAR
)
1152 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1154 /* Textures with a very small height are recommended to be linear. */
1155 if (templ
->target
== PIPE_TEXTURE_1D
||
1156 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1157 templ
->height0
<= 4)
1158 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1160 /* Textures likely to be mapped often. */
1161 if (templ
->usage
== PIPE_USAGE_STAGING
||
1162 templ
->usage
== PIPE_USAGE_STREAM
)
1163 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1166 /* Make small textures 1D tiled. */
1167 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1168 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1169 return RADEON_SURF_MODE_1D
;
1171 /* The allocator will switch to 1D if needed. */
1172 return RADEON_SURF_MODE_2D
;
1175 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1176 const struct pipe_resource
*templ
)
1178 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1179 struct radeon_surf surface
= {0};
1182 r
= r600_init_surface(rscreen
, &surface
, templ
,
1183 r600_choose_tiling(rscreen
, templ
),
1184 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1188 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
1192 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, 0,
1196 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1197 const struct pipe_resource
*templ
,
1198 struct winsys_handle
*whandle
,
1201 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1202 struct pb_buffer
*buf
= NULL
;
1203 unsigned stride
= 0, offset
= 0;
1204 unsigned array_mode
;
1205 struct radeon_surf surface
;
1207 struct radeon_bo_metadata metadata
= {};
1208 struct r600_texture
*rtex
;
1210 /* Support only 2D textures without mipmaps */
1211 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1212 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1215 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1219 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1221 surface
.pipe_config
= metadata
.pipe_config
;
1222 surface
.bankw
= metadata
.bankw
;
1223 surface
.bankh
= metadata
.bankh
;
1224 surface
.tile_split
= metadata
.tile_split
;
1225 surface
.mtilea
= metadata
.mtilea
;
1226 surface
.num_banks
= metadata
.num_banks
;
1228 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1229 array_mode
= RADEON_SURF_MODE_2D
;
1230 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1231 array_mode
= RADEON_SURF_MODE_1D
;
1233 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1235 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
1240 if (metadata
.scanout
)
1241 surface
.flags
|= RADEON_SURF_SCANOUT
;
1243 rtex
= r600_texture_create_object(screen
, templ
, stride
,
1244 offset
, buf
, &surface
);
1248 rtex
->resource
.is_shared
= true;
1249 rtex
->resource
.external_usage
= usage
;
1251 if (rscreen
->apply_opaque_metadata
)
1252 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1254 return &rtex
->resource
.b
.b
;
1257 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1258 struct pipe_resource
*texture
,
1259 struct r600_texture
**staging
)
1261 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1262 struct pipe_resource resource
;
1263 struct r600_texture
**flushed_depth_texture
= staging
?
1264 staging
: &rtex
->flushed_depth_texture
;
1266 if (!staging
&& rtex
->flushed_depth_texture
)
1267 return true; /* it's ready */
1269 resource
.target
= texture
->target
;
1270 resource
.format
= texture
->format
;
1271 resource
.width0
= texture
->width0
;
1272 resource
.height0
= texture
->height0
;
1273 resource
.depth0
= texture
->depth0
;
1274 resource
.array_size
= texture
->array_size
;
1275 resource
.last_level
= texture
->last_level
;
1276 resource
.nr_samples
= texture
->nr_samples
;
1277 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1278 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1279 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1282 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1284 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1285 if (*flushed_depth_texture
== NULL
) {
1286 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1290 (*flushed_depth_texture
)->is_flushing_texture
= true;
1291 (*flushed_depth_texture
)->non_disp_tiling
= false;
1296 * Initialize the pipe_resource descriptor to be of the same size as the box,
1297 * which is supposed to hold a subregion of the texture "orig" at the given
1300 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1301 struct pipe_resource
*orig
,
1302 const struct pipe_box
*box
,
1303 unsigned level
, unsigned flags
)
1305 memset(res
, 0, sizeof(*res
));
1306 res
->format
= orig
->format
;
1307 res
->width0
= box
->width
;
1308 res
->height0
= box
->height
;
1310 res
->array_size
= 1;
1311 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1314 /* We must set the correct texture target and dimensions for a 3D box. */
1315 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1316 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1317 res
->array_size
= box
->depth
;
1319 res
->target
= PIPE_TEXTURE_2D
;
1323 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1324 struct r600_texture
*rtex
,
1325 unsigned transfer_usage
,
1326 const struct pipe_box
*box
)
1328 /* r600g doesn't react to dirty_tex_descriptor_counter */
1329 return rscreen
->chip_class
>= SI
&&
1330 !rtex
->resource
.is_shared
&&
1331 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1332 rtex
->resource
.b
.b
.last_level
== 0 &&
1333 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1334 box
->x
, box
->y
, box
->z
,
1335 box
->width
, box
->height
,
1339 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1340 struct r600_texture
*rtex
)
1342 struct r600_common_screen
*rscreen
= rctx
->screen
;
1344 /* There is no point in discarding depth and tiled buffers. */
1345 assert(!rtex
->is_depth
);
1346 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1348 /* Reallocate the buffer in the same pipe_resource. */
1349 r600_init_resource(rscreen
, &rtex
->resource
, rtex
->size
,
1350 rtex
->surface
.bo_alignment
);
1352 /* Initialize the CMASK base address (needed even without CMASK). */
1353 rtex
->cmask
.base_address_reg
=
1354 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1356 r600_dirty_all_framebuffer_states(rscreen
);
1357 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1359 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1362 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1363 struct pipe_resource
*texture
,
1366 const struct pipe_box
*box
,
1367 struct pipe_transfer
**ptransfer
)
1369 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1370 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1371 struct r600_transfer
*trans
;
1372 struct r600_resource
*buf
;
1373 unsigned offset
= 0;
1375 bool use_staging_texture
= false;
1377 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1379 /* Depth textures use staging unconditionally. */
1380 if (!rtex
->is_depth
) {
1381 /* Degrade the tile mode if we get too many transfers on APUs.
1382 * On dGPUs, the staging texture is always faster.
1383 * Only count uploads that are at least 4x4 pixels large.
1385 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1387 box
->width
>= 4 && box
->height
>= 4 &&
1388 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1389 bool can_invalidate
=
1390 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1393 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1397 /* Tiled textures need to be converted into a linear texture for CPU
1398 * access. The staging texture is always linear and is placed in GART.
1400 * Reading from VRAM is slow, always use the staging texture in
1403 * Use the staging texture for uploads if the underlying BO
1406 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1407 use_staging_texture
= true;
1408 else if (usage
& PIPE_TRANSFER_READ
)
1409 use_staging_texture
= (rtex
->resource
.domains
&
1410 RADEON_DOMAIN_VRAM
) != 0;
1411 /* Write & linear only: */
1412 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1413 RADEON_USAGE_READWRITE
) ||
1414 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1415 RADEON_USAGE_READWRITE
)) {
1417 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1419 r600_texture_invalidate_storage(rctx
, rtex
);
1421 use_staging_texture
= true;
1425 trans
= CALLOC_STRUCT(r600_transfer
);
1428 trans
->transfer
.resource
= texture
;
1429 trans
->transfer
.level
= level
;
1430 trans
->transfer
.usage
= usage
;
1431 trans
->transfer
.box
= *box
;
1433 if (rtex
->is_depth
) {
1434 struct r600_texture
*staging_depth
;
1436 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1437 /* MSAA depth buffers need to be converted to single sample buffers.
1439 * Mapping MSAA depth buffers can occur if ReadPixels is called
1440 * with a multisample GLX visual.
1442 * First downsample the depth buffer to a temporary texture,
1443 * then decompress the temporary one to staging.
1445 * Only the region being mapped is transfered.
1447 struct pipe_resource resource
;
1449 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1451 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1452 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1457 if (usage
& PIPE_TRANSFER_READ
) {
1458 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1460 R600_ERR("failed to create a temporary depth texture\n");
1465 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1466 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1467 0, 0, 0, box
->depth
, 0, 0);
1468 pipe_resource_reference(&temp
, NULL
);
1472 /* XXX: only readback the rectangle which is being mapped? */
1473 /* XXX: when discard is true, no need to read back from depth texture */
1474 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1475 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1480 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1482 box
->z
, box
->z
+ box
->depth
- 1,
1485 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1488 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1489 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1490 trans
->staging
= (struct r600_resource
*)staging_depth
;
1491 buf
= trans
->staging
;
1492 } else if (use_staging_texture
) {
1493 struct pipe_resource resource
;
1494 struct r600_texture
*staging
;
1496 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1497 R600_RESOURCE_FLAG_TRANSFER
);
1498 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1499 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1501 /* Create the temporary texture. */
1502 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1504 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1508 trans
->staging
= &staging
->resource
;
1509 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1510 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1512 if (usage
& PIPE_TRANSFER_READ
)
1513 r600_copy_to_staging_texture(ctx
, trans
);
1515 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1517 buf
= trans
->staging
;
1519 /* the resource is mapped directly */
1520 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1521 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1522 offset
= r600_texture_get_offset(rtex
, level
, box
);
1523 buf
= &rtex
->resource
;
1526 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1527 r600_resource_reference(&trans
->staging
, NULL
);
1532 *ptransfer
= &trans
->transfer
;
1533 return map
+ offset
;
1536 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1537 struct pipe_transfer
* transfer
)
1539 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1540 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1541 struct pipe_resource
*texture
= transfer
->resource
;
1542 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1544 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1545 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1546 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1547 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1548 &rtransfer
->staging
->b
.b
, transfer
->level
,
1551 r600_copy_from_staging_texture(ctx
, rtransfer
);
1555 if (rtransfer
->staging
) {
1556 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1557 r600_resource_reference(&rtransfer
->staging
, NULL
);
1560 /* Heuristic for {upload, draw, upload, draw, ..}:
1562 * Flush the gfx IB if we've allocated too much texture storage.
1564 * The idea is that we don't want to build IBs that use too much
1565 * memory and put pressure on the kernel memory manager and we also
1566 * want to make temporary and invalidated buffers go idle ASAP to
1567 * decrease the total memory usage or make them reusable. The memory
1568 * usage will be slightly higher than given here because of the buffer
1569 * cache in the winsys.
1571 * The result is that the kernel memory manager is never a bottleneck.
1573 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1574 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1575 rctx
->num_alloc_tex_transfer_bytes
= 0;
1581 static const struct u_resource_vtbl r600_texture_vtbl
=
1583 NULL
, /* get_handle */
1584 r600_texture_destroy
, /* resource_destroy */
1585 r600_texture_transfer_map
, /* transfer_map */
1586 u_default_transfer_flush_region
, /* transfer_flush_region */
1587 r600_texture_transfer_unmap
, /* transfer_unmap */
1588 NULL
/* transfer_inline_write */
1591 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1592 struct pipe_resource
*texture
,
1593 const struct pipe_surface
*templ
,
1594 unsigned width
, unsigned height
)
1596 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1597 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1602 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1603 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1605 pipe_reference_init(&surface
->base
.reference
, 1);
1606 pipe_resource_reference(&surface
->base
.texture
, texture
);
1607 surface
->base
.context
= pipe
;
1608 surface
->base
.format
= templ
->format
;
1609 surface
->base
.width
= width
;
1610 surface
->base
.height
= height
;
1611 surface
->base
.u
= templ
->u
;
1612 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1613 return &surface
->base
;
1616 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1617 struct pipe_resource
*tex
,
1618 const struct pipe_surface
*templ
)
1620 unsigned level
= templ
->u
.tex
.level
;
1621 unsigned width
= u_minify(tex
->width0
, level
);
1622 unsigned height
= u_minify(tex
->height0
, level
);
1624 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1625 const struct util_format_description
*tex_desc
1626 = util_format_description(tex
->format
);
1627 const struct util_format_description
*templ_desc
1628 = util_format_description(templ
->format
);
1630 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1632 /* Adjust size of surface if and only if the block width or
1633 * height is changed. */
1634 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1635 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1636 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1637 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1639 width
= nblks_x
* templ_desc
->block
.width
;
1640 height
= nblks_y
* templ_desc
->block
.height
;
1644 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1647 static void r600_surface_destroy(struct pipe_context
*pipe
,
1648 struct pipe_surface
*surface
)
1650 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1651 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1652 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1653 pipe_resource_reference(&surface
->texture
, NULL
);
1657 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1659 const struct util_format_description
*desc
= util_format_description(format
);
1661 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1663 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1664 return V_0280A0_SWAP_STD
;
1666 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1669 switch (desc
->nr_channels
) {
1671 if (HAS_SWIZZLE(0,X
))
1672 return V_0280A0_SWAP_STD
; /* X___ */
1673 else if (HAS_SWIZZLE(3,X
))
1674 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1677 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1678 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1679 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1680 return V_0280A0_SWAP_STD
; /* XY__ */
1681 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1682 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1683 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1685 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1686 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1687 return V_0280A0_SWAP_ALT
; /* X__Y */
1688 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1689 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1692 if (HAS_SWIZZLE(0,X
))
1693 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1694 else if (HAS_SWIZZLE(0,Z
))
1695 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1698 /* check the middle channels, the 1st and 4th channel can be NONE */
1699 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1700 return V_0280A0_SWAP_STD
; /* XYZW */
1701 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1702 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1703 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1704 return V_0280A0_SWAP_ALT
; /* ZYXW */
1705 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1708 return V_0280A0_SWAP_ALT_REV
;
1710 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1717 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1720 * Return the per-context slot where DCC statistics queries for the texture live.
1722 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1723 struct r600_texture
*tex
)
1725 int i
, empty_slot
= -1;
1727 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
1728 /* Return if found. */
1729 if (rctx
->dcc_stats
[i
].tex
== tex
) {
1730 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
1734 /* Record the first seen empty slot. */
1735 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
1739 /* Not found. Remove the oldest member to make space in the array. */
1740 if (empty_slot
== -1) {
1741 int oldest_slot
= 0;
1743 /* Find the oldest slot. */
1744 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1745 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
1746 rctx
->dcc_stats
[i
].last_use_timestamp
)
1749 /* Clean up the oldest slot. */
1750 if (rctx
->dcc_stats
[oldest_slot
].query_active
)
1751 vi_separate_dcc_stop_query(&rctx
->b
,
1752 rctx
->dcc_stats
[oldest_slot
].tex
);
1754 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[oldest_slot
].ps_stats
); i
++)
1755 if (rctx
->dcc_stats
[oldest_slot
].ps_stats
[i
]) {
1756 rctx
->b
.destroy_query(&rctx
->b
,
1757 rctx
->dcc_stats
[oldest_slot
].ps_stats
[i
]);
1758 rctx
->dcc_stats
[oldest_slot
].ps_stats
[i
] = NULL
;
1761 r600_texture_reference(&rctx
->dcc_stats
[oldest_slot
].tex
, NULL
);
1762 empty_slot
= oldest_slot
;
1765 /* Add the texture to the new slot. */
1766 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
1767 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
1771 static struct pipe_query
*
1772 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
1774 struct r600_query_hw
*query
= (struct r600_query_hw
*)
1775 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
1777 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
1778 return (struct pipe_query
*)query
;
1782 * Called when binding a color buffer.
1784 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
1785 struct r600_texture
*tex
)
1787 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1788 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1790 assert(!rctx
->dcc_stats
[i
].query_active
);
1792 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
1793 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
1795 /* begin or resume the query */
1796 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
1797 rctx
->dcc_stats
[i
].query_active
= true;
1801 * Called when unbinding a color buffer.
1803 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
1804 struct r600_texture
*tex
)
1806 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1807 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1809 assert(rctx
->dcc_stats
[i
].query_active
);
1810 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
1812 /* pause or end the query */
1813 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
1814 rctx
->dcc_stats
[i
].query_active
= false;
1817 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
1819 /* The minimum number of fullscreen draws per frame that is required
1821 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
1824 /* Called by fast clear. */
1825 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
1826 struct r600_texture
*tex
)
1828 /* The intent is to use this with shared displayable back buffers,
1829 * but it's not strictly limited only to them.
1831 if (!tex
->resource
.is_shared
||
1832 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
1833 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
1834 tex
->surface
.last_level
> 0 ||
1835 !tex
->surface
.dcc_size
)
1838 if (tex
->dcc_offset
)
1839 return; /* already enabled */
1841 /* Enable the DCC stat gathering. */
1842 if (!tex
->dcc_gather_statistics
) {
1843 tex
->dcc_gather_statistics
= true;
1844 vi_separate_dcc_start_query(&rctx
->b
, tex
);
1847 if (!vi_should_enable_separate_dcc(tex
))
1848 return; /* stats show that DCC decompression is too expensive */
1850 assert(tex
->surface
.level
[0].dcc_enabled
);
1851 assert(!tex
->dcc_separate_buffer
);
1853 r600_texture_discard_cmask(rctx
->screen
, tex
);
1855 /* Get a DCC buffer. */
1856 if (tex
->last_dcc_separate_buffer
) {
1857 assert(tex
->dcc_gather_statistics
);
1858 assert(!tex
->dcc_separate_buffer
);
1859 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
1860 tex
->last_dcc_separate_buffer
= NULL
;
1862 tex
->dcc_separate_buffer
= (struct r600_resource
*)
1863 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
1865 tex
->surface
.dcc_size
,
1866 tex
->surface
.dcc_alignment
);
1867 if (!tex
->dcc_separate_buffer
)
1871 /* dcc_offset is the absolute GPUVM address. */
1872 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
1874 /* no need to flag anything since this is called by fast clear that
1875 * flags framebuffer state
1880 * Called by pipe_context::flush_resource, the place where DCC decompression
1883 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1884 struct r600_texture
*tex
)
1886 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1887 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1888 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
1889 bool disable
= false;
1891 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
1892 union pipe_query_result result
;
1894 /* Read the results. */
1895 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
1897 ctx
->destroy_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2]);
1898 rctx
->dcc_stats
[i
].ps_stats
[2] = NULL
;
1900 /* Compute the approximate number of fullscreen draws. */
1901 tex
->ps_draw_ratio
=
1902 result
.pipeline_statistics
.ps_invocations
/
1903 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
1904 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
1906 disable
= tex
->dcc_separate_buffer
&&
1907 !vi_should_enable_separate_dcc(tex
);
1910 tex
->num_slow_clears
= 0;
1912 /* stop the statistics query for ps_stats[0] */
1914 vi_separate_dcc_stop_query(ctx
, tex
);
1916 /* Move the queries in the queue by one. */
1917 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
1918 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
1919 rctx
->dcc_stats
[i
].ps_stats
[0] = NULL
;
1921 /* create and start a new query as ps_stats[0] */
1923 vi_separate_dcc_start_query(ctx
, tex
);
1926 assert(!tex
->last_dcc_separate_buffer
);
1927 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
1928 tex
->dcc_separate_buffer
= NULL
;
1929 tex
->dcc_offset
= 0;
1930 /* no need to flag anything since this is called after
1931 * decompression that re-sets framebuffer state
1936 /* FAST COLOR CLEAR */
1938 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
1939 enum pipe_format surface_format
,
1940 const union pipe_color_union
*color
)
1942 union util_color uc
;
1944 memset(&uc
, 0, sizeof(uc
));
1946 if (util_format_is_pure_uint(surface_format
)) {
1947 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
1948 } else if (util_format_is_pure_sint(surface_format
)) {
1949 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
1951 util_pack_color(color
->f
, surface_format
, &uc
);
1954 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
1957 static void vi_get_fast_clear_parameters(enum pipe_format surface_format
,
1958 const union pipe_color_union
*color
,
1959 uint32_t* reset_value
,
1960 bool* clear_words_needed
)
1962 bool values
[4] = {};
1964 bool main_value
= false;
1965 bool extra_value
= false;
1967 const struct util_format_description
*desc
= util_format_description(surface_format
);
1969 *clear_words_needed
= true;
1970 *reset_value
= 0x20202020U
;
1972 /* If we want to clear without needing a fast clear eliminate step, we
1973 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1974 * have two sets of flags, one for the last or first channel(extra) and
1975 * one for the other channels(main).
1978 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
1979 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
1980 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
1982 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
1983 if(r600_translate_colorswap(surface_format
, false) <= 1)
1984 extra_channel
= desc
->nr_channels
- 1;
1990 for (i
= 0; i
< 4; ++i
) {
1991 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
1993 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
1994 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
1997 if (util_format_is_pure_sint(surface_format
)) {
1998 values
[i
] = color
->i
[i
] != 0;
1999 if (color
->i
[i
] != 0 && color
->i
[i
] != INT32_MAX
)
2001 } else if (util_format_is_pure_uint(surface_format
)) {
2002 values
[i
] = color
->ui
[i
] != 0U;
2003 if (color
->ui
[i
] != 0U && color
->ui
[i
] != UINT32_MAX
)
2006 values
[i
] = color
->f
[i
] != 0.0F
;
2007 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2011 if (index
== extra_channel
)
2012 extra_value
= values
[i
];
2014 main_value
= values
[i
];
2017 for (int i
= 0; i
< 4; ++i
)
2018 if (values
[i
] != main_value
&&
2019 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2020 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2021 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2024 *clear_words_needed
= false;
2026 *reset_value
|= 0x80808080U
;
2029 *reset_value
|= 0x40404040U
;
2032 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2033 struct r600_texture
*rtex
,
2034 unsigned level
, unsigned clear_value
)
2036 struct pipe_resource
*dcc_buffer
;
2037 uint64_t dcc_offset
;
2039 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2041 if (rtex
->dcc_separate_buffer
) {
2042 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2045 dcc_buffer
= &rtex
->resource
.b
.b
;
2046 dcc_offset
= rtex
->dcc_offset
;
2049 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2051 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2052 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2053 clear_value
, R600_COHERENCY_CB_META
);
2056 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2057 * This allows hitting the MSAA resolve fast path, which requires that both
2058 * src and dst micro tile modes match.
2060 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2061 struct r600_texture
*rtex
)
2063 if (rtex
->resource
.is_shared
||
2064 rtex
->surface
.nsamples
<= 1 ||
2065 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2068 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2069 assert(rtex
->surface
.last_level
== 0);
2071 /* These magic numbers were copied from addrlib. It doesn't use any
2072 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2073 * different bpp and micro tile mode.
2075 if (rscreen
->chip_class
>= CIK
) {
2076 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2077 case 0: /* displayable */
2078 rtex
->surface
.tiling_index
[0] = 10;
2081 rtex
->surface
.tiling_index
[0] = 14;
2083 case 3: /* rotated */
2084 rtex
->surface
.tiling_index
[0] = 28;
2086 default: /* depth, thick */
2087 assert(!"unexpected micro mode");
2091 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2092 case 0: /* displayable */
2093 switch (rtex
->surface
.bpe
) {
2095 rtex
->surface
.tiling_index
[0] = 10;
2098 rtex
->surface
.tiling_index
[0] = 11;
2100 default: /* 32, 64 */
2101 rtex
->surface
.tiling_index
[0] = 12;
2106 switch (rtex
->surface
.bpe
) {
2108 rtex
->surface
.tiling_index
[0] = 14;
2111 rtex
->surface
.tiling_index
[0] = 15;
2114 rtex
->surface
.tiling_index
[0] = 16;
2116 default: /* 64, 128 */
2117 rtex
->surface
.tiling_index
[0] = 17;
2121 default: /* depth, thick */
2122 assert(!"unexpected micro mode");
2127 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2129 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2130 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2133 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2134 struct pipe_framebuffer_state
*fb
,
2135 struct r600_atom
*fb_state
,
2136 unsigned *buffers
, unsigned *dirty_cbufs
,
2137 const union pipe_color_union
*color
)
2141 /* This function is broken in BE, so just disable this path for now */
2142 #ifdef PIPE_ARCH_BIG_ENDIAN
2146 if (rctx
->render_cond
)
2149 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2150 struct r600_texture
*tex
;
2151 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2156 /* if this colorbuffer is not being cleared */
2157 if (!(*buffers
& clear_bit
))
2160 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2162 /* 128-bit formats are unusupported */
2163 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2167 /* the clear is allowed if all layers are bound */
2168 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2169 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2173 /* cannot clear mipmapped textures */
2174 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2178 /* only supported on tiled surfaces */
2179 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2183 /* shared textures can't use fast clear without an explicit flush,
2184 * because there is no way to communicate the clear color among
2187 if (tex
->resource
.is_shared
&&
2188 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2191 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2192 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2193 rctx
->chip_class
>= CIK
&&
2194 rctx
->screen
->info
.drm_major
== 2 &&
2195 rctx
->screen
->info
.drm_minor
< 38) {
2199 /* Fast clear is the most appropriate place to enable DCC for
2200 * displayable surfaces.
2202 if (rctx
->chip_class
>= VI
&&
2203 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2204 vi_separate_dcc_try_enable(rctx
, tex
);
2206 /* Stoney can't do a CMASK-based clear, so all clears are
2207 * considered to be hypothetically slow clears, which
2208 * is weighed when determining to enable separate DCC.
2210 if (tex
->dcc_gather_statistics
&&
2211 rctx
->family
== CHIP_STONEY
)
2212 tex
->num_slow_clears
++;
2215 /* Try to clear DCC first, otherwise try CMASK. */
2216 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2217 uint32_t reset_value
;
2218 bool clear_words_needed
;
2220 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2223 /* We can change the micro tile mode before a full clear. */
2224 if (rctx
->screen
->chip_class
>= SI
)
2225 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2227 vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
, color
, &reset_value
, &clear_words_needed
);
2228 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2230 if (clear_words_needed
)
2231 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2232 tex
->separate_dcc_dirty
= true;
2234 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2235 if (rctx
->family
== CHIP_STONEY
)
2238 /* ensure CMASK is enabled */
2239 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2240 if (tex
->cmask
.size
== 0) {
2244 /* We can change the micro tile mode before a full clear. */
2245 if (rctx
->screen
->chip_class
>= SI
)
2246 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2248 /* Do the fast clear. */
2249 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2250 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2251 R600_COHERENCY_CB_META
);
2253 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2256 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2259 *dirty_cbufs
|= 1 << i
;
2260 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2261 *buffers
&= ~clear_bit
;
2265 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2267 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2268 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2271 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2273 rctx
->b
.create_surface
= r600_create_surface
;
2274 rctx
->b
.surface_destroy
= r600_surface_destroy
;