2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
37 struct pipe_resource
*dst
,
39 unsigned dstx
, unsigned dsty
, unsigned dstz
,
40 struct pipe_resource
*src
,
42 const struct pipe_box
*src_box
)
44 struct pipe_blit_info blit
;
46 memset(&blit
, 0, sizeof(blit
));
47 blit
.src
.resource
= src
;
48 blit
.src
.format
= src
->format
;
49 blit
.src
.level
= src_level
;
50 blit
.src
.box
= *src_box
;
51 blit
.dst
.resource
= dst
;
52 blit
.dst
.format
= dst
->format
;
53 blit
.dst
.level
= dst_level
;
54 blit
.dst
.box
.x
= dstx
;
55 blit
.dst
.box
.y
= dsty
;
56 blit
.dst
.box
.z
= dstz
;
57 blit
.dst
.box
.width
= src_box
->width
;
58 blit
.dst
.box
.height
= src_box
->height
;
59 blit
.dst
.box
.depth
= src_box
->depth
;
60 blit
.mask
= util_format_get_mask(src
->format
) &
61 util_format_get_mask(dst
->format
);
62 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
65 pipe
->blit(pipe
, &blit
);
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
72 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
73 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
74 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
75 struct pipe_resource
*src
= transfer
->resource
;
77 if (src
->nr_samples
> 1) {
78 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
79 src
, transfer
->level
, &transfer
->box
);
83 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
90 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
91 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
92 struct pipe_resource
*dst
= transfer
->resource
;
93 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
96 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
98 if (dst
->nr_samples
> 1) {
99 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
100 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
105 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
106 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
110 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
111 const struct pipe_box
*box
)
113 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
115 return rtex
->surface
.level
[level
].offset
+
116 box
->z
* rtex
->surface
.level
[level
].slice_size
+
117 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
118 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
121 static int r600_init_surface(struct r600_common_screen
*rscreen
,
122 struct radeon_surf
*surface
,
123 const struct pipe_resource
*ptex
,
125 bool is_flushed_depth
)
127 const struct util_format_description
*desc
=
128 util_format_description(ptex
->format
);
129 bool is_depth
, is_stencil
;
131 is_depth
= util_format_has_depth(desc
);
132 is_stencil
= util_format_has_stencil(desc
);
134 surface
->npix_x
= ptex
->width0
;
135 surface
->npix_y
= ptex
->height0
;
136 surface
->npix_z
= ptex
->depth0
;
137 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
138 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
140 surface
->array_size
= 1;
141 surface
->last_level
= ptex
->last_level
;
143 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
144 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
145 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
147 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
148 /* align byte per element on dword */
149 if (surface
->bpe
== 3) {
154 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
155 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
157 switch (ptex
->target
) {
158 case PIPE_TEXTURE_1D
:
159 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
161 case PIPE_TEXTURE_RECT
:
162 case PIPE_TEXTURE_2D
:
163 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
165 case PIPE_TEXTURE_3D
:
166 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
168 case PIPE_TEXTURE_1D_ARRAY
:
169 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
170 surface
->array_size
= ptex
->array_size
;
172 case PIPE_TEXTURE_2D_ARRAY
:
173 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
174 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
175 surface
->array_size
= ptex
->array_size
;
177 case PIPE_TEXTURE_CUBE
:
178 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
184 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
185 surface
->flags
|= RADEON_SURF_SCANOUT
;
188 if (!is_flushed_depth
&& is_depth
) {
189 surface
->flags
|= RADEON_SURF_ZBUFFER
;
192 surface
->flags
|= RADEON_SURF_SBUFFER
|
193 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
196 if (rscreen
->chip_class
>= SI
) {
197 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
202 static int r600_setup_surface(struct pipe_screen
*screen
,
203 struct r600_texture
*rtex
,
204 unsigned pitch_in_bytes_override
)
206 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
209 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
214 rtex
->size
= rtex
->surface
.bo_size
;
216 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
220 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
221 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
222 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
223 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
224 rtex
->surface
.stencil_offset
=
225 rtex
->surface
.stencil_level
[0].offset
= rtex
->surface
.level
[0].slice_size
;
231 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
232 struct pipe_resource
*ptex
,
233 struct winsys_handle
*whandle
)
235 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
236 struct r600_resource
*resource
= &rtex
->resource
;
237 struct radeon_surf
*surface
= &rtex
->surface
;
238 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
240 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
242 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
243 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
244 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
245 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
246 surface
->pipe_config
,
247 surface
->bankw
, surface
->bankh
,
249 surface
->stencil_tile_split
,
250 surface
->mtilea
, surface
->num_banks
,
251 surface
->level
[0].pitch_bytes
,
252 (surface
->flags
& RADEON_SURF_SCANOUT
) != 0);
254 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
255 surface
->level
[0].pitch_bytes
, whandle
);
258 static void r600_texture_destroy(struct pipe_screen
*screen
,
259 struct pipe_resource
*ptex
)
261 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
262 struct r600_resource
*resource
= &rtex
->resource
;
264 if (rtex
->flushed_depth_texture
)
265 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
267 pipe_resource_reference((struct pipe_resource
**)&rtex
->htile_buffer
, NULL
);
268 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
269 pipe_resource_reference((struct pipe_resource
**)&rtex
->cmask_buffer
, NULL
);
271 pipe_resource_reference((struct pipe_resource
**)&rtex
->dcc_buffer
, NULL
);
272 pb_reference(&resource
->buf
, NULL
);
276 static const struct u_resource_vtbl r600_texture_vtbl
;
278 /* The number of samples can be specified independently of the texture. */
279 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
280 struct r600_texture
*rtex
,
282 struct r600_fmask_info
*out
)
284 /* FMASK is allocated like an ordinary texture. */
285 struct radeon_surf fmask
= rtex
->surface
;
287 memset(out
, 0, sizeof(*out
));
289 fmask
.bo_alignment
= 0;
292 fmask
.flags
|= RADEON_SURF_FMASK
;
294 /* Force 2D tiling if it wasn't set. This may occur when creating
295 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
296 * destination buffer must have an FMASK too. */
297 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
298 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
300 if (rscreen
->chip_class
>= SI
) {
301 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
304 switch (nr_samples
) {
308 if (rscreen
->chip_class
<= CAYMAN
) {
316 R600_ERR("Invalid sample count for FMASK allocation.\n");
320 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
321 * This can be fixed by writing a separate FMASK allocator specifically
322 * for R600-R700 asics. */
323 if (rscreen
->chip_class
<= R700
) {
327 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
328 R600_ERR("Got error in surface_init while allocating FMASK.\n");
332 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
334 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
335 if (out
->slice_tile_max
)
336 out
->slice_tile_max
-= 1;
338 out
->tile_mode_index
= fmask
.tiling_index
[0];
339 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
340 out
->bank_height
= fmask
.bankh
;
341 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
342 out
->size
= fmask
.bo_size
;
345 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
346 struct r600_texture
*rtex
)
348 r600_texture_get_fmask_info(rscreen
, rtex
,
349 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
351 rtex
->fmask
.offset
= align(rtex
->size
, rtex
->fmask
.alignment
);
352 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
355 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
356 struct r600_texture
*rtex
,
357 struct r600_cmask_info
*out
)
359 unsigned cmask_tile_width
= 8;
360 unsigned cmask_tile_height
= 8;
361 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
362 unsigned element_bits
= 4;
363 unsigned cmask_cache_bits
= 1024;
364 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
365 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
367 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
368 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
369 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
370 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
371 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
373 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
374 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
376 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
377 unsigned slice_bytes
=
378 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
380 assert(macro_tile_width
% 128 == 0);
381 assert(macro_tile_height
% 128 == 0);
383 out
->pitch
= pitch_elements
;
384 out
->height
= height
;
385 out
->xalign
= macro_tile_width
;
386 out
->yalign
= macro_tile_height
;
387 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
388 out
->alignment
= MAX2(256, base_align
);
389 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
390 align(slice_bytes
, base_align
);
393 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
394 struct r600_texture
*rtex
,
395 struct r600_cmask_info
*out
)
397 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
398 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
399 unsigned cl_width
, cl_height
;
414 case 16: /* Hawaii */
423 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
425 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
426 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
427 unsigned slice_elements
= (width
* height
) / (8*8);
429 /* Each element of CMASK is a nibble. */
430 unsigned slice_bytes
= slice_elements
/ 2;
433 out
->height
= height
;
434 out
->xalign
= cl_width
* 8;
435 out
->yalign
= cl_height
* 8;
436 out
->slice_tile_max
= (width
* height
) / (128*128);
437 if (out
->slice_tile_max
)
438 out
->slice_tile_max
-= 1;
440 out
->alignment
= MAX2(256, base_align
);
441 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
442 align(slice_bytes
, base_align
);
445 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
446 struct r600_texture
*rtex
)
448 if (rscreen
->chip_class
>= SI
) {
449 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
451 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
454 rtex
->cmask
.offset
= align(rtex
->size
, rtex
->cmask
.alignment
);
455 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
457 if (rscreen
->chip_class
>= SI
)
458 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
460 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
463 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
464 struct r600_texture
*rtex
)
466 if (rtex
->cmask_buffer
)
469 assert(rtex
->cmask
.size
== 0);
471 if (rscreen
->chip_class
>= SI
) {
472 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
474 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
477 rtex
->cmask_buffer
= (struct r600_resource
*)
478 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
479 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
480 if (rtex
->cmask_buffer
== NULL
) {
481 rtex
->cmask
.size
= 0;
485 /* update colorbuffer state bits */
486 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
488 if (rscreen
->chip_class
>= SI
)
489 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
491 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
494 static void vi_texture_alloc_dcc_separate(struct r600_common_screen
*rscreen
,
495 struct r600_texture
*rtex
)
497 if (rscreen
->debug_flags
& DBG_NO_DCC
)
500 rtex
->dcc_buffer
= (struct r600_resource
*)
501 r600_aligned_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
502 PIPE_USAGE_DEFAULT
, rtex
->surface
.dcc_size
, rtex
->surface
.dcc_alignment
);
503 if (rtex
->dcc_buffer
== NULL
) {
507 r600_screen_clear_buffer(rscreen
, &rtex
->dcc_buffer
->b
.b
, 0, rtex
->surface
.dcc_size
,
510 rtex
->cb_color_info
|= VI_S_028C70_DCC_ENABLE(1);
513 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
514 struct r600_texture
*rtex
)
516 unsigned cl_width
, cl_height
, width
, height
;
517 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
518 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
520 if (rscreen
->chip_class
<= EVERGREEN
&&
521 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
524 /* HW bug on R6xx. */
525 if (rscreen
->chip_class
== R600
&&
526 (rtex
->surface
.level
[0].npix_x
> 7680 ||
527 rtex
->surface
.level
[0].npix_y
> 7680))
530 /* HTILE is broken with 1D tiling on old kernels and CIK. */
531 if (rscreen
->chip_class
>= CIK
&&
532 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
533 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
562 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
563 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
565 slice_elements
= (width
* height
) / (8 * 8);
566 slice_bytes
= slice_elements
* 4;
568 pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
569 base_align
= num_pipes
* pipe_interleave_bytes
;
571 rtex
->htile
.pitch
= width
;
572 rtex
->htile
.height
= height
;
573 rtex
->htile
.xalign
= cl_width
* 8;
574 rtex
->htile
.yalign
= cl_height
* 8;
576 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
577 align(slice_bytes
, base_align
);
580 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
581 struct r600_texture
*rtex
)
583 unsigned htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
588 rtex
->htile_buffer
= (struct r600_resource
*)
589 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
590 PIPE_USAGE_DEFAULT
, htile_size
);
591 if (rtex
->htile_buffer
== NULL
) {
592 /* this is not a fatal error as we can still keep rendering
593 * without htile buffer */
594 R600_ERR("Failed to create buffer object for htile buffer.\n");
596 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0,
597 htile_size
, 0, true);
602 r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
606 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
607 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
608 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
609 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
610 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
611 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
612 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
613 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
614 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
616 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
617 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
618 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
619 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
620 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
621 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
623 if (rtex
->fmask
.size
)
624 fprintf(f
, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
625 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
626 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
627 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
628 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
630 if (rtex
->cmask
.size
)
631 fprintf(f
, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
632 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
633 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
634 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
635 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
637 if (rtex
->htile_buffer
)
638 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
639 "xalign=%u, yalign=%u\n",
640 rtex
->htile_buffer
->b
.b
.width0
,
641 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
642 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
);
644 if (rtex
->dcc_buffer
) {
645 fprintf(f
, " DCC: size=%u, alignment=%u\n",
646 rtex
->dcc_buffer
->b
.b
.width0
,
647 rtex
->dcc_buffer
->buf
->alignment
);
648 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
649 fprintf(f
, " DCCLevel[%i]: offset=%"PRIu64
"\n",
650 i
, rtex
->surface
.level
[i
].dcc_offset
);
653 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
654 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
655 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
656 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
657 i
, rtex
->surface
.level
[i
].offset
,
658 rtex
->surface
.level
[i
].slice_size
,
659 u_minify(rtex
->resource
.b
.b
.width0
, i
),
660 u_minify(rtex
->resource
.b
.b
.height0
, i
),
661 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
662 rtex
->surface
.level
[i
].nblk_x
,
663 rtex
->surface
.level
[i
].nblk_y
,
664 rtex
->surface
.level
[i
].nblk_z
,
665 rtex
->surface
.level
[i
].pitch_bytes
,
666 rtex
->surface
.level
[i
].mode
);
668 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
669 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
670 fprintf(f
, " StencilLayout: tilesplit=%u\n",
671 rtex
->surface
.stencil_tile_split
);
672 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
673 "slice_size=%"PRIu64
", npix_x=%u, "
674 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
675 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
676 i
, rtex
->surface
.stencil_level
[i
].offset
,
677 rtex
->surface
.stencil_level
[i
].slice_size
,
678 u_minify(rtex
->resource
.b
.b
.width0
, i
),
679 u_minify(rtex
->resource
.b
.b
.height0
, i
),
680 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
681 rtex
->surface
.stencil_level
[i
].nblk_x
,
682 rtex
->surface
.stencil_level
[i
].nblk_y
,
683 rtex
->surface
.stencil_level
[i
].nblk_z
,
684 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
685 rtex
->surface
.stencil_level
[i
].mode
);
690 /* Common processing for r600_texture_create and r600_texture_from_handle */
691 static struct r600_texture
*
692 r600_texture_create_object(struct pipe_screen
*screen
,
693 const struct pipe_resource
*base
,
694 unsigned pitch_in_bytes_override
,
695 struct pb_buffer
*buf
,
696 struct radeon_surf
*surface
)
698 struct r600_texture
*rtex
;
699 struct r600_resource
*resource
;
700 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
702 rtex
= CALLOC_STRUCT(r600_texture
);
706 resource
= &rtex
->resource
;
707 resource
->b
.b
= *base
;
708 resource
->b
.vtbl
= &r600_texture_vtbl
;
709 pipe_reference_init(&resource
->b
.b
.reference
, 1);
710 resource
->b
.b
.screen
= screen
;
712 /* don't include stencil-only formats which we don't support for rendering */
713 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
715 rtex
->surface
= *surface
;
716 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
)) {
721 /* Tiled depth textures utilize the non-displayable tile order.
722 * This must be done after r600_setup_surface.
723 * Applies to R600-Cayman. */
724 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
726 if (rtex
->is_depth
) {
727 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
728 R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
729 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
)) {
731 r600_texture_allocate_htile(rscreen
, rtex
);
734 if (base
->nr_samples
> 1) {
736 r600_texture_allocate_fmask(rscreen
, rtex
);
737 r600_texture_allocate_cmask(rscreen
, rtex
);
738 rtex
->cmask_buffer
= &rtex
->resource
;
740 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
745 if (rtex
->surface
.dcc_size
)
746 vi_texture_alloc_dcc_separate(rscreen
, rtex
);
749 /* Now create the backing buffer. */
751 if (!r600_init_resource(rscreen
, resource
, rtex
->size
,
752 rtex
->surface
.bo_alignment
, TRUE
)) {
758 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
759 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->cs_buf
);
760 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->cs_buf
);
763 if (rtex
->cmask
.size
) {
764 /* Initialize the cmask to 0xCC (= compressed state). */
765 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
766 rtex
->cmask
.offset
, rtex
->cmask
.size
,
770 /* Initialize the CMASK base register value. */
771 rtex
->cmask
.base_address_reg
=
772 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
774 if (rscreen
->debug_flags
& DBG_VM
) {
775 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
776 rtex
->resource
.gpu_address
,
777 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
778 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
779 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
782 if (rscreen
->debug_flags
& DBG_TEX
) {
784 r600_print_texture_info(rtex
, stdout
);
790 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
791 const struct pipe_resource
*templ
)
793 const struct util_format_description
*desc
= util_format_description(templ
->format
);
794 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
796 /* MSAA resources must be 2D tiled. */
797 if (templ
->nr_samples
> 1)
798 return RADEON_SURF_MODE_2D
;
800 /* Transfer resources should be linear. */
801 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
802 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
804 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
805 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
806 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
807 (templ
->target
== PIPE_TEXTURE_2D
||
808 templ
->target
== PIPE_TEXTURE_3D
))
811 /* Handle common candidates for the linear mode.
812 * Compressed textures must always be tiled. */
813 if (!force_tiling
&& !util_format_is_compressed(templ
->format
)) {
814 /* Not everything can be linear, so we cannot enforce it
815 * for all textures. */
816 if ((rscreen
->debug_flags
& DBG_NO_TILING
) &&
817 (!util_format_is_depth_or_stencil(templ
->format
) ||
818 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)))
819 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
821 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
822 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
823 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
825 /* Cursors are linear on SI.
826 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
827 if (rscreen
->chip_class
>= SI
&&
828 (templ
->bind
& PIPE_BIND_CURSOR
))
829 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
831 if (templ
->bind
& PIPE_BIND_LINEAR
)
832 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
834 /* Textures with a very small height are recommended to be linear. */
835 if (templ
->target
== PIPE_TEXTURE_1D
||
836 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
838 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
840 /* Textures likely to be mapped often. */
841 if (templ
->usage
== PIPE_USAGE_STAGING
||
842 templ
->usage
== PIPE_USAGE_STREAM
)
843 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
846 /* Make small textures 1D tiled. */
847 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
848 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
849 return RADEON_SURF_MODE_1D
;
851 /* The allocator will switch to 1D if needed. */
852 return RADEON_SURF_MODE_2D
;
855 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
856 const struct pipe_resource
*templ
)
858 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
859 struct radeon_surf surface
= {0};
862 r
= r600_init_surface(rscreen
, &surface
, templ
,
863 r600_choose_tiling(rscreen
, templ
),
864 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
868 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
872 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
876 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
877 const struct pipe_resource
*templ
,
878 struct winsys_handle
*whandle
)
880 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
881 struct pb_buffer
*buf
= NULL
;
884 enum radeon_bo_layout micro
, macro
;
885 struct radeon_surf surface
;
889 /* Support only 2D textures without mipmaps */
890 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
891 templ
->depth0
!= 1 || templ
->last_level
!= 0)
894 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
898 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
899 &surface
.bankw
, &surface
.bankh
,
901 &surface
.stencil_tile_split
,
902 &surface
.mtilea
, &scanout
);
904 if (macro
== RADEON_LAYOUT_TILED
)
905 array_mode
= RADEON_SURF_MODE_2D
;
906 else if (micro
== RADEON_LAYOUT_TILED
)
907 array_mode
= RADEON_SURF_MODE_1D
;
909 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
911 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
917 surface
.flags
|= RADEON_SURF_SCANOUT
;
919 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
920 stride
, buf
, &surface
);
923 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
924 struct pipe_resource
*texture
,
925 struct r600_texture
**staging
)
927 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
928 struct pipe_resource resource
;
929 struct r600_texture
**flushed_depth_texture
= staging
?
930 staging
: &rtex
->flushed_depth_texture
;
932 if (!staging
&& rtex
->flushed_depth_texture
)
933 return true; /* it's ready */
935 resource
.target
= texture
->target
;
936 resource
.format
= texture
->format
;
937 resource
.width0
= texture
->width0
;
938 resource
.height0
= texture
->height0
;
939 resource
.depth0
= texture
->depth0
;
940 resource
.array_size
= texture
->array_size
;
941 resource
.last_level
= texture
->last_level
;
942 resource
.nr_samples
= texture
->nr_samples
;
943 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
944 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
945 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
948 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
950 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
951 if (*flushed_depth_texture
== NULL
) {
952 R600_ERR("failed to create temporary texture to hold flushed depth\n");
956 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
957 (*flushed_depth_texture
)->non_disp_tiling
= false;
962 * Initialize the pipe_resource descriptor to be of the same size as the box,
963 * which is supposed to hold a subregion of the texture "orig" at the given
966 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
967 struct pipe_resource
*orig
,
968 const struct pipe_box
*box
,
969 unsigned level
, unsigned flags
)
971 memset(res
, 0, sizeof(*res
));
972 res
->format
= orig
->format
;
973 res
->width0
= box
->width
;
974 res
->height0
= box
->height
;
977 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
980 /* We must set the correct texture target and dimensions for a 3D box. */
981 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0)
982 res
->target
= orig
->target
;
984 res
->target
= PIPE_TEXTURE_2D
;
986 switch (res
->target
) {
987 case PIPE_TEXTURE_1D_ARRAY
:
988 case PIPE_TEXTURE_2D_ARRAY
:
989 case PIPE_TEXTURE_CUBE_ARRAY
:
990 res
->array_size
= box
->depth
;
992 case PIPE_TEXTURE_3D
:
993 res
->depth0
= box
->depth
;
999 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1000 struct pipe_resource
*texture
,
1003 const struct pipe_box
*box
,
1004 struct pipe_transfer
**ptransfer
)
1006 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1007 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1008 struct r600_transfer
*trans
;
1009 boolean use_staging_texture
= FALSE
;
1010 struct r600_resource
*buf
;
1011 unsigned offset
= 0;
1014 /* We cannot map a tiled texture directly because the data is
1015 * in a different order, therefore we do detiling using a blit.
1017 * Also, use a temporary in GTT memory for read transfers, as
1018 * the CPU is much happier reading out of cached system memory
1019 * than uncached VRAM.
1021 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
) {
1022 use_staging_texture
= TRUE
;
1023 } else if ((usage
& PIPE_TRANSFER_READ
) && !(usage
& PIPE_TRANSFER_MAP_DIRECTLY
) &&
1024 (rtex
->resource
.domains
== RADEON_DOMAIN_VRAM
)) {
1025 /* Untiled buffers in VRAM, which is slow for CPU reads */
1026 use_staging_texture
= TRUE
;
1027 } else if (!(usage
& PIPE_TRANSFER_READ
) &&
1028 (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
1029 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0, RADEON_USAGE_READWRITE
))) {
1030 /* Use a staging texture for uploads if the underlying BO is busy. */
1031 use_staging_texture
= TRUE
;
1034 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
1035 use_staging_texture
= FALSE
;
1038 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
1042 trans
= CALLOC_STRUCT(r600_transfer
);
1045 trans
->transfer
.resource
= texture
;
1046 trans
->transfer
.level
= level
;
1047 trans
->transfer
.usage
= usage
;
1048 trans
->transfer
.box
= *box
;
1050 if (rtex
->is_depth
) {
1051 struct r600_texture
*staging_depth
;
1053 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1054 /* MSAA depth buffers need to be converted to single sample buffers.
1056 * Mapping MSAA depth buffers can occur if ReadPixels is called
1057 * with a multisample GLX visual.
1059 * First downsample the depth buffer to a temporary texture,
1060 * then decompress the temporary one to staging.
1062 * Only the region being mapped is transfered.
1064 struct pipe_resource resource
;
1066 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1068 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1069 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1074 if (usage
& PIPE_TRANSFER_READ
) {
1075 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1077 R600_ERR("failed to create a temporary depth texture\n");
1082 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1083 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1084 0, 0, 0, box
->depth
, 0, 0);
1085 pipe_resource_reference((struct pipe_resource
**)&temp
, NULL
);
1089 /* XXX: only readback the rectangle which is being mapped? */
1090 /* XXX: when discard is true, no need to read back from depth texture */
1091 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1092 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1097 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1099 box
->z
, box
->z
+ box
->depth
- 1,
1102 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1105 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1106 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1107 trans
->staging
= (struct r600_resource
*)staging_depth
;
1108 } else if (use_staging_texture
) {
1109 struct pipe_resource resource
;
1110 struct r600_texture
*staging
;
1112 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1113 R600_RESOURCE_FLAG_TRANSFER
);
1114 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1115 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1117 /* Create the temporary texture. */
1118 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1119 if (staging
== NULL
) {
1120 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1124 trans
->staging
= &staging
->resource
;
1125 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1126 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1127 if (usage
& PIPE_TRANSFER_READ
) {
1128 r600_copy_to_staging_texture(ctx
, trans
);
1131 /* the resource is mapped directly */
1132 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1133 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1134 offset
= r600_texture_get_offset(rtex
, level
, box
);
1137 if (trans
->staging
) {
1138 buf
= trans
->staging
;
1139 if (!rtex
->is_depth
&& !(usage
& PIPE_TRANSFER_READ
))
1140 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1142 buf
= &rtex
->resource
;
1145 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1146 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
1151 *ptransfer
= &trans
->transfer
;
1152 return map
+ offset
;
1155 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1156 struct pipe_transfer
* transfer
)
1158 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1159 struct pipe_resource
*texture
= transfer
->resource
;
1160 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1162 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1163 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1164 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1165 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1166 &rtransfer
->staging
->b
.b
, transfer
->level
,
1169 r600_copy_from_staging_texture(ctx
, rtransfer
);
1173 if (rtransfer
->staging
)
1174 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
1179 static const struct u_resource_vtbl r600_texture_vtbl
=
1181 NULL
, /* get_handle */
1182 r600_texture_destroy
, /* resource_destroy */
1183 r600_texture_transfer_map
, /* transfer_map */
1184 u_default_transfer_flush_region
, /* transfer_flush_region */
1185 r600_texture_transfer_unmap
, /* transfer_unmap */
1186 NULL
/* transfer_inline_write */
1189 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1190 struct pipe_resource
*texture
,
1191 const struct pipe_surface
*templ
,
1192 unsigned width
, unsigned height
)
1194 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1196 if (surface
== NULL
)
1199 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1200 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1202 pipe_reference_init(&surface
->base
.reference
, 1);
1203 pipe_resource_reference(&surface
->base
.texture
, texture
);
1204 surface
->base
.context
= pipe
;
1205 surface
->base
.format
= templ
->format
;
1206 surface
->base
.width
= width
;
1207 surface
->base
.height
= height
;
1208 surface
->base
.u
= templ
->u
;
1209 return &surface
->base
;
1212 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1213 struct pipe_resource
*tex
,
1214 const struct pipe_surface
*templ
)
1216 unsigned level
= templ
->u
.tex
.level
;
1218 return r600_create_surface_custom(pipe
, tex
, templ
,
1219 u_minify(tex
->width0
, level
),
1220 u_minify(tex
->height0
, level
));
1223 static void r600_surface_destroy(struct pipe_context
*pipe
,
1224 struct pipe_surface
*surface
)
1226 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1227 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
1228 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
1229 pipe_resource_reference(&surface
->texture
, NULL
);
1233 unsigned r600_translate_colorswap(enum pipe_format format
)
1235 const struct util_format_description
*desc
= util_format_description(format
);
1237 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1239 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1240 return V_0280A0_SWAP_STD
;
1242 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1245 switch (desc
->nr_channels
) {
1247 if (HAS_SWIZZLE(0,X
))
1248 return V_0280A0_SWAP_STD
; /* X___ */
1249 else if (HAS_SWIZZLE(3,X
))
1250 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1253 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1254 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1255 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1256 return V_0280A0_SWAP_STD
; /* XY__ */
1257 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1258 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1259 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1260 return V_0280A0_SWAP_STD_REV
; /* YX__ */
1261 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1262 return V_0280A0_SWAP_ALT
; /* X__Y */
1263 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1264 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1267 if (HAS_SWIZZLE(0,X
))
1268 return V_0280A0_SWAP_STD
; /* XYZ */
1269 else if (HAS_SWIZZLE(0,Z
))
1270 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1273 /* check the middle channels, the 1st and 4th channel can be NONE */
1274 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
))
1275 return V_0280A0_SWAP_STD
; /* XYZW */
1276 else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
))
1277 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1278 else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
))
1279 return V_0280A0_SWAP_ALT
; /* ZYXW */
1280 else if (HAS_SWIZZLE(1,X
) && HAS_SWIZZLE(2,Y
))
1281 return V_0280A0_SWAP_ALT_REV
; /* WXYZ */
1287 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
1288 enum pipe_format surface_format
,
1289 const union pipe_color_union
*color
)
1291 union util_color uc
;
1293 memset(&uc
, 0, sizeof(uc
));
1295 if (util_format_is_pure_uint(surface_format
)) {
1296 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
1297 } else if (util_format_is_pure_sint(surface_format
)) {
1298 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
1300 util_pack_color(color
->f
, surface_format
, &uc
);
1303 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
1306 static void vi_get_fast_clear_parameters(enum pipe_format surface_format
,
1307 const union pipe_color_union
*color
,
1308 uint32_t* reset_value
,
1309 bool* clear_words_needed
)
1311 bool values
[4] = {};
1313 bool main_value
= false;
1314 bool extra_value
= false;
1316 const struct util_format_description
*desc
= util_format_description(surface_format
);
1318 *clear_words_needed
= true;
1319 *reset_value
= 0x20202020U
;
1321 /* If we want to clear without needing a fast clear eliminate step, we
1322 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1323 * have two sets of flags, one for the last or first channel(extra) and
1324 * one for the other channels(main).
1327 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
1328 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
1329 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
1331 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
1332 if(r600_translate_colorswap(surface_format
) <= 1)
1333 extra_channel
= desc
->nr_channels
- 1;
1339 for (i
= 0; i
< 4; ++i
) {
1340 int index
= desc
->swizzle
[i
] - UTIL_FORMAT_SWIZZLE_X
;
1342 if (desc
->swizzle
[i
] < UTIL_FORMAT_SWIZZLE_X
||
1343 desc
->swizzle
[i
] > UTIL_FORMAT_SWIZZLE_W
)
1346 if (util_format_is_pure_sint(surface_format
)) {
1347 values
[i
] = color
->i
[i
] != 0;
1348 if (color
->i
[i
] != 0 && color
->i
[i
] != INT32_MAX
)
1350 } else if (util_format_is_pure_uint(surface_format
)) {
1351 values
[i
] = color
->ui
[i
] != 0U;
1352 if (color
->ui
[i
] != 0U && color
->ui
[i
] != UINT32_MAX
)
1355 values
[i
] = color
->f
[i
] != 0.0F
;
1356 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
1360 if (index
== extra_channel
)
1361 extra_value
= values
[i
];
1363 main_value
= values
[i
];
1366 for (int i
= 0; i
< 4; ++i
)
1367 if (values
[i
] != main_value
&&
1368 desc
->swizzle
[i
] - UTIL_FORMAT_SWIZZLE_X
!= extra_channel
&&
1369 desc
->swizzle
[i
] >= UTIL_FORMAT_SWIZZLE_X
&&
1370 desc
->swizzle
[i
] <= UTIL_FORMAT_SWIZZLE_W
)
1373 *clear_words_needed
= false;
1375 *reset_value
|= 0x80808080U
;
1378 *reset_value
|= 0x40404040U
;
1381 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
1382 struct pipe_framebuffer_state
*fb
,
1383 struct r600_atom
*fb_state
,
1384 unsigned *buffers
, unsigned *dirty_cbufs
,
1385 const union pipe_color_union
*color
)
1389 if (rctx
->render_cond
)
1392 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1393 struct r600_texture
*tex
;
1394 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
1399 /* if this colorbuffer is not being cleared */
1400 if (!(*buffers
& clear_bit
))
1403 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
1405 /* 128-bit formats are unusupported */
1406 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
1410 /* the clear is allowed if all layers are bound */
1411 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
1412 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
1416 /* cannot clear mipmapped textures */
1417 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
1421 /* only supported on tiled surfaces */
1422 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
1426 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1427 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
1428 rctx
->chip_class
>= CIK
&&
1429 rctx
->screen
->info
.drm_major
== 2 &&
1430 rctx
->screen
->info
.drm_minor
< 38) {
1434 if (tex
->dcc_buffer
) {
1435 uint32_t reset_value
;
1436 bool clear_words_needed
;
1438 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
1441 vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
, color
, &reset_value
, &clear_words_needed
);
1443 rctx
->clear_buffer(&rctx
->b
, &tex
->dcc_buffer
->b
.b
,
1444 0, tex
->surface
.dcc_size
, reset_value
, true);
1446 if (clear_words_needed
)
1447 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
1449 /* ensure CMASK is enabled */
1450 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
1451 if (tex
->cmask
.size
== 0) {
1455 /* Do the fast clear. */
1456 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
1457 tex
->cmask
.offset
, tex
->cmask
.size
, 0, true);
1459 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
1462 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
1465 *dirty_cbufs
|= 1 << i
;
1466 rctx
->set_atom_dirty(rctx
, fb_state
, true);
1467 *buffers
&= ~clear_bit
;
1471 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
1473 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
1474 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
1477 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
1479 rctx
->b
.create_surface
= r600_create_surface
;
1480 rctx
->b
.surface_destroy
= r600_surface_destroy
;