2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
34 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
35 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
36 struct pipe_resource
*dst
,
38 unsigned dstx
, unsigned dsty
, unsigned dstz
,
39 struct pipe_resource
*src
,
41 const struct pipe_box
*src_box
)
43 struct pipe_blit_info blit
;
45 memset(&blit
, 0, sizeof(blit
));
46 blit
.src
.resource
= src
;
47 blit
.src
.format
= src
->format
;
48 blit
.src
.level
= src_level
;
49 blit
.src
.box
= *src_box
;
50 blit
.dst
.resource
= dst
;
51 blit
.dst
.format
= dst
->format
;
52 blit
.dst
.level
= dst_level
;
53 blit
.dst
.box
.x
= dstx
;
54 blit
.dst
.box
.y
= dsty
;
55 blit
.dst
.box
.z
= dstz
;
56 blit
.dst
.box
.width
= src_box
->width
;
57 blit
.dst
.box
.height
= src_box
->height
;
58 blit
.dst
.box
.depth
= src_box
->depth
;
59 blit
.mask
= util_format_get_mask(src
->format
) &
60 util_format_get_mask(dst
->format
);
61 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
64 pipe
->blit(pipe
, &blit
);
68 /* Copy from a full GPU texture to a transfer's staging one. */
69 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
71 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
72 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
73 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
74 struct pipe_resource
*src
= transfer
->resource
;
76 if (src
->nr_samples
> 1) {
77 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
78 src
, transfer
->level
, &transfer
->box
);
82 if (!rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0,
85 ctx
->resource_copy_region(ctx
, dst
, 0, 0, 0, 0,
86 src
, transfer
->level
, &transfer
->box
);
90 /* Copy from a transfer's staging texture to a full GPU one. */
91 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
93 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
94 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
95 struct pipe_resource
*dst
= transfer
->resource
;
96 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
99 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
101 if (dst
->nr_samples
> 1) {
102 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
103 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
108 if (!rctx
->dma_copy(ctx
, dst
, transfer
->level
,
109 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
111 ctx
->resource_copy_region(ctx
, dst
, transfer
->level
,
112 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
117 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
118 const struct pipe_box
*box
)
120 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
122 return rtex
->surface
.level
[level
].offset
+
123 box
->z
* rtex
->surface
.level
[level
].slice_size
+
124 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
125 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
128 static int r600_init_surface(struct r600_common_screen
*rscreen
,
129 struct radeon_surface
*surface
,
130 const struct pipe_resource
*ptex
,
132 bool is_flushed_depth
)
134 const struct util_format_description
*desc
=
135 util_format_description(ptex
->format
);
136 bool is_depth
, is_stencil
;
138 is_depth
= util_format_has_depth(desc
);
139 is_stencil
= util_format_has_stencil(desc
);
141 surface
->npix_x
= ptex
->width0
;
142 surface
->npix_y
= ptex
->height0
;
143 surface
->npix_z
= ptex
->depth0
;
144 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
145 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
147 surface
->array_size
= 1;
148 surface
->last_level
= ptex
->last_level
;
150 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
151 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
152 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
154 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
155 /* align byte per element on dword */
156 if (surface
->bpe
== 3) {
161 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
162 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
164 switch (ptex
->target
) {
165 case PIPE_TEXTURE_1D
:
166 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
168 case PIPE_TEXTURE_RECT
:
169 case PIPE_TEXTURE_2D
:
170 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
172 case PIPE_TEXTURE_3D
:
173 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
175 case PIPE_TEXTURE_1D_ARRAY
:
176 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
177 surface
->array_size
= ptex
->array_size
;
179 case PIPE_TEXTURE_2D_ARRAY
:
180 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
181 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
182 surface
->array_size
= ptex
->array_size
;
184 case PIPE_TEXTURE_CUBE
:
185 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
191 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
192 surface
->flags
|= RADEON_SURF_SCANOUT
;
195 if (!is_flushed_depth
&& is_depth
) {
196 surface
->flags
|= RADEON_SURF_ZBUFFER
;
199 surface
->flags
|= RADEON_SURF_SBUFFER
|
200 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
203 if (rscreen
->chip_class
>= SI
) {
204 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
209 static int r600_setup_surface(struct pipe_screen
*screen
,
210 struct r600_texture
*rtex
,
211 unsigned pitch_in_bytes_override
)
213 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
216 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
221 rtex
->size
= rtex
->surface
.bo_size
;
223 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
224 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
227 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
228 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
229 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
230 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
231 rtex
->surface
.stencil_offset
=
232 rtex
->surface
.stencil_level
[0].offset
= rtex
->surface
.level
[0].slice_size
;
238 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
239 struct pipe_resource
*ptex
,
240 struct winsys_handle
*whandle
)
242 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
243 struct r600_resource
*resource
= &rtex
->resource
;
244 struct radeon_surface
*surface
= &rtex
->surface
;
245 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
247 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
249 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
250 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
251 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
252 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
253 surface
->bankw
, surface
->bankh
,
255 surface
->stencil_tile_split
,
257 surface
->level
[0].pitch_bytes
,
258 (surface
->flags
& RADEON_SURF_SCANOUT
) != 0);
260 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
261 surface
->level
[0].pitch_bytes
, whandle
);
264 static void r600_texture_destroy(struct pipe_screen
*screen
,
265 struct pipe_resource
*ptex
)
267 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
268 struct r600_resource
*resource
= &rtex
->resource
;
270 if (rtex
->flushed_depth_texture
)
271 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
273 pipe_resource_reference((struct pipe_resource
**)&rtex
->htile_buffer
, NULL
);
274 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
275 pipe_resource_reference((struct pipe_resource
**)&rtex
->cmask_buffer
, NULL
);
277 pb_reference(&resource
->buf
, NULL
);
281 static const struct u_resource_vtbl r600_texture_vtbl
;
283 /* The number of samples can be specified independently of the texture. */
284 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
285 struct r600_texture
*rtex
,
287 struct r600_fmask_info
*out
)
289 /* FMASK is allocated like an ordinary texture. */
290 struct radeon_surface fmask
= rtex
->surface
;
292 memset(out
, 0, sizeof(*out
));
294 fmask
.bo_alignment
= 0;
297 fmask
.flags
|= RADEON_SURF_FMASK
;
299 if (rscreen
->chip_class
>= SI
) {
300 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
303 switch (nr_samples
) {
307 if (rscreen
->chip_class
<= CAYMAN
) {
315 R600_ERR("Invalid sample count for FMASK allocation.\n");
319 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
320 * This can be fixed by writing a separate FMASK allocator specifically
321 * for R600-R700 asics. */
322 if (rscreen
->chip_class
<= R700
) {
326 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
327 R600_ERR("Got error in surface_init while allocating FMASK.\n");
331 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
333 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
334 if (out
->slice_tile_max
)
335 out
->slice_tile_max
-= 1;
337 out
->tile_mode_index
= fmask
.tiling_index
[0];
338 out
->pitch
= fmask
.level
[0].nblk_x
;
339 out
->bank_height
= fmask
.bankh
;
340 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
341 out
->size
= fmask
.bo_size
;
344 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
345 struct r600_texture
*rtex
)
347 r600_texture_get_fmask_info(rscreen
, rtex
,
348 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
350 rtex
->fmask
.offset
= align(rtex
->size
, rtex
->fmask
.alignment
);
351 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
354 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
355 struct r600_texture
*rtex
,
356 struct r600_cmask_info
*out
)
358 unsigned cmask_tile_width
= 8;
359 unsigned cmask_tile_height
= 8;
360 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
361 unsigned element_bits
= 4;
362 unsigned cmask_cache_bits
= 1024;
363 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
364 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
366 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
367 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
368 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
369 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
370 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
372 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
373 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
375 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
376 unsigned slice_bytes
=
377 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
379 assert(macro_tile_width
% 128 == 0);
380 assert(macro_tile_height
% 128 == 0);
382 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
383 out
->alignment
= MAX2(256, base_align
);
384 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
387 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
388 struct r600_texture
*rtex
,
389 struct r600_cmask_info
*out
)
391 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
392 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
393 unsigned cl_width
, cl_height
;
408 case 16: /* Hawaii */
417 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
419 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
420 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
421 unsigned slice_elements
= (width
* height
) / (8*8);
423 /* Each element of CMASK is a nibble. */
424 unsigned slice_bytes
= slice_elements
/ 2;
426 out
->slice_tile_max
= (width
* height
) / (128*128);
427 if (out
->slice_tile_max
)
428 out
->slice_tile_max
-= 1;
430 out
->alignment
= MAX2(256, base_align
);
431 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
434 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
435 struct r600_texture
*rtex
)
437 if (rscreen
->chip_class
>= SI
) {
438 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
440 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
443 rtex
->cmask
.offset
= align(rtex
->size
, rtex
->cmask
.alignment
);
444 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
447 void r600_texture_init_cmask(struct r600_common_screen
*rscreen
,
448 struct r600_texture
*rtex
)
450 assert(rtex
->cmask
.size
== 0);
452 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
454 rtex
->cmask_buffer
= (struct r600_resource
*)
455 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
456 PIPE_USAGE_STATIC
, rtex
->cmask
.size
);
457 if (rtex
->cmask_buffer
== NULL
) {
458 rtex
->cmask
.size
= 0;
462 static unsigned si_texture_htile_alloc_size(struct r600_common_screen
*rscreen
,
463 struct r600_texture
*rtex
)
465 unsigned cl_width
, cl_height
, width
, height
;
466 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
467 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
491 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
492 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
494 slice_elements
= (width
* height
) / (8 * 8);
495 slice_bytes
= slice_elements
* 4;
497 pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
498 base_align
= num_pipes
* pipe_interleave_bytes
;
500 return rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
503 static unsigned r600_texture_htile_alloc_size(struct r600_common_screen
*rscreen
,
504 struct r600_texture
*rtex
)
506 unsigned sw
= rtex
->surface
.level
[0].nblk_x
* rtex
->surface
.blk_w
;
507 unsigned sh
= rtex
->surface
.level
[0].nblk_y
* rtex
->surface
.blk_h
;
508 unsigned npipes
= rscreen
->info
.r600_num_tile_pipes
;
511 /* XXX also use it for other texture targets */
512 if (rscreen
->info
.drm_minor
< 26 ||
513 rtex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
514 rtex
->surface
.level
[0].nblk_x
< 32 ||
515 rtex
->surface
.level
[0].nblk_y
< 32) {
519 /* this alignment and htile size only apply to linear htile buffer */
520 sw
= align(sw
, 16 << 3);
521 sh
= align(sh
, npipes
<< 3);
522 htile_size
= (sw
>> 3) * (sh
>> 3) * 4;
523 /* must be aligned with 2K * npipes */
524 htile_size
= align(htile_size
, (2 << 10) * npipes
);
528 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
529 struct r600_texture
*rtex
)
532 if (rscreen
->chip_class
>= SI
) {
533 htile_size
= si_texture_htile_alloc_size(rscreen
, rtex
);
535 htile_size
= r600_texture_htile_alloc_size(rscreen
, rtex
);
541 /* XXX don't allocate it separately */
542 rtex
->htile_buffer
= (struct r600_resource
*)
543 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
544 PIPE_USAGE_STATIC
, htile_size
);
545 if (rtex
->htile_buffer
== NULL
) {
546 /* this is not a fatal error as we can still keep rendering
547 * without htile buffer */
548 R600_ERR("Failed to create buffer object for htile buffer.\n");
550 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0, htile_size
, 0);
554 /* Common processing for r600_texture_create and r600_texture_from_handle */
555 static struct r600_texture
*
556 r600_texture_create_object(struct pipe_screen
*screen
,
557 const struct pipe_resource
*base
,
558 unsigned pitch_in_bytes_override
,
559 struct pb_buffer
*buf
,
560 struct radeon_surface
*surface
)
562 struct r600_texture
*rtex
;
563 struct r600_resource
*resource
;
564 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
566 rtex
= CALLOC_STRUCT(r600_texture
);
570 resource
= &rtex
->resource
;
571 resource
->b
.b
= *base
;
572 resource
->b
.vtbl
= &r600_texture_vtbl
;
573 pipe_reference_init(&resource
->b
.b
.reference
, 1);
574 resource
->b
.b
.screen
= screen
;
575 rtex
->pitch_override
= pitch_in_bytes_override
;
577 /* don't include stencil-only formats which we don't support for rendering */
578 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
580 rtex
->surface
= *surface
;
581 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
)) {
586 /* Tiled depth textures utilize the non-displayable tile order.
587 * This must be done after r600_setup_surface.
588 * Applies to R600-Cayman. */
589 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
591 if (rtex
->is_depth
) {
592 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
593 R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
594 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
)) {
596 r600_texture_allocate_htile(rscreen
, rtex
);
599 if (base
->nr_samples
> 1) {
601 r600_texture_allocate_fmask(rscreen
, rtex
);
602 r600_texture_allocate_cmask(rscreen
, rtex
);
603 rtex
->cmask_buffer
= &rtex
->resource
;
605 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
612 /* Now create the backing buffer. */
614 unsigned base_align
= rtex
->surface
.bo_alignment
;
615 unsigned usage
= rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
616 PIPE_USAGE_STATIC
: base
->usage
;
618 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, FALSE
, usage
)) {
624 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
625 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
628 if (rtex
->cmask
.size
) {
629 /* Initialize the cmask to 0xCC (= compressed state). */
630 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
631 rtex
->cmask
.offset
, rtex
->cmask
.size
, 0xCCCCCCCC);
634 if (rscreen
->debug_flags
& DBG_VM
) {
635 fprintf(stderr
, "VM start=0x%"PRIu64
" end=0x%"PRIu64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
636 r600_resource_va(screen
, &rtex
->resource
.b
.b
),
637 r600_resource_va(screen
, &rtex
->resource
.b
.b
) + rtex
->resource
.buf
->size
,
638 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
639 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
642 if (rscreen
->debug_flags
& DBG_TEX
||
643 (rtex
->resource
.b
.b
.last_level
> 0 && rscreen
->debug_flags
& DBG_TEXMIP
)) {
644 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
645 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
646 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
647 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
648 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
649 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
650 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
651 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
652 rtex
->surface
.flags
, util_format_short_name(base
->format
));
653 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
654 printf(" L %i: offset=%"PRIu64
", slice_size=%"PRIu64
", npix_x=%u, "
655 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
656 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
657 i
, rtex
->surface
.level
[i
].offset
,
658 rtex
->surface
.level
[i
].slice_size
,
659 u_minify(rtex
->resource
.b
.b
.width0
, i
),
660 u_minify(rtex
->resource
.b
.b
.height0
, i
),
661 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
662 rtex
->surface
.level
[i
].nblk_x
,
663 rtex
->surface
.level
[i
].nblk_y
,
664 rtex
->surface
.level
[i
].nblk_z
,
665 rtex
->surface
.level
[i
].pitch_bytes
,
666 rtex
->surface
.level
[i
].mode
);
668 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
669 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
670 printf(" S %i: offset=%"PRIu64
", slice_size=%"PRIu64
", npix_x=%u, "
671 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
672 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
673 i
, rtex
->surface
.stencil_level
[i
].offset
,
674 rtex
->surface
.stencil_level
[i
].slice_size
,
675 u_minify(rtex
->resource
.b
.b
.width0
, i
),
676 u_minify(rtex
->resource
.b
.b
.height0
, i
),
677 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
678 rtex
->surface
.stencil_level
[i
].nblk_x
,
679 rtex
->surface
.stencil_level
[i
].nblk_y
,
680 rtex
->surface
.stencil_level
[i
].nblk_z
,
681 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
682 rtex
->surface
.stencil_level
[i
].mode
);
689 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
690 const struct pipe_resource
*templ
)
692 const struct util_format_description
*desc
= util_format_description(templ
->format
);
694 /* MSAA resources must be 2D tiled. */
695 if (templ
->nr_samples
> 1)
696 return RADEON_SURF_MODE_2D
;
698 /* Transfer resources should be linear. */
699 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
700 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
702 /* Handle common candidates for the linear mode.
703 * Compressed textures must always be tiled. */
704 if (!(templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
) &&
705 !util_format_is_compressed(templ
->format
)) {
706 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600-Cayman. */
707 if (rscreen
->chip_class
<= CAYMAN
&&
708 desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
709 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
711 /* Cursors are linear on SI.
712 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
713 if (rscreen
->chip_class
>= SI
&&
714 (templ
->bind
& PIPE_BIND_CURSOR
))
715 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
717 if (templ
->bind
& PIPE_BIND_LINEAR
)
718 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
720 /* Textures with a very small height are recommended to be linear. */
721 if (templ
->target
== PIPE_TEXTURE_1D
||
722 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
724 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
726 /* Textures likely to be mapped often. */
727 if (templ
->usage
== PIPE_USAGE_STAGING
||
728 templ
->usage
== PIPE_USAGE_STREAM
)
729 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
732 /* Make small textures 1D tiled. */
733 if (templ
->width0
<= 16 || templ
->height0
<= 16)
734 return RADEON_SURF_MODE_1D
;
736 /* The allocator will switch to 1D if needed. */
737 return RADEON_SURF_MODE_2D
;
740 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
741 const struct pipe_resource
*templ
)
743 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
744 struct radeon_surface surface
= {0};
747 r
= r600_init_surface(rscreen
, &surface
, templ
,
748 r600_choose_tiling(rscreen
, templ
),
749 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
753 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
757 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
761 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
762 const struct pipe_resource
*templ
,
763 struct winsys_handle
*whandle
)
765 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
766 struct pb_buffer
*buf
= NULL
;
769 enum radeon_bo_layout micro
, macro
;
770 struct radeon_surface surface
;
774 /* Support only 2D textures without mipmaps */
775 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
776 templ
->depth0
!= 1 || templ
->last_level
!= 0)
779 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
783 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
784 &surface
.bankw
, &surface
.bankh
,
786 &surface
.stencil_tile_split
,
787 &surface
.mtilea
, &scanout
);
789 if (macro
== RADEON_LAYOUT_TILED
)
790 array_mode
= RADEON_SURF_MODE_2D
;
791 else if (micro
== RADEON_LAYOUT_TILED
)
792 array_mode
= RADEON_SURF_MODE_1D
;
794 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
796 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
802 surface
.flags
|= RADEON_SURF_SCANOUT
;
804 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
805 stride
, buf
, &surface
);
808 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
809 struct pipe_resource
*texture
,
810 struct r600_texture
**staging
)
812 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
813 struct pipe_resource resource
;
814 struct r600_texture
**flushed_depth_texture
= staging
?
815 staging
: &rtex
->flushed_depth_texture
;
817 if (!staging
&& rtex
->flushed_depth_texture
)
818 return true; /* it's ready */
820 resource
.target
= texture
->target
;
821 resource
.format
= texture
->format
;
822 resource
.width0
= texture
->width0
;
823 resource
.height0
= texture
->height0
;
824 resource
.depth0
= texture
->depth0
;
825 resource
.array_size
= texture
->array_size
;
826 resource
.last_level
= texture
->last_level
;
827 resource
.nr_samples
= texture
->nr_samples
;
828 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
829 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
830 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
833 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
835 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
836 if (*flushed_depth_texture
== NULL
) {
837 R600_ERR("failed to create temporary texture to hold flushed depth\n");
841 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
842 (*flushed_depth_texture
)->non_disp_tiling
= false;
847 * Initialize the pipe_resource descriptor to be of the same size as the box,
848 * which is supposed to hold a subregion of the texture "orig" at the given
851 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
852 struct pipe_resource
*orig
,
853 const struct pipe_box
*box
,
854 unsigned level
, unsigned flags
)
856 memset(res
, 0, sizeof(*res
));
857 res
->format
= orig
->format
;
858 res
->width0
= box
->width
;
859 res
->height0
= box
->height
;
862 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
865 /* We must set the correct texture target and dimensions for a 3D box. */
866 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0)
867 res
->target
= orig
->target
;
869 res
->target
= PIPE_TEXTURE_2D
;
871 switch (res
->target
) {
872 case PIPE_TEXTURE_1D_ARRAY
:
873 case PIPE_TEXTURE_2D_ARRAY
:
874 case PIPE_TEXTURE_CUBE_ARRAY
:
875 res
->array_size
= box
->depth
;
877 case PIPE_TEXTURE_3D
:
878 res
->depth0
= box
->depth
;
884 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
885 struct pipe_resource
*texture
,
888 const struct pipe_box
*box
,
889 struct pipe_transfer
**ptransfer
)
891 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
892 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
893 struct r600_transfer
*trans
;
894 boolean use_staging_texture
= FALSE
;
895 struct r600_resource
*buf
;
899 /* We cannot map a tiled texture directly because the data is
900 * in a different order, therefore we do detiling using a blit.
902 * Also, use a temporary in GTT memory for read transfers, as
903 * the CPU is much happier reading out of cached system memory
904 * than uncached VRAM.
906 if (rtex
->surface
.level
[level
].mode
>= RADEON_SURF_MODE_1D
)
907 use_staging_texture
= TRUE
;
909 /* Untiled buffers in VRAM, which is slow for CPU reads */
910 if ((usage
& PIPE_TRANSFER_READ
) && !(usage
& PIPE_TRANSFER_MAP_DIRECTLY
) &&
911 (rtex
->resource
.domains
== RADEON_DOMAIN_VRAM
)) {
912 use_staging_texture
= TRUE
;
915 /* Use a staging texture for uploads if the underlying BO is busy. */
916 if (!(usage
& PIPE_TRANSFER_READ
) &&
917 (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
918 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
919 use_staging_texture
= TRUE
;
922 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
923 use_staging_texture
= FALSE
;
926 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
930 trans
= CALLOC_STRUCT(r600_transfer
);
933 trans
->transfer
.resource
= texture
;
934 trans
->transfer
.level
= level
;
935 trans
->transfer
.usage
= usage
;
936 trans
->transfer
.box
= *box
;
938 if (rtex
->is_depth
) {
939 struct r600_texture
*staging_depth
;
941 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
942 /* MSAA depth buffers need to be converted to single sample buffers.
944 * Mapping MSAA depth buffers can occur if ReadPixels is called
945 * with a multisample GLX visual.
947 * First downsample the depth buffer to a temporary texture,
948 * then decompress the temporary one to staging.
950 * Only the region being mapped is transfered.
952 struct pipe_resource resource
;
954 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
956 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
957 R600_ERR("failed to create temporary texture to hold untiled copy\n");
962 if (usage
& PIPE_TRANSFER_READ
) {
963 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
965 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
966 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
967 0, 0, 0, box
->depth
, 0, 0);
968 pipe_resource_reference((struct pipe_resource
**)&temp
, NULL
);
972 /* XXX: only readback the rectangle which is being mapped? */
973 /* XXX: when discard is true, no need to read back from depth texture */
974 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
975 R600_ERR("failed to create temporary texture to hold untiled copy\n");
980 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
982 box
->z
, box
->z
+ box
->depth
- 1,
985 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
988 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
989 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
990 trans
->staging
= (struct r600_resource
*)staging_depth
;
991 } else if (use_staging_texture
) {
992 struct pipe_resource resource
;
993 struct r600_texture
*staging
;
995 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
996 R600_RESOURCE_FLAG_TRANSFER
);
998 /* Create the temporary texture. */
999 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1000 if (staging
== NULL
) {
1001 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1005 trans
->staging
= &staging
->resource
;
1006 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1007 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1008 if (usage
& PIPE_TRANSFER_READ
) {
1009 r600_copy_to_staging_texture(ctx
, trans
);
1012 /* the resource is mapped directly */
1013 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1014 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1015 offset
= r600_texture_get_offset(rtex
, level
, box
);
1018 if (trans
->staging
) {
1019 buf
= trans
->staging
;
1021 buf
= &rtex
->resource
;
1024 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1025 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
1030 *ptransfer
= &trans
->transfer
;
1031 return map
+ offset
;
1034 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1035 struct pipe_transfer
* transfer
)
1037 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1038 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1039 struct radeon_winsys_cs_handle
*buf
;
1040 struct pipe_resource
*texture
= transfer
->resource
;
1041 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1043 if (rtransfer
->staging
) {
1044 buf
= rtransfer
->staging
->cs_buf
;
1046 buf
= r600_resource(transfer
->resource
)->cs_buf
;
1048 rctx
->ws
->buffer_unmap(buf
);
1050 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1051 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1052 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1053 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1054 &rtransfer
->staging
->b
.b
, transfer
->level
,
1057 r600_copy_from_staging_texture(ctx
, rtransfer
);
1061 if (rtransfer
->staging
)
1062 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
1067 static const struct u_resource_vtbl r600_texture_vtbl
=
1069 r600_texture_get_handle
, /* get_handle */
1070 r600_texture_destroy
, /* resource_destroy */
1071 r600_texture_transfer_map
, /* transfer_map */
1072 NULL
, /* transfer_flush_region */
1073 r600_texture_transfer_unmap
, /* transfer_unmap */
1074 NULL
/* transfer_inline_write */