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radeonsi: implement fast color clear
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 if (!rctx->dma_copy(ctx, dst, 0, 0, 0, 0,
84 src, transfer->level,
85 &transfer->box)) {
86 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
87 src, transfer->level, &transfer->box);
88 }
89 }
90
91 /* Copy from a transfer's staging texture to a full GPU one. */
92 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
93 {
94 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
95 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
96 struct pipe_resource *dst = transfer->resource;
97 struct pipe_resource *src = &rtransfer->staging->b.b;
98 struct pipe_box sbox;
99
100 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
101
102 if (dst->nr_samples > 1) {
103 r600_copy_region_with_blit(ctx, dst, transfer->level,
104 transfer->box.x, transfer->box.y, transfer->box.z,
105 src, 0, &sbox);
106 return;
107 }
108
109 if (!rctx->dma_copy(ctx, dst, transfer->level,
110 transfer->box.x, transfer->box.y, transfer->box.z,
111 src, 0, &sbox)) {
112 ctx->resource_copy_region(ctx, dst, transfer->level,
113 transfer->box.x, transfer->box.y, transfer->box.z,
114 src, 0, &sbox);
115 }
116 }
117
118 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
119 const struct pipe_box *box)
120 {
121 enum pipe_format format = rtex->resource.b.b.format;
122
123 return rtex->surface.level[level].offset +
124 box->z * rtex->surface.level[level].slice_size +
125 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
126 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
127 }
128
129 static int r600_init_surface(struct r600_common_screen *rscreen,
130 struct radeon_surface *surface,
131 const struct pipe_resource *ptex,
132 unsigned array_mode,
133 bool is_flushed_depth)
134 {
135 const struct util_format_description *desc =
136 util_format_description(ptex->format);
137 bool is_depth, is_stencil;
138
139 is_depth = util_format_has_depth(desc);
140 is_stencil = util_format_has_stencil(desc);
141
142 surface->npix_x = ptex->width0;
143 surface->npix_y = ptex->height0;
144 surface->npix_z = ptex->depth0;
145 surface->blk_w = util_format_get_blockwidth(ptex->format);
146 surface->blk_h = util_format_get_blockheight(ptex->format);
147 surface->blk_d = 1;
148 surface->array_size = 1;
149 surface->last_level = ptex->last_level;
150
151 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
152 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
153 surface->bpe = 4; /* stencil is allocated separately on evergreen */
154 } else {
155 surface->bpe = util_format_get_blocksize(ptex->format);
156 /* align byte per element on dword */
157 if (surface->bpe == 3) {
158 surface->bpe = 4;
159 }
160 }
161
162 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
163 surface->flags = RADEON_SURF_SET(array_mode, MODE);
164
165 switch (ptex->target) {
166 case PIPE_TEXTURE_1D:
167 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
168 break;
169 case PIPE_TEXTURE_RECT:
170 case PIPE_TEXTURE_2D:
171 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
172 break;
173 case PIPE_TEXTURE_3D:
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
175 break;
176 case PIPE_TEXTURE_1D_ARRAY:
177 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
178 surface->array_size = ptex->array_size;
179 break;
180 case PIPE_TEXTURE_2D_ARRAY:
181 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
182 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
183 surface->array_size = ptex->array_size;
184 break;
185 case PIPE_TEXTURE_CUBE:
186 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
187 break;
188 case PIPE_BUFFER:
189 default:
190 return -EINVAL;
191 }
192 if (ptex->bind & PIPE_BIND_SCANOUT) {
193 surface->flags |= RADEON_SURF_SCANOUT;
194 }
195
196 if (!is_flushed_depth && is_depth) {
197 surface->flags |= RADEON_SURF_ZBUFFER;
198
199 if (is_stencil) {
200 surface->flags |= RADEON_SURF_SBUFFER |
201 RADEON_SURF_HAS_SBUFFER_MIPTREE;
202 }
203 }
204 if (rscreen->chip_class >= SI) {
205 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
206 }
207 return 0;
208 }
209
210 static int r600_setup_surface(struct pipe_screen *screen,
211 struct r600_texture *rtex,
212 unsigned pitch_in_bytes_override)
213 {
214 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
215 int r;
216
217 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
218 if (r) {
219 return r;
220 }
221
222 rtex->size = rtex->surface.bo_size;
223
224 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
225 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
226 * for those
227 */
228 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
229 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
230 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
231 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
232 rtex->surface.stencil_offset =
233 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
234 }
235 }
236 return 0;
237 }
238
239 static boolean r600_texture_get_handle(struct pipe_screen* screen,
240 struct pipe_resource *ptex,
241 struct winsys_handle *whandle)
242 {
243 struct r600_texture *rtex = (struct r600_texture*)ptex;
244 struct r600_resource *resource = &rtex->resource;
245 struct radeon_surface *surface = &rtex->surface;
246 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
247
248 rscreen->ws->buffer_set_tiling(resource->buf,
249 NULL,
250 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
251 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
252 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
253 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
254 surface->bankw, surface->bankh,
255 surface->tile_split,
256 surface->stencil_tile_split,
257 surface->mtilea,
258 surface->level[0].pitch_bytes,
259 (surface->flags & RADEON_SURF_SCANOUT) != 0);
260
261 return rscreen->ws->buffer_get_handle(resource->buf,
262 surface->level[0].pitch_bytes, whandle);
263 }
264
265 static void r600_texture_destroy(struct pipe_screen *screen,
266 struct pipe_resource *ptex)
267 {
268 struct r600_texture *rtex = (struct r600_texture*)ptex;
269 struct r600_resource *resource = &rtex->resource;
270
271 if (rtex->flushed_depth_texture)
272 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
273
274 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
275 if (rtex->cmask_buffer != &rtex->resource) {
276 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
277 }
278 pb_reference(&resource->buf, NULL);
279 FREE(rtex);
280 }
281
282 static const struct u_resource_vtbl r600_texture_vtbl;
283
284 /* The number of samples can be specified independently of the texture. */
285 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
286 struct r600_texture *rtex,
287 unsigned nr_samples,
288 struct r600_fmask_info *out)
289 {
290 /* FMASK is allocated like an ordinary texture. */
291 struct radeon_surface fmask = rtex->surface;
292
293 memset(out, 0, sizeof(*out));
294
295 fmask.bo_alignment = 0;
296 fmask.bo_size = 0;
297 fmask.nsamples = 1;
298 fmask.flags |= RADEON_SURF_FMASK;
299
300 if (rscreen->chip_class >= SI) {
301 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
302 }
303
304 switch (nr_samples) {
305 case 2:
306 case 4:
307 fmask.bpe = 1;
308 if (rscreen->chip_class <= CAYMAN) {
309 fmask.bankh = 4;
310 }
311 break;
312 case 8:
313 fmask.bpe = 4;
314 break;
315 default:
316 R600_ERR("Invalid sample count for FMASK allocation.\n");
317 return;
318 }
319
320 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
321 * This can be fixed by writing a separate FMASK allocator specifically
322 * for R600-R700 asics. */
323 if (rscreen->chip_class <= R700) {
324 fmask.bpe *= 2;
325 }
326
327 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
328 R600_ERR("Got error in surface_init while allocating FMASK.\n");
329 return;
330 }
331
332 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
333
334 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
335 if (out->slice_tile_max)
336 out->slice_tile_max -= 1;
337
338 out->tile_mode_index = fmask.tiling_index[0];
339 out->pitch = fmask.level[0].nblk_x;
340 out->bank_height = fmask.bankh;
341 out->alignment = MAX2(256, fmask.bo_alignment);
342 out->size = fmask.bo_size;
343 }
344
345 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
346 struct r600_texture *rtex)
347 {
348 r600_texture_get_fmask_info(rscreen, rtex,
349 rtex->resource.b.b.nr_samples, &rtex->fmask);
350
351 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
352 rtex->size = rtex->fmask.offset + rtex->fmask.size;
353 }
354
355 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
356 struct r600_texture *rtex,
357 struct r600_cmask_info *out)
358 {
359 unsigned cmask_tile_width = 8;
360 unsigned cmask_tile_height = 8;
361 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
362 unsigned element_bits = 4;
363 unsigned cmask_cache_bits = 1024;
364 unsigned num_pipes = rscreen->tiling_info.num_channels;
365 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
366
367 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
368 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
369 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
370 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
371 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
372
373 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
374 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
375
376 unsigned base_align = num_pipes * pipe_interleave_bytes;
377 unsigned slice_bytes =
378 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
379
380 assert(macro_tile_width % 128 == 0);
381 assert(macro_tile_height % 128 == 0);
382
383 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
384 out->alignment = MAX2(256, base_align);
385 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
386 }
387
388 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
389 struct r600_texture *rtex,
390 struct r600_cmask_info *out)
391 {
392 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
393 unsigned num_pipes = rscreen->tiling_info.num_channels;
394 unsigned cl_width, cl_height;
395
396 switch (num_pipes) {
397 case 2:
398 cl_width = 32;
399 cl_height = 16;
400 break;
401 case 4:
402 cl_width = 32;
403 cl_height = 32;
404 break;
405 case 8:
406 cl_width = 64;
407 cl_height = 32;
408 break;
409 case 16: /* Hawaii */
410 cl_width = 64;
411 cl_height = 64;
412 break;
413 default:
414 assert(0);
415 return;
416 }
417
418 unsigned base_align = num_pipes * pipe_interleave_bytes;
419
420 unsigned width = align(rtex->surface.npix_x, cl_width*8);
421 unsigned height = align(rtex->surface.npix_y, cl_height*8);
422 unsigned slice_elements = (width * height) / (8*8);
423
424 /* Each element of CMASK is a nibble. */
425 unsigned slice_bytes = slice_elements / 2;
426
427 out->slice_tile_max = (width * height) / (128*128);
428 if (out->slice_tile_max)
429 out->slice_tile_max -= 1;
430
431 out->alignment = MAX2(256, base_align);
432 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
433 }
434
435 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
436 struct r600_texture *rtex)
437 {
438 if (rscreen->chip_class >= SI) {
439 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
440 } else {
441 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
442 }
443
444 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
445 rtex->size = rtex->cmask.offset + rtex->cmask.size;
446
447 if (rscreen->chip_class >= SI)
448 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
449 else
450 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
451 }
452
453 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
454 struct r600_texture *rtex)
455 {
456 if (rtex->cmask_buffer)
457 return;
458
459 assert(rtex->cmask.size == 0);
460
461 if (rscreen->chip_class >= SI) {
462 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
463 } else {
464 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
465 }
466
467 rtex->cmask_buffer = (struct r600_resource *)
468 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
469 PIPE_USAGE_DEFAULT, rtex->cmask.size);
470 if (rtex->cmask_buffer == NULL) {
471 rtex->cmask.size = 0;
472 return;
473 }
474
475 /* update colorbuffer state bits */
476 rtex->cmask.base_address_reg =
477 r600_resource_va(&rscreen->b, &rtex->cmask_buffer->b.b) >> 8;
478
479 if (rscreen->chip_class >= SI)
480 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
481 else
482 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
483 }
484
485 static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
486 struct r600_texture *rtex)
487 {
488 unsigned cl_width, cl_height, width, height;
489 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
490 unsigned num_pipes = rscreen->tiling_info.num_channels;
491
492 /* HTILE doesn't work with 1D tiling (there's massive corruption
493 * in glxgears). */
494 if (rtex->surface.level[0].mode != RADEON_SURF_MODE_2D)
495 return 0;
496
497 switch (num_pipes) {
498 case 2:
499 cl_width = 32;
500 cl_height = 32;
501 break;
502 case 4:
503 cl_width = 64;
504 cl_height = 32;
505 break;
506 case 8:
507 cl_width = 64;
508 cl_height = 64;
509 break;
510 case 16:
511 cl_width = 128;
512 cl_height = 64;
513 break;
514 default:
515 assert(0);
516 return 0;
517 }
518
519 width = align(rtex->surface.npix_x, cl_width * 8);
520 height = align(rtex->surface.npix_y, cl_height * 8);
521
522 slice_elements = (width * height) / (8 * 8);
523 slice_bytes = slice_elements * 4;
524
525 pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
526 base_align = num_pipes * pipe_interleave_bytes;
527
528 return rtex->surface.array_size * align(slice_bytes, base_align);
529 }
530
531 static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
532 struct r600_texture *rtex)
533 {
534 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
535 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
536 unsigned npipes = rscreen->info.r600_num_tile_pipes;
537 unsigned htile_size;
538
539 /* XXX also use it for other texture targets */
540 if (rscreen->info.drm_minor < 26 ||
541 rtex->resource.b.b.target != PIPE_TEXTURE_2D ||
542 rtex->surface.level[0].nblk_x < 32 ||
543 rtex->surface.level[0].nblk_y < 32) {
544 return 0;
545 }
546
547 /* this alignment and htile size only apply to linear htile buffer */
548 sw = align(sw, 16 << 3);
549 sh = align(sh, npipes << 3);
550 htile_size = (sw >> 3) * (sh >> 3) * 4;
551 /* must be aligned with 2K * npipes */
552 htile_size = align(htile_size, (2 << 10) * npipes);
553 return htile_size;
554 }
555
556 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
557 struct r600_texture *rtex)
558 {
559 unsigned htile_size;
560 if (rscreen->chip_class >= SI) {
561 htile_size = si_texture_htile_alloc_size(rscreen, rtex);
562 } else {
563 htile_size = r600_texture_htile_alloc_size(rscreen, rtex);
564 }
565
566 if (!htile_size)
567 return;
568
569 /* XXX don't allocate it separately */
570 rtex->htile_buffer = (struct r600_resource*)
571 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
572 PIPE_USAGE_DEFAULT, htile_size);
573 if (rtex->htile_buffer == NULL) {
574 /* this is not a fatal error as we can still keep rendering
575 * without htile buffer */
576 R600_ERR("Failed to create buffer object for htile buffer.\n");
577 } else {
578 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0, htile_size, 0);
579 }
580 }
581
582 /* Common processing for r600_texture_create and r600_texture_from_handle */
583 static struct r600_texture *
584 r600_texture_create_object(struct pipe_screen *screen,
585 const struct pipe_resource *base,
586 unsigned pitch_in_bytes_override,
587 struct pb_buffer *buf,
588 struct radeon_surface *surface)
589 {
590 struct r600_texture *rtex;
591 struct r600_resource *resource;
592 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
593 uint64_t va;
594
595 rtex = CALLOC_STRUCT(r600_texture);
596 if (rtex == NULL)
597 return NULL;
598
599 resource = &rtex->resource;
600 resource->b.b = *base;
601 resource->b.vtbl = &r600_texture_vtbl;
602 pipe_reference_init(&resource->b.b.reference, 1);
603 resource->b.b.screen = screen;
604 rtex->pitch_override = pitch_in_bytes_override;
605
606 /* don't include stencil-only formats which we don't support for rendering */
607 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
608
609 rtex->surface = *surface;
610 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
611 FREE(rtex);
612 return NULL;
613 }
614
615 /* Tiled depth textures utilize the non-displayable tile order.
616 * This must be done after r600_setup_surface.
617 * Applies to R600-Cayman. */
618 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
619
620 if (rtex->is_depth) {
621 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
622 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
623 (rscreen->debug_flags & DBG_HYPERZ)) {
624
625 r600_texture_allocate_htile(rscreen, rtex);
626 }
627 } else {
628 if (base->nr_samples > 1) {
629 if (!buf) {
630 r600_texture_allocate_fmask(rscreen, rtex);
631 r600_texture_allocate_cmask(rscreen, rtex);
632 rtex->cmask_buffer = &rtex->resource;
633 }
634 if (!rtex->fmask.size || !rtex->cmask.size) {
635 FREE(rtex);
636 return NULL;
637 }
638 }
639 }
640
641 /* Now create the backing buffer. */
642 if (!buf) {
643 if (!r600_init_resource(rscreen, resource, rtex->size,
644 rtex->surface.bo_alignment, FALSE)) {
645 FREE(rtex);
646 return NULL;
647 }
648 } else {
649 resource->buf = buf;
650 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
651 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
652 }
653
654 if (rtex->cmask.size) {
655 /* Initialize the cmask to 0xCC (= compressed state). */
656 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
657 rtex->cmask.offset, rtex->cmask.size, 0xCCCCCCCC);
658 }
659
660 /* Initialize the CMASK base register value. */
661 va = r600_resource_va(&rscreen->b, &rtex->resource.b.b);
662 rtex->cmask.base_address_reg = (va + rtex->cmask.offset) >> 8;
663
664 if (rscreen->debug_flags & DBG_VM) {
665 fprintf(stderr, "VM start=0x%"PRIu64" end=0x%"PRIu64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
666 r600_resource_va(screen, &rtex->resource.b.b),
667 r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
668 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
669 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
670 }
671
672 if (rscreen->debug_flags & DBG_TEX ||
673 (rtex->resource.b.b.last_level > 0 && rscreen->debug_flags & DBG_TEXMIP)) {
674 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
675 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
676 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
677 rtex->surface.npix_x, rtex->surface.npix_y,
678 rtex->surface.npix_z, rtex->surface.blk_w,
679 rtex->surface.blk_h, rtex->surface.blk_d,
680 rtex->surface.array_size, rtex->surface.last_level,
681 rtex->surface.bpe, rtex->surface.nsamples,
682 rtex->surface.flags, util_format_short_name(base->format));
683 for (int i = 0; i <= rtex->surface.last_level; i++) {
684 printf(" L %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
685 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
686 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
687 i, rtex->surface.level[i].offset,
688 rtex->surface.level[i].slice_size,
689 u_minify(rtex->resource.b.b.width0, i),
690 u_minify(rtex->resource.b.b.height0, i),
691 u_minify(rtex->resource.b.b.depth0, i),
692 rtex->surface.level[i].nblk_x,
693 rtex->surface.level[i].nblk_y,
694 rtex->surface.level[i].nblk_z,
695 rtex->surface.level[i].pitch_bytes,
696 rtex->surface.level[i].mode);
697 }
698 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
699 for (int i = 0; i <= rtex->surface.last_level; i++) {
700 printf(" S %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
701 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
702 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
703 i, rtex->surface.stencil_level[i].offset,
704 rtex->surface.stencil_level[i].slice_size,
705 u_minify(rtex->resource.b.b.width0, i),
706 u_minify(rtex->resource.b.b.height0, i),
707 u_minify(rtex->resource.b.b.depth0, i),
708 rtex->surface.stencil_level[i].nblk_x,
709 rtex->surface.stencil_level[i].nblk_y,
710 rtex->surface.stencil_level[i].nblk_z,
711 rtex->surface.stencil_level[i].pitch_bytes,
712 rtex->surface.stencil_level[i].mode);
713 }
714 }
715 }
716 return rtex;
717 }
718
719 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
720 const struct pipe_resource *templ)
721 {
722 const struct util_format_description *desc = util_format_description(templ->format);
723
724 /* MSAA resources must be 2D tiled. */
725 if (templ->nr_samples > 1)
726 return RADEON_SURF_MODE_2D;
727
728 /* Transfer resources should be linear. */
729 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
730 return RADEON_SURF_MODE_LINEAR_ALIGNED;
731
732 /* Handle common candidates for the linear mode.
733 * Compressed textures must always be tiled. */
734 if (!(templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) &&
735 !util_format_is_compressed(templ->format)) {
736 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600-Cayman. */
737 if (rscreen->chip_class <= CAYMAN &&
738 desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
739 return RADEON_SURF_MODE_LINEAR_ALIGNED;
740
741 /* Cursors are linear on SI.
742 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
743 if (rscreen->chip_class >= SI &&
744 (templ->bind & PIPE_BIND_CURSOR))
745 return RADEON_SURF_MODE_LINEAR_ALIGNED;
746
747 if (templ->bind & PIPE_BIND_LINEAR)
748 return RADEON_SURF_MODE_LINEAR_ALIGNED;
749
750 /* Textures with a very small height are recommended to be linear. */
751 if (templ->target == PIPE_TEXTURE_1D ||
752 templ->target == PIPE_TEXTURE_1D_ARRAY ||
753 templ->height0 <= 4)
754 return RADEON_SURF_MODE_LINEAR_ALIGNED;
755
756 /* Textures likely to be mapped often. */
757 if (templ->usage == PIPE_USAGE_STAGING ||
758 templ->usage == PIPE_USAGE_STREAM)
759 return RADEON_SURF_MODE_LINEAR_ALIGNED;
760 }
761
762 /* Make small textures 1D tiled. */
763 if (templ->width0 <= 16 || templ->height0 <= 16)
764 return RADEON_SURF_MODE_1D;
765
766 /* The allocator will switch to 1D if needed. */
767 return RADEON_SURF_MODE_2D;
768 }
769
770 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
771 const struct pipe_resource *templ)
772 {
773 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
774 struct radeon_surface surface = {0};
775 int r;
776
777 r = r600_init_surface(rscreen, &surface, templ,
778 r600_choose_tiling(rscreen, templ),
779 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
780 if (r) {
781 return NULL;
782 }
783 r = rscreen->ws->surface_best(rscreen->ws, &surface);
784 if (r) {
785 return NULL;
786 }
787 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
788 0, NULL, &surface);
789 }
790
791 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
792 const struct pipe_resource *templ,
793 struct winsys_handle *whandle)
794 {
795 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
796 struct pb_buffer *buf = NULL;
797 unsigned stride = 0;
798 unsigned array_mode;
799 enum radeon_bo_layout micro, macro;
800 struct radeon_surface surface;
801 bool scanout;
802 int r;
803
804 /* Support only 2D textures without mipmaps */
805 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
806 templ->depth0 != 1 || templ->last_level != 0)
807 return NULL;
808
809 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
810 if (!buf)
811 return NULL;
812
813 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
814 &surface.bankw, &surface.bankh,
815 &surface.tile_split,
816 &surface.stencil_tile_split,
817 &surface.mtilea, &scanout);
818
819 if (macro == RADEON_LAYOUT_TILED)
820 array_mode = RADEON_SURF_MODE_2D;
821 else if (micro == RADEON_LAYOUT_TILED)
822 array_mode = RADEON_SURF_MODE_1D;
823 else
824 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
825
826 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
827 if (r) {
828 return NULL;
829 }
830
831 if (scanout)
832 surface.flags |= RADEON_SURF_SCANOUT;
833
834 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
835 stride, buf, &surface);
836 }
837
838 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
839 struct pipe_resource *texture,
840 struct r600_texture **staging)
841 {
842 struct r600_texture *rtex = (struct r600_texture*)texture;
843 struct pipe_resource resource;
844 struct r600_texture **flushed_depth_texture = staging ?
845 staging : &rtex->flushed_depth_texture;
846
847 if (!staging && rtex->flushed_depth_texture)
848 return true; /* it's ready */
849
850 resource.target = texture->target;
851 resource.format = texture->format;
852 resource.width0 = texture->width0;
853 resource.height0 = texture->height0;
854 resource.depth0 = texture->depth0;
855 resource.array_size = texture->array_size;
856 resource.last_level = texture->last_level;
857 resource.nr_samples = texture->nr_samples;
858 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
859 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
860 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
861
862 if (staging)
863 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
864
865 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
866 if (*flushed_depth_texture == NULL) {
867 R600_ERR("failed to create temporary texture to hold flushed depth\n");
868 return false;
869 }
870
871 (*flushed_depth_texture)->is_flushing_texture = TRUE;
872 (*flushed_depth_texture)->non_disp_tiling = false;
873 return true;
874 }
875
876 /**
877 * Initialize the pipe_resource descriptor to be of the same size as the box,
878 * which is supposed to hold a subregion of the texture "orig" at the given
879 * mipmap level.
880 */
881 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
882 struct pipe_resource *orig,
883 const struct pipe_box *box,
884 unsigned level, unsigned flags)
885 {
886 memset(res, 0, sizeof(*res));
887 res->format = orig->format;
888 res->width0 = box->width;
889 res->height0 = box->height;
890 res->depth0 = 1;
891 res->array_size = 1;
892 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
893 res->flags = flags;
894
895 /* We must set the correct texture target and dimensions for a 3D box. */
896 if (box->depth > 1 && util_max_layer(orig, level) > 0)
897 res->target = orig->target;
898 else
899 res->target = PIPE_TEXTURE_2D;
900
901 switch (res->target) {
902 case PIPE_TEXTURE_1D_ARRAY:
903 case PIPE_TEXTURE_2D_ARRAY:
904 case PIPE_TEXTURE_CUBE_ARRAY:
905 res->array_size = box->depth;
906 break;
907 case PIPE_TEXTURE_3D:
908 res->depth0 = box->depth;
909 break;
910 default:;
911 }
912 }
913
914 static void *r600_texture_transfer_map(struct pipe_context *ctx,
915 struct pipe_resource *texture,
916 unsigned level,
917 unsigned usage,
918 const struct pipe_box *box,
919 struct pipe_transfer **ptransfer)
920 {
921 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
922 struct r600_texture *rtex = (struct r600_texture*)texture;
923 struct r600_transfer *trans;
924 boolean use_staging_texture = FALSE;
925 struct r600_resource *buf;
926 unsigned offset = 0;
927 char *map;
928
929 /* We cannot map a tiled texture directly because the data is
930 * in a different order, therefore we do detiling using a blit.
931 *
932 * Also, use a temporary in GTT memory for read transfers, as
933 * the CPU is much happier reading out of cached system memory
934 * than uncached VRAM.
935 */
936 if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D)
937 use_staging_texture = TRUE;
938
939 /* Untiled buffers in VRAM, which is slow for CPU reads and writes */
940 if (!(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
941 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
942 use_staging_texture = TRUE;
943 }
944
945 /* Use a staging texture for uploads if the underlying BO is busy. */
946 if (!(usage & PIPE_TRANSFER_READ) &&
947 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
948 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
949 use_staging_texture = TRUE;
950 }
951
952 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
953 use_staging_texture = FALSE;
954 }
955
956 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
957 return NULL;
958 }
959
960 trans = CALLOC_STRUCT(r600_transfer);
961 if (trans == NULL)
962 return NULL;
963 trans->transfer.resource = texture;
964 trans->transfer.level = level;
965 trans->transfer.usage = usage;
966 trans->transfer.box = *box;
967
968 if (rtex->is_depth) {
969 struct r600_texture *staging_depth;
970
971 if (rtex->resource.b.b.nr_samples > 1) {
972 /* MSAA depth buffers need to be converted to single sample buffers.
973 *
974 * Mapping MSAA depth buffers can occur if ReadPixels is called
975 * with a multisample GLX visual.
976 *
977 * First downsample the depth buffer to a temporary texture,
978 * then decompress the temporary one to staging.
979 *
980 * Only the region being mapped is transfered.
981 */
982 struct pipe_resource resource;
983
984 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
985
986 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
987 R600_ERR("failed to create temporary texture to hold untiled copy\n");
988 FREE(trans);
989 return NULL;
990 }
991
992 if (usage & PIPE_TRANSFER_READ) {
993 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
994
995 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
996 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
997 0, 0, 0, box->depth, 0, 0);
998 pipe_resource_reference((struct pipe_resource**)&temp, NULL);
999 }
1000 }
1001 else {
1002 /* XXX: only readback the rectangle which is being mapped? */
1003 /* XXX: when discard is true, no need to read back from depth texture */
1004 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1005 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1006 FREE(trans);
1007 return NULL;
1008 }
1009
1010 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1011 level, level,
1012 box->z, box->z + box->depth - 1,
1013 0, 0);
1014
1015 offset = r600_texture_get_offset(staging_depth, level, box);
1016 }
1017
1018 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1019 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1020 trans->staging = (struct r600_resource*)staging_depth;
1021 } else if (use_staging_texture) {
1022 struct pipe_resource resource;
1023 struct r600_texture *staging;
1024
1025 r600_init_temp_resource_from_box(&resource, texture, box, level,
1026 R600_RESOURCE_FLAG_TRANSFER);
1027
1028 /* Create the temporary texture. */
1029 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1030 if (staging == NULL) {
1031 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1032 FREE(trans);
1033 return NULL;
1034 }
1035 trans->staging = &staging->resource;
1036 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1037 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1038 if (usage & PIPE_TRANSFER_READ) {
1039 r600_copy_to_staging_texture(ctx, trans);
1040 }
1041 } else {
1042 /* the resource is mapped directly */
1043 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1044 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1045 offset = r600_texture_get_offset(rtex, level, box);
1046 }
1047
1048 if (trans->staging) {
1049 buf = trans->staging;
1050 } else {
1051 buf = &rtex->resource;
1052 }
1053
1054 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1055 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1056 FREE(trans);
1057 return NULL;
1058 }
1059
1060 *ptransfer = &trans->transfer;
1061 return map + offset;
1062 }
1063
1064 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1065 struct pipe_transfer* transfer)
1066 {
1067 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1068 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1069 struct radeon_winsys_cs_handle *buf;
1070 struct pipe_resource *texture = transfer->resource;
1071 struct r600_texture *rtex = (struct r600_texture*)texture;
1072
1073 if (rtransfer->staging) {
1074 buf = rtransfer->staging->cs_buf;
1075 } else {
1076 buf = r600_resource(transfer->resource)->cs_buf;
1077 }
1078 rctx->ws->buffer_unmap(buf);
1079
1080 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1081 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1082 ctx->resource_copy_region(ctx, texture, transfer->level,
1083 transfer->box.x, transfer->box.y, transfer->box.z,
1084 &rtransfer->staging->b.b, transfer->level,
1085 &transfer->box);
1086 } else {
1087 r600_copy_from_staging_texture(ctx, rtransfer);
1088 }
1089 }
1090
1091 if (rtransfer->staging)
1092 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1093
1094 FREE(transfer);
1095 }
1096
1097 static const struct u_resource_vtbl r600_texture_vtbl =
1098 {
1099 NULL, /* get_handle */
1100 r600_texture_destroy, /* resource_destroy */
1101 r600_texture_transfer_map, /* transfer_map */
1102 NULL, /* transfer_flush_region */
1103 r600_texture_transfer_unmap, /* transfer_unmap */
1104 NULL /* transfer_inline_write */
1105 };
1106
1107 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1108 struct pipe_resource *texture,
1109 const struct pipe_surface *templ,
1110 unsigned width, unsigned height)
1111 {
1112 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1113
1114 if (surface == NULL)
1115 return NULL;
1116
1117 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1118 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1119
1120 pipe_reference_init(&surface->base.reference, 1);
1121 pipe_resource_reference(&surface->base.texture, texture);
1122 surface->base.context = pipe;
1123 surface->base.format = templ->format;
1124 surface->base.width = width;
1125 surface->base.height = height;
1126 surface->base.u = templ->u;
1127 return &surface->base;
1128 }
1129
1130 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1131 struct pipe_resource *tex,
1132 const struct pipe_surface *templ)
1133 {
1134 unsigned level = templ->u.tex.level;
1135
1136 return r600_create_surface_custom(pipe, tex, templ,
1137 u_minify(tex->width0, level),
1138 u_minify(tex->height0, level));
1139 }
1140
1141 static void r600_surface_destroy(struct pipe_context *pipe,
1142 struct pipe_surface *surface)
1143 {
1144 struct r600_surface *surf = (struct r600_surface*)surface;
1145 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1146 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1147 pipe_resource_reference(&surface->texture, NULL);
1148 FREE(surface);
1149 }
1150
1151 unsigned r600_translate_colorswap(enum pipe_format format)
1152 {
1153 const struct util_format_description *desc = util_format_description(format);
1154
1155 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1156
1157 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1158 return V_0280A0_SWAP_STD;
1159
1160 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1161 return ~0U;
1162
1163 switch (desc->nr_channels) {
1164 case 1:
1165 if (HAS_SWIZZLE(0,X))
1166 return V_0280A0_SWAP_STD; /* X___ */
1167 else if (HAS_SWIZZLE(3,X))
1168 return V_0280A0_SWAP_ALT_REV; /* ___X */
1169 break;
1170 case 2:
1171 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1172 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1173 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1174 return V_0280A0_SWAP_STD; /* XY__ */
1175 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1176 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1177 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1178 return V_0280A0_SWAP_STD_REV; /* YX__ */
1179 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1180 return V_0280A0_SWAP_ALT; /* X__Y */
1181 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1182 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1183 break;
1184 case 3:
1185 if (HAS_SWIZZLE(0,X))
1186 return V_0280A0_SWAP_STD; /* XYZ */
1187 else if (HAS_SWIZZLE(0,Z))
1188 return V_0280A0_SWAP_STD_REV; /* ZYX */
1189 break;
1190 case 4:
1191 /* check the middle channels, the 1st and 4th channel can be NONE */
1192 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1193 return V_0280A0_SWAP_STD; /* XYZW */
1194 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1195 return V_0280A0_SWAP_STD_REV; /* WZYX */
1196 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1197 return V_0280A0_SWAP_ALT; /* ZYXW */
1198 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
1199 return V_0280A0_SWAP_ALT_REV; /* WXYZ */
1200 break;
1201 }
1202 return ~0U;
1203 }
1204
1205 static void evergreen_set_clear_color(struct r600_texture *rtex,
1206 enum pipe_format surface_format,
1207 const union pipe_color_union *color)
1208 {
1209 union util_color uc;
1210
1211 memset(&uc, 0, sizeof(uc));
1212
1213 if (util_format_is_pure_uint(surface_format)) {
1214 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1215 } else if (util_format_is_pure_sint(surface_format)) {
1216 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1217 } else {
1218 util_pack_color(color->f, surface_format, &uc);
1219 }
1220
1221 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1222 }
1223
1224 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1225 struct pipe_framebuffer_state *fb,
1226 struct r600_atom *fb_state,
1227 unsigned *buffers,
1228 const union pipe_color_union *color)
1229 {
1230 int i;
1231
1232 for (i = 0; i < fb->nr_cbufs; i++) {
1233 struct r600_texture *tex;
1234 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1235
1236 if (!fb->cbufs[i])
1237 continue;
1238
1239 /* if this colorbuffer is not being cleared */
1240 if (!(*buffers & clear_bit))
1241 continue;
1242
1243 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1244
1245 /* 128-bit formats are unusupported */
1246 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1247 continue;
1248 }
1249
1250 /* the clear is allowed if all layers are bound */
1251 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1252 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1253 continue;
1254 }
1255
1256 /* cannot clear mipmapped textures */
1257 if (fb->cbufs[i]->texture->last_level != 0) {
1258 continue;
1259 }
1260
1261 /* only supported on tiled surfaces */
1262 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1263 continue;
1264 }
1265
1266 /* ensure CMASK is enabled */
1267 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1268 if (tex->cmask.size == 0) {
1269 continue;
1270 }
1271
1272 /* Do the fast clear. */
1273 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1274 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1275 tex->cmask.offset, tex->cmask.size, 0);
1276
1277 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1278 fb_state->dirty = true;
1279 *buffers &= ~clear_bit;
1280 }
1281 }
1282
1283 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1284 {
1285 rscreen->b.resource_from_handle = r600_texture_from_handle;
1286 rscreen->b.resource_get_handle = r600_texture_get_handle;
1287 }
1288
1289 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1290 {
1291 rctx->b.create_surface = r600_create_surface;
1292 rctx->b.surface_destroy = r600_surface_destroy;
1293 }