2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "os/os_time.h"
38 #include "state_tracker/drm_driver.h"
40 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
41 struct r600_texture
*rtex
);
42 static enum radeon_surf_mode
43 r600_choose_tiling(struct r600_common_screen
*rscreen
,
44 const struct pipe_resource
*templ
);
47 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
48 struct r600_texture
*rdst
,
49 unsigned dst_level
, unsigned dstx
,
50 unsigned dsty
, unsigned dstz
,
51 struct r600_texture
*rsrc
,
53 const struct pipe_box
*src_box
)
58 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
61 /* MSAA: Blits don't exist in the real world. */
62 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
63 rdst
->resource
.b
.b
.nr_samples
> 1)
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
70 if (rsrc
->is_depth
|| rdst
->is_depth
)
74 * src: Use the 3D path. DCC decompression is expensive.
75 * dst: Use the 3D path to compress the pixels with DCC.
77 if (vi_dcc_enabled(rsrc
, src_level
) ||
78 vi_dcc_enabled(rdst
, dst_level
))
82 * src: Both texture and SDMA paths need decompression. Use SDMA.
83 * dst: If overwriting the whole texture, discard CMASK and use
84 * SDMA. Otherwise, use the 3D path.
86 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
87 /* The CMASK clear is only enabled for the first level. */
88 assert(dst_level
== 0);
89 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
90 dstx
, dsty
, dstz
, src_box
->width
,
91 src_box
->height
, src_box
->depth
))
94 r600_texture_discard_cmask(rctx
->screen
, rdst
);
97 /* All requirements are met. Prepare textures for SDMA. */
98 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
99 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
101 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
102 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
107 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
108 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
109 struct pipe_resource
*dst
,
111 unsigned dstx
, unsigned dsty
, unsigned dstz
,
112 struct pipe_resource
*src
,
114 const struct pipe_box
*src_box
)
116 struct pipe_blit_info blit
;
118 memset(&blit
, 0, sizeof(blit
));
119 blit
.src
.resource
= src
;
120 blit
.src
.format
= src
->format
;
121 blit
.src
.level
= src_level
;
122 blit
.src
.box
= *src_box
;
123 blit
.dst
.resource
= dst
;
124 blit
.dst
.format
= dst
->format
;
125 blit
.dst
.level
= dst_level
;
126 blit
.dst
.box
.x
= dstx
;
127 blit
.dst
.box
.y
= dsty
;
128 blit
.dst
.box
.z
= dstz
;
129 blit
.dst
.box
.width
= src_box
->width
;
130 blit
.dst
.box
.height
= src_box
->height
;
131 blit
.dst
.box
.depth
= src_box
->depth
;
132 blit
.mask
= util_format_get_mask(src
->format
) &
133 util_format_get_mask(dst
->format
);
134 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
137 pipe
->blit(pipe
, &blit
);
141 /* Copy from a full GPU texture to a transfer's staging one. */
142 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
144 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
145 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
146 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
147 struct pipe_resource
*src
= transfer
->resource
;
149 if (src
->nr_samples
> 1) {
150 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
151 src
, transfer
->level
, &transfer
->box
);
155 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
159 /* Copy from a transfer's staging texture to a full GPU one. */
160 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
162 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
163 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
164 struct pipe_resource
*dst
= transfer
->resource
;
165 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
166 struct pipe_box sbox
;
168 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
170 if (dst
->nr_samples
> 1) {
171 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
172 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
177 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
178 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
182 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
183 struct r600_texture
*rtex
, unsigned level
,
184 const struct pipe_box
*box
,
186 unsigned *layer_stride
)
188 if (rscreen
->chip_class
>= GFX9
) {
189 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
190 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
195 /* Each texture is an array of slices. Each slice is an array
196 * of mipmap levels. */
197 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
198 rtex
->surface
.u
.gfx9
.offset
[level
] +
199 (box
->y
/ rtex
->surface
.blk_h
*
200 rtex
->surface
.u
.gfx9
.surf_pitch
+
201 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
203 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
205 *layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
208 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
214 (box
->y
/ rtex
->surface
.blk_h
*
215 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
220 static int r600_init_surface(struct r600_common_screen
*rscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 enum radeon_surf_mode array_mode
,
224 unsigned pitch_in_bytes_override
,
228 bool is_flushed_depth
,
229 bool tc_compatible_htile
)
231 const struct util_format_description
*desc
=
232 util_format_description(ptex
->format
);
233 bool is_depth
, is_stencil
;
235 unsigned i
, bpe
, flags
= 0;
237 is_depth
= util_format_has_depth(desc
);
238 is_stencil
= util_format_has_stencil(desc
);
240 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
241 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
242 bpe
= 4; /* stencil is allocated separately on evergreen */
244 bpe
= util_format_get_blocksize(ptex
->format
);
245 assert(util_is_power_of_two(bpe
));
248 if (!is_flushed_depth
&& is_depth
) {
249 flags
|= RADEON_SURF_ZBUFFER
;
251 if (tc_compatible_htile
&&
252 (rscreen
->chip_class
>= GFX9
||
253 array_mode
== RADEON_SURF_MODE_2D
)) {
254 /* TC-compatible HTILE only supports Z32_FLOAT.
255 * GFX9 also supports Z16_UNORM.
256 * On VI, promote Z16 to Z32. DB->CB copies will convert
257 * the format for transfers.
259 if (rscreen
->chip_class
== VI
)
262 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
266 flags
|= RADEON_SURF_SBUFFER
;
269 if (rscreen
->chip_class
>= VI
&&
270 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
271 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
272 flags
|= RADEON_SURF_DISABLE_DCC
;
274 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
275 /* This should catch bugs in gallium users setting incorrect flags. */
276 assert(ptex
->nr_samples
<= 1 &&
277 ptex
->array_size
== 1 &&
279 ptex
->last_level
== 0 &&
280 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
282 flags
|= RADEON_SURF_SCANOUT
;
285 if (ptex
->bind
& PIPE_BIND_SHARED
)
286 flags
|= RADEON_SURF_SHAREABLE
;
288 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
289 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
290 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
292 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
293 array_mode
, surface
);
298 if (rscreen
->chip_class
>= GFX9
) {
299 assert(!pitch_in_bytes_override
||
300 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
301 surface
->u
.gfx9
.surf_offset
= offset
;
303 if (pitch_in_bytes_override
&&
304 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
305 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
308 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
309 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
*
310 surface
->u
.legacy
.level
[0].nblk_y
;
314 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
315 surface
->u
.legacy
.level
[i
].offset
+= offset
;
321 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
322 struct r600_texture
*rtex
,
323 struct radeon_bo_metadata
*metadata
)
325 struct radeon_surf
*surface
= &rtex
->surface
;
327 memset(metadata
, 0, sizeof(*metadata
));
329 if (rscreen
->chip_class
>= GFX9
) {
330 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
332 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
333 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
334 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
335 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
336 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
337 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
338 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
339 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
340 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
341 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
342 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
343 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
347 static void r600_surface_import_metadata(struct r600_common_screen
*rscreen
,
348 struct radeon_surf
*surf
,
349 struct radeon_bo_metadata
*metadata
,
350 enum radeon_surf_mode
*array_mode
,
353 if (rscreen
->chip_class
>= GFX9
) {
354 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
355 *array_mode
= RADEON_SURF_MODE_2D
;
357 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
359 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
360 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
362 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
364 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
365 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
366 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
367 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
368 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
369 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
371 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
372 *array_mode
= RADEON_SURF_MODE_2D
;
373 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
374 *array_mode
= RADEON_SURF_MODE_1D
;
376 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
378 *is_scanout
= metadata
->u
.legacy
.scanout
;
382 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
383 struct r600_texture
*rtex
)
385 struct r600_common_screen
*rscreen
= rctx
->screen
;
386 struct pipe_context
*ctx
= &rctx
->b
;
388 if (ctx
== rscreen
->aux_context
)
389 mtx_lock(&rscreen
->aux_context_lock
);
391 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
392 ctx
->flush(ctx
, NULL
, 0);
394 if (ctx
== rscreen
->aux_context
)
395 mtx_unlock(&rscreen
->aux_context_lock
);
398 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
399 struct r600_texture
*rtex
)
401 if (!rtex
->cmask
.size
)
404 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
407 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
408 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
409 rtex
->dirty_level_mask
= 0;
411 if (rscreen
->chip_class
>= SI
)
412 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
414 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
416 if (rtex
->cmask_buffer
!= &rtex
->resource
)
417 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
419 /* Notify all contexts about the change. */
420 p_atomic_inc(&rscreen
->dirty_tex_counter
);
421 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
424 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
426 /* We can't disable DCC if it can be written by another process. */
427 return rtex
->dcc_offset
&&
428 (!rtex
->resource
.b
.is_shared
||
429 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
432 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
433 struct r600_texture
*rtex
)
435 if (!r600_can_disable_dcc(rtex
))
438 assert(rtex
->dcc_separate_buffer
== NULL
);
441 rtex
->dcc_offset
= 0;
443 /* Notify all contexts about the change. */
444 p_atomic_inc(&rscreen
->dirty_tex_counter
);
449 * Disable DCC for the texture. (first decompress, then discard metadata).
451 * There is unresolved multi-context synchronization issue between
452 * screen::aux_context and the current context. If applications do this with
453 * multiple contexts, it's already undefined behavior for them and we don't
454 * have to worry about that. The scenario is:
456 * If context 1 disables DCC and context 2 has queued commands that write
457 * to the texture via CB with DCC enabled, and the order of operations is
459 * context 2 queues draw calls rendering to the texture, but doesn't flush
460 * context 1 disables DCC and flushes
461 * context 1 & 2 reset descriptors and FB state
462 * context 2 flushes (new compressed tiles written by the draw calls)
463 * context 1 & 2 read garbage, because DCC is disabled, yet there are
466 * \param rctx the current context if you have one, or rscreen->aux_context
469 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
470 struct r600_texture
*rtex
)
472 struct r600_common_screen
*rscreen
= rctx
->screen
;
474 if (!r600_can_disable_dcc(rtex
))
477 if (&rctx
->b
== rscreen
->aux_context
)
478 mtx_lock(&rscreen
->aux_context_lock
);
480 /* Decompress DCC. */
481 rctx
->decompress_dcc(&rctx
->b
, rtex
);
482 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
484 if (&rctx
->b
== rscreen
->aux_context
)
485 mtx_unlock(&rscreen
->aux_context_lock
);
487 return r600_texture_discard_dcc(rscreen
, rtex
);
490 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
491 struct r600_texture
*rtex
,
492 unsigned new_bind_flag
,
493 bool invalidate_storage
)
495 struct pipe_screen
*screen
= rctx
->b
.screen
;
496 struct r600_texture
*new_tex
;
497 struct pipe_resource templ
= rtex
->resource
.b
.b
;
500 templ
.bind
|= new_bind_flag
;
502 /* r600g doesn't react to dirty_tex_descriptor_counter */
503 if (rctx
->chip_class
< SI
)
506 if (rtex
->resource
.b
.is_shared
)
509 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
510 if (rtex
->surface
.is_linear
)
513 /* This fails with MSAA, depth, and compressed textures. */
514 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
515 RADEON_SURF_MODE_LINEAR_ALIGNED
)
519 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
523 /* Copy the pixels to the new texture. */
524 if (!invalidate_storage
) {
525 for (i
= 0; i
<= templ
.last_level
; i
++) {
529 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
530 util_max_layer(&templ
, i
) + 1, &box
);
532 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
533 &rtex
->resource
.b
.b
, i
, &box
);
537 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
538 r600_texture_discard_cmask(rctx
->screen
, rtex
);
539 r600_texture_discard_dcc(rctx
->screen
, rtex
);
542 /* Replace the structure fields of rtex. */
543 rtex
->resource
.b
.b
.bind
= templ
.bind
;
544 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
545 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
546 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
547 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
548 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
549 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
550 rtex
->resource
.domains
= new_tex
->resource
.domains
;
551 rtex
->resource
.flags
= new_tex
->resource
.flags
;
552 rtex
->size
= new_tex
->size
;
553 rtex
->db_render_format
= new_tex
->db_render_format
;
554 rtex
->db_compatible
= new_tex
->db_compatible
;
555 rtex
->can_sample_z
= new_tex
->can_sample_z
;
556 rtex
->can_sample_s
= new_tex
->can_sample_s
;
557 rtex
->surface
= new_tex
->surface
;
558 rtex
->fmask
= new_tex
->fmask
;
559 rtex
->cmask
= new_tex
->cmask
;
560 rtex
->cb_color_info
= new_tex
->cb_color_info
;
561 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
562 rtex
->htile_offset
= new_tex
->htile_offset
;
563 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
564 rtex
->depth_cleared
= new_tex
->depth_cleared
;
565 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
566 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
567 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
568 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
570 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
571 assert(!rtex
->htile_offset
);
572 assert(!rtex
->cmask
.size
);
573 assert(!rtex
->fmask
.size
);
574 assert(!rtex
->dcc_offset
);
575 assert(!rtex
->is_depth
);
578 r600_texture_reference(&new_tex
, NULL
);
580 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
583 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
584 struct pipe_context
*ctx
,
585 struct pipe_resource
*resource
,
586 struct winsys_handle
*whandle
,
589 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
590 struct r600_common_context
*rctx
;
591 struct r600_resource
*res
= (struct r600_resource
*)resource
;
592 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
593 struct radeon_bo_metadata metadata
;
594 bool update_metadata
= false;
595 unsigned stride
, offset
, slice_size
;
597 ctx
= threaded_context_unwrap_sync(ctx
);
598 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
600 if (resource
->target
!= PIPE_BUFFER
) {
601 /* This is not supported now, but it might be required for OpenCL
602 * interop in the future.
604 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
607 /* Move a suballocated texture into a non-suballocated allocation. */
608 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
609 rtex
->surface
.tile_swizzle
||
610 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
611 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
612 assert(!res
->b
.is_shared
);
613 r600_reallocate_texture_inplace(rctx
, rtex
,
614 PIPE_BIND_SHARED
, false);
615 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
616 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
617 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
618 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
619 assert(rtex
->surface
.tile_swizzle
== 0);
622 /* Since shader image stores don't support DCC on VI,
623 * disable it for external clients that want write
626 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
627 if (r600_texture_disable_dcc(rctx
, rtex
))
628 update_metadata
= true;
631 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
632 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
633 /* Eliminate fast clear (both CMASK and DCC) */
634 r600_eliminate_fast_color_clear(rctx
, rtex
);
636 /* Disable CMASK if flush_resource isn't going
639 if (rtex
->cmask
.size
)
640 r600_texture_discard_cmask(rscreen
, rtex
);
644 if (!res
->b
.is_shared
|| update_metadata
) {
645 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
646 if (rscreen
->query_opaque_metadata
)
647 rscreen
->query_opaque_metadata(rscreen
, rtex
,
650 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
653 if (rscreen
->chip_class
>= GFX9
) {
654 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
655 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
657 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
659 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
660 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
662 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
665 /* Move a suballocated buffer into a non-suballocated allocation. */
666 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
667 assert(!res
->b
.is_shared
);
669 /* Allocate a new buffer with PIPE_BIND_SHARED. */
670 struct pipe_resource templ
= res
->b
.b
;
671 templ
.bind
|= PIPE_BIND_SHARED
;
673 struct pipe_resource
*newb
=
674 screen
->resource_create(screen
, &templ
);
678 /* Copy the old buffer contents to the new one. */
680 u_box_1d(0, newb
->width0
, &box
);
681 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
683 /* Move the new buffer storage to the old pipe_resource. */
684 r600_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
685 pipe_resource_reference(&newb
, NULL
);
687 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
688 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
697 if (res
->b
.is_shared
) {
698 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
701 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
702 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
703 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
705 res
->b
.is_shared
= true;
706 res
->external_usage
= usage
;
709 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
710 slice_size
, whandle
);
713 static void r600_texture_destroy(struct pipe_screen
*screen
,
714 struct pipe_resource
*ptex
)
716 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
717 struct r600_resource
*resource
= &rtex
->resource
;
719 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
721 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
722 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
724 pb_reference(&resource
->buf
, NULL
);
725 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
726 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
730 static const struct u_resource_vtbl r600_texture_vtbl
;
732 /* The number of samples can be specified independently of the texture. */
733 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
734 struct r600_texture
*rtex
,
736 struct r600_fmask_info
*out
)
738 /* FMASK is allocated like an ordinary texture. */
739 struct pipe_resource templ
= rtex
->resource
.b
.b
;
740 struct radeon_surf fmask
= {};
743 memset(out
, 0, sizeof(*out
));
745 if (rscreen
->chip_class
>= GFX9
) {
746 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
747 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
751 templ
.nr_samples
= 1;
752 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
754 if (rscreen
->chip_class
<= CAYMAN
) {
755 /* Use the same parameters and tile mode. */
756 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
757 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
758 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
759 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
762 fmask
.u
.legacy
.bankh
= 4;
765 switch (nr_samples
) {
774 R600_ERR("Invalid sample count for FMASK allocation.\n");
778 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
779 * This can be fixed by writing a separate FMASK allocator specifically
780 * for R600-R700 asics. */
781 if (rscreen
->chip_class
<= R700
) {
785 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
786 RADEON_SURF_MODE_2D
, &fmask
)) {
787 R600_ERR("Got error in surface_init while allocating FMASK.\n");
791 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
793 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
794 if (out
->slice_tile_max
)
795 out
->slice_tile_max
-= 1;
797 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
798 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
799 out
->bank_height
= fmask
.u
.legacy
.bankh
;
800 out
->tile_swizzle
= fmask
.tile_swizzle
;
801 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
802 out
->size
= fmask
.surf_size
;
805 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
806 struct r600_texture
*rtex
)
808 r600_texture_get_fmask_info(rscreen
, rtex
,
809 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
811 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
812 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
815 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
816 struct r600_texture
*rtex
,
817 struct r600_cmask_info
*out
)
819 unsigned cmask_tile_width
= 8;
820 unsigned cmask_tile_height
= 8;
821 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
822 unsigned element_bits
= 4;
823 unsigned cmask_cache_bits
= 1024;
824 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
825 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
827 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
828 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
829 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
830 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
831 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
833 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
834 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
836 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
837 unsigned slice_bytes
=
838 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
840 assert(macro_tile_width
% 128 == 0);
841 assert(macro_tile_height
% 128 == 0);
843 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
844 out
->alignment
= MAX2(256, base_align
);
845 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
846 align(slice_bytes
, base_align
);
849 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
850 struct r600_texture
*rtex
,
851 struct r600_cmask_info
*out
)
853 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
854 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
855 unsigned cl_width
, cl_height
;
857 if (rscreen
->chip_class
>= GFX9
) {
858 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
859 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
876 case 16: /* Hawaii */
885 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
887 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
888 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
889 unsigned slice_elements
= (width
* height
) / (8*8);
891 /* Each element of CMASK is a nibble. */
892 unsigned slice_bytes
= slice_elements
/ 2;
894 out
->slice_tile_max
= (width
* height
) / (128*128);
895 if (out
->slice_tile_max
)
896 out
->slice_tile_max
-= 1;
898 out
->alignment
= MAX2(256, base_align
);
899 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
900 align(slice_bytes
, base_align
);
903 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
904 struct r600_texture
*rtex
)
906 if (rscreen
->chip_class
>= SI
) {
907 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
909 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
912 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
913 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
915 if (rscreen
->chip_class
>= SI
)
916 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
918 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
921 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
922 struct r600_texture
*rtex
)
924 if (rtex
->cmask_buffer
)
927 assert(rtex
->cmask
.size
== 0);
929 if (rscreen
->chip_class
>= SI
) {
930 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
932 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
935 rtex
->cmask_buffer
= (struct r600_resource
*)
936 r600_aligned_buffer_create(&rscreen
->b
,
937 R600_RESOURCE_FLAG_UNMAPPABLE
,
940 rtex
->cmask
.alignment
);
941 if (rtex
->cmask_buffer
== NULL
) {
942 rtex
->cmask
.size
= 0;
946 /* update colorbuffer state bits */
947 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
949 if (rscreen
->chip_class
>= SI
)
950 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
952 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
954 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
957 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
958 struct r600_texture
*rtex
)
960 unsigned cl_width
, cl_height
, width
, height
;
961 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
962 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
964 assert(rscreen
->chip_class
<= VI
);
966 rtex
->surface
.htile_size
= 0;
968 if (rscreen
->chip_class
<= EVERGREEN
&&
969 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
972 /* HW bug on R6xx. */
973 if (rscreen
->chip_class
== R600
&&
974 (rtex
->resource
.b
.b
.width0
> 7680 ||
975 rtex
->resource
.b
.b
.height0
> 7680))
978 /* HTILE is broken with 1D tiling on old kernels and CIK. */
979 if (rscreen
->chip_class
>= CIK
&&
980 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
981 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
984 /* Overalign HTILE on P2 configs to work around GPU hangs in
985 * piglit/depthstencil-render-miplevels 585.
987 * This has been confirmed to help Kabini & Stoney, where the hangs
988 * are always reproducible. I think I have seen the test hang
989 * on Carrizo too, though it was very rare there.
991 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
1020 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
1021 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
1023 slice_elements
= (width
* height
) / (8 * 8);
1024 slice_bytes
= slice_elements
* 4;
1026 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
1027 base_align
= num_pipes
* pipe_interleave_bytes
;
1029 rtex
->surface
.htile_alignment
= base_align
;
1030 rtex
->surface
.htile_size
=
1031 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
1032 align(slice_bytes
, base_align
);
1035 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
1036 struct r600_texture
*rtex
)
1038 if (rscreen
->chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
1039 r600_texture_get_htile_size(rscreen
, rtex
);
1041 if (!rtex
->surface
.htile_size
)
1044 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
1045 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
1048 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
1049 struct r600_texture
*rtex
, struct u_log_context
*log
)
1053 /* Common parameters. */
1054 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1055 "blk_h=%u, array_size=%u, last_level=%u, "
1056 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1057 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
1058 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1059 rtex
->surface
.blk_h
,
1060 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
1061 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
1062 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
1064 if (rscreen
->chip_class
>= GFX9
) {
1065 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1066 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1067 rtex
->surface
.surf_size
,
1068 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1069 rtex
->surface
.surf_alignment
,
1070 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1071 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1072 rtex
->surface
.u
.gfx9
.surf_pitch
);
1074 if (rtex
->fmask
.size
) {
1075 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1076 "alignment=%u, swmode=%u, epitch=%u\n",
1078 rtex
->surface
.u
.gfx9
.fmask_size
,
1079 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1080 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1081 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1084 if (rtex
->cmask
.size
) {
1085 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1086 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1088 rtex
->surface
.u
.gfx9
.cmask_size
,
1089 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1090 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1091 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1094 if (rtex
->htile_offset
) {
1095 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1096 "rb_aligned=%u, pipe_aligned=%u\n",
1098 rtex
->surface
.htile_size
,
1099 rtex
->surface
.htile_alignment
,
1100 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1101 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1104 if (rtex
->dcc_offset
) {
1105 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
1106 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1107 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1108 rtex
->surface
.dcc_alignment
,
1109 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1110 rtex
->surface
.num_dcc_levels
);
1113 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1114 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1115 rtex
->surface
.u
.gfx9
.stencil_offset
,
1116 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1117 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1122 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1123 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1124 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1125 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1126 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1127 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1129 if (rtex
->fmask
.size
)
1130 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1131 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1132 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1133 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1134 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1136 if (rtex
->cmask
.size
)
1137 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1138 "slice_tile_max=%u\n",
1139 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1140 rtex
->cmask
.slice_tile_max
);
1142 if (rtex
->htile_offset
)
1143 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", "
1144 "alignment=%u, TC_compatible = %u\n",
1145 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1146 rtex
->surface
.htile_alignment
,
1147 rtex
->tc_compatible_htile
);
1149 if (rtex
->dcc_offset
) {
1150 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1151 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1152 rtex
->surface
.dcc_alignment
);
1153 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1154 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1155 "fast_clear_size=%"PRIu64
"\n",
1156 i
, i
< rtex
->surface
.num_dcc_levels
,
1157 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1158 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1161 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1162 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1163 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1164 "mode=%u, tiling_index = %u\n",
1165 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1166 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1167 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1168 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1169 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1170 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1171 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1172 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1173 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1175 if (rtex
->surface
.has_stencil
) {
1176 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1177 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1178 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1179 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1180 "slice_size=%"PRIu64
", npix_x=%u, "
1181 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1182 "mode=%u, tiling_index = %u\n",
1183 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1184 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1185 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1186 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1187 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1188 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1189 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1190 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1191 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1196 /* Common processing for r600_texture_create and r600_texture_from_handle */
1197 static struct r600_texture
*
1198 r600_texture_create_object(struct pipe_screen
*screen
,
1199 const struct pipe_resource
*base
,
1200 struct pb_buffer
*buf
,
1201 struct radeon_surf
*surface
)
1203 struct r600_texture
*rtex
;
1204 struct r600_resource
*resource
;
1205 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1207 rtex
= CALLOC_STRUCT(r600_texture
);
1211 resource
= &rtex
->resource
;
1212 resource
->b
.b
= *base
;
1213 resource
->b
.b
.next
= NULL
;
1214 resource
->b
.vtbl
= &r600_texture_vtbl
;
1215 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1216 resource
->b
.b
.screen
= screen
;
1218 /* don't include stencil-only formats which we don't support for rendering */
1219 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1221 rtex
->surface
= *surface
;
1222 rtex
->size
= rtex
->surface
.surf_size
;
1224 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1225 (rtex
->surface
.flags
&
1226 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1228 /* TC-compatible HTILE:
1229 * - VI only supports Z32_FLOAT.
1230 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1231 if (rtex
->tc_compatible_htile
) {
1232 if (rscreen
->chip_class
>= GFX9
&&
1233 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1234 rtex
->db_render_format
= base
->format
;
1236 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1238 rtex
->db_render_format
= base
->format
;
1241 /* Tiled depth textures utilize the non-displayable tile order.
1242 * This must be done after r600_setup_surface.
1243 * Applies to R600-Cayman. */
1244 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1245 /* Applies to GCN. */
1246 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1248 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1249 * between frames, so the only thing that can enable separate DCC
1250 * with DRI2 is multiple slow clears within a frame.
1252 rtex
->ps_draw_ratio
= 0;
1254 if (rtex
->is_depth
) {
1255 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1256 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1257 rscreen
->chip_class
>= EVERGREEN
) {
1258 if (rscreen
->chip_class
>= GFX9
) {
1259 rtex
->can_sample_z
= true;
1260 rtex
->can_sample_s
= true;
1262 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1263 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1266 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1267 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1268 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1269 rtex
->can_sample_z
= true;
1272 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1273 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1274 rtex
->db_compatible
= true;
1276 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1277 r600_texture_allocate_htile(rscreen
, rtex
);
1280 if (base
->nr_samples
> 1) {
1282 r600_texture_allocate_fmask(rscreen
, rtex
);
1283 r600_texture_allocate_cmask(rscreen
, rtex
);
1284 rtex
->cmask_buffer
= &rtex
->resource
;
1286 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1292 /* Shared textures must always set up DCC here.
1293 * If it's not present, it will be disabled by
1294 * apply_opaque_metadata later.
1296 if (rtex
->surface
.dcc_size
&&
1297 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1298 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1299 /* Reserve space for the DCC buffer. */
1300 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1301 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1305 /* Now create the backing buffer. */
1307 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1308 rtex
->surface
.surf_alignment
);
1310 /* Displayable surfaces are not suballocated. */
1311 if (resource
->b
.b
.bind
& PIPE_BIND_SCANOUT
)
1312 resource
->flags
|= RADEON_FLAG_NO_SUBALLOC
;
1314 if (!r600_alloc_resource(rscreen
, resource
)) {
1319 resource
->buf
= buf
;
1320 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1321 resource
->bo_size
= buf
->size
;
1322 resource
->bo_alignment
= buf
->alignment
;
1323 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1324 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1325 resource
->vram_usage
= buf
->size
;
1326 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1327 resource
->gart_usage
= buf
->size
;
1330 if (rtex
->cmask
.size
) {
1331 /* Initialize the cmask to 0xCC (= compressed state). */
1332 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1333 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1336 if (rtex
->htile_offset
) {
1337 uint32_t clear_value
= 0;
1339 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1340 clear_value
= 0x0000030F;
1342 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1344 rtex
->surface
.htile_size
,
1348 /* Initialize DCC only if the texture is not being imported. */
1349 if (!buf
&& rtex
->dcc_offset
) {
1350 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1352 rtex
->surface
.dcc_size
,
1356 /* Initialize the CMASK base register value. */
1357 rtex
->cmask
.base_address_reg
=
1358 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1360 if (rscreen
->debug_flags
& DBG_VM
) {
1361 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1362 rtex
->resource
.gpu_address
,
1363 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1364 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1365 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1368 if (rscreen
->debug_flags
& DBG_TEX
) {
1370 struct u_log_context log
;
1371 u_log_context_init(&log
);
1372 r600_print_texture_info(rscreen
, rtex
, &log
);
1373 u_log_new_page_print(&log
, stdout
);
1375 u_log_context_destroy(&log
);
1381 static enum radeon_surf_mode
1382 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1383 const struct pipe_resource
*templ
)
1385 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1386 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1387 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1388 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1390 /* MSAA resources must be 2D tiled. */
1391 if (templ
->nr_samples
> 1)
1392 return RADEON_SURF_MODE_2D
;
1394 /* Transfer resources should be linear. */
1395 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1396 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1398 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1399 * which requires 2D tiling.
1401 if (rscreen
->chip_class
== VI
&&
1403 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1404 return RADEON_SURF_MODE_2D
;
1406 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1407 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1408 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1409 (templ
->target
== PIPE_TEXTURE_2D
||
1410 templ
->target
== PIPE_TEXTURE_3D
))
1411 force_tiling
= true;
1413 /* Handle common candidates for the linear mode.
1414 * Compressed textures and DB surfaces must always be tiled.
1416 if (!force_tiling
&&
1417 !is_depth_stencil
&&
1418 !util_format_is_compressed(templ
->format
)) {
1419 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1420 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1422 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1423 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1424 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1426 /* Cursors are linear on SI.
1427 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1428 if (rscreen
->chip_class
>= SI
&&
1429 (templ
->bind
& PIPE_BIND_CURSOR
))
1430 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1432 if (templ
->bind
& PIPE_BIND_LINEAR
)
1433 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1435 /* Textures with a very small height are recommended to be linear. */
1436 if (templ
->target
== PIPE_TEXTURE_1D
||
1437 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1438 /* Only very thin and long 2D textures should benefit from
1439 * linear_aligned. */
1440 (templ
->width0
> 8 && templ
->height0
<= 2))
1441 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1443 /* Textures likely to be mapped often. */
1444 if (templ
->usage
== PIPE_USAGE_STAGING
||
1445 templ
->usage
== PIPE_USAGE_STREAM
)
1446 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1449 /* Make small textures 1D tiled. */
1450 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1451 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1452 return RADEON_SURF_MODE_1D
;
1454 /* The allocator will switch to 1D if needed. */
1455 return RADEON_SURF_MODE_2D
;
1458 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1459 const struct pipe_resource
*templ
)
1461 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1462 struct radeon_surf surface
= {0};
1463 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1464 bool tc_compatible_htile
=
1465 rscreen
->chip_class
>= VI
&&
1466 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1467 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1468 !is_flushed_depth
&&
1469 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1470 util_format_is_depth_or_stencil(templ
->format
);
1474 r
= r600_init_surface(rscreen
, &surface
, templ
,
1475 r600_choose_tiling(rscreen
, templ
), 0, 0,
1476 false, false, is_flushed_depth
,
1477 tc_compatible_htile
);
1482 return (struct pipe_resource
*)
1483 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1486 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1487 const struct pipe_resource
*templ
,
1488 struct winsys_handle
*whandle
,
1491 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1492 struct pb_buffer
*buf
= NULL
;
1493 unsigned stride
= 0, offset
= 0;
1494 enum radeon_surf_mode array_mode
;
1495 struct radeon_surf surface
= {};
1497 struct radeon_bo_metadata metadata
= {};
1498 struct r600_texture
*rtex
;
1501 /* Support only 2D textures without mipmaps */
1502 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1503 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1506 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1510 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1511 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
1512 &array_mode
, &is_scanout
);
1514 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1515 offset
, true, is_scanout
, false, false);
1520 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1524 rtex
->resource
.b
.is_shared
= true;
1525 rtex
->resource
.external_usage
= usage
;
1527 if (rscreen
->apply_opaque_metadata
)
1528 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1530 assert(rtex
->surface
.tile_swizzle
== 0);
1531 return &rtex
->resource
.b
.b
;
1534 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1535 struct pipe_resource
*texture
,
1536 struct r600_texture
**staging
)
1538 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1539 struct pipe_resource resource
;
1540 struct r600_texture
**flushed_depth_texture
= staging
?
1541 staging
: &rtex
->flushed_depth_texture
;
1542 enum pipe_format pipe_format
= texture
->format
;
1545 if (rtex
->flushed_depth_texture
)
1546 return true; /* it's ready */
1548 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1549 switch (pipe_format
) {
1550 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1551 /* Save memory by not allocating the S plane. */
1552 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1554 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1555 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1556 /* Save memory bandwidth by not copying the
1557 * stencil part during flush.
1559 * This potentially increases memory bandwidth
1560 * if an application uses both Z and S texturing
1561 * simultaneously (a flushed Z24S8 texture
1562 * would be stored compactly), but how often
1563 * does that really happen?
1565 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1569 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1570 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1572 /* DB->CB copies to an 8bpp surface don't work. */
1573 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1577 memset(&resource
, 0, sizeof(resource
));
1578 resource
.target
= texture
->target
;
1579 resource
.format
= pipe_format
;
1580 resource
.width0
= texture
->width0
;
1581 resource
.height0
= texture
->height0
;
1582 resource
.depth0
= texture
->depth0
;
1583 resource
.array_size
= texture
->array_size
;
1584 resource
.last_level
= texture
->last_level
;
1585 resource
.nr_samples
= texture
->nr_samples
;
1586 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1587 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1588 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1591 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1593 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1594 if (*flushed_depth_texture
== NULL
) {
1595 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1599 (*flushed_depth_texture
)->non_disp_tiling
= false;
1604 * Initialize the pipe_resource descriptor to be of the same size as the box,
1605 * which is supposed to hold a subregion of the texture "orig" at the given
1608 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1609 struct pipe_resource
*orig
,
1610 const struct pipe_box
*box
,
1611 unsigned level
, unsigned flags
)
1613 memset(res
, 0, sizeof(*res
));
1614 res
->format
= orig
->format
;
1615 res
->width0
= box
->width
;
1616 res
->height0
= box
->height
;
1618 res
->array_size
= 1;
1619 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1622 /* We must set the correct texture target and dimensions for a 3D box. */
1623 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1624 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1625 res
->array_size
= box
->depth
;
1627 res
->target
= PIPE_TEXTURE_2D
;
1631 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1632 struct r600_texture
*rtex
,
1633 unsigned transfer_usage
,
1634 const struct pipe_box
*box
)
1636 /* r600g doesn't react to dirty_tex_descriptor_counter */
1637 return rscreen
->chip_class
>= SI
&&
1638 !rtex
->resource
.b
.is_shared
&&
1639 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1640 rtex
->resource
.b
.b
.last_level
== 0 &&
1641 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1642 box
->x
, box
->y
, box
->z
,
1643 box
->width
, box
->height
,
1647 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1648 struct r600_texture
*rtex
)
1650 struct r600_common_screen
*rscreen
= rctx
->screen
;
1652 /* There is no point in discarding depth and tiled buffers. */
1653 assert(!rtex
->is_depth
);
1654 assert(rtex
->surface
.is_linear
);
1656 /* Reallocate the buffer in the same pipe_resource. */
1657 r600_alloc_resource(rscreen
, &rtex
->resource
);
1659 /* Initialize the CMASK base address (needed even without CMASK). */
1660 rtex
->cmask
.base_address_reg
=
1661 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1663 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1665 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1668 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1669 struct pipe_resource
*texture
,
1672 const struct pipe_box
*box
,
1673 struct pipe_transfer
**ptransfer
)
1675 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1676 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1677 struct r600_transfer
*trans
;
1678 struct r600_resource
*buf
;
1679 unsigned offset
= 0;
1681 bool use_staging_texture
= false;
1683 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1684 assert(box
->width
&& box
->height
&& box
->depth
);
1686 /* Depth textures use staging unconditionally. */
1687 if (!rtex
->is_depth
) {
1688 /* Degrade the tile mode if we get too many transfers on APUs.
1689 * On dGPUs, the staging texture is always faster.
1690 * Only count uploads that are at least 4x4 pixels large.
1692 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1694 box
->width
>= 4 && box
->height
>= 4 &&
1695 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1696 bool can_invalidate
=
1697 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1700 r600_reallocate_texture_inplace(rctx
, rtex
,
1705 /* Tiled textures need to be converted into a linear texture for CPU
1706 * access. The staging texture is always linear and is placed in GART.
1708 * Reading from VRAM or GTT WC is slow, always use the staging
1709 * texture in this case.
1711 * Use the staging texture for uploads if the underlying BO
1714 if (!rtex
->surface
.is_linear
)
1715 use_staging_texture
= true;
1716 else if (usage
& PIPE_TRANSFER_READ
)
1717 use_staging_texture
=
1718 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1719 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1720 /* Write & linear only: */
1721 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1722 RADEON_USAGE_READWRITE
) ||
1723 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1724 RADEON_USAGE_READWRITE
)) {
1726 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1728 r600_texture_invalidate_storage(rctx
, rtex
);
1730 use_staging_texture
= true;
1734 trans
= CALLOC_STRUCT(r600_transfer
);
1737 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1738 trans
->b
.b
.level
= level
;
1739 trans
->b
.b
.usage
= usage
;
1740 trans
->b
.b
.box
= *box
;
1742 if (rtex
->is_depth
) {
1743 struct r600_texture
*staging_depth
;
1745 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1746 /* MSAA depth buffers need to be converted to single sample buffers.
1748 * Mapping MSAA depth buffers can occur if ReadPixels is called
1749 * with a multisample GLX visual.
1751 * First downsample the depth buffer to a temporary texture,
1752 * then decompress the temporary one to staging.
1754 * Only the region being mapped is transfered.
1756 struct pipe_resource resource
;
1758 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1760 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1761 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1766 if (usage
& PIPE_TRANSFER_READ
) {
1767 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1769 R600_ERR("failed to create a temporary depth texture\n");
1774 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1775 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1776 0, 0, 0, box
->depth
, 0, 0);
1777 pipe_resource_reference(&temp
, NULL
);
1780 /* Just get the strides. */
1781 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1783 &trans
->b
.b
.layer_stride
);
1785 /* XXX: only readback the rectangle which is being mapped? */
1786 /* XXX: when discard is true, no need to read back from depth texture */
1787 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1788 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1793 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1795 box
->z
, box
->z
+ box
->depth
- 1,
1798 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1801 &trans
->b
.b
.layer_stride
);
1804 trans
->staging
= (struct r600_resource
*)staging_depth
;
1805 buf
= trans
->staging
;
1806 } else if (use_staging_texture
) {
1807 struct pipe_resource resource
;
1808 struct r600_texture
*staging
;
1810 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1811 R600_RESOURCE_FLAG_TRANSFER
);
1812 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1813 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1815 /* Create the temporary texture. */
1816 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1818 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1822 trans
->staging
= &staging
->resource
;
1824 /* Just get the strides. */
1825 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1827 &trans
->b
.b
.layer_stride
);
1829 if (usage
& PIPE_TRANSFER_READ
)
1830 r600_copy_to_staging_texture(ctx
, trans
);
1832 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1834 buf
= trans
->staging
;
1836 /* the resource is mapped directly */
1837 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1839 &trans
->b
.b
.layer_stride
);
1840 buf
= &rtex
->resource
;
1843 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1844 r600_resource_reference(&trans
->staging
, NULL
);
1849 *ptransfer
= &trans
->b
.b
;
1850 return map
+ offset
;
1853 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1854 struct pipe_transfer
* transfer
)
1856 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1857 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1858 struct pipe_resource
*texture
= transfer
->resource
;
1859 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1861 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1862 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1863 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1864 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1865 &rtransfer
->staging
->b
.b
, transfer
->level
,
1868 r600_copy_from_staging_texture(ctx
, rtransfer
);
1872 if (rtransfer
->staging
) {
1873 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1874 r600_resource_reference(&rtransfer
->staging
, NULL
);
1877 /* Heuristic for {upload, draw, upload, draw, ..}:
1879 * Flush the gfx IB if we've allocated too much texture storage.
1881 * The idea is that we don't want to build IBs that use too much
1882 * memory and put pressure on the kernel memory manager and we also
1883 * want to make temporary and invalidated buffers go idle ASAP to
1884 * decrease the total memory usage or make them reusable. The memory
1885 * usage will be slightly higher than given here because of the buffer
1886 * cache in the winsys.
1888 * The result is that the kernel memory manager is never a bottleneck.
1890 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1891 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1892 rctx
->num_alloc_tex_transfer_bytes
= 0;
1895 pipe_resource_reference(&transfer
->resource
, NULL
);
1899 static const struct u_resource_vtbl r600_texture_vtbl
=
1901 NULL
, /* get_handle */
1902 r600_texture_destroy
, /* resource_destroy */
1903 r600_texture_transfer_map
, /* transfer_map */
1904 u_default_transfer_flush_region
, /* transfer_flush_region */
1905 r600_texture_transfer_unmap
, /* transfer_unmap */
1908 /* DCC channel type categories within which formats can be reinterpreted
1909 * while keeping the same DCC encoding. The swizzle must also match. */
1910 enum dcc_channel_type
{
1911 dcc_channel_float32
,
1914 dcc_channel_float16
,
1917 dcc_channel_uint_10_10_10_2
,
1920 dcc_channel_incompatible
,
1923 /* Return the type of DCC encoding. */
1924 static enum dcc_channel_type
1925 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1929 /* Find the first non-void channel. */
1930 for (i
= 0; i
< desc
->nr_channels
; i
++)
1931 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1933 if (i
== desc
->nr_channels
)
1934 return dcc_channel_incompatible
;
1936 switch (desc
->channel
[i
].size
) {
1938 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1939 return dcc_channel_float32
;
1940 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1941 return dcc_channel_uint32
;
1942 return dcc_channel_sint32
;
1944 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1945 return dcc_channel_float16
;
1946 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1947 return dcc_channel_uint16
;
1948 return dcc_channel_sint16
;
1950 return dcc_channel_uint_10_10_10_2
;
1952 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1953 return dcc_channel_uint8
;
1954 return dcc_channel_sint8
;
1956 return dcc_channel_incompatible
;
1960 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1961 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1962 enum pipe_format format2
)
1964 const struct util_format_description
*desc1
, *desc2
;
1965 enum dcc_channel_type type1
, type2
;
1968 if (format1
== format2
)
1971 desc1
= util_format_description(format1
);
1972 desc2
= util_format_description(format2
);
1974 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1977 /* Swizzles must be the same. */
1978 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1979 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1980 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1981 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1984 type1
= vi_get_dcc_channel_type(desc1
);
1985 type2
= vi_get_dcc_channel_type(desc2
);
1987 return type1
!= dcc_channel_incompatible
&&
1988 type2
!= dcc_channel_incompatible
&&
1992 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1994 enum pipe_format view_format
)
1996 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1998 return vi_dcc_enabled(rtex
, level
) &&
1999 !vi_dcc_formats_compatible(tex
->format
, view_format
);
2002 /* This can't be merged with the above function, because
2003 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2004 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
2005 struct pipe_resource
*tex
,
2007 enum pipe_format view_format
)
2009 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
2011 if (vi_dcc_enabled(rtex
, level
) &&
2012 !vi_dcc_formats_compatible(tex
->format
, view_format
))
2013 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
2014 rctx
->decompress_dcc(&rctx
->b
, rtex
);
2017 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
2018 struct pipe_resource
*texture
,
2019 const struct pipe_surface
*templ
,
2020 unsigned width0
, unsigned height0
,
2021 unsigned width
, unsigned height
)
2023 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
2028 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2029 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2031 pipe_reference_init(&surface
->base
.reference
, 1);
2032 pipe_resource_reference(&surface
->base
.texture
, texture
);
2033 surface
->base
.context
= pipe
;
2034 surface
->base
.format
= templ
->format
;
2035 surface
->base
.width
= width
;
2036 surface
->base
.height
= height
;
2037 surface
->base
.u
= templ
->u
;
2039 surface
->width0
= width0
;
2040 surface
->height0
= height0
;
2042 surface
->dcc_incompatible
=
2043 texture
->target
!= PIPE_BUFFER
&&
2044 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2046 return &surface
->base
;
2049 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
2050 struct pipe_resource
*tex
,
2051 const struct pipe_surface
*templ
)
2053 unsigned level
= templ
->u
.tex
.level
;
2054 unsigned width
= u_minify(tex
->width0
, level
);
2055 unsigned height
= u_minify(tex
->height0
, level
);
2056 unsigned width0
= tex
->width0
;
2057 unsigned height0
= tex
->height0
;
2059 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2060 const struct util_format_description
*tex_desc
2061 = util_format_description(tex
->format
);
2062 const struct util_format_description
*templ_desc
2063 = util_format_description(templ
->format
);
2065 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2067 /* Adjust size of surface if and only if the block width or
2068 * height is changed. */
2069 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2070 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2071 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2072 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2074 width
= nblks_x
* templ_desc
->block
.width
;
2075 height
= nblks_y
* templ_desc
->block
.height
;
2077 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2078 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2082 return r600_create_surface_custom(pipe
, tex
, templ
,
2087 static void r600_surface_destroy(struct pipe_context
*pipe
,
2088 struct pipe_surface
*surface
)
2090 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
2091 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
2092 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
2093 pipe_resource_reference(&surface
->texture
, NULL
);
2097 static void r600_clear_texture(struct pipe_context
*pipe
,
2098 struct pipe_resource
*tex
,
2100 const struct pipe_box
*box
,
2103 struct pipe_screen
*screen
= pipe
->screen
;
2104 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
2105 struct pipe_surface tmpl
= {{0}};
2106 struct pipe_surface
*sf
;
2107 const struct util_format_description
*desc
=
2108 util_format_description(tex
->format
);
2110 tmpl
.format
= tex
->format
;
2111 tmpl
.u
.tex
.first_layer
= box
->z
;
2112 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
2113 tmpl
.u
.tex
.level
= level
;
2114 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
2118 if (rtex
->is_depth
) {
2121 uint8_t stencil
= 0;
2123 /* Depth is always present. */
2124 clear
= PIPE_CLEAR_DEPTH
;
2125 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
2127 if (rtex
->surface
.has_stencil
) {
2128 clear
|= PIPE_CLEAR_STENCIL
;
2129 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
2132 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
2134 box
->width
, box
->height
, false);
2136 union pipe_color_union color
;
2138 /* pipe_color_union requires the full vec4 representation. */
2139 if (util_format_is_pure_uint(tex
->format
))
2140 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2141 else if (util_format_is_pure_sint(tex
->format
))
2142 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2144 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2146 if (screen
->is_format_supported(screen
, tex
->format
,
2148 PIPE_BIND_RENDER_TARGET
)) {
2149 pipe
->clear_render_target(pipe
, sf
, &color
,
2151 box
->width
, box
->height
, false);
2153 /* Software fallback - just for R9G9B9E5_FLOAT */
2154 util_clear_render_target(pipe
, sf
, &color
,
2156 box
->width
, box
->height
);
2159 pipe_surface_reference(&sf
, NULL
);
2162 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2164 const struct util_format_description
*desc
= util_format_description(format
);
2166 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2168 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2169 return V_0280A0_SWAP_STD
;
2171 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2174 switch (desc
->nr_channels
) {
2176 if (HAS_SWIZZLE(0,X
))
2177 return V_0280A0_SWAP_STD
; /* X___ */
2178 else if (HAS_SWIZZLE(3,X
))
2179 return V_0280A0_SWAP_ALT_REV
; /* ___X */
2182 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2183 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2184 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2185 return V_0280A0_SWAP_STD
; /* XY__ */
2186 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2187 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2188 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2190 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
2191 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2192 return V_0280A0_SWAP_ALT
; /* X__Y */
2193 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2194 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2197 if (HAS_SWIZZLE(0,X
))
2198 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2199 else if (HAS_SWIZZLE(0,Z
))
2200 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2203 /* check the middle channels, the 1st and 4th channel can be NONE */
2204 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2205 return V_0280A0_SWAP_STD
; /* XYZW */
2206 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2207 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2208 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2209 return V_0280A0_SWAP_ALT
; /* ZYXW */
2210 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2213 return V_0280A0_SWAP_ALT_REV
;
2215 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2222 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2224 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2229 if (rctx
->dcc_stats
[slot
].query_active
)
2230 vi_separate_dcc_stop_query(&rctx
->b
,
2231 rctx
->dcc_stats
[slot
].tex
);
2233 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2234 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2235 rctx
->b
.destroy_query(&rctx
->b
,
2236 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2237 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2240 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2244 * Return the per-context slot where DCC statistics queries for the texture live.
2246 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2247 struct r600_texture
*tex
)
2249 int i
, empty_slot
= -1;
2251 /* Remove zombie textures (textures kept alive by this array only). */
2252 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2253 if (rctx
->dcc_stats
[i
].tex
&&
2254 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2255 vi_dcc_clean_up_context_slot(rctx
, i
);
2257 /* Find the texture. */
2258 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2259 /* Return if found. */
2260 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2261 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2265 /* Record the first seen empty slot. */
2266 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2270 /* Not found. Remove the oldest member to make space in the array. */
2271 if (empty_slot
== -1) {
2272 int oldest_slot
= 0;
2274 /* Find the oldest slot. */
2275 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2276 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2277 rctx
->dcc_stats
[i
].last_use_timestamp
)
2280 /* Clean up the oldest slot. */
2281 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2282 empty_slot
= oldest_slot
;
2285 /* Add the texture to the new slot. */
2286 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2287 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2291 static struct pipe_query
*
2292 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2294 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2295 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2297 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2298 return (struct pipe_query
*)query
;
2302 * Called when binding a color buffer.
2304 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2305 struct r600_texture
*tex
)
2307 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2308 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2310 assert(!rctx
->dcc_stats
[i
].query_active
);
2312 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2313 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2315 /* begin or resume the query */
2316 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2317 rctx
->dcc_stats
[i
].query_active
= true;
2321 * Called when unbinding a color buffer.
2323 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2324 struct r600_texture
*tex
)
2326 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2327 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2329 assert(rctx
->dcc_stats
[i
].query_active
);
2330 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2332 /* pause or end the query */
2333 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2334 rctx
->dcc_stats
[i
].query_active
= false;
2337 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2339 /* The minimum number of fullscreen draws per frame that is required
2341 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2344 /* Called by fast clear. */
2345 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2346 struct r600_texture
*tex
)
2348 /* The intent is to use this with shared displayable back buffers,
2349 * but it's not strictly limited only to them.
2351 if (!tex
->resource
.b
.is_shared
||
2352 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2353 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2354 tex
->resource
.b
.b
.last_level
> 0 ||
2355 !tex
->surface
.dcc_size
)
2358 if (tex
->dcc_offset
)
2359 return; /* already enabled */
2361 /* Enable the DCC stat gathering. */
2362 if (!tex
->dcc_gather_statistics
) {
2363 tex
->dcc_gather_statistics
= true;
2364 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2367 if (!vi_should_enable_separate_dcc(tex
))
2368 return; /* stats show that DCC decompression is too expensive */
2370 assert(tex
->surface
.num_dcc_levels
);
2371 assert(!tex
->dcc_separate_buffer
);
2373 r600_texture_discard_cmask(rctx
->screen
, tex
);
2375 /* Get a DCC buffer. */
2376 if (tex
->last_dcc_separate_buffer
) {
2377 assert(tex
->dcc_gather_statistics
);
2378 assert(!tex
->dcc_separate_buffer
);
2379 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2380 tex
->last_dcc_separate_buffer
= NULL
;
2382 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2383 r600_aligned_buffer_create(rctx
->b
.screen
,
2384 R600_RESOURCE_FLAG_UNMAPPABLE
,
2386 tex
->surface
.dcc_size
,
2387 tex
->surface
.dcc_alignment
);
2388 if (!tex
->dcc_separate_buffer
)
2392 /* dcc_offset is the absolute GPUVM address. */
2393 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2395 /* no need to flag anything since this is called by fast clear that
2396 * flags framebuffer state
2401 * Called by pipe_context::flush_resource, the place where DCC decompression
2404 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2405 struct r600_texture
*tex
)
2407 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2408 struct pipe_query
*tmp
;
2409 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2410 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2411 bool disable
= false;
2413 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2414 union pipe_query_result result
;
2416 /* Read the results. */
2417 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2419 r600_query_hw_reset_buffers(rctx
,
2420 (struct r600_query_hw
*)
2421 rctx
->dcc_stats
[i
].ps_stats
[2]);
2423 /* Compute the approximate number of fullscreen draws. */
2424 tex
->ps_draw_ratio
=
2425 result
.pipeline_statistics
.ps_invocations
/
2426 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2427 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2429 disable
= tex
->dcc_separate_buffer
&&
2430 !vi_should_enable_separate_dcc(tex
);
2433 tex
->num_slow_clears
= 0;
2435 /* stop the statistics query for ps_stats[0] */
2437 vi_separate_dcc_stop_query(ctx
, tex
);
2439 /* Move the queries in the queue by one. */
2440 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2441 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2442 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2443 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2445 /* create and start a new query as ps_stats[0] */
2447 vi_separate_dcc_start_query(ctx
, tex
);
2450 assert(!tex
->last_dcc_separate_buffer
);
2451 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2452 tex
->dcc_separate_buffer
= NULL
;
2453 tex
->dcc_offset
= 0;
2454 /* no need to flag anything since this is called after
2455 * decompression that re-sets framebuffer state
2460 /* FAST COLOR CLEAR */
2462 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2463 enum pipe_format surface_format
,
2464 const union pipe_color_union
*color
)
2466 union util_color uc
;
2468 memset(&uc
, 0, sizeof(uc
));
2470 if (rtex
->surface
.bpe
== 16) {
2471 /* DCC fast clear only:
2472 * CLEAR_WORD0 = R = G = B
2475 assert(color
->ui
[0] == color
->ui
[1] &&
2476 color
->ui
[0] == color
->ui
[2]);
2477 uc
.ui
[0] = color
->ui
[0];
2478 uc
.ui
[1] = color
->ui
[3];
2479 } else if (util_format_is_pure_uint(surface_format
)) {
2480 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2481 } else if (util_format_is_pure_sint(surface_format
)) {
2482 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2484 util_pack_color(color
->f
, surface_format
, &uc
);
2487 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2490 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2491 const union pipe_color_union
*color
,
2492 uint32_t* reset_value
,
2493 bool* clear_words_needed
)
2495 bool values
[4] = {};
2497 bool main_value
= false;
2498 bool extra_value
= false;
2501 /* This is needed to get the correct DCC clear value for luminance formats.
2502 * 1) Get the linear format (because the next step can't handle L8_SRGB).
2503 * 2) Convert luminance to red. (the real hw format for luminance)
2505 surface_format
= util_format_linear(surface_format
);
2506 surface_format
= util_format_luminance_to_red(surface_format
);
2508 const struct util_format_description
*desc
= util_format_description(surface_format
);
2510 if (desc
->block
.bits
== 128 &&
2511 (color
->ui
[0] != color
->ui
[1] ||
2512 color
->ui
[0] != color
->ui
[2]))
2515 *clear_words_needed
= true;
2516 *reset_value
= 0x20202020U
;
2518 /* If we want to clear without needing a fast clear eliminate step, we
2519 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2520 * have two sets of flags, one for the last or first channel(extra) and
2521 * one for the other channels(main).
2524 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2525 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2526 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
||
2527 util_format_is_alpha(surface_format
)) {
2529 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2530 if(r600_translate_colorswap(surface_format
, false) <= 1)
2531 extra_channel
= desc
->nr_channels
- 1;
2537 for (i
= 0; i
< 4; ++i
) {
2538 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2540 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2541 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2544 if (desc
->channel
[i
].pure_integer
&&
2545 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2546 /* Use the maximum value for clamping the clear color. */
2547 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2549 values
[i
] = color
->i
[i
] != 0;
2550 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2552 } else if (desc
->channel
[i
].pure_integer
&&
2553 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2554 /* Use the maximum value for clamping the clear color. */
2555 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2557 values
[i
] = color
->ui
[i
] != 0U;
2558 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2561 values
[i
] = color
->f
[i
] != 0.0F
;
2562 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2566 if (index
== extra_channel
)
2567 extra_value
= values
[i
];
2569 main_value
= values
[i
];
2572 for (int i
= 0; i
< 4; ++i
)
2573 if (values
[i
] != main_value
&&
2574 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2575 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2576 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2579 *clear_words_needed
= false;
2581 *reset_value
|= 0x80808080U
;
2584 *reset_value
|= 0x40404040U
;
2588 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2589 struct r600_texture
*rtex
,
2590 unsigned level
, unsigned clear_value
)
2592 struct pipe_resource
*dcc_buffer
;
2593 uint64_t dcc_offset
, clear_size
;
2595 assert(vi_dcc_enabled(rtex
, level
));
2597 if (rtex
->dcc_separate_buffer
) {
2598 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2601 dcc_buffer
= &rtex
->resource
.b
.b
;
2602 dcc_offset
= rtex
->dcc_offset
;
2605 if (rctx
->chip_class
>= GFX9
) {
2606 /* Mipmap level clears aren't implemented. */
2607 assert(rtex
->resource
.b
.b
.last_level
== 0);
2608 /* MSAA needs a different clear size. */
2609 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2610 clear_size
= rtex
->surface
.dcc_size
;
2612 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2613 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2616 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2617 clear_value
, R600_COHERENCY_CB_META
);
2620 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2621 * This allows hitting the MSAA resolve fast path, which requires that both
2622 * src and dst micro tile modes match.
2624 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2625 struct r600_texture
*rtex
)
2627 if (rtex
->resource
.b
.is_shared
||
2628 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2629 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2632 assert(rscreen
->chip_class
>= GFX9
||
2633 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2634 assert(rtex
->resource
.b
.b
.last_level
== 0);
2636 if (rscreen
->chip_class
>= GFX9
) {
2637 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2638 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2640 /* If you do swizzle_mode % 4, you'll get:
2646 * Depth-sample order isn't allowed:
2648 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2650 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2651 case RADEON_MICRO_MODE_DISPLAY
:
2652 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2653 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2655 case RADEON_MICRO_MODE_THIN
:
2656 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2657 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2659 case RADEON_MICRO_MODE_ROTATED
:
2660 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2661 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2663 default: /* depth */
2664 assert(!"unexpected micro mode");
2667 } else if (rscreen
->chip_class
>= CIK
) {
2668 /* These magic numbers were copied from addrlib. It doesn't use
2669 * any definitions for them either. They are all 2D_TILED_THIN1
2670 * modes with different bpp and micro tile mode.
2672 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2673 case RADEON_MICRO_MODE_DISPLAY
:
2674 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2676 case RADEON_MICRO_MODE_THIN
:
2677 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2679 case RADEON_MICRO_MODE_ROTATED
:
2680 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2682 default: /* depth, thick */
2683 assert(!"unexpected micro mode");
2687 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2688 case RADEON_MICRO_MODE_DISPLAY
:
2689 switch (rtex
->surface
.bpe
) {
2691 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2694 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2697 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2701 case RADEON_MICRO_MODE_THIN
:
2702 switch (rtex
->surface
.bpe
) {
2704 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2707 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2710 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2712 default: /* 8, 16 */
2713 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2717 default: /* depth, thick */
2718 assert(!"unexpected micro mode");
2723 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2725 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2728 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2729 struct pipe_framebuffer_state
*fb
,
2730 struct r600_atom
*fb_state
,
2731 unsigned *buffers
, ubyte
*dirty_cbufs
,
2732 const union pipe_color_union
*color
)
2736 /* This function is broken in BE, so just disable this path for now */
2737 #ifdef PIPE_ARCH_BIG_ENDIAN
2741 if (rctx
->render_cond
)
2744 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2745 struct r600_texture
*tex
;
2746 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2751 /* if this colorbuffer is not being cleared */
2752 if (!(*buffers
& clear_bit
))
2755 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2757 /* the clear is allowed if all layers are bound */
2758 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2759 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2763 /* cannot clear mipmapped textures */
2764 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2768 /* only supported on tiled surfaces */
2769 if (tex
->surface
.is_linear
) {
2773 /* shared textures can't use fast clear without an explicit flush,
2774 * because there is no way to communicate the clear color among
2777 if (tex
->resource
.b
.is_shared
&&
2778 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2781 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2782 if (rctx
->chip_class
== CIK
&&
2783 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2784 rctx
->screen
->info
.drm_major
== 2 &&
2785 rctx
->screen
->info
.drm_minor
< 38) {
2789 /* Fast clear is the most appropriate place to enable DCC for
2790 * displayable surfaces.
2792 if (rctx
->chip_class
>= VI
&&
2793 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2794 vi_separate_dcc_try_enable(rctx
, tex
);
2796 /* RB+ isn't supported with a CMASK clear only on Stoney,
2797 * so all clears are considered to be hypothetically slow
2798 * clears, which is weighed when determining whether to
2799 * enable separate DCC.
2801 if (tex
->dcc_gather_statistics
&&
2802 rctx
->family
== CHIP_STONEY
)
2803 tex
->num_slow_clears
++;
2806 /* Try to clear DCC first, otherwise try CMASK. */
2807 if (vi_dcc_enabled(tex
, 0)) {
2808 uint32_t reset_value
;
2809 bool clear_words_needed
;
2811 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2814 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2815 color
, &reset_value
,
2816 &clear_words_needed
))
2819 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2821 unsigned level_bit
= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2822 if (clear_words_needed
) {
2823 bool need_compressed_update
= !tex
->dirty_level_mask
;
2825 tex
->dirty_level_mask
|= level_bit
;
2827 if (need_compressed_update
)
2828 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2830 tex
->separate_dcc_dirty
= true;
2832 /* 128-bit formats are unusupported */
2833 if (tex
->surface
.bpe
> 8) {
2837 /* RB+ doesn't work with CMASK fast clear on Stoney. */
2838 if (rctx
->family
== CHIP_STONEY
)
2841 /* ensure CMASK is enabled */
2842 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2843 if (tex
->cmask
.size
== 0) {
2847 /* Do the fast clear. */
2848 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2849 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2850 R600_COHERENCY_CB_META
);
2852 bool need_compressed_update
= !tex
->dirty_level_mask
;
2854 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2856 if (need_compressed_update
)
2857 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2860 /* We can change the micro tile mode before a full clear. */
2861 if (rctx
->screen
->chip_class
>= SI
)
2862 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2864 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2867 *dirty_cbufs
|= 1 << i
;
2868 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2869 *buffers
&= ~clear_bit
;
2873 static struct pipe_memory_object
*
2874 r600_memobj_from_handle(struct pipe_screen
*screen
,
2875 struct winsys_handle
*whandle
,
2878 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2879 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2880 struct pb_buffer
*buf
= NULL
;
2881 uint32_t stride
, offset
;
2886 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
,
2893 memobj
->b
.dedicated
= dedicated
;
2895 memobj
->stride
= stride
;
2896 memobj
->offset
= offset
;
2898 return (struct pipe_memory_object
*)memobj
;
2903 r600_memobj_destroy(struct pipe_screen
*screen
,
2904 struct pipe_memory_object
*_memobj
)
2906 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2908 pb_reference(&memobj
->buf
, NULL
);
2912 static struct pipe_resource
*
2913 r600_texture_from_memobj(struct pipe_screen
*screen
,
2914 const struct pipe_resource
*templ
,
2915 struct pipe_memory_object
*_memobj
,
2919 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2920 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2921 struct r600_texture
*rtex
;
2922 struct radeon_surf surface
= {};
2923 struct radeon_bo_metadata metadata
= {};
2924 enum radeon_surf_mode array_mode
;
2926 struct pb_buffer
*buf
= NULL
;
2928 if (memobj
->b
.dedicated
) {
2929 rscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2930 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
2931 &array_mode
, &is_scanout
);
2934 * The bo metadata is unset for un-dedicated images. So we fall
2935 * back to linear. See answer to question 5 of the
2936 * VK_KHX_external_memory spec for some details.
2938 * It is possible that this case isn't going to work if the
2939 * surface pitch isn't correctly aligned by default.
2941 * In order to support it correctly we require multi-image
2942 * metadata to be syncrhonized between radv and radeonsi. The
2943 * semantics of associating multiple image metadata to a memory
2944 * object on the vulkan export side are not concretely defined
2947 * All the use cases we are aware of at the moment for memory
2948 * objects use dedicated allocations. So lets keep the initial
2949 * implementation simple.
2951 * A possible alternative is to attempt to reconstruct the
2952 * tiling information when the TexParameter TEXTURE_TILING_EXT
2955 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2960 r
= r600_init_surface(rscreen
, &surface
, templ
,
2961 array_mode
, memobj
->stride
,
2962 offset
, true, is_scanout
,
2967 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2971 /* r600_texture_create_object doesn't increment refcount of
2972 * memobj->buf, so increment it here.
2974 pb_reference(&buf
, memobj
->buf
);
2976 rtex
->resource
.b
.is_shared
= true;
2977 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2979 if (rscreen
->apply_opaque_metadata
)
2980 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
2982 return &rtex
->resource
.b
.b
;
2985 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2987 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2988 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2989 rscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2990 rscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2991 rscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2994 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2996 rctx
->b
.create_surface
= r600_create_surface
;
2997 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2998 rctx
->b
.clear_texture
= r600_clear_texture
;