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gallium/radeon: don't use fast color clear if sharing doesn't allow it
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static void r600_texture_init_metadata(struct r600_texture *rtex,
232 struct radeon_bo_metadata *metadata)
233 {
234 struct radeon_surf *surface = &rtex->surface;
235
236 memset(metadata, 0, sizeof(*metadata));
237 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
238 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
239 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
240 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
241 metadata->pipe_config = surface->pipe_config;
242 metadata->bankw = surface->bankw;
243 metadata->bankh = surface->bankh;
244 metadata->tile_split = surface->tile_split;
245 metadata->stencil_tile_split = surface->stencil_tile_split;
246 metadata->mtilea = surface->mtilea;
247 metadata->num_banks = surface->num_banks;
248 metadata->stride = surface->level[0].pitch_bytes;
249 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
250 }
251
252 static boolean r600_texture_get_handle(struct pipe_screen* screen,
253 struct pipe_resource *resource,
254 struct winsys_handle *whandle,
255 unsigned usage)
256 {
257 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
258 struct r600_resource *res = (struct r600_resource*)resource;
259 struct r600_texture *rtex = (struct r600_texture*)resource;
260 struct radeon_bo_metadata metadata;
261
262 /* This is not supported now, but it might be required for OpenCL
263 * interop in the future.
264 */
265 if (resource->target != PIPE_BUFFER &&
266 (resource->nr_samples > 1 || rtex->is_depth))
267 return NULL;
268
269 if (!res->is_shared) {
270 res->is_shared = true;
271 res->external_usage = usage;
272
273 if (resource->target != PIPE_BUFFER) {
274 r600_texture_init_metadata(rtex, &metadata);
275 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
276 }
277 } else {
278 assert(res->external_usage == usage);
279 }
280
281 return rscreen->ws->buffer_get_handle(res->buf,
282 rtex->surface.level[0].pitch_bytes,
283 whandle);
284 }
285
286 static void r600_texture_destroy(struct pipe_screen *screen,
287 struct pipe_resource *ptex)
288 {
289 struct r600_texture *rtex = (struct r600_texture*)ptex;
290 struct r600_resource *resource = &rtex->resource;
291
292 if (rtex->flushed_depth_texture)
293 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
294
295 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
296 if (rtex->cmask_buffer != &rtex->resource) {
297 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
298 }
299 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
300 pb_reference(&resource->buf, NULL);
301 FREE(rtex);
302 }
303
304 static const struct u_resource_vtbl r600_texture_vtbl;
305
306 /* The number of samples can be specified independently of the texture. */
307 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
308 struct r600_texture *rtex,
309 unsigned nr_samples,
310 struct r600_fmask_info *out)
311 {
312 /* FMASK is allocated like an ordinary texture. */
313 struct radeon_surf fmask = rtex->surface;
314
315 memset(out, 0, sizeof(*out));
316
317 fmask.bo_alignment = 0;
318 fmask.bo_size = 0;
319 fmask.nsamples = 1;
320 fmask.flags |= RADEON_SURF_FMASK;
321
322 /* Force 2D tiling if it wasn't set. This may occur when creating
323 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
324 * destination buffer must have an FMASK too. */
325 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
326 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
327
328 if (rscreen->chip_class >= SI) {
329 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
330 }
331
332 switch (nr_samples) {
333 case 2:
334 case 4:
335 fmask.bpe = 1;
336 if (rscreen->chip_class <= CAYMAN) {
337 fmask.bankh = 4;
338 }
339 break;
340 case 8:
341 fmask.bpe = 4;
342 break;
343 default:
344 R600_ERR("Invalid sample count for FMASK allocation.\n");
345 return;
346 }
347
348 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
349 * This can be fixed by writing a separate FMASK allocator specifically
350 * for R600-R700 asics. */
351 if (rscreen->chip_class <= R700) {
352 fmask.bpe *= 2;
353 }
354
355 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
356 R600_ERR("Got error in surface_init while allocating FMASK.\n");
357 return;
358 }
359
360 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
361
362 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
363 if (out->slice_tile_max)
364 out->slice_tile_max -= 1;
365
366 out->tile_mode_index = fmask.tiling_index[0];
367 out->pitch_in_pixels = fmask.level[0].nblk_x;
368 out->bank_height = fmask.bankh;
369 out->alignment = MAX2(256, fmask.bo_alignment);
370 out->size = fmask.bo_size;
371 }
372
373 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
374 struct r600_texture *rtex)
375 {
376 r600_texture_get_fmask_info(rscreen, rtex,
377 rtex->resource.b.b.nr_samples, &rtex->fmask);
378
379 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
380 rtex->size = rtex->fmask.offset + rtex->fmask.size;
381 }
382
383 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
384 struct r600_texture *rtex,
385 struct r600_cmask_info *out)
386 {
387 unsigned cmask_tile_width = 8;
388 unsigned cmask_tile_height = 8;
389 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
390 unsigned element_bits = 4;
391 unsigned cmask_cache_bits = 1024;
392 unsigned num_pipes = rscreen->info.num_tile_pipes;
393 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
394
395 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
396 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
397 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
398 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
399 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
400
401 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
402 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
403
404 unsigned base_align = num_pipes * pipe_interleave_bytes;
405 unsigned slice_bytes =
406 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
407
408 assert(macro_tile_width % 128 == 0);
409 assert(macro_tile_height % 128 == 0);
410
411 out->pitch = pitch_elements;
412 out->height = height;
413 out->xalign = macro_tile_width;
414 out->yalign = macro_tile_height;
415 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
416 out->alignment = MAX2(256, base_align);
417 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
418 align(slice_bytes, base_align);
419 }
420
421 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
422 struct r600_texture *rtex,
423 struct r600_cmask_info *out)
424 {
425 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
426 unsigned num_pipes = rscreen->info.num_tile_pipes;
427 unsigned cl_width, cl_height;
428
429 switch (num_pipes) {
430 case 2:
431 cl_width = 32;
432 cl_height = 16;
433 break;
434 case 4:
435 cl_width = 32;
436 cl_height = 32;
437 break;
438 case 8:
439 cl_width = 64;
440 cl_height = 32;
441 break;
442 case 16: /* Hawaii */
443 cl_width = 64;
444 cl_height = 64;
445 break;
446 default:
447 assert(0);
448 return;
449 }
450
451 unsigned base_align = num_pipes * pipe_interleave_bytes;
452
453 unsigned width = align(rtex->surface.npix_x, cl_width*8);
454 unsigned height = align(rtex->surface.npix_y, cl_height*8);
455 unsigned slice_elements = (width * height) / (8*8);
456
457 /* Each element of CMASK is a nibble. */
458 unsigned slice_bytes = slice_elements / 2;
459
460 out->pitch = width;
461 out->height = height;
462 out->xalign = cl_width * 8;
463 out->yalign = cl_height * 8;
464 out->slice_tile_max = (width * height) / (128*128);
465 if (out->slice_tile_max)
466 out->slice_tile_max -= 1;
467
468 out->alignment = MAX2(256, base_align);
469 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
470 align(slice_bytes, base_align);
471 }
472
473 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
474 struct r600_texture *rtex)
475 {
476 if (rscreen->chip_class >= SI) {
477 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
478 } else {
479 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
480 }
481
482 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
483 rtex->size = rtex->cmask.offset + rtex->cmask.size;
484
485 if (rscreen->chip_class >= SI)
486 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
487 else
488 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
489 }
490
491 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
492 struct r600_texture *rtex)
493 {
494 if (rtex->cmask_buffer)
495 return;
496
497 assert(rtex->cmask.size == 0);
498
499 if (rscreen->chip_class >= SI) {
500 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
501 } else {
502 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
503 }
504
505 rtex->cmask_buffer = (struct r600_resource *)
506 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
507 PIPE_USAGE_DEFAULT, rtex->cmask.size);
508 if (rtex->cmask_buffer == NULL) {
509 rtex->cmask.size = 0;
510 return;
511 }
512
513 /* update colorbuffer state bits */
514 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
515
516 if (rscreen->chip_class >= SI)
517 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
518 else
519 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
520 }
521
522 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
523 struct r600_texture *rtex)
524 {
525 if (rscreen->debug_flags & DBG_NO_DCC)
526 return;
527
528 rtex->dcc_buffer = (struct r600_resource *)
529 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
530 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
531 if (rtex->dcc_buffer == NULL) {
532 return;
533 }
534
535 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
536 0xFFFFFFFF, true);
537
538 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
539 }
540
541 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
542 struct r600_texture *rtex)
543 {
544 unsigned cl_width, cl_height, width, height;
545 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
546 unsigned num_pipes = rscreen->info.num_tile_pipes;
547
548 if (rscreen->chip_class <= EVERGREEN &&
549 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
550 return 0;
551
552 /* HW bug on R6xx. */
553 if (rscreen->chip_class == R600 &&
554 (rtex->surface.level[0].npix_x > 7680 ||
555 rtex->surface.level[0].npix_y > 7680))
556 return 0;
557
558 /* HTILE is broken with 1D tiling on old kernels and CIK. */
559 if (rscreen->chip_class >= CIK &&
560 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
561 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
562 return 0;
563
564 /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
565 if (rscreen->family == CHIP_STONEY)
566 num_pipes = 4;
567
568 switch (num_pipes) {
569 case 1:
570 cl_width = 32;
571 cl_height = 16;
572 break;
573 case 2:
574 cl_width = 32;
575 cl_height = 32;
576 break;
577 case 4:
578 cl_width = 64;
579 cl_height = 32;
580 break;
581 case 8:
582 cl_width = 64;
583 cl_height = 64;
584 break;
585 case 16:
586 cl_width = 128;
587 cl_height = 64;
588 break;
589 default:
590 assert(0);
591 return 0;
592 }
593
594 width = align(rtex->surface.npix_x, cl_width * 8);
595 height = align(rtex->surface.npix_y, cl_height * 8);
596
597 slice_elements = (width * height) / (8 * 8);
598 slice_bytes = slice_elements * 4;
599
600 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
601 base_align = num_pipes * pipe_interleave_bytes;
602
603 rtex->htile.pitch = width;
604 rtex->htile.height = height;
605 rtex->htile.xalign = cl_width * 8;
606 rtex->htile.yalign = cl_height * 8;
607
608 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
609 align(slice_bytes, base_align);
610 }
611
612 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
613 struct r600_texture *rtex)
614 {
615 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
616
617 if (!htile_size)
618 return;
619
620 rtex->htile_buffer = (struct r600_resource*)
621 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
622 PIPE_USAGE_DEFAULT, htile_size);
623 if (rtex->htile_buffer == NULL) {
624 /* this is not a fatal error as we can still keep rendering
625 * without htile buffer */
626 R600_ERR("Failed to create buffer object for htile buffer.\n");
627 } else {
628 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
629 htile_size, 0, true);
630 }
631 }
632
633 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
634 {
635 int i;
636
637 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
638 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
639 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
640 rtex->surface.npix_x, rtex->surface.npix_y,
641 rtex->surface.npix_z, rtex->surface.blk_w,
642 rtex->surface.blk_h, rtex->surface.blk_d,
643 rtex->surface.array_size, rtex->surface.last_level,
644 rtex->surface.bpe, rtex->surface.nsamples,
645 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
646
647 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
648 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
649 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
650 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
651 rtex->surface.tile_split, rtex->surface.pipe_config,
652 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
653
654 if (rtex->fmask.size)
655 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
656 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
657 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
658 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
659 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
660
661 if (rtex->cmask.size)
662 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
663 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
664 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
665 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
666 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
667
668 if (rtex->htile_buffer)
669 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
670 "xalign=%u, yalign=%u\n",
671 rtex->htile_buffer->b.b.width0,
672 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
673 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
674
675 if (rtex->dcc_buffer) {
676 fprintf(f, " DCC: size=%u, alignment=%u\n",
677 rtex->dcc_buffer->b.b.width0,
678 rtex->dcc_buffer->buf->alignment);
679 for (i = 0; i <= rtex->surface.last_level; i++)
680 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
681 i, rtex->surface.level[i].dcc_offset);
682 }
683
684 for (i = 0; i <= rtex->surface.last_level; i++)
685 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
686 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
687 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
688 i, rtex->surface.level[i].offset,
689 rtex->surface.level[i].slice_size,
690 u_minify(rtex->resource.b.b.width0, i),
691 u_minify(rtex->resource.b.b.height0, i),
692 u_minify(rtex->resource.b.b.depth0, i),
693 rtex->surface.level[i].nblk_x,
694 rtex->surface.level[i].nblk_y,
695 rtex->surface.level[i].nblk_z,
696 rtex->surface.level[i].pitch_bytes,
697 rtex->surface.level[i].mode);
698
699 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
700 for (i = 0; i <= rtex->surface.last_level; i++) {
701 fprintf(f, " StencilLayout: tilesplit=%u\n",
702 rtex->surface.stencil_tile_split);
703 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
704 "slice_size=%"PRIu64", npix_x=%u, "
705 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
706 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
707 i, rtex->surface.stencil_level[i].offset,
708 rtex->surface.stencil_level[i].slice_size,
709 u_minify(rtex->resource.b.b.width0, i),
710 u_minify(rtex->resource.b.b.height0, i),
711 u_minify(rtex->resource.b.b.depth0, i),
712 rtex->surface.stencil_level[i].nblk_x,
713 rtex->surface.stencil_level[i].nblk_y,
714 rtex->surface.stencil_level[i].nblk_z,
715 rtex->surface.stencil_level[i].pitch_bytes,
716 rtex->surface.stencil_level[i].mode);
717 }
718 }
719 }
720
721 /* Common processing for r600_texture_create and r600_texture_from_handle */
722 static struct r600_texture *
723 r600_texture_create_object(struct pipe_screen *screen,
724 const struct pipe_resource *base,
725 unsigned pitch_in_bytes_override,
726 struct pb_buffer *buf,
727 struct radeon_surf *surface)
728 {
729 struct r600_texture *rtex;
730 struct r600_resource *resource;
731 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
732
733 rtex = CALLOC_STRUCT(r600_texture);
734 if (!rtex)
735 return NULL;
736
737 resource = &rtex->resource;
738 resource->b.b = *base;
739 resource->b.vtbl = &r600_texture_vtbl;
740 pipe_reference_init(&resource->b.b.reference, 1);
741 resource->b.b.screen = screen;
742
743 /* don't include stencil-only formats which we don't support for rendering */
744 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
745
746 rtex->surface = *surface;
747 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
748 FREE(rtex);
749 return NULL;
750 }
751
752 /* Tiled depth textures utilize the non-displayable tile order.
753 * This must be done after r600_setup_surface.
754 * Applies to R600-Cayman. */
755 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
756
757 if (rtex->is_depth) {
758 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
759 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
760 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
761
762 r600_texture_allocate_htile(rscreen, rtex);
763 }
764 } else {
765 if (base->nr_samples > 1) {
766 if (!buf) {
767 r600_texture_allocate_fmask(rscreen, rtex);
768 r600_texture_allocate_cmask(rscreen, rtex);
769 rtex->cmask_buffer = &rtex->resource;
770 }
771 if (!rtex->fmask.size || !rtex->cmask.size) {
772 FREE(rtex);
773 return NULL;
774 }
775 }
776 if (rtex->surface.dcc_size)
777 vi_texture_alloc_dcc_separate(rscreen, rtex);
778 }
779
780 /* Now create the backing buffer. */
781 if (!buf) {
782 if (!r600_init_resource(rscreen, resource, rtex->size,
783 rtex->surface.bo_alignment, TRUE)) {
784 FREE(rtex);
785 return NULL;
786 }
787 } else {
788 resource->buf = buf;
789 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
790 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
791 }
792
793 if (rtex->cmask.size) {
794 /* Initialize the cmask to 0xCC (= compressed state). */
795 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
796 rtex->cmask.offset, rtex->cmask.size,
797 0xCCCCCCCC, true);
798 }
799
800 /* Initialize the CMASK base register value. */
801 rtex->cmask.base_address_reg =
802 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
803
804 if (rscreen->debug_flags & DBG_VM) {
805 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
806 rtex->resource.gpu_address,
807 rtex->resource.gpu_address + rtex->resource.buf->size,
808 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
809 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
810 }
811
812 if (rscreen->debug_flags & DBG_TEX) {
813 puts("Texture:");
814 r600_print_texture_info(rtex, stdout);
815 }
816
817 return rtex;
818 }
819
820 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
821 const struct pipe_resource *templ)
822 {
823 const struct util_format_description *desc = util_format_description(templ->format);
824 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
825
826 /* MSAA resources must be 2D tiled. */
827 if (templ->nr_samples > 1)
828 return RADEON_SURF_MODE_2D;
829
830 /* Transfer resources should be linear. */
831 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
832 return RADEON_SURF_MODE_LINEAR_ALIGNED;
833
834 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
835 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
836 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
837 (templ->target == PIPE_TEXTURE_2D ||
838 templ->target == PIPE_TEXTURE_3D))
839 force_tiling = true;
840
841 /* Handle common candidates for the linear mode.
842 * Compressed textures must always be tiled. */
843 if (!force_tiling && !util_format_is_compressed(templ->format)) {
844 /* Not everything can be linear, so we cannot enforce it
845 * for all textures. */
846 if ((rscreen->debug_flags & DBG_NO_TILING) &&
847 (!util_format_is_depth_or_stencil(templ->format) ||
848 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
849 return RADEON_SURF_MODE_LINEAR_ALIGNED;
850
851 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
852 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
853 return RADEON_SURF_MODE_LINEAR_ALIGNED;
854
855 /* Cursors are linear on SI.
856 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
857 if (rscreen->chip_class >= SI &&
858 (templ->bind & PIPE_BIND_CURSOR))
859 return RADEON_SURF_MODE_LINEAR_ALIGNED;
860
861 if (templ->bind & PIPE_BIND_LINEAR)
862 return RADEON_SURF_MODE_LINEAR_ALIGNED;
863
864 /* Textures with a very small height are recommended to be linear. */
865 if (templ->target == PIPE_TEXTURE_1D ||
866 templ->target == PIPE_TEXTURE_1D_ARRAY ||
867 templ->height0 <= 4)
868 return RADEON_SURF_MODE_LINEAR_ALIGNED;
869
870 /* Textures likely to be mapped often. */
871 if (templ->usage == PIPE_USAGE_STAGING ||
872 templ->usage == PIPE_USAGE_STREAM)
873 return RADEON_SURF_MODE_LINEAR_ALIGNED;
874 }
875
876 /* Make small textures 1D tiled. */
877 if (templ->width0 <= 16 || templ->height0 <= 16 ||
878 (rscreen->debug_flags & DBG_NO_2D_TILING))
879 return RADEON_SURF_MODE_1D;
880
881 /* The allocator will switch to 1D if needed. */
882 return RADEON_SURF_MODE_2D;
883 }
884
885 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
886 const struct pipe_resource *templ)
887 {
888 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
889 struct radeon_surf surface = {0};
890 int r;
891
892 r = r600_init_surface(rscreen, &surface, templ,
893 r600_choose_tiling(rscreen, templ),
894 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
895 if (r) {
896 return NULL;
897 }
898 r = rscreen->ws->surface_best(rscreen->ws, &surface);
899 if (r) {
900 return NULL;
901 }
902 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
903 0, NULL, &surface);
904 }
905
906 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
907 const struct pipe_resource *templ,
908 struct winsys_handle *whandle,
909 unsigned usage)
910 {
911 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
912 struct pb_buffer *buf = NULL;
913 unsigned stride = 0;
914 unsigned array_mode;
915 struct radeon_surf surface;
916 int r;
917 struct radeon_bo_metadata metadata = {};
918 struct r600_texture *rtex;
919
920 /* Support only 2D textures without mipmaps */
921 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
922 templ->depth0 != 1 || templ->last_level != 0)
923 return NULL;
924
925 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
926 if (!buf)
927 return NULL;
928
929 rscreen->ws->buffer_get_metadata(buf, &metadata);
930
931 surface.bankw = metadata.bankw;
932 surface.bankh = metadata.bankh;
933 surface.tile_split = metadata.tile_split;
934 surface.stencil_tile_split = metadata.stencil_tile_split;
935 surface.mtilea = metadata.mtilea;
936
937 if (metadata.macrotile == RADEON_LAYOUT_TILED)
938 array_mode = RADEON_SURF_MODE_2D;
939 else if (metadata.microtile == RADEON_LAYOUT_TILED)
940 array_mode = RADEON_SURF_MODE_1D;
941 else
942 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
943
944 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
945 if (r) {
946 return NULL;
947 }
948
949 if (metadata.scanout)
950 surface.flags |= RADEON_SURF_SCANOUT;
951
952 rtex = r600_texture_create_object(screen, templ,
953 stride, buf, &surface);
954 if (!rtex)
955 return NULL;
956
957 rtex->resource.is_shared = true;
958 rtex->resource.external_usage = usage;
959 return &rtex->resource.b.b;
960 }
961
962 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
963 struct pipe_resource *texture,
964 struct r600_texture **staging)
965 {
966 struct r600_texture *rtex = (struct r600_texture*)texture;
967 struct pipe_resource resource;
968 struct r600_texture **flushed_depth_texture = staging ?
969 staging : &rtex->flushed_depth_texture;
970
971 if (!staging && rtex->flushed_depth_texture)
972 return true; /* it's ready */
973
974 resource.target = texture->target;
975 resource.format = texture->format;
976 resource.width0 = texture->width0;
977 resource.height0 = texture->height0;
978 resource.depth0 = texture->depth0;
979 resource.array_size = texture->array_size;
980 resource.last_level = texture->last_level;
981 resource.nr_samples = texture->nr_samples;
982 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
983 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
984 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
985
986 if (staging)
987 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
988
989 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
990 if (*flushed_depth_texture == NULL) {
991 R600_ERR("failed to create temporary texture to hold flushed depth\n");
992 return false;
993 }
994
995 (*flushed_depth_texture)->is_flushing_texture = TRUE;
996 (*flushed_depth_texture)->non_disp_tiling = false;
997 return true;
998 }
999
1000 /**
1001 * Initialize the pipe_resource descriptor to be of the same size as the box,
1002 * which is supposed to hold a subregion of the texture "orig" at the given
1003 * mipmap level.
1004 */
1005 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1006 struct pipe_resource *orig,
1007 const struct pipe_box *box,
1008 unsigned level, unsigned flags)
1009 {
1010 memset(res, 0, sizeof(*res));
1011 res->format = orig->format;
1012 res->width0 = box->width;
1013 res->height0 = box->height;
1014 res->depth0 = 1;
1015 res->array_size = 1;
1016 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1017 res->flags = flags;
1018
1019 /* We must set the correct texture target and dimensions for a 3D box. */
1020 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1021 res->target = orig->target;
1022 else
1023 res->target = PIPE_TEXTURE_2D;
1024
1025 switch (res->target) {
1026 case PIPE_TEXTURE_1D_ARRAY:
1027 case PIPE_TEXTURE_2D_ARRAY:
1028 case PIPE_TEXTURE_CUBE_ARRAY:
1029 res->array_size = box->depth;
1030 break;
1031 case PIPE_TEXTURE_3D:
1032 res->depth0 = box->depth;
1033 break;
1034 default:;
1035 }
1036 }
1037
1038 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1039 struct pipe_resource *texture,
1040 unsigned level,
1041 unsigned usage,
1042 const struct pipe_box *box,
1043 struct pipe_transfer **ptransfer)
1044 {
1045 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1046 struct r600_texture *rtex = (struct r600_texture*)texture;
1047 struct r600_transfer *trans;
1048 boolean use_staging_texture = FALSE;
1049 struct r600_resource *buf;
1050 unsigned offset = 0;
1051 char *map;
1052
1053 /* We cannot map a tiled texture directly because the data is
1054 * in a different order, therefore we do detiling using a blit.
1055 *
1056 * Also, use a temporary in GTT memory for read transfers, as
1057 * the CPU is much happier reading out of cached system memory
1058 * than uncached VRAM.
1059 */
1060 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1061 use_staging_texture = TRUE;
1062 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1063 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1064 /* Untiled buffers in VRAM, which is slow for CPU reads */
1065 use_staging_texture = TRUE;
1066 } else if (!(usage & PIPE_TRANSFER_READ) &&
1067 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1068 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1069 /* Use a staging texture for uploads if the underlying BO is busy. */
1070 use_staging_texture = TRUE;
1071 }
1072
1073 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1074 use_staging_texture = FALSE;
1075 }
1076
1077 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1078 return NULL;
1079 }
1080
1081 trans = CALLOC_STRUCT(r600_transfer);
1082 if (!trans)
1083 return NULL;
1084 trans->transfer.resource = texture;
1085 trans->transfer.level = level;
1086 trans->transfer.usage = usage;
1087 trans->transfer.box = *box;
1088
1089 if (rtex->is_depth) {
1090 struct r600_texture *staging_depth;
1091
1092 if (rtex->resource.b.b.nr_samples > 1) {
1093 /* MSAA depth buffers need to be converted to single sample buffers.
1094 *
1095 * Mapping MSAA depth buffers can occur if ReadPixels is called
1096 * with a multisample GLX visual.
1097 *
1098 * First downsample the depth buffer to a temporary texture,
1099 * then decompress the temporary one to staging.
1100 *
1101 * Only the region being mapped is transfered.
1102 */
1103 struct pipe_resource resource;
1104
1105 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1106
1107 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1108 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1109 FREE(trans);
1110 return NULL;
1111 }
1112
1113 if (usage & PIPE_TRANSFER_READ) {
1114 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1115 if (!temp) {
1116 R600_ERR("failed to create a temporary depth texture\n");
1117 FREE(trans);
1118 return NULL;
1119 }
1120
1121 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1122 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1123 0, 0, 0, box->depth, 0, 0);
1124 pipe_resource_reference(&temp, NULL);
1125 }
1126 }
1127 else {
1128 /* XXX: only readback the rectangle which is being mapped? */
1129 /* XXX: when discard is true, no need to read back from depth texture */
1130 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1131 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1132 FREE(trans);
1133 return NULL;
1134 }
1135
1136 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1137 level, level,
1138 box->z, box->z + box->depth - 1,
1139 0, 0);
1140
1141 offset = r600_texture_get_offset(staging_depth, level, box);
1142 }
1143
1144 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1145 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1146 trans->staging = (struct r600_resource*)staging_depth;
1147 } else if (use_staging_texture) {
1148 struct pipe_resource resource;
1149 struct r600_texture *staging;
1150
1151 r600_init_temp_resource_from_box(&resource, texture, box, level,
1152 R600_RESOURCE_FLAG_TRANSFER);
1153 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1154 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1155
1156 /* Create the temporary texture. */
1157 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1158 if (!staging) {
1159 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1160 FREE(trans);
1161 return NULL;
1162 }
1163 trans->staging = &staging->resource;
1164 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1165 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1166 if (usage & PIPE_TRANSFER_READ) {
1167 r600_copy_to_staging_texture(ctx, trans);
1168 }
1169 } else {
1170 /* the resource is mapped directly */
1171 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1172 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1173 offset = r600_texture_get_offset(rtex, level, box);
1174 }
1175
1176 if (trans->staging) {
1177 buf = trans->staging;
1178 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1179 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1180 } else {
1181 buf = &rtex->resource;
1182 }
1183
1184 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1185 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1186 FREE(trans);
1187 return NULL;
1188 }
1189
1190 *ptransfer = &trans->transfer;
1191 return map + offset;
1192 }
1193
1194 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1195 struct pipe_transfer* transfer)
1196 {
1197 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1198 struct pipe_resource *texture = transfer->resource;
1199 struct r600_texture *rtex = (struct r600_texture*)texture;
1200
1201 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1202 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1203 ctx->resource_copy_region(ctx, texture, transfer->level,
1204 transfer->box.x, transfer->box.y, transfer->box.z,
1205 &rtransfer->staging->b.b, transfer->level,
1206 &transfer->box);
1207 } else {
1208 r600_copy_from_staging_texture(ctx, rtransfer);
1209 }
1210 }
1211
1212 if (rtransfer->staging)
1213 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1214
1215 FREE(transfer);
1216 }
1217
1218 static const struct u_resource_vtbl r600_texture_vtbl =
1219 {
1220 NULL, /* get_handle */
1221 r600_texture_destroy, /* resource_destroy */
1222 r600_texture_transfer_map, /* transfer_map */
1223 u_default_transfer_flush_region, /* transfer_flush_region */
1224 r600_texture_transfer_unmap, /* transfer_unmap */
1225 NULL /* transfer_inline_write */
1226 };
1227
1228 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1229 struct pipe_resource *texture,
1230 const struct pipe_surface *templ,
1231 unsigned width, unsigned height)
1232 {
1233 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1234
1235 if (!surface)
1236 return NULL;
1237
1238 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1239 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1240
1241 pipe_reference_init(&surface->base.reference, 1);
1242 pipe_resource_reference(&surface->base.texture, texture);
1243 surface->base.context = pipe;
1244 surface->base.format = templ->format;
1245 surface->base.width = width;
1246 surface->base.height = height;
1247 surface->base.u = templ->u;
1248 return &surface->base;
1249 }
1250
1251 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1252 struct pipe_resource *tex,
1253 const struct pipe_surface *templ)
1254 {
1255 unsigned level = templ->u.tex.level;
1256 unsigned width = u_minify(tex->width0, level);
1257 unsigned height = u_minify(tex->height0, level);
1258
1259 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1260 const struct util_format_description *tex_desc
1261 = util_format_description(tex->format);
1262 const struct util_format_description *templ_desc
1263 = util_format_description(templ->format);
1264
1265 assert(tex_desc->block.bits == templ_desc->block.bits);
1266
1267 /* Adjust size of surface if and only if the block width or
1268 * height is changed. */
1269 if (tex_desc->block.width != templ_desc->block.width ||
1270 tex_desc->block.height != templ_desc->block.height) {
1271 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1272 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1273
1274 width = nblks_x * templ_desc->block.width;
1275 height = nblks_y * templ_desc->block.height;
1276 }
1277 }
1278
1279 return r600_create_surface_custom(pipe, tex, templ, width, height);
1280 }
1281
1282 static void r600_surface_destroy(struct pipe_context *pipe,
1283 struct pipe_surface *surface)
1284 {
1285 struct r600_surface *surf = (struct r600_surface*)surface;
1286 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1287 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1288 pipe_resource_reference(&surface->texture, NULL);
1289 FREE(surface);
1290 }
1291
1292 unsigned r600_translate_colorswap(enum pipe_format format)
1293 {
1294 const struct util_format_description *desc = util_format_description(format);
1295
1296 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1297
1298 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1299 return V_0280A0_SWAP_STD;
1300
1301 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1302 return ~0U;
1303
1304 switch (desc->nr_channels) {
1305 case 1:
1306 if (HAS_SWIZZLE(0,X))
1307 return V_0280A0_SWAP_STD; /* X___ */
1308 else if (HAS_SWIZZLE(3,X))
1309 return V_0280A0_SWAP_ALT_REV; /* ___X */
1310 break;
1311 case 2:
1312 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1313 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1314 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1315 return V_0280A0_SWAP_STD; /* XY__ */
1316 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1317 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1318 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1319 return V_0280A0_SWAP_STD_REV; /* YX__ */
1320 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1321 return V_0280A0_SWAP_ALT; /* X__Y */
1322 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1323 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1324 break;
1325 case 3:
1326 if (HAS_SWIZZLE(0,X))
1327 return V_0280A0_SWAP_STD; /* XYZ */
1328 else if (HAS_SWIZZLE(0,Z))
1329 return V_0280A0_SWAP_STD_REV; /* ZYX */
1330 break;
1331 case 4:
1332 /* check the middle channels, the 1st and 4th channel can be NONE */
1333 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1334 return V_0280A0_SWAP_STD; /* XYZW */
1335 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1336 return V_0280A0_SWAP_STD_REV; /* WZYX */
1337 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1338 return V_0280A0_SWAP_ALT; /* ZYXW */
1339 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
1340 return V_0280A0_SWAP_ALT_REV; /* YZWX */
1341 break;
1342 }
1343 return ~0U;
1344 }
1345
1346 static void evergreen_set_clear_color(struct r600_texture *rtex,
1347 enum pipe_format surface_format,
1348 const union pipe_color_union *color)
1349 {
1350 union util_color uc;
1351
1352 memset(&uc, 0, sizeof(uc));
1353
1354 if (util_format_is_pure_uint(surface_format)) {
1355 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1356 } else if (util_format_is_pure_sint(surface_format)) {
1357 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1358 } else {
1359 util_pack_color(color->f, surface_format, &uc);
1360 }
1361
1362 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1363 }
1364
1365 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1366 const union pipe_color_union *color,
1367 uint32_t* reset_value,
1368 bool* clear_words_needed)
1369 {
1370 bool values[4] = {};
1371 int i;
1372 bool main_value = false;
1373 bool extra_value = false;
1374 int extra_channel;
1375 const struct util_format_description *desc = util_format_description(surface_format);
1376
1377 *clear_words_needed = true;
1378 *reset_value = 0x20202020U;
1379
1380 /* If we want to clear without needing a fast clear eliminate step, we
1381 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1382 * have two sets of flags, one for the last or first channel(extra) and
1383 * one for the other channels(main).
1384 */
1385
1386 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1387 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1388 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1389 extra_channel = -1;
1390 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1391 if(r600_translate_colorswap(surface_format) <= 1)
1392 extra_channel = desc->nr_channels - 1;
1393 else
1394 extra_channel = 0;
1395 } else
1396 return;
1397
1398 for (i = 0; i < 4; ++i) {
1399 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1400
1401 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1402 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1403 continue;
1404
1405 if (util_format_is_pure_sint(surface_format)) {
1406 values[i] = color->i[i] != 0;
1407 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1408 return;
1409 } else if (util_format_is_pure_uint(surface_format)) {
1410 values[i] = color->ui[i] != 0U;
1411 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1412 return;
1413 } else {
1414 values[i] = color->f[i] != 0.0F;
1415 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1416 return;
1417 }
1418
1419 if (index == extra_channel)
1420 extra_value = values[i];
1421 else
1422 main_value = values[i];
1423 }
1424
1425 for (int i = 0; i < 4; ++i)
1426 if (values[i] != main_value &&
1427 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1428 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1429 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1430 return;
1431
1432 *clear_words_needed = false;
1433 if (main_value)
1434 *reset_value |= 0x80808080U;
1435
1436 if (extra_value)
1437 *reset_value |= 0x40404040U;
1438 }
1439
1440 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1441 struct pipe_framebuffer_state *fb,
1442 struct r600_atom *fb_state,
1443 unsigned *buffers, unsigned *dirty_cbufs,
1444 const union pipe_color_union *color)
1445 {
1446 int i;
1447
1448 /* This function is broken in BE, so just disable this path for now */
1449 #ifdef PIPE_ARCH_BIG_ENDIAN
1450 return;
1451 #endif
1452
1453 if (rctx->render_cond)
1454 return;
1455
1456 for (i = 0; i < fb->nr_cbufs; i++) {
1457 struct r600_texture *tex;
1458 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1459
1460 if (!fb->cbufs[i])
1461 continue;
1462
1463 /* if this colorbuffer is not being cleared */
1464 if (!(*buffers & clear_bit))
1465 continue;
1466
1467 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1468
1469 /* 128-bit formats are unusupported */
1470 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1471 continue;
1472 }
1473
1474 /* the clear is allowed if all layers are bound */
1475 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1476 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1477 continue;
1478 }
1479
1480 /* cannot clear mipmapped textures */
1481 if (fb->cbufs[i]->texture->last_level != 0) {
1482 continue;
1483 }
1484
1485 /* only supported on tiled surfaces */
1486 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1487 continue;
1488 }
1489
1490 /* shared textures can't use fast clear without an explicit flush,
1491 * because there is no way to communicate the clear color among
1492 * all clients
1493 */
1494 if (tex->resource.is_shared &&
1495 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1496 continue;
1497
1498 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1499 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1500 rctx->chip_class >= CIK &&
1501 rctx->screen->info.drm_major == 2 &&
1502 rctx->screen->info.drm_minor < 38) {
1503 continue;
1504 }
1505
1506 if (tex->dcc_buffer) {
1507 uint32_t reset_value;
1508 bool clear_words_needed;
1509
1510 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1511 continue;
1512
1513 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1514
1515 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1516 0, tex->surface.dcc_size, reset_value, true);
1517
1518 if (clear_words_needed)
1519 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1520 } else {
1521 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1522 if (rctx->family == CHIP_STONEY)
1523 continue;
1524
1525 /* ensure CMASK is enabled */
1526 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1527 if (tex->cmask.size == 0) {
1528 continue;
1529 }
1530
1531 /* Do the fast clear. */
1532 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1533 tex->cmask.offset, tex->cmask.size, 0, true);
1534
1535 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1536 }
1537
1538 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1539
1540 if (dirty_cbufs)
1541 *dirty_cbufs |= 1 << i;
1542 rctx->set_atom_dirty(rctx, fb_state, true);
1543 *buffers &= ~clear_bit;
1544 }
1545 }
1546
1547 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1548 {
1549 rscreen->b.resource_from_handle = r600_texture_from_handle;
1550 rscreen->b.resource_get_handle = r600_texture_get_handle;
1551 }
1552
1553 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1554 {
1555 rctx->b.create_surface = r600_create_surface;
1556 rctx->b.surface_destroy = r600_surface_destroy;
1557 }