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gallium/radeon: don't set texture metadata for buffers
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static void r600_texture_init_metadata(struct r600_texture *rtex,
232 struct radeon_bo_metadata *metadata)
233 {
234 struct radeon_surf *surface = &rtex->surface;
235
236 memset(metadata, 0, sizeof(*metadata));
237 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
238 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
239 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
240 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
241 metadata->pipe_config = surface->pipe_config;
242 metadata->bankw = surface->bankw;
243 metadata->bankh = surface->bankh;
244 metadata->tile_split = surface->tile_split;
245 metadata->stencil_tile_split = surface->stencil_tile_split;
246 metadata->mtilea = surface->mtilea;
247 metadata->num_banks = surface->num_banks;
248 metadata->stride = surface->level[0].pitch_bytes;
249 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
250 }
251
252 static boolean r600_texture_get_handle(struct pipe_screen* screen,
253 struct pipe_resource *resource,
254 struct winsys_handle *whandle,
255 unsigned usage)
256 {
257 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
258 struct r600_resource *res = (struct r600_resource*)resource;
259 struct r600_texture *rtex = (struct r600_texture*)resource;
260 struct radeon_bo_metadata metadata;
261
262 if (!res->is_shared) {
263 res->is_shared = true;
264
265 if (resource->target != PIPE_BUFFER) {
266 r600_texture_init_metadata(rtex, &metadata);
267 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
268 }
269 }
270
271 return rscreen->ws->buffer_get_handle(res->buf,
272 rtex->surface.level[0].pitch_bytes,
273 whandle);
274 }
275
276 static void r600_texture_destroy(struct pipe_screen *screen,
277 struct pipe_resource *ptex)
278 {
279 struct r600_texture *rtex = (struct r600_texture*)ptex;
280 struct r600_resource *resource = &rtex->resource;
281
282 if (rtex->flushed_depth_texture)
283 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
284
285 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
286 if (rtex->cmask_buffer != &rtex->resource) {
287 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
288 }
289 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
290 pb_reference(&resource->buf, NULL);
291 FREE(rtex);
292 }
293
294 static const struct u_resource_vtbl r600_texture_vtbl;
295
296 /* The number of samples can be specified independently of the texture. */
297 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
298 struct r600_texture *rtex,
299 unsigned nr_samples,
300 struct r600_fmask_info *out)
301 {
302 /* FMASK is allocated like an ordinary texture. */
303 struct radeon_surf fmask = rtex->surface;
304
305 memset(out, 0, sizeof(*out));
306
307 fmask.bo_alignment = 0;
308 fmask.bo_size = 0;
309 fmask.nsamples = 1;
310 fmask.flags |= RADEON_SURF_FMASK;
311
312 /* Force 2D tiling if it wasn't set. This may occur when creating
313 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
314 * destination buffer must have an FMASK too. */
315 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
316 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
317
318 if (rscreen->chip_class >= SI) {
319 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
320 }
321
322 switch (nr_samples) {
323 case 2:
324 case 4:
325 fmask.bpe = 1;
326 if (rscreen->chip_class <= CAYMAN) {
327 fmask.bankh = 4;
328 }
329 break;
330 case 8:
331 fmask.bpe = 4;
332 break;
333 default:
334 R600_ERR("Invalid sample count for FMASK allocation.\n");
335 return;
336 }
337
338 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
339 * This can be fixed by writing a separate FMASK allocator specifically
340 * for R600-R700 asics. */
341 if (rscreen->chip_class <= R700) {
342 fmask.bpe *= 2;
343 }
344
345 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
346 R600_ERR("Got error in surface_init while allocating FMASK.\n");
347 return;
348 }
349
350 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
351
352 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
353 if (out->slice_tile_max)
354 out->slice_tile_max -= 1;
355
356 out->tile_mode_index = fmask.tiling_index[0];
357 out->pitch_in_pixels = fmask.level[0].nblk_x;
358 out->bank_height = fmask.bankh;
359 out->alignment = MAX2(256, fmask.bo_alignment);
360 out->size = fmask.bo_size;
361 }
362
363 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
364 struct r600_texture *rtex)
365 {
366 r600_texture_get_fmask_info(rscreen, rtex,
367 rtex->resource.b.b.nr_samples, &rtex->fmask);
368
369 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
370 rtex->size = rtex->fmask.offset + rtex->fmask.size;
371 }
372
373 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
374 struct r600_texture *rtex,
375 struct r600_cmask_info *out)
376 {
377 unsigned cmask_tile_width = 8;
378 unsigned cmask_tile_height = 8;
379 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
380 unsigned element_bits = 4;
381 unsigned cmask_cache_bits = 1024;
382 unsigned num_pipes = rscreen->info.num_tile_pipes;
383 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
384
385 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
386 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
387 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
388 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
389 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
390
391 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
392 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
393
394 unsigned base_align = num_pipes * pipe_interleave_bytes;
395 unsigned slice_bytes =
396 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
397
398 assert(macro_tile_width % 128 == 0);
399 assert(macro_tile_height % 128 == 0);
400
401 out->pitch = pitch_elements;
402 out->height = height;
403 out->xalign = macro_tile_width;
404 out->yalign = macro_tile_height;
405 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
406 out->alignment = MAX2(256, base_align);
407 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
408 align(slice_bytes, base_align);
409 }
410
411 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
412 struct r600_texture *rtex,
413 struct r600_cmask_info *out)
414 {
415 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
416 unsigned num_pipes = rscreen->info.num_tile_pipes;
417 unsigned cl_width, cl_height;
418
419 switch (num_pipes) {
420 case 2:
421 cl_width = 32;
422 cl_height = 16;
423 break;
424 case 4:
425 cl_width = 32;
426 cl_height = 32;
427 break;
428 case 8:
429 cl_width = 64;
430 cl_height = 32;
431 break;
432 case 16: /* Hawaii */
433 cl_width = 64;
434 cl_height = 64;
435 break;
436 default:
437 assert(0);
438 return;
439 }
440
441 unsigned base_align = num_pipes * pipe_interleave_bytes;
442
443 unsigned width = align(rtex->surface.npix_x, cl_width*8);
444 unsigned height = align(rtex->surface.npix_y, cl_height*8);
445 unsigned slice_elements = (width * height) / (8*8);
446
447 /* Each element of CMASK is a nibble. */
448 unsigned slice_bytes = slice_elements / 2;
449
450 out->pitch = width;
451 out->height = height;
452 out->xalign = cl_width * 8;
453 out->yalign = cl_height * 8;
454 out->slice_tile_max = (width * height) / (128*128);
455 if (out->slice_tile_max)
456 out->slice_tile_max -= 1;
457
458 out->alignment = MAX2(256, base_align);
459 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
460 align(slice_bytes, base_align);
461 }
462
463 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
464 struct r600_texture *rtex)
465 {
466 if (rscreen->chip_class >= SI) {
467 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
468 } else {
469 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
470 }
471
472 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
473 rtex->size = rtex->cmask.offset + rtex->cmask.size;
474
475 if (rscreen->chip_class >= SI)
476 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
477 else
478 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
479 }
480
481 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
482 struct r600_texture *rtex)
483 {
484 if (rtex->cmask_buffer)
485 return;
486
487 assert(rtex->cmask.size == 0);
488
489 if (rscreen->chip_class >= SI) {
490 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
491 } else {
492 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
493 }
494
495 rtex->cmask_buffer = (struct r600_resource *)
496 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
497 PIPE_USAGE_DEFAULT, rtex->cmask.size);
498 if (rtex->cmask_buffer == NULL) {
499 rtex->cmask.size = 0;
500 return;
501 }
502
503 /* update colorbuffer state bits */
504 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
505
506 if (rscreen->chip_class >= SI)
507 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
508 else
509 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
510 }
511
512 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
513 struct r600_texture *rtex)
514 {
515 if (rscreen->debug_flags & DBG_NO_DCC)
516 return;
517
518 rtex->dcc_buffer = (struct r600_resource *)
519 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
520 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
521 if (rtex->dcc_buffer == NULL) {
522 return;
523 }
524
525 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
526 0xFFFFFFFF, true);
527
528 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
529 }
530
531 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
532 struct r600_texture *rtex)
533 {
534 unsigned cl_width, cl_height, width, height;
535 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
536 unsigned num_pipes = rscreen->info.num_tile_pipes;
537
538 if (rscreen->chip_class <= EVERGREEN &&
539 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
540 return 0;
541
542 /* HW bug on R6xx. */
543 if (rscreen->chip_class == R600 &&
544 (rtex->surface.level[0].npix_x > 7680 ||
545 rtex->surface.level[0].npix_y > 7680))
546 return 0;
547
548 /* HTILE is broken with 1D tiling on old kernels and CIK. */
549 if (rscreen->chip_class >= CIK &&
550 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
551 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
552 return 0;
553
554 /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
555 if (rscreen->family == CHIP_STONEY)
556 num_pipes = 4;
557
558 switch (num_pipes) {
559 case 1:
560 cl_width = 32;
561 cl_height = 16;
562 break;
563 case 2:
564 cl_width = 32;
565 cl_height = 32;
566 break;
567 case 4:
568 cl_width = 64;
569 cl_height = 32;
570 break;
571 case 8:
572 cl_width = 64;
573 cl_height = 64;
574 break;
575 case 16:
576 cl_width = 128;
577 cl_height = 64;
578 break;
579 default:
580 assert(0);
581 return 0;
582 }
583
584 width = align(rtex->surface.npix_x, cl_width * 8);
585 height = align(rtex->surface.npix_y, cl_height * 8);
586
587 slice_elements = (width * height) / (8 * 8);
588 slice_bytes = slice_elements * 4;
589
590 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
591 base_align = num_pipes * pipe_interleave_bytes;
592
593 rtex->htile.pitch = width;
594 rtex->htile.height = height;
595 rtex->htile.xalign = cl_width * 8;
596 rtex->htile.yalign = cl_height * 8;
597
598 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
599 align(slice_bytes, base_align);
600 }
601
602 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
603 struct r600_texture *rtex)
604 {
605 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
606
607 if (!htile_size)
608 return;
609
610 rtex->htile_buffer = (struct r600_resource*)
611 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
612 PIPE_USAGE_DEFAULT, htile_size);
613 if (rtex->htile_buffer == NULL) {
614 /* this is not a fatal error as we can still keep rendering
615 * without htile buffer */
616 R600_ERR("Failed to create buffer object for htile buffer.\n");
617 } else {
618 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
619 htile_size, 0, true);
620 }
621 }
622
623 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
624 {
625 int i;
626
627 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
628 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
629 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
630 rtex->surface.npix_x, rtex->surface.npix_y,
631 rtex->surface.npix_z, rtex->surface.blk_w,
632 rtex->surface.blk_h, rtex->surface.blk_d,
633 rtex->surface.array_size, rtex->surface.last_level,
634 rtex->surface.bpe, rtex->surface.nsamples,
635 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
636
637 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
638 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
639 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
640 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
641 rtex->surface.tile_split, rtex->surface.pipe_config,
642 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
643
644 if (rtex->fmask.size)
645 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
646 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
647 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
648 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
649 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
650
651 if (rtex->cmask.size)
652 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
653 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
654 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
655 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
656 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
657
658 if (rtex->htile_buffer)
659 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
660 "xalign=%u, yalign=%u\n",
661 rtex->htile_buffer->b.b.width0,
662 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
663 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
664
665 if (rtex->dcc_buffer) {
666 fprintf(f, " DCC: size=%u, alignment=%u\n",
667 rtex->dcc_buffer->b.b.width0,
668 rtex->dcc_buffer->buf->alignment);
669 for (i = 0; i <= rtex->surface.last_level; i++)
670 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
671 i, rtex->surface.level[i].dcc_offset);
672 }
673
674 for (i = 0; i <= rtex->surface.last_level; i++)
675 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
676 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
677 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
678 i, rtex->surface.level[i].offset,
679 rtex->surface.level[i].slice_size,
680 u_minify(rtex->resource.b.b.width0, i),
681 u_minify(rtex->resource.b.b.height0, i),
682 u_minify(rtex->resource.b.b.depth0, i),
683 rtex->surface.level[i].nblk_x,
684 rtex->surface.level[i].nblk_y,
685 rtex->surface.level[i].nblk_z,
686 rtex->surface.level[i].pitch_bytes,
687 rtex->surface.level[i].mode);
688
689 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
690 for (i = 0; i <= rtex->surface.last_level; i++) {
691 fprintf(f, " StencilLayout: tilesplit=%u\n",
692 rtex->surface.stencil_tile_split);
693 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
694 "slice_size=%"PRIu64", npix_x=%u, "
695 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
696 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
697 i, rtex->surface.stencil_level[i].offset,
698 rtex->surface.stencil_level[i].slice_size,
699 u_minify(rtex->resource.b.b.width0, i),
700 u_minify(rtex->resource.b.b.height0, i),
701 u_minify(rtex->resource.b.b.depth0, i),
702 rtex->surface.stencil_level[i].nblk_x,
703 rtex->surface.stencil_level[i].nblk_y,
704 rtex->surface.stencil_level[i].nblk_z,
705 rtex->surface.stencil_level[i].pitch_bytes,
706 rtex->surface.stencil_level[i].mode);
707 }
708 }
709 }
710
711 /* Common processing for r600_texture_create and r600_texture_from_handle */
712 static struct r600_texture *
713 r600_texture_create_object(struct pipe_screen *screen,
714 const struct pipe_resource *base,
715 unsigned pitch_in_bytes_override,
716 struct pb_buffer *buf,
717 struct radeon_surf *surface)
718 {
719 struct r600_texture *rtex;
720 struct r600_resource *resource;
721 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
722
723 rtex = CALLOC_STRUCT(r600_texture);
724 if (!rtex)
725 return NULL;
726
727 resource = &rtex->resource;
728 resource->b.b = *base;
729 resource->b.vtbl = &r600_texture_vtbl;
730 pipe_reference_init(&resource->b.b.reference, 1);
731 resource->b.b.screen = screen;
732
733 /* don't include stencil-only formats which we don't support for rendering */
734 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
735
736 rtex->surface = *surface;
737 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
738 FREE(rtex);
739 return NULL;
740 }
741
742 /* Tiled depth textures utilize the non-displayable tile order.
743 * This must be done after r600_setup_surface.
744 * Applies to R600-Cayman. */
745 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
746
747 if (rtex->is_depth) {
748 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
749 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
750 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
751
752 r600_texture_allocate_htile(rscreen, rtex);
753 }
754 } else {
755 if (base->nr_samples > 1) {
756 if (!buf) {
757 r600_texture_allocate_fmask(rscreen, rtex);
758 r600_texture_allocate_cmask(rscreen, rtex);
759 rtex->cmask_buffer = &rtex->resource;
760 }
761 if (!rtex->fmask.size || !rtex->cmask.size) {
762 FREE(rtex);
763 return NULL;
764 }
765 }
766 if (rtex->surface.dcc_size)
767 vi_texture_alloc_dcc_separate(rscreen, rtex);
768 }
769
770 /* Now create the backing buffer. */
771 if (!buf) {
772 if (!r600_init_resource(rscreen, resource, rtex->size,
773 rtex->surface.bo_alignment, TRUE)) {
774 FREE(rtex);
775 return NULL;
776 }
777 } else {
778 resource->buf = buf;
779 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
780 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
781 }
782
783 if (rtex->cmask.size) {
784 /* Initialize the cmask to 0xCC (= compressed state). */
785 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
786 rtex->cmask.offset, rtex->cmask.size,
787 0xCCCCCCCC, true);
788 }
789
790 /* Initialize the CMASK base register value. */
791 rtex->cmask.base_address_reg =
792 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
793
794 if (rscreen->debug_flags & DBG_VM) {
795 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
796 rtex->resource.gpu_address,
797 rtex->resource.gpu_address + rtex->resource.buf->size,
798 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
799 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
800 }
801
802 if (rscreen->debug_flags & DBG_TEX) {
803 puts("Texture:");
804 r600_print_texture_info(rtex, stdout);
805 }
806
807 return rtex;
808 }
809
810 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
811 const struct pipe_resource *templ)
812 {
813 const struct util_format_description *desc = util_format_description(templ->format);
814 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
815
816 /* MSAA resources must be 2D tiled. */
817 if (templ->nr_samples > 1)
818 return RADEON_SURF_MODE_2D;
819
820 /* Transfer resources should be linear. */
821 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
822 return RADEON_SURF_MODE_LINEAR_ALIGNED;
823
824 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
825 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
826 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
827 (templ->target == PIPE_TEXTURE_2D ||
828 templ->target == PIPE_TEXTURE_3D))
829 force_tiling = true;
830
831 /* Handle common candidates for the linear mode.
832 * Compressed textures must always be tiled. */
833 if (!force_tiling && !util_format_is_compressed(templ->format)) {
834 /* Not everything can be linear, so we cannot enforce it
835 * for all textures. */
836 if ((rscreen->debug_flags & DBG_NO_TILING) &&
837 (!util_format_is_depth_or_stencil(templ->format) ||
838 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
839 return RADEON_SURF_MODE_LINEAR_ALIGNED;
840
841 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
842 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
843 return RADEON_SURF_MODE_LINEAR_ALIGNED;
844
845 /* Cursors are linear on SI.
846 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
847 if (rscreen->chip_class >= SI &&
848 (templ->bind & PIPE_BIND_CURSOR))
849 return RADEON_SURF_MODE_LINEAR_ALIGNED;
850
851 if (templ->bind & PIPE_BIND_LINEAR)
852 return RADEON_SURF_MODE_LINEAR_ALIGNED;
853
854 /* Textures with a very small height are recommended to be linear. */
855 if (templ->target == PIPE_TEXTURE_1D ||
856 templ->target == PIPE_TEXTURE_1D_ARRAY ||
857 templ->height0 <= 4)
858 return RADEON_SURF_MODE_LINEAR_ALIGNED;
859
860 /* Textures likely to be mapped often. */
861 if (templ->usage == PIPE_USAGE_STAGING ||
862 templ->usage == PIPE_USAGE_STREAM)
863 return RADEON_SURF_MODE_LINEAR_ALIGNED;
864 }
865
866 /* Make small textures 1D tiled. */
867 if (templ->width0 <= 16 || templ->height0 <= 16 ||
868 (rscreen->debug_flags & DBG_NO_2D_TILING))
869 return RADEON_SURF_MODE_1D;
870
871 /* The allocator will switch to 1D if needed. */
872 return RADEON_SURF_MODE_2D;
873 }
874
875 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
876 const struct pipe_resource *templ)
877 {
878 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
879 struct radeon_surf surface = {0};
880 int r;
881
882 r = r600_init_surface(rscreen, &surface, templ,
883 r600_choose_tiling(rscreen, templ),
884 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
885 if (r) {
886 return NULL;
887 }
888 r = rscreen->ws->surface_best(rscreen->ws, &surface);
889 if (r) {
890 return NULL;
891 }
892 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
893 0, NULL, &surface);
894 }
895
896 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
897 const struct pipe_resource *templ,
898 struct winsys_handle *whandle,
899 unsigned usage)
900 {
901 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
902 struct pb_buffer *buf = NULL;
903 unsigned stride = 0;
904 unsigned array_mode;
905 struct radeon_surf surface;
906 int r;
907 struct radeon_bo_metadata metadata = {};
908
909 /* Support only 2D textures without mipmaps */
910 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
911 templ->depth0 != 1 || templ->last_level != 0)
912 return NULL;
913
914 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
915 if (!buf)
916 return NULL;
917
918 rscreen->ws->buffer_get_metadata(buf, &metadata);
919
920 surface.bankw = metadata.bankw;
921 surface.bankh = metadata.bankh;
922 surface.tile_split = metadata.tile_split;
923 surface.stencil_tile_split = metadata.stencil_tile_split;
924 surface.mtilea = metadata.mtilea;
925
926 if (metadata.macrotile == RADEON_LAYOUT_TILED)
927 array_mode = RADEON_SURF_MODE_2D;
928 else if (metadata.microtile == RADEON_LAYOUT_TILED)
929 array_mode = RADEON_SURF_MODE_1D;
930 else
931 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
932
933 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
934 if (r) {
935 return NULL;
936 }
937
938 if (metadata.scanout)
939 surface.flags |= RADEON_SURF_SCANOUT;
940
941 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
942 stride, buf, &surface);
943 }
944
945 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
946 struct pipe_resource *texture,
947 struct r600_texture **staging)
948 {
949 struct r600_texture *rtex = (struct r600_texture*)texture;
950 struct pipe_resource resource;
951 struct r600_texture **flushed_depth_texture = staging ?
952 staging : &rtex->flushed_depth_texture;
953
954 if (!staging && rtex->flushed_depth_texture)
955 return true; /* it's ready */
956
957 resource.target = texture->target;
958 resource.format = texture->format;
959 resource.width0 = texture->width0;
960 resource.height0 = texture->height0;
961 resource.depth0 = texture->depth0;
962 resource.array_size = texture->array_size;
963 resource.last_level = texture->last_level;
964 resource.nr_samples = texture->nr_samples;
965 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
966 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
967 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
968
969 if (staging)
970 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
971
972 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
973 if (*flushed_depth_texture == NULL) {
974 R600_ERR("failed to create temporary texture to hold flushed depth\n");
975 return false;
976 }
977
978 (*flushed_depth_texture)->is_flushing_texture = TRUE;
979 (*flushed_depth_texture)->non_disp_tiling = false;
980 return true;
981 }
982
983 /**
984 * Initialize the pipe_resource descriptor to be of the same size as the box,
985 * which is supposed to hold a subregion of the texture "orig" at the given
986 * mipmap level.
987 */
988 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
989 struct pipe_resource *orig,
990 const struct pipe_box *box,
991 unsigned level, unsigned flags)
992 {
993 memset(res, 0, sizeof(*res));
994 res->format = orig->format;
995 res->width0 = box->width;
996 res->height0 = box->height;
997 res->depth0 = 1;
998 res->array_size = 1;
999 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1000 res->flags = flags;
1001
1002 /* We must set the correct texture target and dimensions for a 3D box. */
1003 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1004 res->target = orig->target;
1005 else
1006 res->target = PIPE_TEXTURE_2D;
1007
1008 switch (res->target) {
1009 case PIPE_TEXTURE_1D_ARRAY:
1010 case PIPE_TEXTURE_2D_ARRAY:
1011 case PIPE_TEXTURE_CUBE_ARRAY:
1012 res->array_size = box->depth;
1013 break;
1014 case PIPE_TEXTURE_3D:
1015 res->depth0 = box->depth;
1016 break;
1017 default:;
1018 }
1019 }
1020
1021 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1022 struct pipe_resource *texture,
1023 unsigned level,
1024 unsigned usage,
1025 const struct pipe_box *box,
1026 struct pipe_transfer **ptransfer)
1027 {
1028 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1029 struct r600_texture *rtex = (struct r600_texture*)texture;
1030 struct r600_transfer *trans;
1031 boolean use_staging_texture = FALSE;
1032 struct r600_resource *buf;
1033 unsigned offset = 0;
1034 char *map;
1035
1036 /* We cannot map a tiled texture directly because the data is
1037 * in a different order, therefore we do detiling using a blit.
1038 *
1039 * Also, use a temporary in GTT memory for read transfers, as
1040 * the CPU is much happier reading out of cached system memory
1041 * than uncached VRAM.
1042 */
1043 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1044 use_staging_texture = TRUE;
1045 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1046 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1047 /* Untiled buffers in VRAM, which is slow for CPU reads */
1048 use_staging_texture = TRUE;
1049 } else if (!(usage & PIPE_TRANSFER_READ) &&
1050 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1051 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1052 /* Use a staging texture for uploads if the underlying BO is busy. */
1053 use_staging_texture = TRUE;
1054 }
1055
1056 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1057 use_staging_texture = FALSE;
1058 }
1059
1060 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1061 return NULL;
1062 }
1063
1064 trans = CALLOC_STRUCT(r600_transfer);
1065 if (!trans)
1066 return NULL;
1067 trans->transfer.resource = texture;
1068 trans->transfer.level = level;
1069 trans->transfer.usage = usage;
1070 trans->transfer.box = *box;
1071
1072 if (rtex->is_depth) {
1073 struct r600_texture *staging_depth;
1074
1075 if (rtex->resource.b.b.nr_samples > 1) {
1076 /* MSAA depth buffers need to be converted to single sample buffers.
1077 *
1078 * Mapping MSAA depth buffers can occur if ReadPixels is called
1079 * with a multisample GLX visual.
1080 *
1081 * First downsample the depth buffer to a temporary texture,
1082 * then decompress the temporary one to staging.
1083 *
1084 * Only the region being mapped is transfered.
1085 */
1086 struct pipe_resource resource;
1087
1088 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1089
1090 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1091 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1092 FREE(trans);
1093 return NULL;
1094 }
1095
1096 if (usage & PIPE_TRANSFER_READ) {
1097 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1098 if (!temp) {
1099 R600_ERR("failed to create a temporary depth texture\n");
1100 FREE(trans);
1101 return NULL;
1102 }
1103
1104 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1105 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1106 0, 0, 0, box->depth, 0, 0);
1107 pipe_resource_reference(&temp, NULL);
1108 }
1109 }
1110 else {
1111 /* XXX: only readback the rectangle which is being mapped? */
1112 /* XXX: when discard is true, no need to read back from depth texture */
1113 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1114 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1115 FREE(trans);
1116 return NULL;
1117 }
1118
1119 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1120 level, level,
1121 box->z, box->z + box->depth - 1,
1122 0, 0);
1123
1124 offset = r600_texture_get_offset(staging_depth, level, box);
1125 }
1126
1127 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1128 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1129 trans->staging = (struct r600_resource*)staging_depth;
1130 } else if (use_staging_texture) {
1131 struct pipe_resource resource;
1132 struct r600_texture *staging;
1133
1134 r600_init_temp_resource_from_box(&resource, texture, box, level,
1135 R600_RESOURCE_FLAG_TRANSFER);
1136 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1137 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1138
1139 /* Create the temporary texture. */
1140 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1141 if (!staging) {
1142 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1143 FREE(trans);
1144 return NULL;
1145 }
1146 trans->staging = &staging->resource;
1147 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1148 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1149 if (usage & PIPE_TRANSFER_READ) {
1150 r600_copy_to_staging_texture(ctx, trans);
1151 }
1152 } else {
1153 /* the resource is mapped directly */
1154 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1155 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1156 offset = r600_texture_get_offset(rtex, level, box);
1157 }
1158
1159 if (trans->staging) {
1160 buf = trans->staging;
1161 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1162 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1163 } else {
1164 buf = &rtex->resource;
1165 }
1166
1167 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1168 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1169 FREE(trans);
1170 return NULL;
1171 }
1172
1173 *ptransfer = &trans->transfer;
1174 return map + offset;
1175 }
1176
1177 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1178 struct pipe_transfer* transfer)
1179 {
1180 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1181 struct pipe_resource *texture = transfer->resource;
1182 struct r600_texture *rtex = (struct r600_texture*)texture;
1183
1184 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1185 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1186 ctx->resource_copy_region(ctx, texture, transfer->level,
1187 transfer->box.x, transfer->box.y, transfer->box.z,
1188 &rtransfer->staging->b.b, transfer->level,
1189 &transfer->box);
1190 } else {
1191 r600_copy_from_staging_texture(ctx, rtransfer);
1192 }
1193 }
1194
1195 if (rtransfer->staging)
1196 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1197
1198 FREE(transfer);
1199 }
1200
1201 static const struct u_resource_vtbl r600_texture_vtbl =
1202 {
1203 NULL, /* get_handle */
1204 r600_texture_destroy, /* resource_destroy */
1205 r600_texture_transfer_map, /* transfer_map */
1206 u_default_transfer_flush_region, /* transfer_flush_region */
1207 r600_texture_transfer_unmap, /* transfer_unmap */
1208 NULL /* transfer_inline_write */
1209 };
1210
1211 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1212 struct pipe_resource *texture,
1213 const struct pipe_surface *templ,
1214 unsigned width, unsigned height)
1215 {
1216 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1217
1218 if (!surface)
1219 return NULL;
1220
1221 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1222 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1223
1224 pipe_reference_init(&surface->base.reference, 1);
1225 pipe_resource_reference(&surface->base.texture, texture);
1226 surface->base.context = pipe;
1227 surface->base.format = templ->format;
1228 surface->base.width = width;
1229 surface->base.height = height;
1230 surface->base.u = templ->u;
1231 return &surface->base;
1232 }
1233
1234 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1235 struct pipe_resource *tex,
1236 const struct pipe_surface *templ)
1237 {
1238 unsigned level = templ->u.tex.level;
1239 unsigned width = u_minify(tex->width0, level);
1240 unsigned height = u_minify(tex->height0, level);
1241
1242 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1243 const struct util_format_description *tex_desc
1244 = util_format_description(tex->format);
1245 const struct util_format_description *templ_desc
1246 = util_format_description(templ->format);
1247
1248 assert(tex_desc->block.bits == templ_desc->block.bits);
1249
1250 /* Adjust size of surface if and only if the block width or
1251 * height is changed. */
1252 if (tex_desc->block.width != templ_desc->block.width ||
1253 tex_desc->block.height != templ_desc->block.height) {
1254 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1255 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1256
1257 width = nblks_x * templ_desc->block.width;
1258 height = nblks_y * templ_desc->block.height;
1259 }
1260 }
1261
1262 return r600_create_surface_custom(pipe, tex, templ, width, height);
1263 }
1264
1265 static void r600_surface_destroy(struct pipe_context *pipe,
1266 struct pipe_surface *surface)
1267 {
1268 struct r600_surface *surf = (struct r600_surface*)surface;
1269 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1270 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1271 pipe_resource_reference(&surface->texture, NULL);
1272 FREE(surface);
1273 }
1274
1275 unsigned r600_translate_colorswap(enum pipe_format format)
1276 {
1277 const struct util_format_description *desc = util_format_description(format);
1278
1279 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1280
1281 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1282 return V_0280A0_SWAP_STD;
1283
1284 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1285 return ~0U;
1286
1287 switch (desc->nr_channels) {
1288 case 1:
1289 if (HAS_SWIZZLE(0,X))
1290 return V_0280A0_SWAP_STD; /* X___ */
1291 else if (HAS_SWIZZLE(3,X))
1292 return V_0280A0_SWAP_ALT_REV; /* ___X */
1293 break;
1294 case 2:
1295 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1296 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1297 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1298 return V_0280A0_SWAP_STD; /* XY__ */
1299 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1300 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1301 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1302 return V_0280A0_SWAP_STD_REV; /* YX__ */
1303 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1304 return V_0280A0_SWAP_ALT; /* X__Y */
1305 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1306 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1307 break;
1308 case 3:
1309 if (HAS_SWIZZLE(0,X))
1310 return V_0280A0_SWAP_STD; /* XYZ */
1311 else if (HAS_SWIZZLE(0,Z))
1312 return V_0280A0_SWAP_STD_REV; /* ZYX */
1313 break;
1314 case 4:
1315 /* check the middle channels, the 1st and 4th channel can be NONE */
1316 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1317 return V_0280A0_SWAP_STD; /* XYZW */
1318 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1319 return V_0280A0_SWAP_STD_REV; /* WZYX */
1320 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1321 return V_0280A0_SWAP_ALT; /* ZYXW */
1322 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
1323 return V_0280A0_SWAP_ALT_REV; /* YZWX */
1324 break;
1325 }
1326 return ~0U;
1327 }
1328
1329 static void evergreen_set_clear_color(struct r600_texture *rtex,
1330 enum pipe_format surface_format,
1331 const union pipe_color_union *color)
1332 {
1333 union util_color uc;
1334
1335 memset(&uc, 0, sizeof(uc));
1336
1337 if (util_format_is_pure_uint(surface_format)) {
1338 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1339 } else if (util_format_is_pure_sint(surface_format)) {
1340 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1341 } else {
1342 util_pack_color(color->f, surface_format, &uc);
1343 }
1344
1345 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1346 }
1347
1348 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1349 const union pipe_color_union *color,
1350 uint32_t* reset_value,
1351 bool* clear_words_needed)
1352 {
1353 bool values[4] = {};
1354 int i;
1355 bool main_value = false;
1356 bool extra_value = false;
1357 int extra_channel;
1358 const struct util_format_description *desc = util_format_description(surface_format);
1359
1360 *clear_words_needed = true;
1361 *reset_value = 0x20202020U;
1362
1363 /* If we want to clear without needing a fast clear eliminate step, we
1364 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1365 * have two sets of flags, one for the last or first channel(extra) and
1366 * one for the other channels(main).
1367 */
1368
1369 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1370 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1371 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1372 extra_channel = -1;
1373 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1374 if(r600_translate_colorswap(surface_format) <= 1)
1375 extra_channel = desc->nr_channels - 1;
1376 else
1377 extra_channel = 0;
1378 } else
1379 return;
1380
1381 for (i = 0; i < 4; ++i) {
1382 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1383
1384 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1385 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1386 continue;
1387
1388 if (util_format_is_pure_sint(surface_format)) {
1389 values[i] = color->i[i] != 0;
1390 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1391 return;
1392 } else if (util_format_is_pure_uint(surface_format)) {
1393 values[i] = color->ui[i] != 0U;
1394 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1395 return;
1396 } else {
1397 values[i] = color->f[i] != 0.0F;
1398 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1399 return;
1400 }
1401
1402 if (index == extra_channel)
1403 extra_value = values[i];
1404 else
1405 main_value = values[i];
1406 }
1407
1408 for (int i = 0; i < 4; ++i)
1409 if (values[i] != main_value &&
1410 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1411 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1412 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1413 return;
1414
1415 *clear_words_needed = false;
1416 if (main_value)
1417 *reset_value |= 0x80808080U;
1418
1419 if (extra_value)
1420 *reset_value |= 0x40404040U;
1421 }
1422
1423 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1424 struct pipe_framebuffer_state *fb,
1425 struct r600_atom *fb_state,
1426 unsigned *buffers, unsigned *dirty_cbufs,
1427 const union pipe_color_union *color)
1428 {
1429 int i;
1430
1431 /* This function is broken in BE, so just disable this path for now */
1432 #ifdef PIPE_ARCH_BIG_ENDIAN
1433 return;
1434 #endif
1435
1436 if (rctx->render_cond)
1437 return;
1438
1439 for (i = 0; i < fb->nr_cbufs; i++) {
1440 struct r600_texture *tex;
1441 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1442
1443 if (!fb->cbufs[i])
1444 continue;
1445
1446 /* if this colorbuffer is not being cleared */
1447 if (!(*buffers & clear_bit))
1448 continue;
1449
1450 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1451
1452 /* 128-bit formats are unusupported */
1453 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1454 continue;
1455 }
1456
1457 /* the clear is allowed if all layers are bound */
1458 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1459 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1460 continue;
1461 }
1462
1463 /* cannot clear mipmapped textures */
1464 if (fb->cbufs[i]->texture->last_level != 0) {
1465 continue;
1466 }
1467
1468 /* only supported on tiled surfaces */
1469 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1470 continue;
1471 }
1472
1473 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1474 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1475 rctx->chip_class >= CIK &&
1476 rctx->screen->info.drm_major == 2 &&
1477 rctx->screen->info.drm_minor < 38) {
1478 continue;
1479 }
1480
1481 if (tex->dcc_buffer) {
1482 uint32_t reset_value;
1483 bool clear_words_needed;
1484
1485 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1486 continue;
1487
1488 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1489
1490 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1491 0, tex->surface.dcc_size, reset_value, true);
1492
1493 if (clear_words_needed)
1494 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1495 } else {
1496 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1497 if (rctx->family == CHIP_STONEY)
1498 continue;
1499
1500 /* ensure CMASK is enabled */
1501 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1502 if (tex->cmask.size == 0) {
1503 continue;
1504 }
1505
1506 /* Do the fast clear. */
1507 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1508 tex->cmask.offset, tex->cmask.size, 0, true);
1509
1510 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1511 }
1512
1513 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1514
1515 if (dirty_cbufs)
1516 *dirty_cbufs |= 1 << i;
1517 rctx->set_atom_dirty(rctx, fb_state, true);
1518 *buffers &= ~clear_bit;
1519 }
1520 }
1521
1522 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1523 {
1524 rscreen->b.resource_from_handle = r600_texture_from_handle;
1525 rscreen->b.resource_get_handle = r600_texture_get_handle;
1526 }
1527
1528 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1529 {
1530 rctx->b.create_surface = r600_create_surface;
1531 rctx->b.surface_destroy = r600_surface_destroy;
1532 }