projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g,radeonsi: disable fast clear if render condition is on
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surface *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static boolean r600_texture_get_handle(struct pipe_screen* screen,
232 struct pipe_resource *ptex,
233 struct winsys_handle *whandle)
234 {
235 struct r600_texture *rtex = (struct r600_texture*)ptex;
236 struct r600_resource *resource = &rtex->resource;
237 struct radeon_surface *surface = &rtex->surface;
238 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
239
240 rscreen->ws->buffer_set_tiling(resource->buf,
241 NULL,
242 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
243 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
244 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
245 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
246 surface->bankw, surface->bankh,
247 surface->tile_split,
248 surface->stencil_tile_split,
249 surface->mtilea,
250 surface->level[0].pitch_bytes,
251 (surface->flags & RADEON_SURF_SCANOUT) != 0);
252
253 return rscreen->ws->buffer_get_handle(resource->buf,
254 surface->level[0].pitch_bytes, whandle);
255 }
256
257 static void r600_texture_destroy(struct pipe_screen *screen,
258 struct pipe_resource *ptex)
259 {
260 struct r600_texture *rtex = (struct r600_texture*)ptex;
261 struct r600_resource *resource = &rtex->resource;
262
263 if (rtex->flushed_depth_texture)
264 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
265
266 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
267 if (rtex->cmask_buffer != &rtex->resource) {
268 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
269 }
270 pb_reference(&resource->buf, NULL);
271 FREE(rtex);
272 }
273
274 static const struct u_resource_vtbl r600_texture_vtbl;
275
276 /* The number of samples can be specified independently of the texture. */
277 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
278 struct r600_texture *rtex,
279 unsigned nr_samples,
280 struct r600_fmask_info *out)
281 {
282 /* FMASK is allocated like an ordinary texture. */
283 struct radeon_surface fmask = rtex->surface;
284
285 memset(out, 0, sizeof(*out));
286
287 fmask.bo_alignment = 0;
288 fmask.bo_size = 0;
289 fmask.nsamples = 1;
290 fmask.flags |= RADEON_SURF_FMASK;
291
292 /* Force 2D tiling if it wasn't set. This may occur when creating
293 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
294 * destination buffer must have an FMASK too. */
295 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
296 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
297
298 if (rscreen->chip_class >= SI) {
299 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
300 }
301
302 switch (nr_samples) {
303 case 2:
304 case 4:
305 fmask.bpe = 1;
306 if (rscreen->chip_class <= CAYMAN) {
307 fmask.bankh = 4;
308 }
309 break;
310 case 8:
311 fmask.bpe = 4;
312 break;
313 default:
314 R600_ERR("Invalid sample count for FMASK allocation.\n");
315 return;
316 }
317
318 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
319 * This can be fixed by writing a separate FMASK allocator specifically
320 * for R600-R700 asics. */
321 if (rscreen->chip_class <= R700) {
322 fmask.bpe *= 2;
323 }
324
325 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
326 R600_ERR("Got error in surface_init while allocating FMASK.\n");
327 return;
328 }
329
330 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
331
332 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
333 if (out->slice_tile_max)
334 out->slice_tile_max -= 1;
335
336 out->tile_mode_index = fmask.tiling_index[0];
337 out->pitch = fmask.level[0].nblk_x;
338 out->bank_height = fmask.bankh;
339 out->alignment = MAX2(256, fmask.bo_alignment);
340 out->size = fmask.bo_size;
341 }
342
343 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
344 struct r600_texture *rtex)
345 {
346 r600_texture_get_fmask_info(rscreen, rtex,
347 rtex->resource.b.b.nr_samples, &rtex->fmask);
348
349 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
350 rtex->size = rtex->fmask.offset + rtex->fmask.size;
351 }
352
353 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
354 struct r600_texture *rtex,
355 struct r600_cmask_info *out)
356 {
357 unsigned cmask_tile_width = 8;
358 unsigned cmask_tile_height = 8;
359 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
360 unsigned element_bits = 4;
361 unsigned cmask_cache_bits = 1024;
362 unsigned num_pipes = rscreen->tiling_info.num_channels;
363 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
364
365 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
366 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
367 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
368 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
369 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
370
371 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
372 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
373
374 unsigned base_align = num_pipes * pipe_interleave_bytes;
375 unsigned slice_bytes =
376 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
377
378 assert(macro_tile_width % 128 == 0);
379 assert(macro_tile_height % 128 == 0);
380
381 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
382 out->alignment = MAX2(256, base_align);
383 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
384 }
385
386 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
387 struct r600_texture *rtex,
388 struct r600_cmask_info *out)
389 {
390 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
391 unsigned num_pipes = rscreen->tiling_info.num_channels;
392 unsigned cl_width, cl_height;
393
394 switch (num_pipes) {
395 case 2:
396 cl_width = 32;
397 cl_height = 16;
398 break;
399 case 4:
400 cl_width = 32;
401 cl_height = 32;
402 break;
403 case 8:
404 cl_width = 64;
405 cl_height = 32;
406 break;
407 case 16: /* Hawaii */
408 cl_width = 64;
409 cl_height = 64;
410 break;
411 default:
412 assert(0);
413 return;
414 }
415
416 unsigned base_align = num_pipes * pipe_interleave_bytes;
417
418 unsigned width = align(rtex->surface.npix_x, cl_width*8);
419 unsigned height = align(rtex->surface.npix_y, cl_height*8);
420 unsigned slice_elements = (width * height) / (8*8);
421
422 /* Each element of CMASK is a nibble. */
423 unsigned slice_bytes = slice_elements / 2;
424
425 out->slice_tile_max = (width * height) / (128*128);
426 if (out->slice_tile_max)
427 out->slice_tile_max -= 1;
428
429 out->alignment = MAX2(256, base_align);
430 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
431 }
432
433 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
434 struct r600_texture *rtex)
435 {
436 if (rscreen->chip_class >= SI) {
437 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
438 } else {
439 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
440 }
441
442 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
443 rtex->size = rtex->cmask.offset + rtex->cmask.size;
444
445 if (rscreen->chip_class >= SI)
446 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
447 else
448 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
449 }
450
451 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
452 struct r600_texture *rtex)
453 {
454 if (rtex->cmask_buffer)
455 return;
456
457 assert(rtex->cmask.size == 0);
458
459 if (rscreen->chip_class >= SI) {
460 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
461 } else {
462 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
463 }
464
465 rtex->cmask_buffer = (struct r600_resource *)
466 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
467 PIPE_USAGE_DEFAULT, rtex->cmask.size);
468 if (rtex->cmask_buffer == NULL) {
469 rtex->cmask.size = 0;
470 return;
471 }
472
473 /* update colorbuffer state bits */
474 rtex->cmask.base_address_reg =
475 r600_resource_va(&rscreen->b, &rtex->cmask_buffer->b.b) >> 8;
476
477 if (rscreen->chip_class >= SI)
478 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
479 else
480 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
481 }
482
483 static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
484 struct r600_texture *rtex)
485 {
486 unsigned cl_width, cl_height, width, height;
487 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
488 unsigned num_pipes = rscreen->tiling_info.num_channels;
489
490 /* HTILE is broken with 1D tiling on old kernels and CIK. */
491 if (rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
492 rscreen->chip_class >= CIK && rscreen->info.drm_minor < 38)
493 return 0;
494
495 switch (num_pipes) {
496 case 2:
497 cl_width = 32;
498 cl_height = 32;
499 break;
500 case 4:
501 cl_width = 64;
502 cl_height = 32;
503 break;
504 case 8:
505 cl_width = 64;
506 cl_height = 64;
507 break;
508 case 16:
509 cl_width = 128;
510 cl_height = 64;
511 break;
512 default:
513 assert(0);
514 return 0;
515 }
516
517 width = align(rtex->surface.npix_x, cl_width * 8);
518 height = align(rtex->surface.npix_y, cl_height * 8);
519
520 slice_elements = (width * height) / (8 * 8);
521 slice_bytes = slice_elements * 4;
522
523 pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
524 base_align = num_pipes * pipe_interleave_bytes;
525
526 return rtex->surface.array_size * align(slice_bytes, base_align);
527 }
528
529 static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
530 struct r600_texture *rtex)
531 {
532 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
533 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
534 unsigned npipes = rscreen->info.r600_num_tile_pipes;
535 unsigned htile_size;
536
537 /* XXX also use it for other texture targets */
538 if (rscreen->info.drm_minor < 26 ||
539 rtex->resource.b.b.target != PIPE_TEXTURE_2D ||
540 rtex->surface.level[0].nblk_x < 32 ||
541 rtex->surface.level[0].nblk_y < 32) {
542 return 0;
543 }
544
545 /* HW bug on R6xx. */
546 if (rscreen->chip_class == R600 &&
547 (rtex->surface.level[0].npix_x > 7680 ||
548 rtex->surface.level[0].npix_y > 7680))
549 return 0;
550
551 /* this alignment and htile size only apply to linear htile buffer */
552 sw = align(sw, 16 << 3);
553 sh = align(sh, npipes << 3);
554 htile_size = (sw >> 3) * (sh >> 3) * 4;
555 /* must be aligned with 2K * npipes */
556 htile_size = align(htile_size, (2 << 10) * npipes);
557 return htile_size;
558 }
559
560 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
561 struct r600_texture *rtex)
562 {
563 unsigned htile_size;
564 if (rscreen->chip_class >= SI) {
565 htile_size = si_texture_htile_alloc_size(rscreen, rtex);
566 } else {
567 htile_size = r600_texture_htile_alloc_size(rscreen, rtex);
568 }
569
570 if (!htile_size)
571 return;
572
573 /* XXX don't allocate it separately */
574 rtex->htile_buffer = (struct r600_resource*)
575 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
576 PIPE_USAGE_DEFAULT, htile_size);
577 if (rtex->htile_buffer == NULL) {
578 /* this is not a fatal error as we can still keep rendering
579 * without htile buffer */
580 R600_ERR("Failed to create buffer object for htile buffer.\n");
581 } else {
582 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0, htile_size, 0);
583 }
584 }
585
586 /* Common processing for r600_texture_create and r600_texture_from_handle */
587 static struct r600_texture *
588 r600_texture_create_object(struct pipe_screen *screen,
589 const struct pipe_resource *base,
590 unsigned pitch_in_bytes_override,
591 struct pb_buffer *buf,
592 struct radeon_surface *surface)
593 {
594 struct r600_texture *rtex;
595 struct r600_resource *resource;
596 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
597 uint64_t va;
598
599 rtex = CALLOC_STRUCT(r600_texture);
600 if (rtex == NULL)
601 return NULL;
602
603 resource = &rtex->resource;
604 resource->b.b = *base;
605 resource->b.vtbl = &r600_texture_vtbl;
606 pipe_reference_init(&resource->b.b.reference, 1);
607 resource->b.b.screen = screen;
608 rtex->pitch_override = pitch_in_bytes_override;
609
610 /* don't include stencil-only formats which we don't support for rendering */
611 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
612
613 rtex->surface = *surface;
614 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
615 FREE(rtex);
616 return NULL;
617 }
618
619 /* Tiled depth textures utilize the non-displayable tile order.
620 * This must be done after r600_setup_surface.
621 * Applies to R600-Cayman. */
622 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
623
624 if (rtex->is_depth) {
625 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
626 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
627 (rscreen->debug_flags & DBG_HYPERZ)) {
628
629 r600_texture_allocate_htile(rscreen, rtex);
630 }
631 } else {
632 if (base->nr_samples > 1) {
633 if (!buf) {
634 r600_texture_allocate_fmask(rscreen, rtex);
635 r600_texture_allocate_cmask(rscreen, rtex);
636 rtex->cmask_buffer = &rtex->resource;
637 }
638 if (!rtex->fmask.size || !rtex->cmask.size) {
639 FREE(rtex);
640 return NULL;
641 }
642 }
643 }
644
645 /* Now create the backing buffer. */
646 if (!buf) {
647 if (!r600_init_resource(rscreen, resource, rtex->size,
648 rtex->surface.bo_alignment, TRUE)) {
649 FREE(rtex);
650 return NULL;
651 }
652 } else {
653 resource->buf = buf;
654 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
655 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->cs_buf);
656 }
657
658 if (rtex->cmask.size) {
659 /* Initialize the cmask to 0xCC (= compressed state). */
660 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
661 rtex->cmask.offset, rtex->cmask.size, 0xCCCCCCCC);
662 }
663
664 /* Initialize the CMASK base register value. */
665 va = r600_resource_va(&rscreen->b, &rtex->resource.b.b);
666 rtex->cmask.base_address_reg = (va + rtex->cmask.offset) >> 8;
667
668 if (rscreen->debug_flags & DBG_VM) {
669 fprintf(stderr, "VM start=0x%"PRIu64" end=0x%"PRIu64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
670 r600_resource_va(screen, &rtex->resource.b.b),
671 r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
672 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
673 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
674 }
675
676 if (rscreen->debug_flags & DBG_TEX ||
677 (rtex->resource.b.b.last_level > 0 && rscreen->debug_flags & DBG_TEXMIP)) {
678 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
679 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
680 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
681 rtex->surface.npix_x, rtex->surface.npix_y,
682 rtex->surface.npix_z, rtex->surface.blk_w,
683 rtex->surface.blk_h, rtex->surface.blk_d,
684 rtex->surface.array_size, rtex->surface.last_level,
685 rtex->surface.bpe, rtex->surface.nsamples,
686 rtex->surface.flags, util_format_short_name(base->format));
687 for (int i = 0; i <= rtex->surface.last_level; i++) {
688 printf(" L %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
689 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
690 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
691 i, rtex->surface.level[i].offset,
692 rtex->surface.level[i].slice_size,
693 u_minify(rtex->resource.b.b.width0, i),
694 u_minify(rtex->resource.b.b.height0, i),
695 u_minify(rtex->resource.b.b.depth0, i),
696 rtex->surface.level[i].nblk_x,
697 rtex->surface.level[i].nblk_y,
698 rtex->surface.level[i].nblk_z,
699 rtex->surface.level[i].pitch_bytes,
700 rtex->surface.level[i].mode);
701 }
702 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
703 for (int i = 0; i <= rtex->surface.last_level; i++) {
704 printf(" S %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
705 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
706 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
707 i, rtex->surface.stencil_level[i].offset,
708 rtex->surface.stencil_level[i].slice_size,
709 u_minify(rtex->resource.b.b.width0, i),
710 u_minify(rtex->resource.b.b.height0, i),
711 u_minify(rtex->resource.b.b.depth0, i),
712 rtex->surface.stencil_level[i].nblk_x,
713 rtex->surface.stencil_level[i].nblk_y,
714 rtex->surface.stencil_level[i].nblk_z,
715 rtex->surface.stencil_level[i].pitch_bytes,
716 rtex->surface.stencil_level[i].mode);
717 }
718 }
719 }
720 return rtex;
721 }
722
723 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
724 const struct pipe_resource *templ)
725 {
726 const struct util_format_description *desc = util_format_description(templ->format);
727
728 /* MSAA resources must be 2D tiled. */
729 if (templ->nr_samples > 1)
730 return RADEON_SURF_MODE_2D;
731
732 /* Transfer resources should be linear. */
733 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
734 return RADEON_SURF_MODE_LINEAR_ALIGNED;
735
736 /* Handle common candidates for the linear mode.
737 * Compressed textures must always be tiled. */
738 if (!(templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) &&
739 !util_format_is_compressed(templ->format)) {
740 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600-Cayman. */
741 if (rscreen->chip_class <= CAYMAN &&
742 desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
743 return RADEON_SURF_MODE_LINEAR_ALIGNED;
744
745 /* Cursors are linear on SI.
746 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
747 if (rscreen->chip_class >= SI &&
748 (templ->bind & PIPE_BIND_CURSOR))
749 return RADEON_SURF_MODE_LINEAR_ALIGNED;
750
751 if (templ->bind & PIPE_BIND_LINEAR)
752 return RADEON_SURF_MODE_LINEAR_ALIGNED;
753
754 /* Textures with a very small height are recommended to be linear. */
755 if (templ->target == PIPE_TEXTURE_1D ||
756 templ->target == PIPE_TEXTURE_1D_ARRAY ||
757 templ->height0 <= 4)
758 return RADEON_SURF_MODE_LINEAR_ALIGNED;
759
760 /* Textures likely to be mapped often. */
761 if (templ->usage == PIPE_USAGE_STAGING ||
762 templ->usage == PIPE_USAGE_STREAM)
763 return RADEON_SURF_MODE_LINEAR_ALIGNED;
764 }
765
766 /* Make small textures 1D tiled. */
767 if (templ->width0 <= 16 || templ->height0 <= 16)
768 return RADEON_SURF_MODE_1D;
769
770 /* The allocator will switch to 1D if needed. */
771 return RADEON_SURF_MODE_2D;
772 }
773
774 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
775 const struct pipe_resource *templ)
776 {
777 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
778 struct radeon_surface surface = {0};
779 int r;
780
781 r = r600_init_surface(rscreen, &surface, templ,
782 r600_choose_tiling(rscreen, templ),
783 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
784 if (r) {
785 return NULL;
786 }
787 r = rscreen->ws->surface_best(rscreen->ws, &surface);
788 if (r) {
789 return NULL;
790 }
791 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
792 0, NULL, &surface);
793 }
794
795 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
796 const struct pipe_resource *templ,
797 struct winsys_handle *whandle)
798 {
799 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
800 struct pb_buffer *buf = NULL;
801 unsigned stride = 0;
802 unsigned array_mode;
803 enum radeon_bo_layout micro, macro;
804 struct radeon_surface surface;
805 bool scanout;
806 int r;
807
808 /* Support only 2D textures without mipmaps */
809 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
810 templ->depth0 != 1 || templ->last_level != 0)
811 return NULL;
812
813 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
814 if (!buf)
815 return NULL;
816
817 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
818 &surface.bankw, &surface.bankh,
819 &surface.tile_split,
820 &surface.stencil_tile_split,
821 &surface.mtilea, &scanout);
822
823 if (macro == RADEON_LAYOUT_TILED)
824 array_mode = RADEON_SURF_MODE_2D;
825 else if (micro == RADEON_LAYOUT_TILED)
826 array_mode = RADEON_SURF_MODE_1D;
827 else
828 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
829
830 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
831 if (r) {
832 return NULL;
833 }
834
835 if (scanout)
836 surface.flags |= RADEON_SURF_SCANOUT;
837
838 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
839 stride, buf, &surface);
840 }
841
842 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
843 struct pipe_resource *texture,
844 struct r600_texture **staging)
845 {
846 struct r600_texture *rtex = (struct r600_texture*)texture;
847 struct pipe_resource resource;
848 struct r600_texture **flushed_depth_texture = staging ?
849 staging : &rtex->flushed_depth_texture;
850
851 if (!staging && rtex->flushed_depth_texture)
852 return true; /* it's ready */
853
854 resource.target = texture->target;
855 resource.format = texture->format;
856 resource.width0 = texture->width0;
857 resource.height0 = texture->height0;
858 resource.depth0 = texture->depth0;
859 resource.array_size = texture->array_size;
860 resource.last_level = texture->last_level;
861 resource.nr_samples = texture->nr_samples;
862 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
863 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
864 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
865
866 if (staging)
867 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
868
869 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
870 if (*flushed_depth_texture == NULL) {
871 R600_ERR("failed to create temporary texture to hold flushed depth\n");
872 return false;
873 }
874
875 (*flushed_depth_texture)->is_flushing_texture = TRUE;
876 (*flushed_depth_texture)->non_disp_tiling = false;
877 return true;
878 }
879
880 /**
881 * Initialize the pipe_resource descriptor to be of the same size as the box,
882 * which is supposed to hold a subregion of the texture "orig" at the given
883 * mipmap level.
884 */
885 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
886 struct pipe_resource *orig,
887 const struct pipe_box *box,
888 unsigned level, unsigned flags)
889 {
890 memset(res, 0, sizeof(*res));
891 res->format = orig->format;
892 res->width0 = box->width;
893 res->height0 = box->height;
894 res->depth0 = 1;
895 res->array_size = 1;
896 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
897 res->flags = flags;
898
899 /* We must set the correct texture target and dimensions for a 3D box. */
900 if (box->depth > 1 && util_max_layer(orig, level) > 0)
901 res->target = orig->target;
902 else
903 res->target = PIPE_TEXTURE_2D;
904
905 switch (res->target) {
906 case PIPE_TEXTURE_1D_ARRAY:
907 case PIPE_TEXTURE_2D_ARRAY:
908 case PIPE_TEXTURE_CUBE_ARRAY:
909 res->array_size = box->depth;
910 break;
911 case PIPE_TEXTURE_3D:
912 res->depth0 = box->depth;
913 break;
914 default:;
915 }
916 }
917
918 static void *r600_texture_transfer_map(struct pipe_context *ctx,
919 struct pipe_resource *texture,
920 unsigned level,
921 unsigned usage,
922 const struct pipe_box *box,
923 struct pipe_transfer **ptransfer)
924 {
925 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
926 struct r600_texture *rtex = (struct r600_texture*)texture;
927 struct r600_transfer *trans;
928 boolean use_staging_texture = FALSE;
929 struct r600_resource *buf;
930 unsigned offset = 0;
931 char *map;
932
933 /* We cannot map a tiled texture directly because the data is
934 * in a different order, therefore we do detiling using a blit.
935 *
936 * Also, use a temporary in GTT memory for read transfers, as
937 * the CPU is much happier reading out of cached system memory
938 * than uncached VRAM.
939 */
940 if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D)
941 use_staging_texture = TRUE;
942
943 /* Untiled buffers in VRAM, which is slow for CPU reads */
944 if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
945 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
946 use_staging_texture = TRUE;
947 }
948
949 /* Use a staging texture for uploads if the underlying BO is busy. */
950 if (!(usage & PIPE_TRANSFER_READ) &&
951 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
952 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
953 use_staging_texture = TRUE;
954 }
955
956 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
957 use_staging_texture = FALSE;
958 }
959
960 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
961 return NULL;
962 }
963
964 trans = CALLOC_STRUCT(r600_transfer);
965 if (trans == NULL)
966 return NULL;
967 trans->transfer.resource = texture;
968 trans->transfer.level = level;
969 trans->transfer.usage = usage;
970 trans->transfer.box = *box;
971
972 if (rtex->is_depth) {
973 struct r600_texture *staging_depth;
974
975 if (rtex->resource.b.b.nr_samples > 1) {
976 /* MSAA depth buffers need to be converted to single sample buffers.
977 *
978 * Mapping MSAA depth buffers can occur if ReadPixels is called
979 * with a multisample GLX visual.
980 *
981 * First downsample the depth buffer to a temporary texture,
982 * then decompress the temporary one to staging.
983 *
984 * Only the region being mapped is transfered.
985 */
986 struct pipe_resource resource;
987
988 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
989
990 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
991 R600_ERR("failed to create temporary texture to hold untiled copy\n");
992 FREE(trans);
993 return NULL;
994 }
995
996 if (usage & PIPE_TRANSFER_READ) {
997 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
998
999 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1000 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1001 0, 0, 0, box->depth, 0, 0);
1002 pipe_resource_reference((struct pipe_resource**)&temp, NULL);
1003 }
1004 }
1005 else {
1006 /* XXX: only readback the rectangle which is being mapped? */
1007 /* XXX: when discard is true, no need to read back from depth texture */
1008 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1009 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1010 FREE(trans);
1011 return NULL;
1012 }
1013
1014 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1015 level, level,
1016 box->z, box->z + box->depth - 1,
1017 0, 0);
1018
1019 offset = r600_texture_get_offset(staging_depth, level, box);
1020 }
1021
1022 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1023 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1024 trans->staging = (struct r600_resource*)staging_depth;
1025 } else if (use_staging_texture) {
1026 struct pipe_resource resource;
1027 struct r600_texture *staging;
1028
1029 r600_init_temp_resource_from_box(&resource, texture, box, level,
1030 R600_RESOURCE_FLAG_TRANSFER);
1031
1032 /* Create the temporary texture. */
1033 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1034 if (staging == NULL) {
1035 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1036 FREE(trans);
1037 return NULL;
1038 }
1039 trans->staging = &staging->resource;
1040 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1041 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1042 if (usage & PIPE_TRANSFER_READ) {
1043 r600_copy_to_staging_texture(ctx, trans);
1044 }
1045 } else {
1046 /* the resource is mapped directly */
1047 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1048 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1049 offset = r600_texture_get_offset(rtex, level, box);
1050 }
1051
1052 if (trans->staging) {
1053 buf = trans->staging;
1054 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1055 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1056 } else {
1057 buf = &rtex->resource;
1058 }
1059
1060 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1061 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1062 FREE(trans);
1063 return NULL;
1064 }
1065
1066 *ptransfer = &trans->transfer;
1067 return map + offset;
1068 }
1069
1070 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1071 struct pipe_transfer* transfer)
1072 {
1073 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1074 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1075 struct radeon_winsys_cs_handle *buf;
1076 struct pipe_resource *texture = transfer->resource;
1077 struct r600_texture *rtex = (struct r600_texture*)texture;
1078
1079 if (rtransfer->staging) {
1080 buf = rtransfer->staging->cs_buf;
1081 } else {
1082 buf = r600_resource(transfer->resource)->cs_buf;
1083 }
1084 rctx->ws->buffer_unmap(buf);
1085
1086 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1087 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1088 ctx->resource_copy_region(ctx, texture, transfer->level,
1089 transfer->box.x, transfer->box.y, transfer->box.z,
1090 &rtransfer->staging->b.b, transfer->level,
1091 &transfer->box);
1092 } else {
1093 r600_copy_from_staging_texture(ctx, rtransfer);
1094 }
1095 }
1096
1097 if (rtransfer->staging)
1098 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1099
1100 FREE(transfer);
1101 }
1102
1103 static const struct u_resource_vtbl r600_texture_vtbl =
1104 {
1105 NULL, /* get_handle */
1106 r600_texture_destroy, /* resource_destroy */
1107 r600_texture_transfer_map, /* transfer_map */
1108 NULL, /* transfer_flush_region */
1109 r600_texture_transfer_unmap, /* transfer_unmap */
1110 NULL /* transfer_inline_write */
1111 };
1112
1113 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1114 struct pipe_resource *texture,
1115 const struct pipe_surface *templ,
1116 unsigned width, unsigned height)
1117 {
1118 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1119
1120 if (surface == NULL)
1121 return NULL;
1122
1123 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1124 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1125
1126 pipe_reference_init(&surface->base.reference, 1);
1127 pipe_resource_reference(&surface->base.texture, texture);
1128 surface->base.context = pipe;
1129 surface->base.format = templ->format;
1130 surface->base.width = width;
1131 surface->base.height = height;
1132 surface->base.u = templ->u;
1133 return &surface->base;
1134 }
1135
1136 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1137 struct pipe_resource *tex,
1138 const struct pipe_surface *templ)
1139 {
1140 unsigned level = templ->u.tex.level;
1141
1142 return r600_create_surface_custom(pipe, tex, templ,
1143 u_minify(tex->width0, level),
1144 u_minify(tex->height0, level));
1145 }
1146
1147 static void r600_surface_destroy(struct pipe_context *pipe,
1148 struct pipe_surface *surface)
1149 {
1150 struct r600_surface *surf = (struct r600_surface*)surface;
1151 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1152 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1153 pipe_resource_reference(&surface->texture, NULL);
1154 FREE(surface);
1155 }
1156
1157 unsigned r600_translate_colorswap(enum pipe_format format)
1158 {
1159 const struct util_format_description *desc = util_format_description(format);
1160
1161 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1162
1163 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1164 return V_0280A0_SWAP_STD;
1165
1166 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1167 return ~0U;
1168
1169 switch (desc->nr_channels) {
1170 case 1:
1171 if (HAS_SWIZZLE(0,X))
1172 return V_0280A0_SWAP_STD; /* X___ */
1173 else if (HAS_SWIZZLE(3,X))
1174 return V_0280A0_SWAP_ALT_REV; /* ___X */
1175 break;
1176 case 2:
1177 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1178 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1179 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1180 return V_0280A0_SWAP_STD; /* XY__ */
1181 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1182 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1183 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1184 return V_0280A0_SWAP_STD_REV; /* YX__ */
1185 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1186 return V_0280A0_SWAP_ALT; /* X__Y */
1187 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1188 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1189 break;
1190 case 3:
1191 if (HAS_SWIZZLE(0,X))
1192 return V_0280A0_SWAP_STD; /* XYZ */
1193 else if (HAS_SWIZZLE(0,Z))
1194 return V_0280A0_SWAP_STD_REV; /* ZYX */
1195 break;
1196 case 4:
1197 /* check the middle channels, the 1st and 4th channel can be NONE */
1198 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1199 return V_0280A0_SWAP_STD; /* XYZW */
1200 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1201 return V_0280A0_SWAP_STD_REV; /* WZYX */
1202 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1203 return V_0280A0_SWAP_ALT; /* ZYXW */
1204 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
1205 return V_0280A0_SWAP_ALT_REV; /* WXYZ */
1206 break;
1207 }
1208 return ~0U;
1209 }
1210
1211 static void evergreen_set_clear_color(struct r600_texture *rtex,
1212 enum pipe_format surface_format,
1213 const union pipe_color_union *color)
1214 {
1215 union util_color uc;
1216
1217 memset(&uc, 0, sizeof(uc));
1218
1219 if (util_format_is_pure_uint(surface_format)) {
1220 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1221 } else if (util_format_is_pure_sint(surface_format)) {
1222 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1223 } else {
1224 util_pack_color(color->f, surface_format, &uc);
1225 }
1226
1227 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1228 }
1229
1230 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1231 struct pipe_framebuffer_state *fb,
1232 struct r600_atom *fb_state,
1233 unsigned *buffers,
1234 const union pipe_color_union *color)
1235 {
1236 int i;
1237
1238 if (rctx->current_render_cond)
1239 return;
1240
1241 for (i = 0; i < fb->nr_cbufs; i++) {
1242 struct r600_texture *tex;
1243 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1244
1245 if (!fb->cbufs[i])
1246 continue;
1247
1248 /* if this colorbuffer is not being cleared */
1249 if (!(*buffers & clear_bit))
1250 continue;
1251
1252 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1253
1254 /* 128-bit formats are unusupported */
1255 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1256 continue;
1257 }
1258
1259 /* the clear is allowed if all layers are bound */
1260 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1261 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1262 continue;
1263 }
1264
1265 /* cannot clear mipmapped textures */
1266 if (fb->cbufs[i]->texture->last_level != 0) {
1267 continue;
1268 }
1269
1270 /* only supported on tiled surfaces */
1271 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1272 continue;
1273 }
1274
1275 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1276 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1277 rctx->chip_class >= CIK && rctx->screen->info.drm_minor < 38) {
1278 continue;
1279 }
1280
1281 /* ensure CMASK is enabled */
1282 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1283 if (tex->cmask.size == 0) {
1284 continue;
1285 }
1286
1287 /* Do the fast clear. */
1288 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1289 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1290 tex->cmask.offset, tex->cmask.size, 0);
1291
1292 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1293 fb_state->dirty = true;
1294 *buffers &= ~clear_bit;
1295 }
1296 }
1297
1298 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1299 {
1300 rscreen->b.resource_from_handle = r600_texture_from_handle;
1301 rscreen->b.resource_get_handle = r600_texture_get_handle;
1302 }
1303
1304 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1305 {
1306 rctx->b.create_surface = r600_create_surface;
1307 rctx->b.surface_destroy = r600_surface_destroy;
1308 }