2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
34 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
35 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
36 struct pipe_resource
*dst
,
38 unsigned dstx
, unsigned dsty
, unsigned dstz
,
39 struct pipe_resource
*src
,
41 const struct pipe_box
*src_box
)
43 struct pipe_blit_info blit
;
45 memset(&blit
, 0, sizeof(blit
));
46 blit
.src
.resource
= src
;
47 blit
.src
.format
= src
->format
;
48 blit
.src
.level
= src_level
;
49 blit
.src
.box
= *src_box
;
50 blit
.dst
.resource
= dst
;
51 blit
.dst
.format
= dst
->format
;
52 blit
.dst
.level
= dst_level
;
53 blit
.dst
.box
.x
= dstx
;
54 blit
.dst
.box
.y
= dsty
;
55 blit
.dst
.box
.z
= dstz
;
56 blit
.dst
.box
.width
= src_box
->width
;
57 blit
.dst
.box
.height
= src_box
->height
;
58 blit
.dst
.box
.depth
= src_box
->depth
;
59 blit
.mask
= util_format_get_mask(src
->format
) &
60 util_format_get_mask(dst
->format
);
61 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
64 pipe
->blit(pipe
, &blit
);
68 /* Copy from a full GPU texture to a transfer's staging one. */
69 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
71 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
72 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
73 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
74 struct pipe_resource
*src
= transfer
->resource
;
76 if (src
->nr_samples
> 1) {
77 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
78 src
, transfer
->level
, &transfer
->box
);
82 if (!rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0,
85 ctx
->resource_copy_region(ctx
, dst
, 0, 0, 0, 0,
86 src
, transfer
->level
, &transfer
->box
);
90 /* Copy from a transfer's staging texture to a full GPU one. */
91 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
93 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
94 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
95 struct pipe_resource
*dst
= transfer
->resource
;
96 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
99 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
101 if (dst
->nr_samples
> 1) {
102 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
103 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
108 if (!rctx
->dma_copy(ctx
, dst
, transfer
->level
,
109 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
111 ctx
->resource_copy_region(ctx
, dst
, transfer
->level
,
112 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
117 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
118 const struct pipe_box
*box
)
120 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
122 return rtex
->surface
.level
[level
].offset
+
123 box
->z
* rtex
->surface
.level
[level
].slice_size
+
124 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
125 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
128 static int r600_init_surface(struct r600_common_screen
*rscreen
,
129 struct radeon_surface
*surface
,
130 const struct pipe_resource
*ptex
,
132 bool is_flushed_depth
)
134 const struct util_format_description
*desc
=
135 util_format_description(ptex
->format
);
136 bool is_depth
, is_stencil
;
138 is_depth
= util_format_has_depth(desc
);
139 is_stencil
= util_format_has_stencil(desc
);
141 surface
->npix_x
= ptex
->width0
;
142 surface
->npix_y
= ptex
->height0
;
143 surface
->npix_z
= ptex
->depth0
;
144 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
145 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
147 surface
->array_size
= 1;
148 surface
->last_level
= ptex
->last_level
;
150 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
151 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
152 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
154 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
155 /* align byte per element on dword */
156 if (surface
->bpe
== 3) {
161 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
162 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
164 switch (ptex
->target
) {
165 case PIPE_TEXTURE_1D
:
166 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
168 case PIPE_TEXTURE_RECT
:
169 case PIPE_TEXTURE_2D
:
170 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
172 case PIPE_TEXTURE_3D
:
173 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
175 case PIPE_TEXTURE_1D_ARRAY
:
176 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
177 surface
->array_size
= ptex
->array_size
;
179 case PIPE_TEXTURE_2D_ARRAY
:
180 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
181 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
182 surface
->array_size
= ptex
->array_size
;
184 case PIPE_TEXTURE_CUBE
:
185 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
191 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
192 surface
->flags
|= RADEON_SURF_SCANOUT
;
195 if (!is_flushed_depth
&& is_depth
) {
196 surface
->flags
|= RADEON_SURF_ZBUFFER
;
199 surface
->flags
|= RADEON_SURF_SBUFFER
|
200 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
203 if (rscreen
->chip_class
>= SI
) {
204 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
209 static int r600_setup_surface(struct pipe_screen
*screen
,
210 struct r600_texture
*rtex
,
211 unsigned pitch_in_bytes_override
)
213 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
216 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
221 rtex
->size
= rtex
->surface
.bo_size
;
223 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
224 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
227 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
228 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
229 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
230 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
231 rtex
->surface
.stencil_offset
=
232 rtex
->surface
.stencil_level
[0].offset
= rtex
->surface
.level
[0].slice_size
;
238 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
239 struct pipe_resource
*ptex
,
240 struct winsys_handle
*whandle
)
242 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
243 struct r600_resource
*resource
= &rtex
->resource
;
244 struct radeon_surface
*surface
= &rtex
->surface
;
245 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
247 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
249 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
250 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
251 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
252 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
253 surface
->bankw
, surface
->bankh
,
255 surface
->stencil_tile_split
,
257 surface
->level
[0].pitch_bytes
,
258 (surface
->flags
& RADEON_SURF_SCANOUT
) != 0);
260 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
261 surface
->level
[0].pitch_bytes
, whandle
);
264 static void r600_texture_destroy(struct pipe_screen
*screen
,
265 struct pipe_resource
*ptex
)
267 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
268 struct r600_resource
*resource
= &rtex
->resource
;
270 if (rtex
->flushed_depth_texture
)
271 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
273 pipe_resource_reference((struct pipe_resource
**)&rtex
->htile_buffer
, NULL
);
274 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
275 pipe_resource_reference((struct pipe_resource
**)&rtex
->cmask_buffer
, NULL
);
277 pb_reference(&resource
->buf
, NULL
);
281 static const struct u_resource_vtbl r600_texture_vtbl
;
283 /* The number of samples can be specified independently of the texture. */
284 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
285 struct r600_texture
*rtex
,
287 struct r600_fmask_info
*out
)
289 /* FMASK is allocated like an ordinary texture. */
290 struct radeon_surface fmask
= rtex
->surface
;
292 memset(out
, 0, sizeof(*out
));
294 fmask
.bo_alignment
= 0;
297 fmask
.flags
|= RADEON_SURF_FMASK
;
299 if (rscreen
->chip_class
>= SI
) {
300 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
303 switch (nr_samples
) {
307 if (rscreen
->chip_class
<= CAYMAN
) {
315 R600_ERR("Invalid sample count for FMASK allocation.\n");
319 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
320 * This can be fixed by writing a separate FMASK allocator specifically
321 * for R600-R700 asics. */
322 if (rscreen
->chip_class
<= R700
) {
326 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
327 R600_ERR("Got error in surface_init while allocating FMASK.\n");
331 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
333 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
334 if (out
->slice_tile_max
)
335 out
->slice_tile_max
-= 1;
337 out
->tile_mode_index
= fmask
.tiling_index
[0];
338 out
->pitch
= fmask
.level
[0].nblk_x
;
339 out
->bank_height
= fmask
.bankh
;
340 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
341 out
->size
= fmask
.bo_size
;
344 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
345 struct r600_texture
*rtex
)
347 r600_texture_get_fmask_info(rscreen
, rtex
,
348 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
350 rtex
->fmask
.offset
= align(rtex
->size
, rtex
->fmask
.alignment
);
351 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
354 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
355 struct r600_texture
*rtex
,
356 struct r600_cmask_info
*out
)
358 unsigned cmask_tile_width
= 8;
359 unsigned cmask_tile_height
= 8;
360 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
361 unsigned element_bits
= 4;
362 unsigned cmask_cache_bits
= 1024;
363 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
364 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
366 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
367 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
368 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
369 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
370 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
372 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
373 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
375 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
376 unsigned slice_bytes
=
377 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
379 assert(macro_tile_width
% 128 == 0);
380 assert(macro_tile_height
% 128 == 0);
382 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
383 out
->alignment
= MAX2(256, base_align
);
384 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
387 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
388 struct r600_texture
*rtex
,
389 struct r600_cmask_info
*out
)
391 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
392 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
393 unsigned cl_width
, cl_height
;
408 case 16: /* Hawaii */
417 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
419 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
420 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
421 unsigned slice_elements
= (width
* height
) / (8*8);
423 /* Each element of CMASK is a nibble. */
424 unsigned slice_bytes
= slice_elements
/ 2;
426 out
->slice_tile_max
= (width
* height
) / (128*128);
427 if (out
->slice_tile_max
)
428 out
->slice_tile_max
-= 1;
430 out
->alignment
= MAX2(256, base_align
);
431 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
434 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
435 struct r600_texture
*rtex
)
437 if (rscreen
->chip_class
>= SI
) {
438 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
440 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
443 rtex
->cmask
.offset
= align(rtex
->size
, rtex
->cmask
.alignment
);
444 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
447 void r600_texture_init_cmask(struct r600_common_screen
*rscreen
,
448 struct r600_texture
*rtex
)
450 assert(rtex
->cmask
.size
== 0);
452 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
454 rtex
->cmask_buffer
= (struct r600_resource
*)
455 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
456 PIPE_USAGE_STATIC
, rtex
->cmask
.size
);
457 if (rtex
->cmask_buffer
== NULL
) {
458 rtex
->cmask
.size
= 0;
462 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
463 struct r600_texture
*rtex
)
465 unsigned sw
= rtex
->surface
.level
[0].nblk_x
* rtex
->surface
.blk_w
;
466 unsigned sh
= rtex
->surface
.level
[0].nblk_y
* rtex
->surface
.blk_h
;
468 unsigned npipes
= rscreen
->info
.r600_num_tile_pipes
;
470 /* XXX also use it for other texture targets */
471 if (rscreen
->info
.drm_minor
< 26 ||
472 rtex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
473 rtex
->surface
.level
[0].nblk_x
< 32 ||
474 rtex
->surface
.level
[0].nblk_y
< 32) {
478 /* this alignment and htile size only apply to linear htile buffer */
479 sw
= align(sw
, 16 << 3);
480 sh
= align(sh
, npipes
<< 3);
481 htile_size
= (sw
>> 3) * (sh
>> 3) * 4;
482 /* must be aligned with 2K * npipes */
483 htile_size
= align(htile_size
, (2 << 10) * npipes
);
485 /* XXX don't allocate it separately */
486 rtex
->htile_buffer
= (struct r600_resource
*)pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
487 PIPE_USAGE_STATIC
, htile_size
);
488 if (rtex
->htile_buffer
== NULL
) {
489 /* this is not a fatal error as we can still keep rendering
490 * without htile buffer
492 R600_ERR("r600: failed to create bo for htile buffers\n");
494 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0, htile_size
, 0);
498 /* Common processing for r600_texture_create and r600_texture_from_handle */
499 static struct r600_texture
*
500 r600_texture_create_object(struct pipe_screen
*screen
,
501 const struct pipe_resource
*base
,
502 unsigned pitch_in_bytes_override
,
503 struct pb_buffer
*buf
,
504 struct radeon_surface
*surface
)
506 struct r600_texture
*rtex
;
507 struct r600_resource
*resource
;
508 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
510 rtex
= CALLOC_STRUCT(r600_texture
);
514 resource
= &rtex
->resource
;
515 resource
->b
.b
= *base
;
516 resource
->b
.vtbl
= &r600_texture_vtbl
;
517 pipe_reference_init(&resource
->b
.b
.reference
, 1);
518 resource
->b
.b
.screen
= screen
;
519 rtex
->pitch_override
= pitch_in_bytes_override
;
521 /* don't include stencil-only formats which we don't support for rendering */
522 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
524 rtex
->surface
= *surface
;
525 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
)) {
530 /* Tiled depth textures utilize the non-displayable tile order.
531 * This must be done after r600_setup_surface.
532 * Applies to R600-Cayman. */
533 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
535 if (rtex
->is_depth
) {
536 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
537 R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
538 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
)) {
539 if (rscreen
->chip_class
>= SI
) {
540 /* XXX implement Hyper-Z for SI.
541 * Reuse the CMASK allocator, which is almost the same as HTILE. */
543 r600_texture_allocate_htile(rscreen
, rtex
);
547 if (base
->nr_samples
> 1) {
549 r600_texture_allocate_fmask(rscreen
, rtex
);
550 r600_texture_allocate_cmask(rscreen
, rtex
);
551 rtex
->cmask_buffer
= &rtex
->resource
;
553 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
560 /* Now create the backing buffer. */
562 unsigned base_align
= rtex
->surface
.bo_alignment
;
563 unsigned usage
= rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
564 PIPE_USAGE_STATIC
: base
->usage
;
566 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, FALSE
, usage
)) {
572 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
573 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
576 if (rtex
->cmask
.size
) {
577 /* Initialize the cmask to 0xCC (= compressed state). */
578 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
579 rtex
->cmask
.offset
, rtex
->cmask
.size
, 0xCCCCCCCC);
582 if (rscreen
->debug_flags
& DBG_VM
) {
583 fprintf(stderr
, "VM start=0x%"PRIu64
" end=0x%"PRIu64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
584 r600_resource_va(screen
, &rtex
->resource
.b
.b
),
585 r600_resource_va(screen
, &rtex
->resource
.b
.b
) + rtex
->resource
.buf
->size
,
586 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
587 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
590 if (rscreen
->debug_flags
& DBG_TEX
||
591 (rtex
->resource
.b
.b
.last_level
> 0 && rscreen
->debug_flags
& DBG_TEXMIP
)) {
592 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
593 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
594 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
595 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
596 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
597 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
598 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
599 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
600 rtex
->surface
.flags
, util_format_short_name(base
->format
));
601 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
602 printf(" L %i: offset=%"PRIu64
", slice_size=%"PRIu64
", npix_x=%u, "
603 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
604 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
605 i
, rtex
->surface
.level
[i
].offset
,
606 rtex
->surface
.level
[i
].slice_size
,
607 u_minify(rtex
->resource
.b
.b
.width0
, i
),
608 u_minify(rtex
->resource
.b
.b
.height0
, i
),
609 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
610 rtex
->surface
.level
[i
].nblk_x
,
611 rtex
->surface
.level
[i
].nblk_y
,
612 rtex
->surface
.level
[i
].nblk_z
,
613 rtex
->surface
.level
[i
].pitch_bytes
,
614 rtex
->surface
.level
[i
].mode
);
616 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
617 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
618 printf(" S %i: offset=%"PRIu64
", slice_size=%"PRIu64
", npix_x=%u, "
619 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
620 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
621 i
, rtex
->surface
.stencil_level
[i
].offset
,
622 rtex
->surface
.stencil_level
[i
].slice_size
,
623 u_minify(rtex
->resource
.b
.b
.width0
, i
),
624 u_minify(rtex
->resource
.b
.b
.height0
, i
),
625 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
626 rtex
->surface
.stencil_level
[i
].nblk_x
,
627 rtex
->surface
.stencil_level
[i
].nblk_y
,
628 rtex
->surface
.stencil_level
[i
].nblk_z
,
629 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
630 rtex
->surface
.stencil_level
[i
].mode
);
637 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
638 const struct pipe_resource
*templ
)
640 const struct util_format_description
*desc
= util_format_description(templ
->format
);
642 /* MSAA resources must be 2D tiled. */
643 if (templ
->nr_samples
> 1)
644 return RADEON_SURF_MODE_2D
;
646 /* Transfer resources should be linear. */
647 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
648 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
650 /* Handle common candidates for the linear mode.
651 * Compressed textures must always be tiled. */
652 if (!(templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
) &&
653 !util_format_is_compressed(templ
->format
)) {
654 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600-Cayman. */
655 if (rscreen
->chip_class
<= CAYMAN
&&
656 desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
657 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
659 /* Cursors are linear on SI.
660 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
661 if (rscreen
->chip_class
>= SI
&&
662 (templ
->bind
& PIPE_BIND_CURSOR
))
663 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
665 if (templ
->bind
& PIPE_BIND_LINEAR
)
666 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
668 /* Textures with a very small height are recommended to be linear. */
669 if (templ
->target
== PIPE_TEXTURE_1D
||
670 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
672 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
674 /* Textures likely to be mapped often. */
675 if (templ
->usage
== PIPE_USAGE_STAGING
||
676 templ
->usage
== PIPE_USAGE_STREAM
)
677 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
680 /* Make small textures 1D tiled. */
681 if (templ
->width0
<= 16 || templ
->height0
<= 16)
682 return RADEON_SURF_MODE_1D
;
684 /* The allocator will switch to 1D if needed. */
685 return RADEON_SURF_MODE_2D
;
688 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
689 const struct pipe_resource
*templ
)
691 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
692 struct radeon_surface surface
= {0};
695 r
= r600_init_surface(rscreen
, &surface
, templ
,
696 r600_choose_tiling(rscreen
, templ
),
697 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
701 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
705 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
709 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
710 const struct pipe_resource
*templ
,
711 struct winsys_handle
*whandle
)
713 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
714 struct pb_buffer
*buf
= NULL
;
717 enum radeon_bo_layout micro
, macro
;
718 struct radeon_surface surface
;
722 /* Support only 2D textures without mipmaps */
723 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
724 templ
->depth0
!= 1 || templ
->last_level
!= 0)
727 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
731 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
732 &surface
.bankw
, &surface
.bankh
,
734 &surface
.stencil_tile_split
,
735 &surface
.mtilea
, &scanout
);
737 if (macro
== RADEON_LAYOUT_TILED
)
738 array_mode
= RADEON_SURF_MODE_2D
;
739 else if (micro
== RADEON_LAYOUT_TILED
)
740 array_mode
= RADEON_SURF_MODE_1D
;
742 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
744 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
750 surface
.flags
|= RADEON_SURF_SCANOUT
;
752 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
753 stride
, buf
, &surface
);
756 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
757 struct pipe_resource
*texture
,
758 struct r600_texture
**staging
)
760 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
761 struct pipe_resource resource
;
762 struct r600_texture
**flushed_depth_texture
= staging
?
763 staging
: &rtex
->flushed_depth_texture
;
765 if (!staging
&& rtex
->flushed_depth_texture
)
766 return true; /* it's ready */
768 resource
.target
= texture
->target
;
769 resource
.format
= texture
->format
;
770 resource
.width0
= texture
->width0
;
771 resource
.height0
= texture
->height0
;
772 resource
.depth0
= texture
->depth0
;
773 resource
.array_size
= texture
->array_size
;
774 resource
.last_level
= texture
->last_level
;
775 resource
.nr_samples
= texture
->nr_samples
;
776 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
777 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
778 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
781 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
783 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
784 if (*flushed_depth_texture
== NULL
) {
785 R600_ERR("failed to create temporary texture to hold flushed depth\n");
789 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
790 (*flushed_depth_texture
)->non_disp_tiling
= false;
795 * Initialize the pipe_resource descriptor to be of the same size as the box,
796 * which is supposed to hold a subregion of the texture "orig" at the given
799 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
800 struct pipe_resource
*orig
,
801 const struct pipe_box
*box
,
802 unsigned level
, unsigned flags
)
804 memset(res
, 0, sizeof(*res
));
805 res
->format
= orig
->format
;
806 res
->width0
= box
->width
;
807 res
->height0
= box
->height
;
810 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
813 /* We must set the correct texture target and dimensions for a 3D box. */
814 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0)
815 res
->target
= orig
->target
;
817 res
->target
= PIPE_TEXTURE_2D
;
819 switch (res
->target
) {
820 case PIPE_TEXTURE_1D_ARRAY
:
821 case PIPE_TEXTURE_2D_ARRAY
:
822 case PIPE_TEXTURE_CUBE_ARRAY
:
823 res
->array_size
= box
->depth
;
825 case PIPE_TEXTURE_3D
:
826 res
->depth0
= box
->depth
;
832 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
833 struct pipe_resource
*texture
,
836 const struct pipe_box
*box
,
837 struct pipe_transfer
**ptransfer
)
839 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
840 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
841 struct r600_transfer
*trans
;
842 boolean use_staging_texture
= FALSE
;
843 struct r600_resource
*buf
;
847 /* We cannot map a tiled texture directly because the data is
848 * in a different order, therefore we do detiling using a blit.
850 * Also, use a temporary in GTT memory for read transfers, as
851 * the CPU is much happier reading out of cached system memory
852 * than uncached VRAM.
854 if (rtex
->surface
.level
[level
].mode
>= RADEON_SURF_MODE_1D
)
855 use_staging_texture
= TRUE
;
857 /* Untiled buffers in VRAM, which is slow for CPU reads */
858 if ((usage
& PIPE_TRANSFER_READ
) && !(usage
& PIPE_TRANSFER_MAP_DIRECTLY
) &&
859 (rtex
->resource
.domains
== RADEON_DOMAIN_VRAM
)) {
860 use_staging_texture
= TRUE
;
863 /* Use a staging texture for uploads if the underlying BO is busy. */
864 if (!(usage
& PIPE_TRANSFER_READ
) &&
865 (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
866 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
867 use_staging_texture
= TRUE
;
870 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
871 use_staging_texture
= FALSE
;
874 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
878 trans
= CALLOC_STRUCT(r600_transfer
);
881 trans
->transfer
.resource
= texture
;
882 trans
->transfer
.level
= level
;
883 trans
->transfer
.usage
= usage
;
884 trans
->transfer
.box
= *box
;
886 if (rtex
->is_depth
) {
887 struct r600_texture
*staging_depth
;
889 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
890 /* MSAA depth buffers need to be converted to single sample buffers.
892 * Mapping MSAA depth buffers can occur if ReadPixels is called
893 * with a multisample GLX visual.
895 * First downsample the depth buffer to a temporary texture,
896 * then decompress the temporary one to staging.
898 * Only the region being mapped is transfered.
900 struct pipe_resource resource
;
902 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
904 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
905 R600_ERR("failed to create temporary texture to hold untiled copy\n");
910 if (usage
& PIPE_TRANSFER_READ
) {
911 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
913 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
914 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
915 0, 0, 0, box
->depth
, 0, 0);
916 pipe_resource_reference((struct pipe_resource
**)&temp
, NULL
);
920 /* XXX: only readback the rectangle which is being mapped? */
921 /* XXX: when discard is true, no need to read back from depth texture */
922 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
923 R600_ERR("failed to create temporary texture to hold untiled copy\n");
928 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
930 box
->z
, box
->z
+ box
->depth
- 1,
933 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
936 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
937 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
938 trans
->staging
= (struct r600_resource
*)staging_depth
;
939 } else if (use_staging_texture
) {
940 struct pipe_resource resource
;
941 struct r600_texture
*staging
;
943 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
944 R600_RESOURCE_FLAG_TRANSFER
);
946 /* Create the temporary texture. */
947 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
948 if (staging
== NULL
) {
949 R600_ERR("failed to create temporary texture to hold untiled copy\n");
953 trans
->staging
= &staging
->resource
;
954 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
955 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
956 if (usage
& PIPE_TRANSFER_READ
) {
957 r600_copy_to_staging_texture(ctx
, trans
);
960 /* the resource is mapped directly */
961 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
962 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
963 offset
= r600_texture_get_offset(rtex
, level
, box
);
966 if (trans
->staging
) {
967 buf
= trans
->staging
;
969 buf
= &rtex
->resource
;
972 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
973 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
978 *ptransfer
= &trans
->transfer
;
982 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
983 struct pipe_transfer
* transfer
)
985 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
986 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
987 struct radeon_winsys_cs_handle
*buf
;
988 struct pipe_resource
*texture
= transfer
->resource
;
989 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
991 if (rtransfer
->staging
) {
992 buf
= rtransfer
->staging
->cs_buf
;
994 buf
= r600_resource(transfer
->resource
)->cs_buf
;
996 rctx
->ws
->buffer_unmap(buf
);
998 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
999 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1000 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1001 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1002 &rtransfer
->staging
->b
.b
, transfer
->level
,
1005 r600_copy_from_staging_texture(ctx
, rtransfer
);
1009 if (rtransfer
->staging
)
1010 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
1015 static const struct u_resource_vtbl r600_texture_vtbl
=
1017 r600_texture_get_handle
, /* get_handle */
1018 r600_texture_destroy
, /* resource_destroy */
1019 r600_texture_transfer_map
, /* transfer_map */
1020 NULL
, /* transfer_flush_region */
1021 r600_texture_transfer_unmap
, /* transfer_unmap */
1022 NULL
/* transfer_inline_write */