2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
41 const struct pipe_resource
*templ
);
44 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
56 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
76 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
185 return rtex
->surface
.level
[level
].offset
+
186 box
->z
* rtex
->surface
.level
[level
].slice_size
+
187 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
188 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
191 static int r600_init_surface(struct r600_common_screen
*rscreen
,
192 struct radeon_surf
*surface
,
193 const struct pipe_resource
*ptex
,
195 bool is_flushed_depth
,
196 bool tc_compatible_htile
)
198 const struct util_format_description
*desc
=
199 util_format_description(ptex
->format
);
200 bool is_depth
, is_stencil
;
202 is_depth
= util_format_has_depth(desc
);
203 is_stencil
= util_format_has_stencil(desc
);
205 surface
->npix_x
= ptex
->width0
;
206 surface
->npix_y
= ptex
->height0
;
207 surface
->npix_z
= ptex
->depth0
;
208 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
209 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
211 surface
->array_size
= 1;
212 surface
->last_level
= ptex
->last_level
;
214 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
215 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
216 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
218 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
219 /* align byte per element on dword */
220 if (surface
->bpe
== 3) {
225 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
226 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
228 switch (ptex
->target
) {
229 case PIPE_TEXTURE_1D
:
230 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
232 case PIPE_TEXTURE_RECT
:
233 case PIPE_TEXTURE_2D
:
234 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
236 case PIPE_TEXTURE_3D
:
237 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
239 case PIPE_TEXTURE_1D_ARRAY
:
240 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
241 surface
->array_size
= ptex
->array_size
;
243 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
244 assert(ptex
->array_size
% 6 == 0);
245 case PIPE_TEXTURE_2D_ARRAY
:
246 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
247 surface
->array_size
= ptex
->array_size
;
249 case PIPE_TEXTURE_CUBE
:
250 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
257 if (!is_flushed_depth
&& is_depth
) {
258 surface
->flags
|= RADEON_SURF_ZBUFFER
;
260 if (tc_compatible_htile
&&
261 array_mode
== RADEON_SURF_MODE_2D
) {
262 /* TC-compatible HTILE only supports Z32_FLOAT.
263 * Promote Z16 to Z32. DB->CB copies will convert
264 * the format for transfers.
267 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
271 surface
->flags
|= RADEON_SURF_SBUFFER
|
272 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
276 if (rscreen
->chip_class
>= SI
) {
277 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
280 if (rscreen
->chip_class
>= VI
&&
281 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
282 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
283 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
285 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
286 /* This should catch bugs in gallium users setting incorrect flags. */
287 assert(surface
->nsamples
== 1 &&
288 surface
->array_size
== 1 &&
289 surface
->npix_z
== 1 &&
290 surface
->last_level
== 0 &&
291 !(surface
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
293 surface
->flags
|= RADEON_SURF_SCANOUT
;
298 static int r600_setup_surface(struct pipe_screen
*screen
,
299 struct r600_texture
*rtex
,
300 unsigned pitch_in_bytes_override
,
303 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
307 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
312 rtex
->size
= rtex
->surface
.bo_size
;
314 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
315 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
318 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
319 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
320 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
324 for (i
= 0; i
< ARRAY_SIZE(rtex
->surface
.level
); ++i
)
325 rtex
->surface
.level
[i
].offset
+= offset
;
330 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
331 struct radeon_bo_metadata
*metadata
)
333 struct radeon_surf
*surface
= &rtex
->surface
;
335 memset(metadata
, 0, sizeof(*metadata
));
336 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
337 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
338 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
339 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
340 metadata
->pipe_config
= surface
->pipe_config
;
341 metadata
->bankw
= surface
->bankw
;
342 metadata
->bankh
= surface
->bankh
;
343 metadata
->tile_split
= surface
->tile_split
;
344 metadata
->mtilea
= surface
->mtilea
;
345 metadata
->num_banks
= surface
->num_banks
;
346 metadata
->stride
= surface
->level
[0].pitch_bytes
;
347 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
350 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
352 p_atomic_inc(&rscreen
->dirty_fb_counter
);
355 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
356 struct r600_texture
*rtex
)
358 struct r600_common_screen
*rscreen
= rctx
->screen
;
359 struct pipe_context
*ctx
= &rctx
->b
;
361 if (ctx
== rscreen
->aux_context
)
362 pipe_mutex_lock(rscreen
->aux_context_lock
);
364 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
365 ctx
->flush(ctx
, NULL
, 0);
367 if (ctx
== rscreen
->aux_context
)
368 pipe_mutex_unlock(rscreen
->aux_context_lock
);
371 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
372 struct r600_texture
*rtex
)
374 if (!rtex
->cmask
.size
)
377 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
380 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
381 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
382 rtex
->dirty_level_mask
= 0;
384 if (rscreen
->chip_class
>= SI
)
385 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
387 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
389 if (rtex
->cmask_buffer
!= &rtex
->resource
)
390 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
392 /* Notify all contexts about the change. */
393 r600_dirty_all_framebuffer_states(rscreen
);
394 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
397 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
399 /* We can't disable DCC if it can be written by another process. */
400 return rtex
->dcc_offset
&&
401 (!rtex
->resource
.is_shared
||
402 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
405 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
406 struct r600_texture
*rtex
)
408 if (!r600_can_disable_dcc(rtex
))
411 assert(rtex
->dcc_separate_buffer
== NULL
);
414 rtex
->dcc_offset
= 0;
416 /* Notify all contexts about the change. */
417 r600_dirty_all_framebuffer_states(rscreen
);
422 * Disable DCC for the texture. (first decompress, then discard metadata).
424 * There is unresolved multi-context synchronization issue between
425 * screen::aux_context and the current context. If applications do this with
426 * multiple contexts, it's already undefined behavior for them and we don't
427 * have to worry about that. The scenario is:
429 * If context 1 disables DCC and context 2 has queued commands that write
430 * to the texture via CB with DCC enabled, and the order of operations is
432 * context 2 queues draw calls rendering to the texture, but doesn't flush
433 * context 1 disables DCC and flushes
434 * context 1 & 2 reset descriptors and FB state
435 * context 2 flushes (new compressed tiles written by the draw calls)
436 * context 1 & 2 read garbage, because DCC is disabled, yet there are
439 * \param rctx the current context if you have one, or rscreen->aux_context
442 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
443 struct r600_texture
*rtex
)
445 struct r600_common_screen
*rscreen
= rctx
->screen
;
447 if (!r600_can_disable_dcc(rtex
))
450 if (&rctx
->b
== rscreen
->aux_context
)
451 pipe_mutex_lock(rscreen
->aux_context_lock
);
453 /* Decompress DCC. */
454 rctx
->decompress_dcc(&rctx
->b
, rtex
);
455 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
457 if (&rctx
->b
== rscreen
->aux_context
)
458 pipe_mutex_unlock(rscreen
->aux_context_lock
);
460 return r600_texture_discard_dcc(rscreen
, rtex
);
463 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
464 struct r600_texture
*rtex
,
465 bool invalidate_storage
)
467 struct pipe_screen
*screen
= rctx
->b
.screen
;
468 struct r600_texture
*new_tex
;
469 struct pipe_resource templ
= rtex
->resource
.b
.b
;
472 templ
.bind
|= PIPE_BIND_LINEAR
;
474 /* r600g doesn't react to dirty_tex_descriptor_counter */
475 if (rctx
->chip_class
< SI
)
478 if (rtex
->resource
.is_shared
||
479 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
482 /* This fails with MSAA, depth, and compressed textures. */
483 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
484 RADEON_SURF_MODE_LINEAR_ALIGNED
)
487 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
491 /* Copy the pixels to the new texture. */
492 if (!invalidate_storage
) {
493 for (i
= 0; i
<= templ
.last_level
; i
++) {
497 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
498 util_max_layer(&templ
, i
) + 1, &box
);
500 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
501 &rtex
->resource
.b
.b
, i
, &box
);
505 r600_texture_discard_cmask(rctx
->screen
, rtex
);
506 r600_texture_discard_dcc(rctx
->screen
, rtex
);
508 /* Replace the structure fields of rtex. */
509 rtex
->resource
.b
.b
.bind
= templ
.bind
;
510 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
511 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
512 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
513 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
514 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
515 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
516 rtex
->resource
.domains
= new_tex
->resource
.domains
;
517 rtex
->resource
.flags
= new_tex
->resource
.flags
;
518 rtex
->size
= new_tex
->size
;
519 rtex
->surface
= new_tex
->surface
;
520 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
521 rtex
->cb_color_info
= new_tex
->cb_color_info
;
522 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
524 assert(!rtex
->htile_buffer
);
525 assert(!rtex
->cmask
.size
);
526 assert(!rtex
->fmask
.size
);
527 assert(!rtex
->dcc_offset
);
528 assert(!rtex
->is_depth
);
530 r600_texture_reference(&new_tex
, NULL
);
532 r600_dirty_all_framebuffer_states(rctx
->screen
);
533 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
536 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
537 struct pipe_context
*ctx
,
538 struct pipe_resource
*resource
,
539 struct winsys_handle
*whandle
,
542 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
543 struct r600_common_context
*rctx
= (struct r600_common_context
*)
544 (ctx
? ctx
: rscreen
->aux_context
);
545 struct r600_resource
*res
= (struct r600_resource
*)resource
;
546 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
547 struct radeon_bo_metadata metadata
;
548 bool update_metadata
= false;
550 /* This is not supported now, but it might be required for OpenCL
551 * interop in the future.
553 if (resource
->target
!= PIPE_BUFFER
&&
554 (resource
->nr_samples
> 1 || rtex
->is_depth
))
557 if (resource
->target
!= PIPE_BUFFER
) {
558 /* Since shader image stores don't support DCC on VI,
559 * disable it for external clients that want write
562 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
563 if (r600_texture_disable_dcc(rctx
, rtex
))
564 update_metadata
= true;
567 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
568 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
569 /* Eliminate fast clear (both CMASK and DCC) */
570 r600_eliminate_fast_color_clear(rctx
, rtex
);
572 /* Disable CMASK if flush_resource isn't going
575 if (rtex
->cmask
.size
)
576 r600_texture_discard_cmask(rscreen
, rtex
);
580 if (!res
->is_shared
|| update_metadata
) {
581 r600_texture_init_metadata(rtex
, &metadata
);
582 if (rscreen
->query_opaque_metadata
)
583 rscreen
->query_opaque_metadata(rscreen
, rtex
,
586 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
590 if (res
->is_shared
) {
591 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
594 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
595 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
596 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
598 res
->is_shared
= true;
599 res
->external_usage
= usage
;
602 return rscreen
->ws
->buffer_get_handle(res
->buf
,
603 rtex
->surface
.level
[0].pitch_bytes
,
604 rtex
->surface
.level
[0].offset
,
605 rtex
->surface
.level
[0].slice_size
,
609 static void r600_texture_destroy(struct pipe_screen
*screen
,
610 struct pipe_resource
*ptex
)
612 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
613 struct r600_resource
*resource
= &rtex
->resource
;
615 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
617 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
618 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
619 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
621 pb_reference(&resource
->buf
, NULL
);
622 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
623 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
627 static const struct u_resource_vtbl r600_texture_vtbl
;
629 /* The number of samples can be specified independently of the texture. */
630 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
631 struct r600_texture
*rtex
,
633 struct r600_fmask_info
*out
)
635 /* FMASK is allocated like an ordinary texture. */
636 struct radeon_surf fmask
= rtex
->surface
;
638 memset(out
, 0, sizeof(*out
));
640 fmask
.bo_alignment
= 0;
643 fmask
.flags
|= RADEON_SURF_FMASK
;
645 /* Force 2D tiling if it wasn't set. This may occur when creating
646 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
647 * destination buffer must have an FMASK too. */
648 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
649 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
651 if (rscreen
->chip_class
>= SI
) {
652 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
655 switch (nr_samples
) {
659 if (rscreen
->chip_class
<= CAYMAN
) {
667 R600_ERR("Invalid sample count for FMASK allocation.\n");
671 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
672 * This can be fixed by writing a separate FMASK allocator specifically
673 * for R600-R700 asics. */
674 if (rscreen
->chip_class
<= R700
) {
678 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
679 R600_ERR("Got error in surface_init while allocating FMASK.\n");
683 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
685 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
686 if (out
->slice_tile_max
)
687 out
->slice_tile_max
-= 1;
689 out
->tile_mode_index
= fmask
.tiling_index
[0];
690 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
691 out
->bank_height
= fmask
.bankh
;
692 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
693 out
->size
= fmask
.bo_size
;
696 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
697 struct r600_texture
*rtex
)
699 r600_texture_get_fmask_info(rscreen
, rtex
,
700 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
702 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
703 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
706 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
707 struct r600_texture
*rtex
,
708 struct r600_cmask_info
*out
)
710 unsigned cmask_tile_width
= 8;
711 unsigned cmask_tile_height
= 8;
712 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
713 unsigned element_bits
= 4;
714 unsigned cmask_cache_bits
= 1024;
715 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
716 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
718 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
719 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
720 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
721 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
722 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
724 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
725 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
727 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
728 unsigned slice_bytes
=
729 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
731 assert(macro_tile_width
% 128 == 0);
732 assert(macro_tile_height
% 128 == 0);
734 out
->pitch
= pitch_elements
;
735 out
->height
= height
;
736 out
->xalign
= macro_tile_width
;
737 out
->yalign
= macro_tile_height
;
738 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
739 out
->alignment
= MAX2(256, base_align
);
740 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
741 align(slice_bytes
, base_align
);
744 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
745 struct r600_texture
*rtex
,
746 struct r600_cmask_info
*out
)
748 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
749 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
750 unsigned cl_width
, cl_height
;
765 case 16: /* Hawaii */
774 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
776 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
777 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
778 unsigned slice_elements
= (width
* height
) / (8*8);
780 /* Each element of CMASK is a nibble. */
781 unsigned slice_bytes
= slice_elements
/ 2;
784 out
->height
= height
;
785 out
->xalign
= cl_width
* 8;
786 out
->yalign
= cl_height
* 8;
787 out
->slice_tile_max
= (width
* height
) / (128*128);
788 if (out
->slice_tile_max
)
789 out
->slice_tile_max
-= 1;
791 out
->alignment
= MAX2(256, base_align
);
792 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
793 align(slice_bytes
, base_align
);
796 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
797 struct r600_texture
*rtex
)
799 if (rscreen
->chip_class
>= SI
) {
800 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
802 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
805 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
806 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
808 if (rscreen
->chip_class
>= SI
)
809 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
811 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
814 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
815 struct r600_texture
*rtex
)
817 if (rtex
->cmask_buffer
)
820 assert(rtex
->cmask
.size
== 0);
822 if (rscreen
->chip_class
>= SI
) {
823 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
825 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
828 rtex
->cmask_buffer
= (struct r600_resource
*)
829 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
830 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
831 if (rtex
->cmask_buffer
== NULL
) {
832 rtex
->cmask
.size
= 0;
836 /* update colorbuffer state bits */
837 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
839 if (rscreen
->chip_class
>= SI
)
840 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
842 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
844 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
847 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
848 struct r600_texture
*rtex
)
850 unsigned cl_width
, cl_height
, width
, height
;
851 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
852 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
854 if (rscreen
->chip_class
<= EVERGREEN
&&
855 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
858 /* HW bug on R6xx. */
859 if (rscreen
->chip_class
== R600
&&
860 (rtex
->surface
.level
[0].npix_x
> 7680 ||
861 rtex
->surface
.level
[0].npix_y
> 7680))
864 /* HTILE is broken with 1D tiling on old kernels and CIK. */
865 if (rscreen
->chip_class
>= CIK
&&
866 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
867 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
870 /* Overalign HTILE on P2 configs to work around GPU hangs in
871 * piglit/depthstencil-render-miplevels 585.
873 * This has been confirmed to help Kabini & Stoney, where the hangs
874 * are always reproducible. I think I have seen the test hang
875 * on Carrizo too, though it was very rare there.
877 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
906 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
907 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
909 slice_elements
= (width
* height
) / (8 * 8);
910 slice_bytes
= slice_elements
* 4;
912 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
913 base_align
= num_pipes
* pipe_interleave_bytes
;
915 rtex
->htile
.pitch
= width
;
916 rtex
->htile
.height
= height
;
917 rtex
->htile
.xalign
= cl_width
* 8;
918 rtex
->htile
.yalign
= cl_height
* 8;
919 rtex
->htile
.alignment
= base_align
;
921 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
922 align(slice_bytes
, base_align
);
925 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
926 struct r600_texture
*rtex
)
928 uint64_t htile_size
, alignment
;
929 uint32_t clear_value
;
931 if (rtex
->tc_compatible_htile
) {
932 htile_size
= rtex
->surface
.htile_size
;
933 alignment
= rtex
->surface
.htile_alignment
;
934 clear_value
= 0x0000030F;
936 htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
937 alignment
= rtex
->htile
.alignment
;
944 rtex
->htile_buffer
= (struct r600_resource
*)
945 r600_aligned_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
947 htile_size
, alignment
);
948 if (rtex
->htile_buffer
== NULL
) {
949 /* this is not a fatal error as we can still keep rendering
950 * without htile buffer */
951 R600_ERR("Failed to create buffer object for htile buffer.\n");
953 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
954 0, htile_size
, clear_value
,
955 R600_COHERENCY_NONE
);
959 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
963 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
964 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
965 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
966 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
967 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
968 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
969 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
970 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
971 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
973 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
974 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
975 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
976 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
977 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
978 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
980 if (rtex
->fmask
.size
)
981 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
982 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
983 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
984 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
985 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
987 if (rtex
->cmask
.size
)
988 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
989 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
990 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
991 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
992 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
994 if (rtex
->htile_buffer
)
995 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
996 "xalign=%u, yalign=%u, TC_compatible = %u\n",
997 rtex
->htile_buffer
->b
.b
.width0
,
998 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
999 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
,
1000 rtex
->tc_compatible_htile
);
1002 if (rtex
->dcc_offset
) {
1003 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
1004 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1005 rtex
->surface
.dcc_alignment
);
1006 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
1007 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1008 "fast_clear_size=%"PRIu64
"\n",
1009 i
, rtex
->surface
.level
[i
].dcc_enabled
,
1010 rtex
->surface
.level
[i
].dcc_offset
,
1011 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
1014 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
1015 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1016 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1017 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
1018 i
, rtex
->surface
.level
[i
].offset
,
1019 rtex
->surface
.level
[i
].slice_size
,
1020 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1021 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1022 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1023 rtex
->surface
.level
[i
].nblk_x
,
1024 rtex
->surface
.level
[i
].nblk_y
,
1025 rtex
->surface
.level
[i
].nblk_z
,
1026 rtex
->surface
.level
[i
].pitch_bytes
,
1027 rtex
->surface
.level
[i
].mode
);
1029 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1030 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1031 rtex
->surface
.stencil_tile_split
);
1032 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
1033 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1034 "slice_size=%"PRIu64
", npix_x=%u, "
1035 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1036 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
1037 i
, rtex
->surface
.stencil_level
[i
].offset
,
1038 rtex
->surface
.stencil_level
[i
].slice_size
,
1039 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1040 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1041 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1042 rtex
->surface
.stencil_level
[i
].nblk_x
,
1043 rtex
->surface
.stencil_level
[i
].nblk_y
,
1044 rtex
->surface
.stencil_level
[i
].nblk_z
,
1045 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
1046 rtex
->surface
.stencil_level
[i
].mode
);
1051 /* Common processing for r600_texture_create and r600_texture_from_handle */
1052 static struct r600_texture
*
1053 r600_texture_create_object(struct pipe_screen
*screen
,
1054 const struct pipe_resource
*base
,
1055 unsigned pitch_in_bytes_override
,
1057 struct pb_buffer
*buf
,
1058 struct radeon_surf
*surface
)
1060 struct r600_texture
*rtex
;
1061 struct r600_resource
*resource
;
1062 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1064 rtex
= CALLOC_STRUCT(r600_texture
);
1068 resource
= &rtex
->resource
;
1069 resource
->b
.b
= *base
;
1070 resource
->b
.b
.next
= NULL
;
1071 resource
->b
.vtbl
= &r600_texture_vtbl
;
1072 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1073 resource
->b
.b
.screen
= screen
;
1075 /* don't include stencil-only formats which we don't support for rendering */
1076 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1078 rtex
->surface
= *surface
;
1079 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
, offset
)) {
1084 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0;
1085 assert(!!(rtex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) ==
1086 rtex
->tc_compatible_htile
);
1088 /* TC-compatible HTILE only supports Z32_FLOAT. */
1089 if (rtex
->tc_compatible_htile
)
1090 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1092 rtex
->db_render_format
= base
->format
;
1094 /* Tiled depth textures utilize the non-displayable tile order.
1095 * This must be done after r600_setup_surface.
1096 * Applies to R600-Cayman. */
1097 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1098 /* Applies to GCN. */
1099 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1101 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1102 * between frames, so the only thing that can enable separate DCC
1103 * with DRI2 is multiple slow clears within a frame.
1105 rtex
->ps_draw_ratio
= 0;
1107 if (rtex
->is_depth
) {
1108 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1109 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1110 rscreen
->chip_class
>= EVERGREEN
) {
1111 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1112 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1114 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1115 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1116 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1117 rtex
->can_sample_z
= true;
1120 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1121 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1122 rtex
->db_compatible
= true;
1124 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1125 r600_texture_allocate_htile(rscreen
, rtex
);
1128 if (base
->nr_samples
> 1) {
1130 r600_texture_allocate_fmask(rscreen
, rtex
);
1131 r600_texture_allocate_cmask(rscreen
, rtex
);
1132 rtex
->cmask_buffer
= &rtex
->resource
;
1134 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1140 /* Shared textures must always set up DCC here.
1141 * If it's not present, it will be disabled by
1142 * apply_opaque_metadata later.
1144 if (rtex
->surface
.dcc_size
&&
1145 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1146 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1147 /* Reserve space for the DCC buffer. */
1148 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1149 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1153 /* Now create the backing buffer. */
1155 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1156 rtex
->surface
.bo_alignment
);
1158 resource
->flags
|= RADEON_FLAG_HANDLE
;
1160 if (!r600_alloc_resource(rscreen
, resource
)) {
1165 resource
->buf
= buf
;
1166 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1167 resource
->bo_size
= buf
->size
;
1168 resource
->bo_alignment
= buf
->alignment
;
1169 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1170 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1171 resource
->vram_usage
= buf
->size
;
1172 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1173 resource
->gart_usage
= buf
->size
;
1176 if (rtex
->cmask
.size
) {
1177 /* Initialize the cmask to 0xCC (= compressed state). */
1178 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1179 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1180 0xCCCCCCCC, R600_COHERENCY_NONE
);
1183 /* Initialize DCC only if the texture is not being imported. */
1184 if (!buf
&& rtex
->dcc_offset
) {
1185 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1187 rtex
->surface
.dcc_size
,
1188 0xFFFFFFFF, R600_COHERENCY_NONE
);
1191 /* Initialize the CMASK base register value. */
1192 rtex
->cmask
.base_address_reg
=
1193 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1195 if (rscreen
->debug_flags
& DBG_VM
) {
1196 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1197 rtex
->resource
.gpu_address
,
1198 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1199 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1200 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1203 if (rscreen
->debug_flags
& DBG_TEX
) {
1205 r600_print_texture_info(rtex
, stdout
);
1212 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
1213 const struct pipe_resource
*templ
)
1215 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1216 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1218 /* MSAA resources must be 2D tiled. */
1219 if (templ
->nr_samples
> 1)
1220 return RADEON_SURF_MODE_2D
;
1222 /* Transfer resources should be linear. */
1223 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1224 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1226 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1227 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1228 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1229 (templ
->target
== PIPE_TEXTURE_2D
||
1230 templ
->target
== PIPE_TEXTURE_3D
))
1231 force_tiling
= true;
1233 /* Handle common candidates for the linear mode.
1234 * Compressed textures and DB surfaces must always be tiled.
1236 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1237 (!util_format_is_depth_or_stencil(templ
->format
) ||
1238 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1239 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1240 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1242 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1243 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1244 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1246 /* Cursors are linear on SI.
1247 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1248 if (rscreen
->chip_class
>= SI
&&
1249 (templ
->bind
& PIPE_BIND_CURSOR
))
1250 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1252 if (templ
->bind
& PIPE_BIND_LINEAR
)
1253 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1255 /* Textures with a very small height are recommended to be linear. */
1256 if (templ
->target
== PIPE_TEXTURE_1D
||
1257 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1258 templ
->height0
<= 4)
1259 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1261 /* Textures likely to be mapped often. */
1262 if (templ
->usage
== PIPE_USAGE_STAGING
||
1263 templ
->usage
== PIPE_USAGE_STREAM
)
1264 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1267 /* Make small textures 1D tiled. */
1268 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1269 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1270 return RADEON_SURF_MODE_1D
;
1272 /* The allocator will switch to 1D if needed. */
1273 return RADEON_SURF_MODE_2D
;
1276 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1277 const struct pipe_resource
*templ
)
1279 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1280 struct radeon_surf surface
= {0};
1281 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1282 bool tc_compatible_htile
=
1283 rscreen
->chip_class
>= VI
&&
1284 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1285 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1286 !is_flushed_depth
&&
1287 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1288 util_format_is_depth_or_stencil(templ
->format
);
1292 r
= r600_init_surface(rscreen
, &surface
, templ
,
1293 r600_choose_tiling(rscreen
, templ
),
1294 is_flushed_depth
, tc_compatible_htile
);
1298 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
1302 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, 0,
1306 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1307 const struct pipe_resource
*templ
,
1308 struct winsys_handle
*whandle
,
1311 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1312 struct pb_buffer
*buf
= NULL
;
1313 unsigned stride
= 0, offset
= 0;
1314 unsigned array_mode
;
1315 struct radeon_surf surface
;
1317 struct radeon_bo_metadata metadata
= {};
1318 struct r600_texture
*rtex
;
1320 /* Support only 2D textures without mipmaps */
1321 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1322 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1325 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1329 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1331 surface
.pipe_config
= metadata
.pipe_config
;
1332 surface
.bankw
= metadata
.bankw
;
1333 surface
.bankh
= metadata
.bankh
;
1334 surface
.tile_split
= metadata
.tile_split
;
1335 surface
.mtilea
= metadata
.mtilea
;
1336 surface
.num_banks
= metadata
.num_banks
;
1338 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1339 array_mode
= RADEON_SURF_MODE_2D
;
1340 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1341 array_mode
= RADEON_SURF_MODE_1D
;
1343 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1345 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
,
1351 if (metadata
.scanout
)
1352 surface
.flags
|= RADEON_SURF_SCANOUT
;
1354 rtex
= r600_texture_create_object(screen
, templ
, stride
,
1355 offset
, buf
, &surface
);
1359 rtex
->resource
.is_shared
= true;
1360 rtex
->resource
.external_usage
= usage
;
1362 if (rscreen
->apply_opaque_metadata
)
1363 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1365 return &rtex
->resource
.b
.b
;
1368 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1369 struct pipe_resource
*texture
,
1370 struct r600_texture
**staging
)
1372 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1373 struct pipe_resource resource
;
1374 struct r600_texture
**flushed_depth_texture
= staging
?
1375 staging
: &rtex
->flushed_depth_texture
;
1376 enum pipe_format pipe_format
= texture
->format
;
1379 if (rtex
->flushed_depth_texture
)
1380 return true; /* it's ready */
1382 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1383 switch (pipe_format
) {
1384 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1385 /* Save memory by not allocating the S plane. */
1386 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1388 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1389 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1390 /* Save memory bandwidth by not copying the
1391 * stencil part during flush.
1393 * This potentially increases memory bandwidth
1394 * if an application uses both Z and S texturing
1395 * simultaneously (a flushed Z24S8 texture
1396 * would be stored compactly), but how often
1397 * does that really happen?
1399 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1403 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1404 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1406 /* DB->CB copies to an 8bpp surface don't work. */
1407 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1411 memset(&resource
, 0, sizeof(resource
));
1412 resource
.target
= texture
->target
;
1413 resource
.format
= pipe_format
;
1414 resource
.width0
= texture
->width0
;
1415 resource
.height0
= texture
->height0
;
1416 resource
.depth0
= texture
->depth0
;
1417 resource
.array_size
= texture
->array_size
;
1418 resource
.last_level
= texture
->last_level
;
1419 resource
.nr_samples
= texture
->nr_samples
;
1420 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1421 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1422 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1425 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1427 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1428 if (*flushed_depth_texture
== NULL
) {
1429 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1433 (*flushed_depth_texture
)->non_disp_tiling
= false;
1438 * Initialize the pipe_resource descriptor to be of the same size as the box,
1439 * which is supposed to hold a subregion of the texture "orig" at the given
1442 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1443 struct pipe_resource
*orig
,
1444 const struct pipe_box
*box
,
1445 unsigned level
, unsigned flags
)
1447 memset(res
, 0, sizeof(*res
));
1448 res
->format
= orig
->format
;
1449 res
->width0
= box
->width
;
1450 res
->height0
= box
->height
;
1452 res
->array_size
= 1;
1453 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1456 /* We must set the correct texture target and dimensions for a 3D box. */
1457 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1458 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1459 res
->array_size
= box
->depth
;
1461 res
->target
= PIPE_TEXTURE_2D
;
1465 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1466 struct r600_texture
*rtex
,
1467 unsigned transfer_usage
,
1468 const struct pipe_box
*box
)
1470 /* r600g doesn't react to dirty_tex_descriptor_counter */
1471 return rscreen
->chip_class
>= SI
&&
1472 !rtex
->resource
.is_shared
&&
1473 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1474 rtex
->resource
.b
.b
.last_level
== 0 &&
1475 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1476 box
->x
, box
->y
, box
->z
,
1477 box
->width
, box
->height
,
1481 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1482 struct r600_texture
*rtex
)
1484 struct r600_common_screen
*rscreen
= rctx
->screen
;
1486 /* There is no point in discarding depth and tiled buffers. */
1487 assert(!rtex
->is_depth
);
1488 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1490 /* Reallocate the buffer in the same pipe_resource. */
1491 r600_alloc_resource(rscreen
, &rtex
->resource
);
1493 /* Initialize the CMASK base address (needed even without CMASK). */
1494 rtex
->cmask
.base_address_reg
=
1495 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1497 r600_dirty_all_framebuffer_states(rscreen
);
1498 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1500 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1503 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1504 struct pipe_resource
*texture
,
1507 const struct pipe_box
*box
,
1508 struct pipe_transfer
**ptransfer
)
1510 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1511 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1512 struct r600_transfer
*trans
;
1513 struct r600_resource
*buf
;
1514 unsigned offset
= 0;
1516 bool use_staging_texture
= false;
1518 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1520 /* Depth textures use staging unconditionally. */
1521 if (!rtex
->is_depth
) {
1522 /* Degrade the tile mode if we get too many transfers on APUs.
1523 * On dGPUs, the staging texture is always faster.
1524 * Only count uploads that are at least 4x4 pixels large.
1526 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1528 box
->width
>= 4 && box
->height
>= 4 &&
1529 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1530 bool can_invalidate
=
1531 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1534 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1538 /* Tiled textures need to be converted into a linear texture for CPU
1539 * access. The staging texture is always linear and is placed in GART.
1541 * Reading from VRAM is slow, always use the staging texture in
1544 * Use the staging texture for uploads if the underlying BO
1547 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1548 use_staging_texture
= true;
1549 else if (usage
& PIPE_TRANSFER_READ
)
1550 use_staging_texture
= (rtex
->resource
.domains
&
1551 RADEON_DOMAIN_VRAM
) != 0;
1552 /* Write & linear only: */
1553 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1554 RADEON_USAGE_READWRITE
) ||
1555 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1556 RADEON_USAGE_READWRITE
)) {
1558 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1560 r600_texture_invalidate_storage(rctx
, rtex
);
1562 use_staging_texture
= true;
1566 trans
= CALLOC_STRUCT(r600_transfer
);
1569 trans
->transfer
.resource
= texture
;
1570 trans
->transfer
.level
= level
;
1571 trans
->transfer
.usage
= usage
;
1572 trans
->transfer
.box
= *box
;
1574 if (rtex
->is_depth
) {
1575 struct r600_texture
*staging_depth
;
1577 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1578 /* MSAA depth buffers need to be converted to single sample buffers.
1580 * Mapping MSAA depth buffers can occur if ReadPixels is called
1581 * with a multisample GLX visual.
1583 * First downsample the depth buffer to a temporary texture,
1584 * then decompress the temporary one to staging.
1586 * Only the region being mapped is transfered.
1588 struct pipe_resource resource
;
1590 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1592 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1593 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1598 if (usage
& PIPE_TRANSFER_READ
) {
1599 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1601 R600_ERR("failed to create a temporary depth texture\n");
1606 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1607 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1608 0, 0, 0, box
->depth
, 0, 0);
1609 pipe_resource_reference(&temp
, NULL
);
1613 /* XXX: only readback the rectangle which is being mapped? */
1614 /* XXX: when discard is true, no need to read back from depth texture */
1615 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1616 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1621 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1623 box
->z
, box
->z
+ box
->depth
- 1,
1626 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1629 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1630 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1631 trans
->staging
= (struct r600_resource
*)staging_depth
;
1632 buf
= trans
->staging
;
1633 } else if (use_staging_texture
) {
1634 struct pipe_resource resource
;
1635 struct r600_texture
*staging
;
1637 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1638 R600_RESOURCE_FLAG_TRANSFER
);
1639 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1640 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1642 /* Create the temporary texture. */
1643 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1645 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1649 trans
->staging
= &staging
->resource
;
1650 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1651 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1653 if (usage
& PIPE_TRANSFER_READ
)
1654 r600_copy_to_staging_texture(ctx
, trans
);
1656 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1658 buf
= trans
->staging
;
1660 /* the resource is mapped directly */
1661 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1662 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1663 offset
= r600_texture_get_offset(rtex
, level
, box
);
1664 buf
= &rtex
->resource
;
1667 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1668 r600_resource_reference(&trans
->staging
, NULL
);
1673 *ptransfer
= &trans
->transfer
;
1674 return map
+ offset
;
1677 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1678 struct pipe_transfer
* transfer
)
1680 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1681 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1682 struct pipe_resource
*texture
= transfer
->resource
;
1683 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1685 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1686 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1687 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1688 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1689 &rtransfer
->staging
->b
.b
, transfer
->level
,
1692 r600_copy_from_staging_texture(ctx
, rtransfer
);
1696 if (rtransfer
->staging
) {
1697 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1698 r600_resource_reference(&rtransfer
->staging
, NULL
);
1701 /* Heuristic for {upload, draw, upload, draw, ..}:
1703 * Flush the gfx IB if we've allocated too much texture storage.
1705 * The idea is that we don't want to build IBs that use too much
1706 * memory and put pressure on the kernel memory manager and we also
1707 * want to make temporary and invalidated buffers go idle ASAP to
1708 * decrease the total memory usage or make them reusable. The memory
1709 * usage will be slightly higher than given here because of the buffer
1710 * cache in the winsys.
1712 * The result is that the kernel memory manager is never a bottleneck.
1714 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1715 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1716 rctx
->num_alloc_tex_transfer_bytes
= 0;
1722 static const struct u_resource_vtbl r600_texture_vtbl
=
1724 NULL
, /* get_handle */
1725 r600_texture_destroy
, /* resource_destroy */
1726 r600_texture_transfer_map
, /* transfer_map */
1727 u_default_transfer_flush_region
, /* transfer_flush_region */
1728 r600_texture_transfer_unmap
, /* transfer_unmap */
1731 /* DCC channel type categories within which formats can be reinterpreted
1732 * while keeping the same DCC encoding. The swizzle must also match. */
1733 enum dcc_channel_type
{
1734 dcc_channel_float32
,
1737 dcc_channel_float16
,
1740 dcc_channel_uint_10_10_10_2
,
1743 dcc_channel_incompatible
,
1746 /* Return the type of DCC encoding. */
1747 static enum dcc_channel_type
1748 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1752 /* Find the first non-void channel. */
1753 for (i
= 0; i
< desc
->nr_channels
; i
++)
1754 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1756 if (i
== desc
->nr_channels
)
1757 return dcc_channel_incompatible
;
1759 switch (desc
->channel
[i
].size
) {
1761 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1762 return dcc_channel_float32
;
1763 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1764 return dcc_channel_uint32
;
1765 return dcc_channel_sint32
;
1767 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1768 return dcc_channel_float16
;
1769 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1770 return dcc_channel_uint16
;
1771 return dcc_channel_sint16
;
1773 return dcc_channel_uint_10_10_10_2
;
1775 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1776 return dcc_channel_uint8
;
1777 return dcc_channel_sint8
;
1779 return dcc_channel_incompatible
;
1783 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1784 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1785 enum pipe_format format2
)
1787 const struct util_format_description
*desc1
, *desc2
;
1788 enum dcc_channel_type type1
, type2
;
1791 if (format1
== format2
)
1794 desc1
= util_format_description(format1
);
1795 desc2
= util_format_description(format2
);
1797 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1800 /* Swizzles must be the same. */
1801 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1802 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1803 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1804 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1807 type1
= vi_get_dcc_channel_type(desc1
);
1808 type2
= vi_get_dcc_channel_type(desc2
);
1810 return type1
!= dcc_channel_incompatible
&&
1811 type2
!= dcc_channel_incompatible
&&
1815 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1816 struct pipe_resource
*tex
,
1818 enum pipe_format view_format
)
1820 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1822 if (rtex
->dcc_offset
&&
1823 rtex
->surface
.level
[level
].dcc_enabled
&&
1824 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1825 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1826 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1829 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1830 struct pipe_resource
*texture
,
1831 const struct pipe_surface
*templ
,
1832 unsigned width
, unsigned height
)
1834 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1835 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1836 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1841 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1842 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1844 pipe_reference_init(&surface
->base
.reference
, 1);
1845 pipe_resource_reference(&surface
->base
.texture
, texture
);
1846 surface
->base
.context
= pipe
;
1847 surface
->base
.format
= templ
->format
;
1848 surface
->base
.width
= width
;
1849 surface
->base
.height
= height
;
1850 surface
->base
.u
= templ
->u
;
1851 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1853 if (texture
->target
!= PIPE_BUFFER
)
1854 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1858 return &surface
->base
;
1861 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1862 struct pipe_resource
*tex
,
1863 const struct pipe_surface
*templ
)
1865 unsigned level
= templ
->u
.tex
.level
;
1866 unsigned width
= u_minify(tex
->width0
, level
);
1867 unsigned height
= u_minify(tex
->height0
, level
);
1869 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1870 const struct util_format_description
*tex_desc
1871 = util_format_description(tex
->format
);
1872 const struct util_format_description
*templ_desc
1873 = util_format_description(templ
->format
);
1875 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1877 /* Adjust size of surface if and only if the block width or
1878 * height is changed. */
1879 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1880 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1881 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1882 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1884 width
= nblks_x
* templ_desc
->block
.width
;
1885 height
= nblks_y
* templ_desc
->block
.height
;
1889 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1892 static void r600_surface_destroy(struct pipe_context
*pipe
,
1893 struct pipe_surface
*surface
)
1895 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1896 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1897 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1898 pipe_resource_reference(&surface
->texture
, NULL
);
1902 static void r600_clear_texture(struct pipe_context
*pipe
,
1903 struct pipe_resource
*tex
,
1905 const struct pipe_box
*box
,
1908 struct pipe_screen
*screen
= pipe
->screen
;
1909 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1910 struct pipe_surface tmpl
= {{0}};
1911 struct pipe_surface
*sf
;
1912 const struct util_format_description
*desc
=
1913 util_format_description(tex
->format
);
1915 tmpl
.format
= tex
->format
;
1916 tmpl
.u
.tex
.first_layer
= box
->z
;
1917 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1918 tmpl
.u
.tex
.level
= level
;
1919 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1923 if (rtex
->is_depth
) {
1926 uint8_t stencil
= 0;
1928 /* Depth is always present. */
1929 clear
= PIPE_CLEAR_DEPTH
;
1930 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1932 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1933 clear
|= PIPE_CLEAR_STENCIL
;
1934 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1937 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1939 box
->width
, box
->height
, false);
1941 union pipe_color_union color
;
1943 /* pipe_color_union requires the full vec4 representation. */
1944 if (util_format_is_pure_uint(tex
->format
))
1945 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1946 else if (util_format_is_pure_sint(tex
->format
))
1947 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1949 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1951 if (screen
->is_format_supported(screen
, tex
->format
,
1953 PIPE_BIND_RENDER_TARGET
)) {
1954 pipe
->clear_render_target(pipe
, sf
, &color
,
1956 box
->width
, box
->height
, false);
1958 /* Software fallback - just for R9G9B9E5_FLOAT */
1959 util_clear_render_target(pipe
, sf
, &color
,
1961 box
->width
, box
->height
);
1964 pipe_surface_reference(&sf
, NULL
);
1967 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1969 const struct util_format_description
*desc
= util_format_description(format
);
1971 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1973 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1974 return V_0280A0_SWAP_STD
;
1976 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1979 switch (desc
->nr_channels
) {
1981 if (HAS_SWIZZLE(0,X
))
1982 return V_0280A0_SWAP_STD
; /* X___ */
1983 else if (HAS_SWIZZLE(3,X
))
1984 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1987 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1988 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1989 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1990 return V_0280A0_SWAP_STD
; /* XY__ */
1991 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1992 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1993 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1995 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1996 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1997 return V_0280A0_SWAP_ALT
; /* X__Y */
1998 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1999 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2002 if (HAS_SWIZZLE(0,X
))
2003 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2004 else if (HAS_SWIZZLE(0,Z
))
2005 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2008 /* check the middle channels, the 1st and 4th channel can be NONE */
2009 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2010 return V_0280A0_SWAP_STD
; /* XYZW */
2011 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2012 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2013 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2014 return V_0280A0_SWAP_ALT
; /* ZYXW */
2015 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2018 return V_0280A0_SWAP_ALT_REV
;
2020 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2027 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2029 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2034 if (rctx
->dcc_stats
[slot
].query_active
)
2035 vi_separate_dcc_stop_query(&rctx
->b
,
2036 rctx
->dcc_stats
[slot
].tex
);
2038 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2039 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2040 rctx
->b
.destroy_query(&rctx
->b
,
2041 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2042 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2045 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2049 * Return the per-context slot where DCC statistics queries for the texture live.
2051 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2052 struct r600_texture
*tex
)
2054 int i
, empty_slot
= -1;
2056 /* Remove zombie textures (textures kept alive by this array only). */
2057 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2058 if (rctx
->dcc_stats
[i
].tex
&&
2059 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2060 vi_dcc_clean_up_context_slot(rctx
, i
);
2062 /* Find the texture. */
2063 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2064 /* Return if found. */
2065 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2066 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2070 /* Record the first seen empty slot. */
2071 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2075 /* Not found. Remove the oldest member to make space in the array. */
2076 if (empty_slot
== -1) {
2077 int oldest_slot
= 0;
2079 /* Find the oldest slot. */
2080 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2081 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2082 rctx
->dcc_stats
[i
].last_use_timestamp
)
2085 /* Clean up the oldest slot. */
2086 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2087 empty_slot
= oldest_slot
;
2090 /* Add the texture to the new slot. */
2091 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2092 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2096 static struct pipe_query
*
2097 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2099 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2100 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2102 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2103 return (struct pipe_query
*)query
;
2107 * Called when binding a color buffer.
2109 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2110 struct r600_texture
*tex
)
2112 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2113 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2115 assert(!rctx
->dcc_stats
[i
].query_active
);
2117 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2118 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2120 /* begin or resume the query */
2121 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2122 rctx
->dcc_stats
[i
].query_active
= true;
2126 * Called when unbinding a color buffer.
2128 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2129 struct r600_texture
*tex
)
2131 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2132 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2134 assert(rctx
->dcc_stats
[i
].query_active
);
2135 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2137 /* pause or end the query */
2138 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2139 rctx
->dcc_stats
[i
].query_active
= false;
2142 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2144 /* The minimum number of fullscreen draws per frame that is required
2146 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2149 /* Called by fast clear. */
2150 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2151 struct r600_texture
*tex
)
2153 /* The intent is to use this with shared displayable back buffers,
2154 * but it's not strictly limited only to them.
2156 if (!tex
->resource
.is_shared
||
2157 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2158 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2159 tex
->surface
.last_level
> 0 ||
2160 !tex
->surface
.dcc_size
)
2163 if (tex
->dcc_offset
)
2164 return; /* already enabled */
2166 /* Enable the DCC stat gathering. */
2167 if (!tex
->dcc_gather_statistics
) {
2168 tex
->dcc_gather_statistics
= true;
2169 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2172 if (!vi_should_enable_separate_dcc(tex
))
2173 return; /* stats show that DCC decompression is too expensive */
2175 assert(tex
->surface
.level
[0].dcc_enabled
);
2176 assert(!tex
->dcc_separate_buffer
);
2178 r600_texture_discard_cmask(rctx
->screen
, tex
);
2180 /* Get a DCC buffer. */
2181 if (tex
->last_dcc_separate_buffer
) {
2182 assert(tex
->dcc_gather_statistics
);
2183 assert(!tex
->dcc_separate_buffer
);
2184 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2185 tex
->last_dcc_separate_buffer
= NULL
;
2187 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2188 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
2190 tex
->surface
.dcc_size
,
2191 tex
->surface
.dcc_alignment
);
2192 if (!tex
->dcc_separate_buffer
)
2196 /* dcc_offset is the absolute GPUVM address. */
2197 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2199 /* no need to flag anything since this is called by fast clear that
2200 * flags framebuffer state
2205 * Called by pipe_context::flush_resource, the place where DCC decompression
2208 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2209 struct r600_texture
*tex
)
2211 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2212 struct pipe_query
*tmp
;
2213 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2214 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2215 bool disable
= false;
2217 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2218 union pipe_query_result result
;
2220 /* Read the results. */
2221 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2223 r600_query_hw_reset_buffers(rctx
,
2224 (struct r600_query_hw
*)
2225 rctx
->dcc_stats
[i
].ps_stats
[2]);
2227 /* Compute the approximate number of fullscreen draws. */
2228 tex
->ps_draw_ratio
=
2229 result
.pipeline_statistics
.ps_invocations
/
2230 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2231 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2233 disable
= tex
->dcc_separate_buffer
&&
2234 !vi_should_enable_separate_dcc(tex
);
2237 tex
->num_slow_clears
= 0;
2239 /* stop the statistics query for ps_stats[0] */
2241 vi_separate_dcc_stop_query(ctx
, tex
);
2243 /* Move the queries in the queue by one. */
2244 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2245 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2246 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2247 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2249 /* create and start a new query as ps_stats[0] */
2251 vi_separate_dcc_start_query(ctx
, tex
);
2254 assert(!tex
->last_dcc_separate_buffer
);
2255 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2256 tex
->dcc_separate_buffer
= NULL
;
2257 tex
->dcc_offset
= 0;
2258 /* no need to flag anything since this is called after
2259 * decompression that re-sets framebuffer state
2264 /* FAST COLOR CLEAR */
2266 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2267 enum pipe_format surface_format
,
2268 const union pipe_color_union
*color
)
2270 union util_color uc
;
2272 memset(&uc
, 0, sizeof(uc
));
2274 if (util_format_get_blocksizebits(surface_format
) == 128) {
2275 /* DCC fast clear only:
2276 * CLEAR_WORD0 = R = G = B
2279 assert(color
->ui
[0] == color
->ui
[1] &&
2280 color
->ui
[0] == color
->ui
[2]);
2281 uc
.ui
[0] = color
->ui
[0];
2282 uc
.ui
[1] = color
->ui
[3];
2283 } else if (util_format_is_pure_uint(surface_format
)) {
2284 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2285 } else if (util_format_is_pure_sint(surface_format
)) {
2286 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2288 util_pack_color(color
->f
, surface_format
, &uc
);
2291 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2294 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2295 const union pipe_color_union
*color
,
2296 uint32_t* reset_value
,
2297 bool* clear_words_needed
)
2299 bool values
[4] = {};
2301 bool main_value
= false;
2302 bool extra_value
= false;
2304 const struct util_format_description
*desc
= util_format_description(surface_format
);
2306 if (desc
->block
.bits
== 128 &&
2307 (color
->ui
[0] != color
->ui
[1] ||
2308 color
->ui
[0] != color
->ui
[2]))
2311 *clear_words_needed
= true;
2312 *reset_value
= 0x20202020U
;
2314 /* If we want to clear without needing a fast clear eliminate step, we
2315 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2316 * have two sets of flags, one for the last or first channel(extra) and
2317 * one for the other channels(main).
2320 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2321 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2322 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2324 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2325 if(r600_translate_colorswap(surface_format
, false) <= 1)
2326 extra_channel
= desc
->nr_channels
- 1;
2332 for (i
= 0; i
< 4; ++i
) {
2333 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2335 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2336 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2339 if (desc
->channel
[i
].pure_integer
&&
2340 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2341 /* Use the maximum value for clamping the clear color. */
2342 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2344 values
[i
] = color
->i
[i
] != 0;
2345 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2347 } else if (desc
->channel
[i
].pure_integer
&&
2348 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2349 /* Use the maximum value for clamping the clear color. */
2350 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2352 values
[i
] = color
->ui
[i
] != 0U;
2353 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2356 values
[i
] = color
->f
[i
] != 0.0F
;
2357 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2361 if (index
== extra_channel
)
2362 extra_value
= values
[i
];
2364 main_value
= values
[i
];
2367 for (int i
= 0; i
< 4; ++i
)
2368 if (values
[i
] != main_value
&&
2369 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2370 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2371 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2374 *clear_words_needed
= false;
2376 *reset_value
|= 0x80808080U
;
2379 *reset_value
|= 0x40404040U
;
2383 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2384 struct r600_texture
*rtex
,
2385 unsigned level
, unsigned clear_value
)
2387 struct pipe_resource
*dcc_buffer
;
2388 uint64_t dcc_offset
;
2390 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2392 if (rtex
->dcc_separate_buffer
) {
2393 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2396 dcc_buffer
= &rtex
->resource
.b
.b
;
2397 dcc_offset
= rtex
->dcc_offset
;
2400 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2402 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2403 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2404 clear_value
, R600_COHERENCY_CB_META
);
2407 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2408 * This allows hitting the MSAA resolve fast path, which requires that both
2409 * src and dst micro tile modes match.
2411 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2412 struct r600_texture
*rtex
)
2414 if (rtex
->resource
.is_shared
||
2415 rtex
->surface
.nsamples
<= 1 ||
2416 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2419 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2420 assert(rtex
->surface
.last_level
== 0);
2422 /* These magic numbers were copied from addrlib. It doesn't use any
2423 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2424 * different bpp and micro tile mode.
2426 if (rscreen
->chip_class
>= CIK
) {
2427 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2428 case 0: /* displayable */
2429 rtex
->surface
.tiling_index
[0] = 10;
2432 rtex
->surface
.tiling_index
[0] = 14;
2434 case 3: /* rotated */
2435 rtex
->surface
.tiling_index
[0] = 28;
2437 default: /* depth, thick */
2438 assert(!"unexpected micro mode");
2442 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2443 case 0: /* displayable */
2444 switch (rtex
->surface
.bpe
) {
2446 rtex
->surface
.tiling_index
[0] = 10;
2449 rtex
->surface
.tiling_index
[0] = 11;
2451 default: /* 32, 64 */
2452 rtex
->surface
.tiling_index
[0] = 12;
2457 switch (rtex
->surface
.bpe
) {
2459 rtex
->surface
.tiling_index
[0] = 14;
2462 rtex
->surface
.tiling_index
[0] = 15;
2465 rtex
->surface
.tiling_index
[0] = 16;
2467 default: /* 64, 128 */
2468 rtex
->surface
.tiling_index
[0] = 17;
2472 default: /* depth, thick */
2473 assert(!"unexpected micro mode");
2478 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2480 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2481 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2484 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2485 struct pipe_framebuffer_state
*fb
,
2486 struct r600_atom
*fb_state
,
2487 unsigned *buffers
, unsigned *dirty_cbufs
,
2488 const union pipe_color_union
*color
)
2492 /* This function is broken in BE, so just disable this path for now */
2493 #ifdef PIPE_ARCH_BIG_ENDIAN
2497 if (rctx
->render_cond
)
2500 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2501 struct r600_texture
*tex
;
2502 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2507 /* if this colorbuffer is not being cleared */
2508 if (!(*buffers
& clear_bit
))
2511 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2513 /* the clear is allowed if all layers are bound */
2514 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2515 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2519 /* cannot clear mipmapped textures */
2520 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2524 /* only supported on tiled surfaces */
2525 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2529 /* shared textures can't use fast clear without an explicit flush,
2530 * because there is no way to communicate the clear color among
2533 if (tex
->resource
.is_shared
&&
2534 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2537 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2538 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2539 rctx
->chip_class
>= CIK
&&
2540 rctx
->screen
->info
.drm_major
== 2 &&
2541 rctx
->screen
->info
.drm_minor
< 38) {
2545 /* Fast clear is the most appropriate place to enable DCC for
2546 * displayable surfaces.
2548 if (rctx
->chip_class
>= VI
&&
2549 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2550 vi_separate_dcc_try_enable(rctx
, tex
);
2552 /* Stoney can't do a CMASK-based clear, so all clears are
2553 * considered to be hypothetically slow clears, which
2554 * is weighed when determining to enable separate DCC.
2556 if (tex
->dcc_gather_statistics
&&
2557 rctx
->family
== CHIP_STONEY
)
2558 tex
->num_slow_clears
++;
2561 /* Try to clear DCC first, otherwise try CMASK. */
2562 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2563 uint32_t reset_value
;
2564 bool clear_words_needed
;
2566 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2569 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2570 color
, &reset_value
,
2571 &clear_words_needed
))
2574 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2576 if (clear_words_needed
)
2577 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2578 tex
->separate_dcc_dirty
= true;
2580 /* 128-bit formats are unusupported */
2581 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2585 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2586 if (rctx
->family
== CHIP_STONEY
)
2589 /* ensure CMASK is enabled */
2590 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2591 if (tex
->cmask
.size
== 0) {
2595 /* Do the fast clear. */
2596 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2597 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2598 R600_COHERENCY_CB_META
);
2600 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2603 /* We can change the micro tile mode before a full clear. */
2604 if (rctx
->screen
->chip_class
>= SI
)
2605 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2607 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2610 *dirty_cbufs
|= 1 << i
;
2611 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2612 *buffers
&= ~clear_bit
;
2616 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2618 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2619 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2622 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2624 rctx
->b
.create_surface
= r600_create_surface
;
2625 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2626 rctx
->b
.clear_texture
= r600_clear_texture
;