2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& src_level
< rsrc
->surface
.num_dcc_levels
) ||
76 (rdst
->dcc_offset
&& dst_level
< rdst
->surface
.num_dcc_levels
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
184 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
185 (box
->y
/ rtex
->surface
.blk_h
*
186 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
187 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
190 static int r600_init_surface(struct r600_common_screen
*rscreen
,
191 struct radeon_surf
*surface
,
192 const struct pipe_resource
*ptex
,
193 enum radeon_surf_mode array_mode
,
194 unsigned pitch_in_bytes_override
,
198 bool is_flushed_depth
,
199 bool tc_compatible_htile
)
201 const struct util_format_description
*desc
=
202 util_format_description(ptex
->format
);
203 bool is_depth
, is_stencil
;
205 unsigned i
, bpe
, flags
= 0;
207 is_depth
= util_format_has_depth(desc
);
208 is_stencil
= util_format_has_stencil(desc
);
210 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
211 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
212 bpe
= 4; /* stencil is allocated separately on evergreen */
214 bpe
= util_format_get_blocksize(ptex
->format
);
215 /* align byte per element on dword */
221 if (!is_flushed_depth
&& is_depth
) {
222 flags
|= RADEON_SURF_ZBUFFER
;
224 if (tc_compatible_htile
&&
225 (rscreen
->chip_class
>= GFX9
||
226 array_mode
== RADEON_SURF_MODE_2D
)) {
227 /* TC-compatible HTILE only supports Z32_FLOAT.
228 * GFX9 also supports Z16_UNORM.
229 * On VI, promote Z16 to Z32. DB->CB copies will convert
230 * the format for transfers.
232 if (rscreen
->chip_class
== VI
)
235 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
239 flags
|= RADEON_SURF_SBUFFER
;
242 if (rscreen
->chip_class
>= VI
&&
243 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
244 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
245 flags
|= RADEON_SURF_DISABLE_DCC
;
247 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
248 /* This should catch bugs in gallium users setting incorrect flags. */
249 assert(ptex
->nr_samples
<= 1 &&
250 ptex
->array_size
== 1 &&
252 ptex
->last_level
== 0 &&
253 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
255 flags
|= RADEON_SURF_SCANOUT
;
259 flags
|= RADEON_SURF_IMPORTED
;
260 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
261 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
263 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
264 array_mode
, surface
);
269 if (pitch_in_bytes_override
&&
270 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
271 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
274 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
275 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
* surface
->u
.legacy
.level
[0].nblk_y
;
279 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
280 surface
->u
.legacy
.level
[i
].offset
+= offset
;
285 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
286 struct r600_texture
*rtex
,
287 struct radeon_bo_metadata
*metadata
)
289 struct radeon_surf
*surface
= &rtex
->surface
;
291 memset(metadata
, 0, sizeof(*metadata
));
293 if (rscreen
->chip_class
>= GFX9
) {
294 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
296 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
297 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
298 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
299 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
300 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
301 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
302 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
303 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
304 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
305 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
306 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
307 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
311 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
312 struct r600_texture
*rtex
)
314 struct r600_common_screen
*rscreen
= rctx
->screen
;
315 struct pipe_context
*ctx
= &rctx
->b
;
317 if (ctx
== rscreen
->aux_context
)
318 mtx_lock(&rscreen
->aux_context_lock
);
320 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
321 ctx
->flush(ctx
, NULL
, 0);
323 if (ctx
== rscreen
->aux_context
)
324 mtx_unlock(&rscreen
->aux_context_lock
);
327 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
328 struct r600_texture
*rtex
)
330 if (!rtex
->cmask
.size
)
333 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
336 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
337 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
338 rtex
->dirty_level_mask
= 0;
340 if (rscreen
->chip_class
>= SI
)
341 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
343 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
345 if (rtex
->cmask_buffer
!= &rtex
->resource
)
346 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
348 /* Notify all contexts about the change. */
349 p_atomic_inc(&rscreen
->dirty_tex_counter
);
350 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
353 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
355 /* We can't disable DCC if it can be written by another process. */
356 return rtex
->dcc_offset
&&
357 (!rtex
->resource
.is_shared
||
358 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
361 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
362 struct r600_texture
*rtex
)
364 if (!r600_can_disable_dcc(rtex
))
367 assert(rtex
->dcc_separate_buffer
== NULL
);
370 rtex
->dcc_offset
= 0;
372 /* Notify all contexts about the change. */
373 p_atomic_inc(&rscreen
->dirty_tex_counter
);
378 * Disable DCC for the texture. (first decompress, then discard metadata).
380 * There is unresolved multi-context synchronization issue between
381 * screen::aux_context and the current context. If applications do this with
382 * multiple contexts, it's already undefined behavior for them and we don't
383 * have to worry about that. The scenario is:
385 * If context 1 disables DCC and context 2 has queued commands that write
386 * to the texture via CB with DCC enabled, and the order of operations is
388 * context 2 queues draw calls rendering to the texture, but doesn't flush
389 * context 1 disables DCC and flushes
390 * context 1 & 2 reset descriptors and FB state
391 * context 2 flushes (new compressed tiles written by the draw calls)
392 * context 1 & 2 read garbage, because DCC is disabled, yet there are
395 * \param rctx the current context if you have one, or rscreen->aux_context
398 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
399 struct r600_texture
*rtex
)
401 struct r600_common_screen
*rscreen
= rctx
->screen
;
403 if (!r600_can_disable_dcc(rtex
))
406 if (&rctx
->b
== rscreen
->aux_context
)
407 mtx_lock(&rscreen
->aux_context_lock
);
409 /* Decompress DCC. */
410 rctx
->decompress_dcc(&rctx
->b
, rtex
);
411 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
413 if (&rctx
->b
== rscreen
->aux_context
)
414 mtx_unlock(&rscreen
->aux_context_lock
);
416 return r600_texture_discard_dcc(rscreen
, rtex
);
419 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
420 struct r600_texture
*rtex
,
421 bool invalidate_storage
)
423 struct pipe_screen
*screen
= rctx
->b
.screen
;
424 struct r600_texture
*new_tex
;
425 struct pipe_resource templ
= rtex
->resource
.b
.b
;
428 templ
.bind
|= PIPE_BIND_LINEAR
;
430 /* r600g doesn't react to dirty_tex_descriptor_counter */
431 if (rctx
->chip_class
< SI
)
434 if (rtex
->resource
.is_shared
||
435 rtex
->surface
.is_linear
)
438 /* This fails with MSAA, depth, and compressed textures. */
439 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
440 RADEON_SURF_MODE_LINEAR_ALIGNED
)
443 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
447 /* Copy the pixels to the new texture. */
448 if (!invalidate_storage
) {
449 for (i
= 0; i
<= templ
.last_level
; i
++) {
453 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
454 util_max_layer(&templ
, i
) + 1, &box
);
456 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
457 &rtex
->resource
.b
.b
, i
, &box
);
461 r600_texture_discard_cmask(rctx
->screen
, rtex
);
462 r600_texture_discard_dcc(rctx
->screen
, rtex
);
464 /* Replace the structure fields of rtex. */
465 rtex
->resource
.b
.b
.bind
= templ
.bind
;
466 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
467 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
468 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
469 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
470 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
471 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
472 rtex
->resource
.domains
= new_tex
->resource
.domains
;
473 rtex
->resource
.flags
= new_tex
->resource
.flags
;
474 rtex
->size
= new_tex
->size
;
475 rtex
->surface
= new_tex
->surface
;
476 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
477 rtex
->cb_color_info
= new_tex
->cb_color_info
;
478 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
480 assert(!rtex
->htile_buffer
);
481 assert(!rtex
->cmask
.size
);
482 assert(!rtex
->fmask
.size
);
483 assert(!rtex
->dcc_offset
);
484 assert(!rtex
->is_depth
);
486 r600_texture_reference(&new_tex
, NULL
);
488 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
491 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
492 struct pipe_context
*ctx
,
493 struct pipe_resource
*resource
,
494 struct winsys_handle
*whandle
,
497 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
498 struct r600_common_context
*rctx
= (struct r600_common_context
*)
499 (ctx
? ctx
: rscreen
->aux_context
);
500 struct r600_resource
*res
= (struct r600_resource
*)resource
;
501 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
502 struct radeon_bo_metadata metadata
;
503 bool update_metadata
= false;
504 unsigned stride
, offset
, slice_size
;
506 /* This is not supported now, but it might be required for OpenCL
507 * interop in the future.
509 if (resource
->target
!= PIPE_BUFFER
&&
510 (resource
->nr_samples
> 1 || rtex
->is_depth
))
513 if (resource
->target
!= PIPE_BUFFER
) {
514 /* Since shader image stores don't support DCC on VI,
515 * disable it for external clients that want write
518 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
519 if (r600_texture_disable_dcc(rctx
, rtex
))
520 update_metadata
= true;
523 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
524 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
525 /* Eliminate fast clear (both CMASK and DCC) */
526 r600_eliminate_fast_color_clear(rctx
, rtex
);
528 /* Disable CMASK if flush_resource isn't going
531 if (rtex
->cmask
.size
)
532 r600_texture_discard_cmask(rscreen
, rtex
);
536 if (!res
->is_shared
|| update_metadata
) {
537 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
538 if (rscreen
->query_opaque_metadata
)
539 rscreen
->query_opaque_metadata(rscreen
, rtex
,
542 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
546 if (res
->is_shared
) {
547 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
550 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
551 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
552 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
554 res
->is_shared
= true;
555 res
->external_usage
= usage
;
558 if (rscreen
->chip_class
>= GFX9
) {
559 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
560 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
562 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
564 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
565 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
567 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
569 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
570 slice_size
, whandle
);
573 static void r600_texture_destroy(struct pipe_screen
*screen
,
574 struct pipe_resource
*ptex
)
576 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
577 struct r600_resource
*resource
= &rtex
->resource
;
579 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
581 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
582 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
583 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
585 pb_reference(&resource
->buf
, NULL
);
586 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
587 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
591 static const struct u_resource_vtbl r600_texture_vtbl
;
593 /* The number of samples can be specified independently of the texture. */
594 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
595 struct r600_texture
*rtex
,
597 struct r600_fmask_info
*out
)
599 /* FMASK is allocated like an ordinary texture. */
600 struct pipe_resource templ
= rtex
->resource
.b
.b
;
601 struct radeon_surf fmask
= {};
604 memset(out
, 0, sizeof(*out
));
606 if (rscreen
->chip_class
>= GFX9
) {
607 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
608 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
612 templ
.nr_samples
= 1;
613 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
615 if (rscreen
->chip_class
<= CAYMAN
) {
616 /* Use the same parameters and tile mode. */
617 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
618 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
619 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
620 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
623 fmask
.u
.legacy
.bankh
= 4;
626 switch (nr_samples
) {
635 R600_ERR("Invalid sample count for FMASK allocation.\n");
639 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
640 * This can be fixed by writing a separate FMASK allocator specifically
641 * for R600-R700 asics. */
642 if (rscreen
->chip_class
<= R700
) {
646 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
647 RADEON_SURF_MODE_2D
, &fmask
)) {
648 R600_ERR("Got error in surface_init while allocating FMASK.\n");
652 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
654 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
655 if (out
->slice_tile_max
)
656 out
->slice_tile_max
-= 1;
658 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
659 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
660 out
->bank_height
= fmask
.u
.legacy
.bankh
;
661 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
662 out
->size
= fmask
.surf_size
;
665 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
666 struct r600_texture
*rtex
)
668 r600_texture_get_fmask_info(rscreen
, rtex
,
669 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
671 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
672 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
675 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
676 struct r600_texture
*rtex
,
677 struct r600_cmask_info
*out
)
679 unsigned cmask_tile_width
= 8;
680 unsigned cmask_tile_height
= 8;
681 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
682 unsigned element_bits
= 4;
683 unsigned cmask_cache_bits
= 1024;
684 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
685 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
687 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
688 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
689 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
690 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
691 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
693 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
694 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
696 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
697 unsigned slice_bytes
=
698 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
700 assert(macro_tile_width
% 128 == 0);
701 assert(macro_tile_height
% 128 == 0);
703 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
704 out
->alignment
= MAX2(256, base_align
);
705 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
706 align(slice_bytes
, base_align
);
709 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
710 struct r600_texture
*rtex
,
711 struct r600_cmask_info
*out
)
713 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
714 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
715 unsigned cl_width
, cl_height
;
717 if (rscreen
->chip_class
>= GFX9
) {
718 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
719 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
736 case 16: /* Hawaii */
745 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
747 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
748 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
749 unsigned slice_elements
= (width
* height
) / (8*8);
751 /* Each element of CMASK is a nibble. */
752 unsigned slice_bytes
= slice_elements
/ 2;
754 out
->slice_tile_max
= (width
* height
) / (128*128);
755 if (out
->slice_tile_max
)
756 out
->slice_tile_max
-= 1;
758 out
->alignment
= MAX2(256, base_align
);
759 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
760 align(slice_bytes
, base_align
);
763 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
764 struct r600_texture
*rtex
)
766 if (rscreen
->chip_class
>= SI
) {
767 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
769 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
772 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
773 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
775 if (rscreen
->chip_class
>= SI
)
776 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
778 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
781 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
782 struct r600_texture
*rtex
)
784 if (rtex
->cmask_buffer
)
787 assert(rtex
->cmask
.size
== 0);
789 if (rscreen
->chip_class
>= SI
) {
790 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
792 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
795 rtex
->cmask_buffer
= (struct r600_resource
*)
796 r600_aligned_buffer_create(&rscreen
->b
,
797 R600_RESOURCE_FLAG_UNMAPPABLE
,
800 rtex
->cmask
.alignment
);
801 if (rtex
->cmask_buffer
== NULL
) {
802 rtex
->cmask
.size
= 0;
806 /* update colorbuffer state bits */
807 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
809 if (rscreen
->chip_class
>= SI
)
810 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
812 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
814 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
817 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
818 struct r600_texture
*rtex
)
820 unsigned cl_width
, cl_height
, width
, height
;
821 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
822 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
824 assert(rscreen
->chip_class
<= VI
);
826 rtex
->surface
.htile_size
= 0;
828 if (rscreen
->chip_class
<= EVERGREEN
&&
829 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
832 /* HW bug on R6xx. */
833 if (rscreen
->chip_class
== R600
&&
834 (rtex
->resource
.b
.b
.width0
> 7680 ||
835 rtex
->resource
.b
.b
.height0
> 7680))
838 /* HTILE is broken with 1D tiling on old kernels and CIK. */
839 if (rscreen
->chip_class
>= CIK
&&
840 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
841 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
844 /* Overalign HTILE on P2 configs to work around GPU hangs in
845 * piglit/depthstencil-render-miplevels 585.
847 * This has been confirmed to help Kabini & Stoney, where the hangs
848 * are always reproducible. I think I have seen the test hang
849 * on Carrizo too, though it was very rare there.
851 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
880 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
881 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
883 slice_elements
= (width
* height
) / (8 * 8);
884 slice_bytes
= slice_elements
* 4;
886 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
887 base_align
= num_pipes
* pipe_interleave_bytes
;
889 rtex
->surface
.htile_alignment
= base_align
;
890 rtex
->surface
.htile_size
=
891 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
892 align(slice_bytes
, base_align
);
895 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
896 struct r600_texture
*rtex
)
898 uint32_t clear_value
;
900 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
) {
901 clear_value
= 0x0000030F;
903 r600_texture_get_htile_size(rscreen
, rtex
);
907 if (!rtex
->surface
.htile_size
)
910 rtex
->htile_buffer
= (struct r600_resource
*)
911 r600_aligned_buffer_create(&rscreen
->b
,
912 R600_RESOURCE_FLAG_UNMAPPABLE
,
914 rtex
->surface
.htile_size
,
915 rtex
->surface
.htile_alignment
);
916 if (rtex
->htile_buffer
== NULL
) {
917 /* this is not a fatal error as we can still keep rendering
918 * without htile buffer */
919 R600_ERR("Failed to create buffer object for htile buffer.\n");
921 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
922 0, rtex
->surface
.htile_size
,
927 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
928 struct r600_texture
*rtex
, FILE *f
)
932 /* Common parameters. */
933 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
934 "blk_h=%u, array_size=%u, last_level=%u, "
935 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
936 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
937 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
939 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
940 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
941 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
943 if (rscreen
->chip_class
>= GFX9
) {
944 fprintf(f
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
945 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
946 rtex
->surface
.surf_size
,
947 rtex
->surface
.u
.gfx9
.surf_slice_size
,
948 rtex
->surface
.surf_alignment
,
949 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
950 rtex
->surface
.u
.gfx9
.surf
.epitch
,
951 rtex
->surface
.u
.gfx9
.surf_pitch
);
953 if (rtex
->fmask
.size
) {
954 fprintf(f
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
955 "alignment=%u, swmode=%u, epitch=%u\n",
957 rtex
->surface
.u
.gfx9
.fmask_size
,
958 rtex
->surface
.u
.gfx9
.fmask_alignment
,
959 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
960 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
963 if (rtex
->cmask
.size
) {
964 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
965 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
967 rtex
->surface
.u
.gfx9
.cmask_size
,
968 rtex
->surface
.u
.gfx9
.cmask_alignment
,
969 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
970 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
973 if (rtex
->htile_buffer
) {
974 fprintf(f
, " HTile: size=%u, alignment=%u, "
975 "rb_aligned=%u, pipe_aligned=%u\n",
976 rtex
->htile_buffer
->b
.b
.width0
,
977 rtex
->htile_buffer
->buf
->alignment
,
978 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
979 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
982 if (rtex
->dcc_offset
) {
983 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
984 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
985 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
986 rtex
->surface
.dcc_alignment
,
987 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
988 rtex
->surface
.num_dcc_levels
);
991 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
992 fprintf(f
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
993 rtex
->surface
.u
.gfx9
.stencil_offset
,
994 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
995 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1000 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1001 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1002 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1003 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1004 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1005 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1007 if (rtex
->fmask
.size
)
1008 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1009 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1010 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1011 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1012 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1014 if (rtex
->cmask
.size
)
1015 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1016 "slice_tile_max=%u\n",
1017 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1018 rtex
->cmask
.slice_tile_max
);
1020 if (rtex
->htile_buffer
)
1021 fprintf(f
, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
1022 rtex
->htile_buffer
->b
.b
.width0
,
1023 rtex
->htile_buffer
->buf
->alignment
,
1024 rtex
->tc_compatible_htile
);
1026 if (rtex
->dcc_offset
) {
1027 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1028 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1029 rtex
->surface
.dcc_alignment
);
1030 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1031 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1032 "fast_clear_size=%"PRIu64
"\n",
1033 i
, i
< rtex
->surface
.num_dcc_levels
,
1034 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1035 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1038 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1039 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1040 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1041 "mode=%u, tiling_index = %u\n",
1042 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1043 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1044 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1045 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1046 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1047 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1048 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1049 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1050 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1052 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1053 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1054 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1055 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1056 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1057 "slice_size=%"PRIu64
", npix_x=%u, "
1058 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1059 "mode=%u, tiling_index = %u\n",
1060 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1061 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1062 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1063 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1064 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1065 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1066 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1067 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1068 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1073 /* Common processing for r600_texture_create and r600_texture_from_handle */
1074 static struct r600_texture
*
1075 r600_texture_create_object(struct pipe_screen
*screen
,
1076 const struct pipe_resource
*base
,
1077 struct pb_buffer
*buf
,
1078 struct radeon_surf
*surface
)
1080 struct r600_texture
*rtex
;
1081 struct r600_resource
*resource
;
1082 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1084 rtex
= CALLOC_STRUCT(r600_texture
);
1088 resource
= &rtex
->resource
;
1089 resource
->b
.b
= *base
;
1090 resource
->b
.b
.next
= NULL
;
1091 resource
->b
.vtbl
= &r600_texture_vtbl
;
1092 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1093 resource
->b
.b
.screen
= screen
;
1095 /* don't include stencil-only formats which we don't support for rendering */
1096 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1098 rtex
->surface
= *surface
;
1099 rtex
->size
= rtex
->surface
.surf_size
;
1101 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1102 (rtex
->surface
.flags
&
1103 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1105 /* TC-compatible HTILE:
1106 * - VI only supports Z32_FLOAT.
1107 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1108 if (rtex
->tc_compatible_htile
) {
1109 if (rscreen
->chip_class
>= GFX9
&&
1110 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1111 rtex
->db_render_format
= base
->format
;
1113 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1115 rtex
->db_render_format
= base
->format
;
1118 /* Tiled depth textures utilize the non-displayable tile order.
1119 * This must be done after r600_setup_surface.
1120 * Applies to R600-Cayman. */
1121 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1122 /* Applies to GCN. */
1123 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1125 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1126 * between frames, so the only thing that can enable separate DCC
1127 * with DRI2 is multiple slow clears within a frame.
1129 rtex
->ps_draw_ratio
= 0;
1131 if (rtex
->is_depth
) {
1132 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1133 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1134 rscreen
->chip_class
>= EVERGREEN
) {
1135 if (rscreen
->chip_class
>= GFX9
) {
1136 rtex
->can_sample_z
= true;
1137 rtex
->can_sample_s
= true;
1139 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1140 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1143 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1144 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1145 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1146 rtex
->can_sample_z
= true;
1149 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1150 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1151 rtex
->db_compatible
= true;
1153 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1154 r600_texture_allocate_htile(rscreen
, rtex
);
1157 if (base
->nr_samples
> 1) {
1159 r600_texture_allocate_fmask(rscreen
, rtex
);
1160 r600_texture_allocate_cmask(rscreen
, rtex
);
1161 rtex
->cmask_buffer
= &rtex
->resource
;
1163 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1169 /* Shared textures must always set up DCC here.
1170 * If it's not present, it will be disabled by
1171 * apply_opaque_metadata later.
1173 if (rtex
->surface
.dcc_size
&&
1174 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1175 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1176 /* Reserve space for the DCC buffer. */
1177 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1178 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1182 /* Now create the backing buffer. */
1184 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1185 rtex
->surface
.surf_alignment
);
1187 resource
->flags
|= RADEON_FLAG_HANDLE
;
1189 if (!r600_alloc_resource(rscreen
, resource
)) {
1194 resource
->buf
= buf
;
1195 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1196 resource
->bo_size
= buf
->size
;
1197 resource
->bo_alignment
= buf
->alignment
;
1198 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1199 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1200 resource
->vram_usage
= buf
->size
;
1201 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1202 resource
->gart_usage
= buf
->size
;
1205 if (rtex
->cmask
.size
) {
1206 /* Initialize the cmask to 0xCC (= compressed state). */
1207 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1208 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1212 /* Initialize DCC only if the texture is not being imported. */
1213 if (!buf
&& rtex
->dcc_offset
) {
1214 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1216 rtex
->surface
.dcc_size
,
1220 /* Initialize the CMASK base register value. */
1221 rtex
->cmask
.base_address_reg
=
1222 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1224 if (rscreen
->debug_flags
& DBG_VM
) {
1225 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1226 rtex
->resource
.gpu_address
,
1227 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1228 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1229 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1232 if (rscreen
->debug_flags
& DBG_TEX
) {
1234 r600_print_texture_info(rscreen
, rtex
, stdout
);
1241 static enum radeon_surf_mode
1242 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1243 const struct pipe_resource
*templ
)
1245 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1246 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1248 /* MSAA resources must be 2D tiled. */
1249 if (templ
->nr_samples
> 1)
1250 return RADEON_SURF_MODE_2D
;
1252 /* Transfer resources should be linear. */
1253 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1254 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1256 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1257 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1258 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1259 (templ
->target
== PIPE_TEXTURE_2D
||
1260 templ
->target
== PIPE_TEXTURE_3D
))
1261 force_tiling
= true;
1263 /* Handle common candidates for the linear mode.
1264 * Compressed textures and DB surfaces must always be tiled.
1266 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1267 (!util_format_is_depth_or_stencil(templ
->format
) ||
1268 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1269 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1270 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1272 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1273 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1274 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1276 /* Cursors are linear on SI.
1277 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1278 if (rscreen
->chip_class
>= SI
&&
1279 (templ
->bind
& PIPE_BIND_CURSOR
))
1280 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1282 if (templ
->bind
& PIPE_BIND_LINEAR
)
1283 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1285 /* Textures with a very small height are recommended to be linear. */
1286 if (templ
->target
== PIPE_TEXTURE_1D
||
1287 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1288 /* Only very thin and long 2D textures should benefit from
1289 * linear_aligned. */
1290 (templ
->width0
> 8 && templ
->height0
<= 2))
1291 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1293 /* Textures likely to be mapped often. */
1294 if (templ
->usage
== PIPE_USAGE_STAGING
||
1295 templ
->usage
== PIPE_USAGE_STREAM
)
1296 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1299 /* Make small textures 1D tiled. */
1300 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1301 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1302 return RADEON_SURF_MODE_1D
;
1304 /* The allocator will switch to 1D if needed. */
1305 return RADEON_SURF_MODE_2D
;
1308 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1309 const struct pipe_resource
*templ
)
1311 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1312 struct radeon_surf surface
= {0};
1313 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1314 bool tc_compatible_htile
=
1315 rscreen
->chip_class
>= VI
&&
1316 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1317 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1318 !is_flushed_depth
&&
1319 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1320 util_format_is_depth_or_stencil(templ
->format
);
1324 r
= r600_init_surface(rscreen
, &surface
, templ
,
1325 r600_choose_tiling(rscreen
, templ
), 0, 0,
1326 false, false, is_flushed_depth
,
1327 tc_compatible_htile
);
1332 return (struct pipe_resource
*)
1333 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1336 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1337 const struct pipe_resource
*templ
,
1338 struct winsys_handle
*whandle
,
1341 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1342 struct pb_buffer
*buf
= NULL
;
1343 unsigned stride
= 0, offset
= 0;
1344 unsigned array_mode
;
1345 struct radeon_surf surface
;
1347 struct radeon_bo_metadata metadata
= {};
1348 struct r600_texture
*rtex
;
1351 /* Support only 2D textures without mipmaps */
1352 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1353 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1356 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1360 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1362 if (rscreen
->chip_class
>= GFX9
) {
1363 if (metadata
.u
.gfx9
.swizzle_mode
> 0)
1364 array_mode
= RADEON_SURF_MODE_2D
;
1366 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1368 is_scanout
= metadata
.u
.gfx9
.swizzle_mode
== 0 ||
1369 metadata
.u
.gfx9
.swizzle_mode
% 4 == 2;
1371 surface
.u
.legacy
.pipe_config
= metadata
.u
.legacy
.pipe_config
;
1372 surface
.u
.legacy
.bankw
= metadata
.u
.legacy
.bankw
;
1373 surface
.u
.legacy
.bankh
= metadata
.u
.legacy
.bankh
;
1374 surface
.u
.legacy
.tile_split
= metadata
.u
.legacy
.tile_split
;
1375 surface
.u
.legacy
.mtilea
= metadata
.u
.legacy
.mtilea
;
1376 surface
.u
.legacy
.num_banks
= metadata
.u
.legacy
.num_banks
;
1378 if (metadata
.u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1379 array_mode
= RADEON_SURF_MODE_2D
;
1380 else if (metadata
.u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1381 array_mode
= RADEON_SURF_MODE_1D
;
1383 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1385 is_scanout
= metadata
.u
.legacy
.scanout
;
1388 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1389 offset
, true, is_scanout
, false, false);
1394 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1398 rtex
->resource
.is_shared
= true;
1399 rtex
->resource
.external_usage
= usage
;
1401 if (rscreen
->apply_opaque_metadata
)
1402 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1404 /* Validate that addrlib arrived at the same surface parameters. */
1405 if (rscreen
->chip_class
>= GFX9
) {
1406 struct gfx9_surf_layout
*gfx9
= &surface
.u
.gfx9
;
1408 assert(metadata
.u
.gfx9
.swizzle_mode
== gfx9
->surf
.swizzle_mode
);
1411 return &rtex
->resource
.b
.b
;
1414 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1415 struct pipe_resource
*texture
,
1416 struct r600_texture
**staging
)
1418 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1419 struct pipe_resource resource
;
1420 struct r600_texture
**flushed_depth_texture
= staging
?
1421 staging
: &rtex
->flushed_depth_texture
;
1422 enum pipe_format pipe_format
= texture
->format
;
1425 if (rtex
->flushed_depth_texture
)
1426 return true; /* it's ready */
1428 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1429 switch (pipe_format
) {
1430 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1431 /* Save memory by not allocating the S plane. */
1432 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1434 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1435 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1436 /* Save memory bandwidth by not copying the
1437 * stencil part during flush.
1439 * This potentially increases memory bandwidth
1440 * if an application uses both Z and S texturing
1441 * simultaneously (a flushed Z24S8 texture
1442 * would be stored compactly), but how often
1443 * does that really happen?
1445 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1449 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1450 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1452 /* DB->CB copies to an 8bpp surface don't work. */
1453 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1457 memset(&resource
, 0, sizeof(resource
));
1458 resource
.target
= texture
->target
;
1459 resource
.format
= pipe_format
;
1460 resource
.width0
= texture
->width0
;
1461 resource
.height0
= texture
->height0
;
1462 resource
.depth0
= texture
->depth0
;
1463 resource
.array_size
= texture
->array_size
;
1464 resource
.last_level
= texture
->last_level
;
1465 resource
.nr_samples
= texture
->nr_samples
;
1466 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1467 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1468 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1471 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1473 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1474 if (*flushed_depth_texture
== NULL
) {
1475 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1479 (*flushed_depth_texture
)->non_disp_tiling
= false;
1484 * Initialize the pipe_resource descriptor to be of the same size as the box,
1485 * which is supposed to hold a subregion of the texture "orig" at the given
1488 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1489 struct pipe_resource
*orig
,
1490 const struct pipe_box
*box
,
1491 unsigned level
, unsigned flags
)
1493 memset(res
, 0, sizeof(*res
));
1494 res
->format
= orig
->format
;
1495 res
->width0
= box
->width
;
1496 res
->height0
= box
->height
;
1498 res
->array_size
= 1;
1499 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1502 /* We must set the correct texture target and dimensions for a 3D box. */
1503 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1504 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1505 res
->array_size
= box
->depth
;
1507 res
->target
= PIPE_TEXTURE_2D
;
1511 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1512 struct r600_texture
*rtex
,
1513 unsigned transfer_usage
,
1514 const struct pipe_box
*box
)
1516 /* r600g doesn't react to dirty_tex_descriptor_counter */
1517 return rscreen
->chip_class
>= SI
&&
1518 !rtex
->resource
.is_shared
&&
1519 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1520 rtex
->resource
.b
.b
.last_level
== 0 &&
1521 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1522 box
->x
, box
->y
, box
->z
,
1523 box
->width
, box
->height
,
1527 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1528 struct r600_texture
*rtex
)
1530 struct r600_common_screen
*rscreen
= rctx
->screen
;
1532 /* There is no point in discarding depth and tiled buffers. */
1533 assert(!rtex
->is_depth
);
1534 assert(rtex
->surface
.is_linear
);
1536 /* Reallocate the buffer in the same pipe_resource. */
1537 r600_alloc_resource(rscreen
, &rtex
->resource
);
1539 /* Initialize the CMASK base address (needed even without CMASK). */
1540 rtex
->cmask
.base_address_reg
=
1541 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1543 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1545 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1548 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1549 struct pipe_resource
*texture
,
1552 const struct pipe_box
*box
,
1553 struct pipe_transfer
**ptransfer
)
1555 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1556 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1557 struct r600_transfer
*trans
;
1558 struct r600_resource
*buf
;
1559 unsigned offset
= 0;
1561 bool use_staging_texture
= false;
1563 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1564 assert(box
->width
&& box
->height
&& box
->depth
);
1566 /* Depth textures use staging unconditionally. */
1567 if (!rtex
->is_depth
) {
1568 /* Degrade the tile mode if we get too many transfers on APUs.
1569 * On dGPUs, the staging texture is always faster.
1570 * Only count uploads that are at least 4x4 pixels large.
1572 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1574 box
->width
>= 4 && box
->height
>= 4 &&
1575 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1576 bool can_invalidate
=
1577 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1580 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1584 /* Tiled textures need to be converted into a linear texture for CPU
1585 * access. The staging texture is always linear and is placed in GART.
1587 * Reading from VRAM or GTT WC is slow, always use the staging
1588 * texture in this case.
1590 * Use the staging texture for uploads if the underlying BO
1593 if (!rtex
->surface
.is_linear
)
1594 use_staging_texture
= true;
1595 else if (usage
& PIPE_TRANSFER_READ
)
1596 use_staging_texture
=
1597 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1598 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1599 /* Write & linear only: */
1600 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1601 RADEON_USAGE_READWRITE
) ||
1602 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1603 RADEON_USAGE_READWRITE
)) {
1605 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1607 r600_texture_invalidate_storage(rctx
, rtex
);
1609 use_staging_texture
= true;
1613 trans
= CALLOC_STRUCT(r600_transfer
);
1616 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
1617 trans
->transfer
.level
= level
;
1618 trans
->transfer
.usage
= usage
;
1619 trans
->transfer
.box
= *box
;
1621 if (rtex
->is_depth
) {
1622 struct r600_texture
*staging_depth
;
1624 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1625 /* MSAA depth buffers need to be converted to single sample buffers.
1627 * Mapping MSAA depth buffers can occur if ReadPixels is called
1628 * with a multisample GLX visual.
1630 * First downsample the depth buffer to a temporary texture,
1631 * then decompress the temporary one to staging.
1633 * Only the region being mapped is transfered.
1635 struct pipe_resource resource
;
1637 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1639 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1640 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1645 if (usage
& PIPE_TRANSFER_READ
) {
1646 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1648 R600_ERR("failed to create a temporary depth texture\n");
1653 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1654 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1655 0, 0, 0, box
->depth
, 0, 0);
1656 pipe_resource_reference(&temp
, NULL
);
1660 /* XXX: only readback the rectangle which is being mapped? */
1661 /* XXX: when discard is true, no need to read back from depth texture */
1662 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1663 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1668 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1670 box
->z
, box
->z
+ box
->depth
- 1,
1673 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1676 trans
->transfer
.stride
= staging_depth
->surface
.u
.legacy
.level
[level
].nblk_x
*
1677 staging_depth
->surface
.bpe
;
1678 trans
->transfer
.layer_stride
= staging_depth
->surface
.u
.legacy
.level
[level
].slice_size
;
1679 trans
->staging
= (struct r600_resource
*)staging_depth
;
1680 buf
= trans
->staging
;
1681 } else if (use_staging_texture
) {
1682 struct pipe_resource resource
;
1683 struct r600_texture
*staging
;
1685 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1686 R600_RESOURCE_FLAG_TRANSFER
);
1687 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1688 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1690 /* Create the temporary texture. */
1691 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1693 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1697 trans
->staging
= &staging
->resource
;
1698 trans
->transfer
.stride
= staging
->surface
.u
.legacy
.level
[0].nblk_x
*
1699 staging
->surface
.bpe
;
1700 trans
->transfer
.layer_stride
= staging
->surface
.u
.legacy
.level
[0].slice_size
;
1702 if (usage
& PIPE_TRANSFER_READ
)
1703 r600_copy_to_staging_texture(ctx
, trans
);
1705 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1707 buf
= trans
->staging
;
1709 /* the resource is mapped directly */
1710 trans
->transfer
.stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
1712 trans
->transfer
.layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
1713 offset
= r600_texture_get_offset(rtex
, level
, box
);
1714 buf
= &rtex
->resource
;
1717 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1718 r600_resource_reference(&trans
->staging
, NULL
);
1723 *ptransfer
= &trans
->transfer
;
1724 return map
+ offset
;
1727 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1728 struct pipe_transfer
* transfer
)
1730 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1731 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1732 struct pipe_resource
*texture
= transfer
->resource
;
1733 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1735 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1736 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1737 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1738 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1739 &rtransfer
->staging
->b
.b
, transfer
->level
,
1742 r600_copy_from_staging_texture(ctx
, rtransfer
);
1746 if (rtransfer
->staging
) {
1747 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1748 r600_resource_reference(&rtransfer
->staging
, NULL
);
1751 /* Heuristic for {upload, draw, upload, draw, ..}:
1753 * Flush the gfx IB if we've allocated too much texture storage.
1755 * The idea is that we don't want to build IBs that use too much
1756 * memory and put pressure on the kernel memory manager and we also
1757 * want to make temporary and invalidated buffers go idle ASAP to
1758 * decrease the total memory usage or make them reusable. The memory
1759 * usage will be slightly higher than given here because of the buffer
1760 * cache in the winsys.
1762 * The result is that the kernel memory manager is never a bottleneck.
1764 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1765 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1766 rctx
->num_alloc_tex_transfer_bytes
= 0;
1769 pipe_resource_reference(&transfer
->resource
, NULL
);
1773 static const struct u_resource_vtbl r600_texture_vtbl
=
1775 NULL
, /* get_handle */
1776 r600_texture_destroy
, /* resource_destroy */
1777 r600_texture_transfer_map
, /* transfer_map */
1778 u_default_transfer_flush_region
, /* transfer_flush_region */
1779 r600_texture_transfer_unmap
, /* transfer_unmap */
1782 /* DCC channel type categories within which formats can be reinterpreted
1783 * while keeping the same DCC encoding. The swizzle must also match. */
1784 enum dcc_channel_type
{
1785 dcc_channel_float32
,
1788 dcc_channel_float16
,
1791 dcc_channel_uint_10_10_10_2
,
1794 dcc_channel_incompatible
,
1797 /* Return the type of DCC encoding. */
1798 static enum dcc_channel_type
1799 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1803 /* Find the first non-void channel. */
1804 for (i
= 0; i
< desc
->nr_channels
; i
++)
1805 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1807 if (i
== desc
->nr_channels
)
1808 return dcc_channel_incompatible
;
1810 switch (desc
->channel
[i
].size
) {
1812 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1813 return dcc_channel_float32
;
1814 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1815 return dcc_channel_uint32
;
1816 return dcc_channel_sint32
;
1818 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1819 return dcc_channel_float16
;
1820 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1821 return dcc_channel_uint16
;
1822 return dcc_channel_sint16
;
1824 return dcc_channel_uint_10_10_10_2
;
1826 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1827 return dcc_channel_uint8
;
1828 return dcc_channel_sint8
;
1830 return dcc_channel_incompatible
;
1834 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1835 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1836 enum pipe_format format2
)
1838 const struct util_format_description
*desc1
, *desc2
;
1839 enum dcc_channel_type type1
, type2
;
1842 if (format1
== format2
)
1845 desc1
= util_format_description(format1
);
1846 desc2
= util_format_description(format2
);
1848 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1851 /* Swizzles must be the same. */
1852 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1853 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1854 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1855 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1858 type1
= vi_get_dcc_channel_type(desc1
);
1859 type2
= vi_get_dcc_channel_type(desc2
);
1861 return type1
!= dcc_channel_incompatible
&&
1862 type2
!= dcc_channel_incompatible
&&
1866 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1867 struct pipe_resource
*tex
,
1869 enum pipe_format view_format
)
1871 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1873 if (rtex
->dcc_offset
&&
1874 level
< rtex
->surface
.num_dcc_levels
&&
1875 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1876 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1877 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1880 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1881 struct pipe_resource
*texture
,
1882 const struct pipe_surface
*templ
,
1883 unsigned width0
, unsigned height0
,
1884 unsigned width
, unsigned height
)
1886 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1887 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1892 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1893 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1895 pipe_reference_init(&surface
->base
.reference
, 1);
1896 pipe_resource_reference(&surface
->base
.texture
, texture
);
1897 surface
->base
.context
= pipe
;
1898 surface
->base
.format
= templ
->format
;
1899 surface
->base
.width
= width
;
1900 surface
->base
.height
= height
;
1901 surface
->base
.u
= templ
->u
;
1903 surface
->width0
= width0
;
1904 surface
->height0
= height0
;
1906 if (texture
->target
!= PIPE_BUFFER
)
1907 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1911 return &surface
->base
;
1914 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1915 struct pipe_resource
*tex
,
1916 const struct pipe_surface
*templ
)
1918 unsigned level
= templ
->u
.tex
.level
;
1919 unsigned width
= u_minify(tex
->width0
, level
);
1920 unsigned height
= u_minify(tex
->height0
, level
);
1922 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1923 const struct util_format_description
*tex_desc
1924 = util_format_description(tex
->format
);
1925 const struct util_format_description
*templ_desc
1926 = util_format_description(templ
->format
);
1928 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1930 /* Adjust size of surface if and only if the block width or
1931 * height is changed. */
1932 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1933 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1934 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1935 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1937 width
= nblks_x
* templ_desc
->block
.width
;
1938 height
= nblks_y
* templ_desc
->block
.height
;
1942 return r600_create_surface_custom(pipe
, tex
, templ
,
1943 tex
->width0
, tex
->height0
,
1947 static void r600_surface_destroy(struct pipe_context
*pipe
,
1948 struct pipe_surface
*surface
)
1950 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1951 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1952 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1953 pipe_resource_reference(&surface
->texture
, NULL
);
1957 static void r600_clear_texture(struct pipe_context
*pipe
,
1958 struct pipe_resource
*tex
,
1960 const struct pipe_box
*box
,
1963 struct pipe_screen
*screen
= pipe
->screen
;
1964 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1965 struct pipe_surface tmpl
= {{0}};
1966 struct pipe_surface
*sf
;
1967 const struct util_format_description
*desc
=
1968 util_format_description(tex
->format
);
1970 tmpl
.format
= tex
->format
;
1971 tmpl
.u
.tex
.first_layer
= box
->z
;
1972 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1973 tmpl
.u
.tex
.level
= level
;
1974 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1978 if (rtex
->is_depth
) {
1981 uint8_t stencil
= 0;
1983 /* Depth is always present. */
1984 clear
= PIPE_CLEAR_DEPTH
;
1985 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1987 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1988 clear
|= PIPE_CLEAR_STENCIL
;
1989 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1992 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1994 box
->width
, box
->height
, false);
1996 union pipe_color_union color
;
1998 /* pipe_color_union requires the full vec4 representation. */
1999 if (util_format_is_pure_uint(tex
->format
))
2000 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2001 else if (util_format_is_pure_sint(tex
->format
))
2002 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2004 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2006 if (screen
->is_format_supported(screen
, tex
->format
,
2008 PIPE_BIND_RENDER_TARGET
)) {
2009 pipe
->clear_render_target(pipe
, sf
, &color
,
2011 box
->width
, box
->height
, false);
2013 /* Software fallback - just for R9G9B9E5_FLOAT */
2014 util_clear_render_target(pipe
, sf
, &color
,
2016 box
->width
, box
->height
);
2019 pipe_surface_reference(&sf
, NULL
);
2022 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2024 const struct util_format_description
*desc
= util_format_description(format
);
2026 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2028 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2029 return V_0280A0_SWAP_STD
;
2031 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2034 switch (desc
->nr_channels
) {
2036 if (HAS_SWIZZLE(0,X
))
2037 return V_0280A0_SWAP_STD
; /* X___ */
2038 else if (HAS_SWIZZLE(3,X
))
2039 return V_0280A0_SWAP_ALT_REV
; /* ___X */
2042 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2043 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2044 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2045 return V_0280A0_SWAP_STD
; /* XY__ */
2046 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2047 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2048 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2050 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
2051 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2052 return V_0280A0_SWAP_ALT
; /* X__Y */
2053 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2054 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2057 if (HAS_SWIZZLE(0,X
))
2058 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2059 else if (HAS_SWIZZLE(0,Z
))
2060 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2063 /* check the middle channels, the 1st and 4th channel can be NONE */
2064 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2065 return V_0280A0_SWAP_STD
; /* XYZW */
2066 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2067 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2068 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2069 return V_0280A0_SWAP_ALT
; /* ZYXW */
2070 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2073 return V_0280A0_SWAP_ALT_REV
;
2075 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2082 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2084 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2089 if (rctx
->dcc_stats
[slot
].query_active
)
2090 vi_separate_dcc_stop_query(&rctx
->b
,
2091 rctx
->dcc_stats
[slot
].tex
);
2093 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2094 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2095 rctx
->b
.destroy_query(&rctx
->b
,
2096 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2097 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2100 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2104 * Return the per-context slot where DCC statistics queries for the texture live.
2106 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2107 struct r600_texture
*tex
)
2109 int i
, empty_slot
= -1;
2111 /* Remove zombie textures (textures kept alive by this array only). */
2112 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2113 if (rctx
->dcc_stats
[i
].tex
&&
2114 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2115 vi_dcc_clean_up_context_slot(rctx
, i
);
2117 /* Find the texture. */
2118 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2119 /* Return if found. */
2120 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2121 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2125 /* Record the first seen empty slot. */
2126 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2130 /* Not found. Remove the oldest member to make space in the array. */
2131 if (empty_slot
== -1) {
2132 int oldest_slot
= 0;
2134 /* Find the oldest slot. */
2135 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2136 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2137 rctx
->dcc_stats
[i
].last_use_timestamp
)
2140 /* Clean up the oldest slot. */
2141 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2142 empty_slot
= oldest_slot
;
2145 /* Add the texture to the new slot. */
2146 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2147 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2151 static struct pipe_query
*
2152 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2154 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2155 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2157 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2158 return (struct pipe_query
*)query
;
2162 * Called when binding a color buffer.
2164 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2165 struct r600_texture
*tex
)
2167 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2168 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2170 assert(!rctx
->dcc_stats
[i
].query_active
);
2172 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2173 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2175 /* begin or resume the query */
2176 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2177 rctx
->dcc_stats
[i
].query_active
= true;
2181 * Called when unbinding a color buffer.
2183 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2184 struct r600_texture
*tex
)
2186 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2187 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2189 assert(rctx
->dcc_stats
[i
].query_active
);
2190 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2192 /* pause or end the query */
2193 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2194 rctx
->dcc_stats
[i
].query_active
= false;
2197 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2199 /* The minimum number of fullscreen draws per frame that is required
2201 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2204 /* Called by fast clear. */
2205 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2206 struct r600_texture
*tex
)
2208 /* The intent is to use this with shared displayable back buffers,
2209 * but it's not strictly limited only to them.
2211 if (!tex
->resource
.is_shared
||
2212 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2213 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2214 tex
->resource
.b
.b
.last_level
> 0 ||
2215 !tex
->surface
.dcc_size
)
2218 if (tex
->dcc_offset
)
2219 return; /* already enabled */
2221 /* Enable the DCC stat gathering. */
2222 if (!tex
->dcc_gather_statistics
) {
2223 tex
->dcc_gather_statistics
= true;
2224 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2227 if (!vi_should_enable_separate_dcc(tex
))
2228 return; /* stats show that DCC decompression is too expensive */
2230 assert(tex
->surface
.num_dcc_levels
);
2231 assert(!tex
->dcc_separate_buffer
);
2233 r600_texture_discard_cmask(rctx
->screen
, tex
);
2235 /* Get a DCC buffer. */
2236 if (tex
->last_dcc_separate_buffer
) {
2237 assert(tex
->dcc_gather_statistics
);
2238 assert(!tex
->dcc_separate_buffer
);
2239 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2240 tex
->last_dcc_separate_buffer
= NULL
;
2242 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2243 r600_aligned_buffer_create(rctx
->b
.screen
,
2244 R600_RESOURCE_FLAG_UNMAPPABLE
,
2246 tex
->surface
.dcc_size
,
2247 tex
->surface
.dcc_alignment
);
2248 if (!tex
->dcc_separate_buffer
)
2252 /* dcc_offset is the absolute GPUVM address. */
2253 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2255 /* no need to flag anything since this is called by fast clear that
2256 * flags framebuffer state
2261 * Called by pipe_context::flush_resource, the place where DCC decompression
2264 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2265 struct r600_texture
*tex
)
2267 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2268 struct pipe_query
*tmp
;
2269 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2270 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2271 bool disable
= false;
2273 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2274 union pipe_query_result result
;
2276 /* Read the results. */
2277 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2279 r600_query_hw_reset_buffers(rctx
,
2280 (struct r600_query_hw
*)
2281 rctx
->dcc_stats
[i
].ps_stats
[2]);
2283 /* Compute the approximate number of fullscreen draws. */
2284 tex
->ps_draw_ratio
=
2285 result
.pipeline_statistics
.ps_invocations
/
2286 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2287 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2289 disable
= tex
->dcc_separate_buffer
&&
2290 !vi_should_enable_separate_dcc(tex
);
2293 tex
->num_slow_clears
= 0;
2295 /* stop the statistics query for ps_stats[0] */
2297 vi_separate_dcc_stop_query(ctx
, tex
);
2299 /* Move the queries in the queue by one. */
2300 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2301 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2302 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2303 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2305 /* create and start a new query as ps_stats[0] */
2307 vi_separate_dcc_start_query(ctx
, tex
);
2310 assert(!tex
->last_dcc_separate_buffer
);
2311 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2312 tex
->dcc_separate_buffer
= NULL
;
2313 tex
->dcc_offset
= 0;
2314 /* no need to flag anything since this is called after
2315 * decompression that re-sets framebuffer state
2320 /* FAST COLOR CLEAR */
2322 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2323 enum pipe_format surface_format
,
2324 const union pipe_color_union
*color
)
2326 union util_color uc
;
2328 memset(&uc
, 0, sizeof(uc
));
2330 if (rtex
->surface
.bpe
== 16) {
2331 /* DCC fast clear only:
2332 * CLEAR_WORD0 = R = G = B
2335 assert(color
->ui
[0] == color
->ui
[1] &&
2336 color
->ui
[0] == color
->ui
[2]);
2337 uc
.ui
[0] = color
->ui
[0];
2338 uc
.ui
[1] = color
->ui
[3];
2339 } else if (util_format_is_pure_uint(surface_format
)) {
2340 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2341 } else if (util_format_is_pure_sint(surface_format
)) {
2342 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2344 util_pack_color(color
->f
, surface_format
, &uc
);
2347 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2350 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2351 const union pipe_color_union
*color
,
2352 uint32_t* reset_value
,
2353 bool* clear_words_needed
)
2355 bool values
[4] = {};
2357 bool main_value
= false;
2358 bool extra_value
= false;
2360 const struct util_format_description
*desc
= util_format_description(surface_format
);
2362 if (desc
->block
.bits
== 128 &&
2363 (color
->ui
[0] != color
->ui
[1] ||
2364 color
->ui
[0] != color
->ui
[2]))
2367 *clear_words_needed
= true;
2368 *reset_value
= 0x20202020U
;
2370 /* If we want to clear without needing a fast clear eliminate step, we
2371 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2372 * have two sets of flags, one for the last or first channel(extra) and
2373 * one for the other channels(main).
2376 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2377 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2378 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2380 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2381 if(r600_translate_colorswap(surface_format
, false) <= 1)
2382 extra_channel
= desc
->nr_channels
- 1;
2388 for (i
= 0; i
< 4; ++i
) {
2389 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2391 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2392 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2395 if (desc
->channel
[i
].pure_integer
&&
2396 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2397 /* Use the maximum value for clamping the clear color. */
2398 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2400 values
[i
] = color
->i
[i
] != 0;
2401 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2403 } else if (desc
->channel
[i
].pure_integer
&&
2404 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2405 /* Use the maximum value for clamping the clear color. */
2406 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2408 values
[i
] = color
->ui
[i
] != 0U;
2409 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2412 values
[i
] = color
->f
[i
] != 0.0F
;
2413 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2417 if (index
== extra_channel
)
2418 extra_value
= values
[i
];
2420 main_value
= values
[i
];
2423 for (int i
= 0; i
< 4; ++i
)
2424 if (values
[i
] != main_value
&&
2425 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2426 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2427 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2430 *clear_words_needed
= false;
2432 *reset_value
|= 0x80808080U
;
2435 *reset_value
|= 0x40404040U
;
2439 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2440 struct r600_texture
*rtex
,
2441 unsigned level
, unsigned clear_value
)
2443 struct pipe_resource
*dcc_buffer
;
2444 uint64_t dcc_offset
, clear_size
;
2446 assert(rtex
->dcc_offset
&& level
< rtex
->surface
.num_dcc_levels
);
2448 if (rtex
->dcc_separate_buffer
) {
2449 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2452 dcc_buffer
= &rtex
->resource
.b
.b
;
2453 dcc_offset
= rtex
->dcc_offset
;
2456 if (rctx
->chip_class
>= GFX9
) {
2457 /* Mipmap level clears aren't implemented. */
2458 assert(rtex
->resource
.b
.b
.last_level
== 0);
2459 /* MSAA needs a different clear size. */
2460 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2461 clear_size
= rtex
->surface
.dcc_size
;
2463 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2464 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2467 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2468 clear_value
, R600_COHERENCY_CB_META
);
2471 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2472 * This allows hitting the MSAA resolve fast path, which requires that both
2473 * src and dst micro tile modes match.
2475 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2476 struct r600_texture
*rtex
)
2478 if (rtex
->resource
.is_shared
||
2479 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2480 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2483 assert(rscreen
->chip_class
>= GFX9
||
2484 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2485 assert(rtex
->resource
.b
.b
.last_level
== 0);
2487 if (rscreen
->chip_class
>= GFX9
) {
2488 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2489 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2491 /* If you do swizzle_mode % 4, you'll get:
2497 * Depth-sample order isn't allowed:
2499 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2501 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2502 case RADEON_MICRO_MODE_DISPLAY
:
2503 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2504 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2506 case RADEON_MICRO_MODE_THIN
:
2507 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2508 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2510 case RADEON_MICRO_MODE_ROTATED
:
2511 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2512 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2514 default: /* depth */
2515 assert(!"unexpected micro mode");
2518 } else if (rscreen
->chip_class
>= CIK
) {
2519 /* These magic numbers were copied from addrlib. It doesn't use
2520 * any definitions for them either. They are all 2D_TILED_THIN1
2521 * modes with different bpp and micro tile mode.
2523 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2524 case RADEON_MICRO_MODE_DISPLAY
:
2525 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2527 case RADEON_MICRO_MODE_THIN
:
2528 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2530 case RADEON_MICRO_MODE_ROTATED
:
2531 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2533 default: /* depth, thick */
2534 assert(!"unexpected micro mode");
2538 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2539 case RADEON_MICRO_MODE_DISPLAY
:
2540 switch (rtex
->surface
.bpe
) {
2542 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2545 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2548 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2552 case RADEON_MICRO_MODE_THIN
:
2553 switch (rtex
->surface
.bpe
) {
2555 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2558 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2561 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2563 default: /* 8, 16 */
2564 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2568 default: /* depth, thick */
2569 assert(!"unexpected micro mode");
2574 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2576 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2579 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2580 struct pipe_framebuffer_state
*fb
,
2581 struct r600_atom
*fb_state
,
2582 unsigned *buffers
, unsigned *dirty_cbufs
,
2583 const union pipe_color_union
*color
)
2587 /* This function is broken in BE, so just disable this path for now */
2588 #ifdef PIPE_ARCH_BIG_ENDIAN
2592 if (rctx
->render_cond
)
2595 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2596 struct r600_texture
*tex
;
2597 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2602 /* if this colorbuffer is not being cleared */
2603 if (!(*buffers
& clear_bit
))
2606 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2608 /* the clear is allowed if all layers are bound */
2609 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2610 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2614 /* cannot clear mipmapped textures */
2615 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2619 /* only supported on tiled surfaces */
2620 if (tex
->surface
.is_linear
) {
2624 /* shared textures can't use fast clear without an explicit flush,
2625 * because there is no way to communicate the clear color among
2628 if (tex
->resource
.is_shared
&&
2629 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2632 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2633 if (rctx
->chip_class
== CIK
&&
2634 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2635 rctx
->screen
->info
.drm_major
== 2 &&
2636 rctx
->screen
->info
.drm_minor
< 38) {
2640 /* Fast clear is the most appropriate place to enable DCC for
2641 * displayable surfaces.
2643 if (rctx
->chip_class
>= VI
&&
2644 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2645 vi_separate_dcc_try_enable(rctx
, tex
);
2647 /* RB+ isn't supported with a CMASK-based clear, so all
2648 * clears are considered to be hypothetically slow
2649 * clears, which is weighed when determining whether to
2650 * enable separate DCC.
2652 if (tex
->dcc_gather_statistics
&&
2653 rctx
->screen
->rbplus_allowed
)
2654 tex
->num_slow_clears
++;
2657 /* Try to clear DCC first, otherwise try CMASK. */
2658 if (tex
->dcc_offset
&& tex
->surface
.num_dcc_levels
) {
2659 uint32_t reset_value
;
2660 bool clear_words_needed
;
2662 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2665 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2666 color
, &reset_value
,
2667 &clear_words_needed
))
2670 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2672 if (clear_words_needed
)
2673 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2674 tex
->separate_dcc_dirty
= true;
2676 /* 128-bit formats are unusupported */
2677 if (tex
->surface
.bpe
> 8) {
2681 /* RB+ doesn't work with CMASK fast clear. */
2682 if (rctx
->screen
->rbplus_allowed
)
2685 /* ensure CMASK is enabled */
2686 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2687 if (tex
->cmask
.size
== 0) {
2691 /* Do the fast clear. */
2692 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2693 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2694 R600_COHERENCY_CB_META
);
2696 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2699 /* We can change the micro tile mode before a full clear. */
2700 if (rctx
->screen
->chip_class
>= SI
)
2701 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2703 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2706 *dirty_cbufs
|= 1 << i
;
2707 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2708 *buffers
&= ~clear_bit
;
2712 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2714 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2715 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2718 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2720 rctx
->b
.create_surface
= r600_create_surface
;
2721 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2722 rctx
->b
.clear_texture
= r600_clear_texture
;