2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
33 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
34 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
35 struct pipe_resource
*dst
,
37 unsigned dstx
, unsigned dsty
, unsigned dstz
,
38 struct pipe_resource
*src
,
40 const struct pipe_box
*src_box
)
42 struct pipe_blit_info blit
;
44 memset(&blit
, 0, sizeof(blit
));
45 blit
.src
.resource
= src
;
46 blit
.src
.format
= src
->format
;
47 blit
.src
.level
= src_level
;
48 blit
.src
.box
= *src_box
;
49 blit
.dst
.resource
= dst
;
50 blit
.dst
.format
= dst
->format
;
51 blit
.dst
.level
= dst_level
;
52 blit
.dst
.box
.x
= dstx
;
53 blit
.dst
.box
.y
= dsty
;
54 blit
.dst
.box
.z
= dstz
;
55 blit
.dst
.box
.width
= src_box
->width
;
56 blit
.dst
.box
.height
= src_box
->height
;
57 blit
.dst
.box
.depth
= src_box
->depth
;
58 blit
.mask
= util_format_get_mask(src
->format
) &
59 util_format_get_mask(dst
->format
);
60 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
63 pipe
->blit(pipe
, &blit
);
67 /* Copy from a full GPU texture to a transfer's staging one. */
68 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
70 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
71 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
72 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
73 struct pipe_resource
*src
= transfer
->resource
;
75 if (src
->nr_samples
> 1) {
76 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
77 src
, transfer
->level
, &transfer
->box
);
81 if (!rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0,
84 ctx
->resource_copy_region(ctx
, dst
, 0, 0, 0, 0,
85 src
, transfer
->level
, &transfer
->box
);
89 /* Copy from a transfer's staging texture to a full GPU one. */
90 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
92 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
93 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
94 struct pipe_resource
*dst
= transfer
->resource
;
95 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
98 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
100 if (dst
->nr_samples
> 1) {
101 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
102 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
107 if (!rctx
->dma_copy(ctx
, dst
, transfer
->level
,
108 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
110 ctx
->resource_copy_region(ctx
, dst
, transfer
->level
,
111 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
116 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
117 const struct pipe_box
*box
)
119 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
121 return rtex
->surface
.level
[level
].offset
+
122 box
->z
* rtex
->surface
.level
[level
].slice_size
+
123 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
124 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
127 static int r600_init_surface(struct r600_common_screen
*rscreen
,
128 struct radeon_surface
*surface
,
129 const struct pipe_resource
*ptex
,
131 bool is_flushed_depth
)
133 const struct util_format_description
*desc
=
134 util_format_description(ptex
->format
);
135 bool is_depth
, is_stencil
;
137 is_depth
= util_format_has_depth(desc
);
138 is_stencil
= util_format_has_stencil(desc
);
140 surface
->npix_x
= ptex
->width0
;
141 surface
->npix_y
= ptex
->height0
;
142 surface
->npix_z
= ptex
->depth0
;
143 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
144 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
146 surface
->array_size
= 1;
147 surface
->last_level
= ptex
->last_level
;
149 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
150 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
151 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
153 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
154 /* align byte per element on dword */
155 if (surface
->bpe
== 3) {
160 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
161 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
163 switch (ptex
->target
) {
164 case PIPE_TEXTURE_1D
:
165 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
167 case PIPE_TEXTURE_RECT
:
168 case PIPE_TEXTURE_2D
:
169 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
171 case PIPE_TEXTURE_3D
:
172 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
174 case PIPE_TEXTURE_1D_ARRAY
:
175 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
176 surface
->array_size
= ptex
->array_size
;
178 case PIPE_TEXTURE_2D_ARRAY
:
179 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
180 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
181 surface
->array_size
= ptex
->array_size
;
183 case PIPE_TEXTURE_CUBE
:
184 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
190 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
191 surface
->flags
|= RADEON_SURF_SCANOUT
;
194 if (!is_flushed_depth
&& is_depth
) {
195 surface
->flags
|= RADEON_SURF_ZBUFFER
;
198 surface
->flags
|= RADEON_SURF_SBUFFER
|
199 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
202 if (rscreen
->chip_class
>= SI
) {
203 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
208 static int r600_setup_surface(struct pipe_screen
*screen
,
209 struct r600_texture
*rtex
,
210 unsigned pitch_in_bytes_override
)
212 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
215 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
220 rtex
->size
= rtex
->surface
.bo_size
;
222 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
223 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
226 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
227 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
228 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
229 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
230 rtex
->surface
.stencil_offset
=
231 rtex
->surface
.stencil_level
[0].offset
= rtex
->surface
.level
[0].slice_size
;
237 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
238 struct pipe_resource
*ptex
,
239 struct winsys_handle
*whandle
)
241 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
242 struct r600_resource
*resource
= &rtex
->resource
;
243 struct radeon_surface
*surface
= &rtex
->surface
;
244 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
246 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
248 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
249 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
250 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
251 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
252 surface
->bankw
, surface
->bankh
,
254 surface
->stencil_tile_split
,
256 surface
->level
[0].pitch_bytes
);
258 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
259 surface
->level
[0].pitch_bytes
, whandle
);
262 static void r600_texture_destroy(struct pipe_screen
*screen
,
263 struct pipe_resource
*ptex
)
265 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
266 struct r600_resource
*resource
= &rtex
->resource
;
268 if (rtex
->flushed_depth_texture
)
269 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
271 pipe_resource_reference((struct pipe_resource
**)&rtex
->htile
, NULL
);
272 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
273 pipe_resource_reference((struct pipe_resource
**)&rtex
->cmask_buffer
, NULL
);
275 pb_reference(&resource
->buf
, NULL
);
279 static const struct u_resource_vtbl r600_texture_vtbl
;
281 /* The number of samples can be specified independently of the texture. */
282 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
283 struct r600_texture
*rtex
,
285 struct r600_fmask_info
*out
)
287 /* FMASK is allocated like an ordinary texture. */
288 struct radeon_surface fmask
= rtex
->surface
;
290 memset(out
, 0, sizeof(*out
));
292 fmask
.bo_alignment
= 0;
295 fmask
.flags
|= RADEON_SURF_FMASK
;
297 if (rscreen
->chip_class
>= SI
) {
298 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
301 switch (nr_samples
) {
305 if (rscreen
->chip_class
<= CAYMAN
) {
313 R600_ERR("Invalid sample count for FMASK allocation.\n");
317 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
318 * This can be fixed by writing a separate FMASK allocator specifically
319 * for R600-R700 asics. */
320 if (rscreen
->chip_class
<= R700
) {
324 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
325 R600_ERR("Got error in surface_init while allocating FMASK.\n");
329 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
331 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
332 if (out
->slice_tile_max
)
333 out
->slice_tile_max
-= 1;
335 out
->tile_mode_index
= fmask
.tiling_index
[0];
336 out
->pitch
= fmask
.level
[0].nblk_x
;
337 out
->bank_height
= fmask
.bankh
;
338 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
339 out
->size
= fmask
.bo_size
;
342 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
343 struct r600_texture
*rtex
)
345 r600_texture_get_fmask_info(rscreen
, rtex
,
346 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
348 rtex
->fmask
.offset
= align(rtex
->size
, rtex
->fmask
.alignment
);
349 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
352 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
353 struct r600_texture
*rtex
,
354 struct r600_cmask_info
*out
)
356 unsigned cmask_tile_width
= 8;
357 unsigned cmask_tile_height
= 8;
358 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
359 unsigned element_bits
= 4;
360 unsigned cmask_cache_bits
= 1024;
361 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
362 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
364 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
365 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
366 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
367 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
368 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
370 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
371 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
373 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
374 unsigned slice_bytes
=
375 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
377 assert(macro_tile_width
% 128 == 0);
378 assert(macro_tile_height
% 128 == 0);
380 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
381 out
->alignment
= MAX2(256, base_align
);
382 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
385 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
386 struct r600_texture
*rtex
,
387 struct r600_cmask_info
*out
)
389 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
390 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
391 unsigned cl_width
, cl_height
;
411 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
413 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
414 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
415 unsigned slice_elements
= (width
* height
) / (8*8);
417 /* Each element of CMASK is a nibble. */
418 unsigned slice_bytes
= slice_elements
/ 2;
420 out
->slice_tile_max
= (width
* height
) / (128*128);
421 if (out
->slice_tile_max
)
422 out
->slice_tile_max
-= 1;
424 out
->alignment
= MAX2(256, base_align
);
425 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
428 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
429 struct r600_texture
*rtex
)
431 if (rscreen
->chip_class
>= SI
) {
432 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
434 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
437 rtex
->cmask
.offset
= align(rtex
->size
, rtex
->cmask
.alignment
);
438 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
441 void r600_texture_init_cmask(struct r600_common_screen
*rscreen
,
442 struct r600_texture
*rtex
)
444 assert(rtex
->cmask
.size
== 0);
446 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
448 rtex
->cmask_buffer
= (struct r600_resource
*)
449 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
450 PIPE_USAGE_STATIC
, rtex
->cmask
.size
);
451 if (rtex
->cmask_buffer
== NULL
) {
452 rtex
->cmask
.size
= 0;
456 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
457 struct r600_texture
*rtex
)
459 unsigned sw
= rtex
->surface
.level
[0].nblk_x
* rtex
->surface
.blk_w
;
460 unsigned sh
= rtex
->surface
.level
[0].nblk_y
* rtex
->surface
.blk_h
;
462 unsigned npipes
= rscreen
->info
.r600_num_tile_pipes
;
464 /* XXX also use it for other texture targets */
465 if (rscreen
->info
.drm_minor
< 26 ||
466 rtex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
467 rtex
->surface
.level
[0].nblk_x
< 32 ||
468 rtex
->surface
.level
[0].nblk_y
< 32) {
472 /* this alignment and htile size only apply to linear htile buffer */
473 sw
= align(sw
, 16 << 3);
474 sh
= align(sh
, npipes
<< 3);
475 htile_size
= (sw
>> 3) * (sh
>> 3) * 4;
476 /* must be aligned with 2K * npipes */
477 htile_size
= align(htile_size
, (2 << 10) * npipes
);
479 /* XXX don't allocate it separately */
480 rtex
->htile
= (struct r600_resource
*)pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
481 PIPE_USAGE_STATIC
, htile_size
);
482 if (rtex
->htile
== NULL
) {
483 /* this is not a fatal error as we can still keep rendering
484 * without htile buffer
486 R600_ERR("r600: failed to create bo for htile buffers\n");
488 r600_screen_clear_buffer(rscreen
, &rtex
->htile
->b
.b
, 0, htile_size
, 0);
492 static struct r600_texture
*
493 r600_texture_create_object(struct pipe_screen
*screen
,
494 const struct pipe_resource
*base
,
495 unsigned pitch_in_bytes_override
,
496 struct pb_buffer
*buf
,
497 struct radeon_surface
*surface
)
499 struct r600_texture
*rtex
;
500 struct r600_resource
*resource
;
501 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
504 rtex
= CALLOC_STRUCT(r600_texture
);
508 resource
= &rtex
->resource
;
509 resource
->b
.b
= *base
;
510 resource
->b
.vtbl
= &r600_texture_vtbl
;
511 pipe_reference_init(&resource
->b
.b
.reference
, 1);
512 resource
->b
.b
.screen
= screen
;
513 rtex
->pitch_override
= pitch_in_bytes_override
;
515 /* don't include stencil-only formats which we don't support for rendering */
516 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
518 /* Tiled depth textures utilize the non-displayable tile order.
519 * Applies to R600-Cayman. */
520 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
522 rtex
->surface
= *surface
;
523 r
= r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
);
529 if (base
->nr_samples
> 1 && !rtex
->is_depth
&& !buf
) {
530 r600_texture_allocate_fmask(rscreen
, rtex
);
531 r600_texture_allocate_cmask(rscreen
, rtex
);
532 rtex
->cmask_buffer
= &rtex
->resource
;
535 if (!rtex
->is_depth
&& base
->nr_samples
> 1 &&
536 (!rtex
->fmask
.size
|| !rtex
->cmask
.size
)) {
541 if (rtex
->is_depth
&&
542 !(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
543 R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
544 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
)) {
545 if (rscreen
->chip_class
>= SI
) {
546 /* XXX implement Hyper-Z for SI.
547 * Reuse the CMASK allocator, which is almost the same as HTILE. */
549 r600_texture_allocate_htile(rscreen
, rtex
);
553 /* Now create the backing buffer. */
555 unsigned base_align
= rtex
->surface
.bo_alignment
;
556 unsigned usage
= rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
557 PIPE_USAGE_STATIC
: base
->usage
;
559 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, FALSE
, usage
)) {
565 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
566 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
569 if (rtex
->cmask
.size
) {
570 /* Initialize the cmask to 0xCC (= compressed state). */
571 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
572 rtex
->cmask
.offset
, rtex
->cmask
.size
, 0xCCCCCCCC);
575 if (rscreen
->debug_flags
& DBG_VM
) {
576 fprintf(stderr
, "VM start=0x%llX end=0x%llX | Texture %ix%ix%i, %i levels, %i samples, %s\n",
577 r600_resource_va(screen
, &rtex
->resource
.b
.b
),
578 r600_resource_va(screen
, &rtex
->resource
.b
.b
) + rtex
->resource
.buf
->size
,
579 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
580 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
583 if (rscreen
->debug_flags
& DBG_TEX_DEPTH
&& rtex
->is_depth
) {
584 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
585 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
586 "bpe=%u, nsamples=%u, flags=%u\n",
587 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
588 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
589 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
590 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
591 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
592 rtex
->surface
.flags
);
593 if (rtex
->surface
.flags
& RADEON_SURF_ZBUFFER
) {
594 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
595 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
596 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
597 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
598 i
, rtex
->surface
.level
[i
].offset
,
599 rtex
->surface
.level
[i
].slice_size
,
600 u_minify(rtex
->resource
.b
.b
.width0
, i
),
601 u_minify(rtex
->resource
.b
.b
.height0
, i
),
602 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
603 rtex
->surface
.level
[i
].nblk_x
,
604 rtex
->surface
.level
[i
].nblk_y
,
605 rtex
->surface
.level
[i
].nblk_z
,
606 rtex
->surface
.level
[i
].pitch_bytes
,
607 rtex
->surface
.level
[i
].mode
);
610 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
611 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
612 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
613 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
614 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
615 i
, rtex
->surface
.stencil_level
[i
].offset
,
616 rtex
->surface
.stencil_level
[i
].slice_size
,
617 u_minify(rtex
->resource
.b
.b
.width0
, i
),
618 u_minify(rtex
->resource
.b
.b
.height0
, i
),
619 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
620 rtex
->surface
.stencil_level
[i
].nblk_x
,
621 rtex
->surface
.stencil_level
[i
].nblk_y
,
622 rtex
->surface
.stencil_level
[i
].nblk_z
,
623 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
624 rtex
->surface
.stencil_level
[i
].mode
);
631 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
632 const struct pipe_resource
*templ
)
634 const struct util_format_description
*desc
= util_format_description(templ
->format
);
636 /* MSAA resources must be 2D tiled. */
637 if (templ
->nr_samples
> 1)
638 return RADEON_SURF_MODE_2D
;
640 /* Transfer resources should be linear. */
641 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
642 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
644 /* Handle common candidates for the linear mode.
645 * Compressed textures must always be tiled. */
646 if (!(templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
) &&
647 !util_format_is_compressed(templ
->format
)) {
648 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600-Cayman. */
649 if (rscreen
->chip_class
<= CAYMAN
&&
650 desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
651 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
653 /* Cursors are linear on SI.
654 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
655 if (rscreen
->chip_class
>= SI
&&
656 (templ
->bind
& PIPE_BIND_CURSOR
))
657 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
659 if (templ
->bind
& PIPE_BIND_LINEAR
)
660 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
662 /* Textures with a very small height are recommended to be linear. */
663 if (templ
->target
== PIPE_TEXTURE_1D
||
664 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
666 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
668 /* Textures likely to be mapped often. */
669 if (templ
->usage
== PIPE_USAGE_STAGING
||
670 templ
->usage
== PIPE_USAGE_STREAM
)
671 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
674 /* Make small textures 1D tiled. */
675 if (templ
->width0
<= 16 || templ
->height0
<= 16)
676 return RADEON_SURF_MODE_1D
;
678 /* XXX 2D tiling is currently unimplemented on CIK */
679 if (rscreen
->chip_class
>= CIK
)
680 return RADEON_SURF_MODE_1D
;
682 /* The allocator will switch to 1D if needed. */
683 return RADEON_SURF_MODE_2D
;
686 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
687 const struct pipe_resource
*templ
)
689 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
690 struct radeon_surface surface
= {0};
693 r
= r600_init_surface(rscreen
, &surface
, templ
,
694 r600_choose_tiling(rscreen
, templ
),
695 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
699 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
703 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
707 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
708 const struct pipe_resource
*templ
,
709 struct winsys_handle
*whandle
)
711 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
712 struct pb_buffer
*buf
= NULL
;
715 enum radeon_bo_layout micro
, macro
;
716 struct radeon_surface surface
;
719 /* Support only 2D textures without mipmaps */
720 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
721 templ
->depth0
!= 1 || templ
->last_level
!= 0)
724 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
728 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
729 &surface
.bankw
, &surface
.bankh
,
731 &surface
.stencil_tile_split
,
734 if (macro
== RADEON_LAYOUT_TILED
)
735 array_mode
= RADEON_SURF_MODE_2D
;
736 else if (micro
== RADEON_LAYOUT_TILED
)
737 array_mode
= RADEON_SURF_MODE_1D
;
739 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
741 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
746 /* always set the scanout flags on SI */
747 if (rscreen
->chip_class
>= SI
)
748 surface
.flags
|= RADEON_SURF_SCANOUT
;
750 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
751 stride
, buf
, &surface
);
754 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
755 struct pipe_resource
*texture
,
756 struct r600_texture
**staging
)
758 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
759 struct pipe_resource resource
;
760 struct r600_texture
**flushed_depth_texture
= staging
?
761 staging
: &rtex
->flushed_depth_texture
;
763 if (!staging
&& rtex
->flushed_depth_texture
)
764 return true; /* it's ready */
766 resource
.target
= texture
->target
;
767 resource
.format
= texture
->format
;
768 resource
.width0
= texture
->width0
;
769 resource
.height0
= texture
->height0
;
770 resource
.depth0
= texture
->depth0
;
771 resource
.array_size
= texture
->array_size
;
772 resource
.last_level
= texture
->last_level
;
773 resource
.nr_samples
= texture
->nr_samples
;
774 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
775 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
776 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
779 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
781 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
782 if (*flushed_depth_texture
== NULL
) {
783 R600_ERR("failed to create temporary texture to hold flushed depth\n");
787 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
788 (*flushed_depth_texture
)->non_disp_tiling
= false;
793 * Initialize the pipe_resource descriptor to be of the same size as the box,
794 * which is supposed to hold a subregion of the texture "orig" at the given
797 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
798 struct pipe_resource
*orig
,
799 const struct pipe_box
*box
,
800 unsigned level
, unsigned flags
)
802 memset(res
, 0, sizeof(*res
));
803 res
->format
= orig
->format
;
804 res
->width0
= box
->width
;
805 res
->height0
= box
->height
;
808 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
811 /* We must set the correct texture target and dimensions for a 3D box. */
812 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0)
813 res
->target
= orig
->target
;
815 res
->target
= PIPE_TEXTURE_2D
;
817 switch (res
->target
) {
818 case PIPE_TEXTURE_1D_ARRAY
:
819 case PIPE_TEXTURE_2D_ARRAY
:
820 case PIPE_TEXTURE_CUBE_ARRAY
:
821 res
->array_size
= box
->depth
;
823 case PIPE_TEXTURE_3D
:
824 res
->depth0
= box
->depth
;
830 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
831 struct pipe_resource
*texture
,
834 const struct pipe_box
*box
,
835 struct pipe_transfer
**ptransfer
)
837 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
838 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
839 struct r600_transfer
*trans
;
840 boolean use_staging_texture
= FALSE
;
841 struct r600_resource
*buf
;
845 /* We cannot map a tiled texture directly because the data is
846 * in a different order, therefore we do detiling using a blit.
848 * Also, use a temporary in GTT memory for read transfers, as
849 * the CPU is much happier reading out of cached system memory
850 * than uncached VRAM.
852 if (rtex
->surface
.level
[level
].mode
>= RADEON_SURF_MODE_1D
)
853 use_staging_texture
= TRUE
;
855 /* Use a staging texture for uploads if the underlying BO is busy. */
856 if (!(usage
& PIPE_TRANSFER_READ
) &&
857 (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
858 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
859 use_staging_texture
= TRUE
;
862 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
863 use_staging_texture
= FALSE
;
866 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
870 trans
= CALLOC_STRUCT(r600_transfer
);
873 trans
->transfer
.resource
= texture
;
874 trans
->transfer
.level
= level
;
875 trans
->transfer
.usage
= usage
;
876 trans
->transfer
.box
= *box
;
878 if (rtex
->is_depth
) {
879 struct r600_texture
*staging_depth
;
881 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
882 /* MSAA depth buffers need to be converted to single sample buffers.
884 * Mapping MSAA depth buffers can occur if ReadPixels is called
885 * with a multisample GLX visual.
887 * First downsample the depth buffer to a temporary texture,
888 * then decompress the temporary one to staging.
890 * Only the region being mapped is transfered.
892 struct pipe_resource resource
;
894 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
896 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
897 R600_ERR("failed to create temporary texture to hold untiled copy\n");
902 if (usage
& PIPE_TRANSFER_READ
) {
903 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
905 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
906 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
907 0, 0, 0, box
->depth
, 0, 0);
908 pipe_resource_reference((struct pipe_resource
**)&temp
, NULL
);
912 /* XXX: only readback the rectangle which is being mapped? */
913 /* XXX: when discard is true, no need to read back from depth texture */
914 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
915 R600_ERR("failed to create temporary texture to hold untiled copy\n");
920 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
922 box
->z
, box
->z
+ box
->depth
- 1,
925 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
928 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
929 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
930 trans
->staging
= (struct r600_resource
*)staging_depth
;
931 } else if (use_staging_texture
) {
932 struct pipe_resource resource
;
933 struct r600_texture
*staging
;
935 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
936 R600_RESOURCE_FLAG_TRANSFER
);
938 /* Create the temporary texture. */
939 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
940 if (staging
== NULL
) {
941 R600_ERR("failed to create temporary texture to hold untiled copy\n");
945 trans
->staging
= &staging
->resource
;
946 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
947 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
948 if (usage
& PIPE_TRANSFER_READ
) {
949 r600_copy_to_staging_texture(ctx
, trans
);
952 /* the resource is mapped directly */
953 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
954 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
955 offset
= r600_texture_get_offset(rtex
, level
, box
);
958 if (trans
->staging
) {
959 buf
= trans
->staging
;
961 buf
= &rtex
->resource
;
964 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
965 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
970 *ptransfer
= &trans
->transfer
;
974 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
975 struct pipe_transfer
* transfer
)
977 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
978 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
979 struct radeon_winsys_cs_handle
*buf
;
980 struct pipe_resource
*texture
= transfer
->resource
;
981 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
983 if (rtransfer
->staging
) {
984 buf
= rtransfer
->staging
->cs_buf
;
986 buf
= r600_resource(transfer
->resource
)->cs_buf
;
988 rctx
->ws
->buffer_unmap(buf
);
990 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
991 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
992 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
993 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
994 &rtransfer
->staging
->b
.b
, transfer
->level
,
997 r600_copy_from_staging_texture(ctx
, rtransfer
);
1001 if (rtransfer
->staging
)
1002 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
1007 static const struct u_resource_vtbl r600_texture_vtbl
=
1009 r600_texture_get_handle
, /* get_handle */
1010 r600_texture_destroy
, /* resource_destroy */
1011 r600_texture_transfer_map
, /* transfer_map */
1012 NULL
, /* transfer_flush_region */
1013 r600_texture_transfer_unmap
, /* transfer_unmap */
1014 NULL
/* transfer_inline_write */