2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& src_level
< rsrc
->surface
.num_dcc_levels
) ||
76 (rdst
->dcc_offset
&& dst_level
< rdst
->surface
.num_dcc_levels
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 return rtex
->surface
.level
[level
].offset
+
184 box
->z
* rtex
->surface
.level
[level
].slice_size
+
185 (box
->y
/ rtex
->surface
.blk_h
*
186 rtex
->surface
.level
[level
].nblk_x
+
187 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
190 static int r600_init_surface(struct r600_common_screen
*rscreen
,
191 struct radeon_surf
*surface
,
192 const struct pipe_resource
*ptex
,
193 enum radeon_surf_mode array_mode
,
194 unsigned pitch_in_bytes_override
,
198 bool is_flushed_depth
,
199 bool tc_compatible_htile
)
201 const struct util_format_description
*desc
=
202 util_format_description(ptex
->format
);
203 bool is_depth
, is_stencil
;
205 unsigned i
, bpe
, flags
= 0;
207 is_depth
= util_format_has_depth(desc
);
208 is_stencil
= util_format_has_stencil(desc
);
210 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
211 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
212 bpe
= 4; /* stencil is allocated separately on evergreen */
214 bpe
= util_format_get_blocksize(ptex
->format
);
215 /* align byte per element on dword */
221 if (!is_flushed_depth
&& is_depth
) {
222 flags
|= RADEON_SURF_ZBUFFER
;
224 if (tc_compatible_htile
&&
225 array_mode
== RADEON_SURF_MODE_2D
) {
226 /* TC-compatible HTILE only supports Z32_FLOAT.
227 * Promote Z16 to Z32. DB->CB copies will convert
228 * the format for transfers.
231 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
235 flags
|= RADEON_SURF_SBUFFER
;
238 if (rscreen
->chip_class
>= VI
&&
239 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
240 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
241 flags
|= RADEON_SURF_DISABLE_DCC
;
243 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
244 /* This should catch bugs in gallium users setting incorrect flags. */
245 assert(ptex
->nr_samples
<= 1 &&
246 ptex
->array_size
== 1 &&
248 ptex
->last_level
== 0 &&
249 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
251 flags
|= RADEON_SURF_SCANOUT
;
255 flags
|= RADEON_SURF_IMPORTED
;
256 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
257 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
259 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
260 array_mode
, surface
);
265 if (pitch_in_bytes_override
&&
266 pitch_in_bytes_override
!= surface
->level
[0].nblk_x
* bpe
) {
267 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
270 surface
->level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
271 surface
->level
[0].slice_size
= pitch_in_bytes_override
* surface
->level
[0].nblk_y
;
275 for (i
= 0; i
< ARRAY_SIZE(surface
->level
); ++i
)
276 surface
->level
[i
].offset
+= offset
;
281 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
282 struct radeon_bo_metadata
*metadata
)
284 struct radeon_surf
*surface
= &rtex
->surface
;
286 memset(metadata
, 0, sizeof(*metadata
));
287 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
288 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
289 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
290 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
291 metadata
->pipe_config
= surface
->pipe_config
;
292 metadata
->bankw
= surface
->bankw
;
293 metadata
->bankh
= surface
->bankh
;
294 metadata
->tile_split
= surface
->tile_split
;
295 metadata
->mtilea
= surface
->mtilea
;
296 metadata
->num_banks
= surface
->num_banks
;
297 metadata
->stride
= surface
->level
[0].nblk_x
* surface
->bpe
;
298 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
301 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
302 struct r600_texture
*rtex
)
304 struct r600_common_screen
*rscreen
= rctx
->screen
;
305 struct pipe_context
*ctx
= &rctx
->b
;
307 if (ctx
== rscreen
->aux_context
)
308 pipe_mutex_lock(rscreen
->aux_context_lock
);
310 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
311 ctx
->flush(ctx
, NULL
, 0);
313 if (ctx
== rscreen
->aux_context
)
314 pipe_mutex_unlock(rscreen
->aux_context_lock
);
317 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
318 struct r600_texture
*rtex
)
320 if (!rtex
->cmask
.size
)
323 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
326 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
327 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
328 rtex
->dirty_level_mask
= 0;
330 if (rscreen
->chip_class
>= SI
)
331 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
333 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
335 if (rtex
->cmask_buffer
!= &rtex
->resource
)
336 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
338 /* Notify all contexts about the change. */
339 p_atomic_inc(&rscreen
->dirty_tex_counter
);
340 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
343 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
345 /* We can't disable DCC if it can be written by another process. */
346 return rtex
->dcc_offset
&&
347 (!rtex
->resource
.is_shared
||
348 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
351 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
352 struct r600_texture
*rtex
)
354 if (!r600_can_disable_dcc(rtex
))
357 assert(rtex
->dcc_separate_buffer
== NULL
);
360 rtex
->dcc_offset
= 0;
362 /* Notify all contexts about the change. */
363 p_atomic_inc(&rscreen
->dirty_tex_counter
);
368 * Disable DCC for the texture. (first decompress, then discard metadata).
370 * There is unresolved multi-context synchronization issue between
371 * screen::aux_context and the current context. If applications do this with
372 * multiple contexts, it's already undefined behavior for them and we don't
373 * have to worry about that. The scenario is:
375 * If context 1 disables DCC and context 2 has queued commands that write
376 * to the texture via CB with DCC enabled, and the order of operations is
378 * context 2 queues draw calls rendering to the texture, but doesn't flush
379 * context 1 disables DCC and flushes
380 * context 1 & 2 reset descriptors and FB state
381 * context 2 flushes (new compressed tiles written by the draw calls)
382 * context 1 & 2 read garbage, because DCC is disabled, yet there are
385 * \param rctx the current context if you have one, or rscreen->aux_context
388 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
389 struct r600_texture
*rtex
)
391 struct r600_common_screen
*rscreen
= rctx
->screen
;
393 if (!r600_can_disable_dcc(rtex
))
396 if (&rctx
->b
== rscreen
->aux_context
)
397 pipe_mutex_lock(rscreen
->aux_context_lock
);
399 /* Decompress DCC. */
400 rctx
->decompress_dcc(&rctx
->b
, rtex
);
401 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
403 if (&rctx
->b
== rscreen
->aux_context
)
404 pipe_mutex_unlock(rscreen
->aux_context_lock
);
406 return r600_texture_discard_dcc(rscreen
, rtex
);
409 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
410 struct r600_texture
*rtex
,
411 bool invalidate_storage
)
413 struct pipe_screen
*screen
= rctx
->b
.screen
;
414 struct r600_texture
*new_tex
;
415 struct pipe_resource templ
= rtex
->resource
.b
.b
;
418 templ
.bind
|= PIPE_BIND_LINEAR
;
420 /* r600g doesn't react to dirty_tex_descriptor_counter */
421 if (rctx
->chip_class
< SI
)
424 if (rtex
->resource
.is_shared
||
425 rtex
->surface
.is_linear
)
428 /* This fails with MSAA, depth, and compressed textures. */
429 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
430 RADEON_SURF_MODE_LINEAR_ALIGNED
)
433 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
437 /* Copy the pixels to the new texture. */
438 if (!invalidate_storage
) {
439 for (i
= 0; i
<= templ
.last_level
; i
++) {
443 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
444 util_max_layer(&templ
, i
) + 1, &box
);
446 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
447 &rtex
->resource
.b
.b
, i
, &box
);
451 r600_texture_discard_cmask(rctx
->screen
, rtex
);
452 r600_texture_discard_dcc(rctx
->screen
, rtex
);
454 /* Replace the structure fields of rtex. */
455 rtex
->resource
.b
.b
.bind
= templ
.bind
;
456 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
457 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
458 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
459 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
460 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
461 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
462 rtex
->resource
.domains
= new_tex
->resource
.domains
;
463 rtex
->resource
.flags
= new_tex
->resource
.flags
;
464 rtex
->size
= new_tex
->size
;
465 rtex
->surface
= new_tex
->surface
;
466 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
467 rtex
->cb_color_info
= new_tex
->cb_color_info
;
468 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
470 assert(!rtex
->htile_buffer
);
471 assert(!rtex
->cmask
.size
);
472 assert(!rtex
->fmask
.size
);
473 assert(!rtex
->dcc_offset
);
474 assert(!rtex
->is_depth
);
476 r600_texture_reference(&new_tex
, NULL
);
478 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
481 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
482 struct pipe_context
*ctx
,
483 struct pipe_resource
*resource
,
484 struct winsys_handle
*whandle
,
487 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
488 struct r600_common_context
*rctx
= (struct r600_common_context
*)
489 (ctx
? ctx
: rscreen
->aux_context
);
490 struct r600_resource
*res
= (struct r600_resource
*)resource
;
491 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
492 struct radeon_bo_metadata metadata
;
493 bool update_metadata
= false;
495 /* This is not supported now, but it might be required for OpenCL
496 * interop in the future.
498 if (resource
->target
!= PIPE_BUFFER
&&
499 (resource
->nr_samples
> 1 || rtex
->is_depth
))
502 if (resource
->target
!= PIPE_BUFFER
) {
503 /* Since shader image stores don't support DCC on VI,
504 * disable it for external clients that want write
507 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
508 if (r600_texture_disable_dcc(rctx
, rtex
))
509 update_metadata
= true;
512 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
513 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
514 /* Eliminate fast clear (both CMASK and DCC) */
515 r600_eliminate_fast_color_clear(rctx
, rtex
);
517 /* Disable CMASK if flush_resource isn't going
520 if (rtex
->cmask
.size
)
521 r600_texture_discard_cmask(rscreen
, rtex
);
525 if (!res
->is_shared
|| update_metadata
) {
526 r600_texture_init_metadata(rtex
, &metadata
);
527 if (rscreen
->query_opaque_metadata
)
528 rscreen
->query_opaque_metadata(rscreen
, rtex
,
531 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
535 if (res
->is_shared
) {
536 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
539 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
540 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
541 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
543 res
->is_shared
= true;
544 res
->external_usage
= usage
;
547 return rscreen
->ws
->buffer_get_handle(res
->buf
,
548 rtex
->surface
.level
[0].nblk_x
*
550 rtex
->surface
.level
[0].offset
,
551 rtex
->surface
.level
[0].slice_size
,
555 static void r600_texture_destroy(struct pipe_screen
*screen
,
556 struct pipe_resource
*ptex
)
558 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
559 struct r600_resource
*resource
= &rtex
->resource
;
561 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
563 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
564 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
565 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
567 pb_reference(&resource
->buf
, NULL
);
568 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
569 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
573 static const struct u_resource_vtbl r600_texture_vtbl
;
575 /* The number of samples can be specified independently of the texture. */
576 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
577 struct r600_texture
*rtex
,
579 struct r600_fmask_info
*out
)
581 /* FMASK is allocated like an ordinary texture. */
582 struct pipe_resource templ
= rtex
->resource
.b
.b
;
583 struct radeon_surf fmask
= {};
586 memset(out
, 0, sizeof(*out
));
588 templ
.nr_samples
= 1;
589 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
591 if (rscreen
->chip_class
<= CAYMAN
) {
592 /* Use the same parameters and tile mode. */
593 fmask
.bankw
= rtex
->surface
.bankw
;
594 fmask
.bankh
= rtex
->surface
.bankh
;
595 fmask
.mtilea
= rtex
->surface
.mtilea
;
596 fmask
.tile_split
= rtex
->surface
.tile_split
;
602 switch (nr_samples
) {
611 R600_ERR("Invalid sample count for FMASK allocation.\n");
615 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
616 * This can be fixed by writing a separate FMASK allocator specifically
617 * for R600-R700 asics. */
618 if (rscreen
->chip_class
<= R700
) {
622 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
623 RADEON_SURF_MODE_2D
, &fmask
)) {
624 R600_ERR("Got error in surface_init while allocating FMASK.\n");
628 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
630 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
631 if (out
->slice_tile_max
)
632 out
->slice_tile_max
-= 1;
634 out
->tile_mode_index
= fmask
.tiling_index
[0];
635 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
636 out
->bank_height
= fmask
.bankh
;
637 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
638 out
->size
= fmask
.surf_size
;
641 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
642 struct r600_texture
*rtex
)
644 r600_texture_get_fmask_info(rscreen
, rtex
,
645 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
647 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
648 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
651 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
652 struct r600_texture
*rtex
,
653 struct r600_cmask_info
*out
)
655 unsigned cmask_tile_width
= 8;
656 unsigned cmask_tile_height
= 8;
657 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
658 unsigned element_bits
= 4;
659 unsigned cmask_cache_bits
= 1024;
660 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
661 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
663 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
664 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
665 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
666 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
667 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
669 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
670 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
672 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
673 unsigned slice_bytes
=
674 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
676 assert(macro_tile_width
% 128 == 0);
677 assert(macro_tile_height
% 128 == 0);
679 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
680 out
->alignment
= MAX2(256, base_align
);
681 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
682 align(slice_bytes
, base_align
);
685 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
686 struct r600_texture
*rtex
,
687 struct r600_cmask_info
*out
)
689 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
690 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
691 unsigned cl_width
, cl_height
;
706 case 16: /* Hawaii */
715 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
717 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
718 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
719 unsigned slice_elements
= (width
* height
) / (8*8);
721 /* Each element of CMASK is a nibble. */
722 unsigned slice_bytes
= slice_elements
/ 2;
724 out
->slice_tile_max
= (width
* height
) / (128*128);
725 if (out
->slice_tile_max
)
726 out
->slice_tile_max
-= 1;
728 out
->alignment
= MAX2(256, base_align
);
729 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
730 align(slice_bytes
, base_align
);
733 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
734 struct r600_texture
*rtex
)
736 if (rscreen
->chip_class
>= SI
) {
737 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
739 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
742 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
743 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
745 if (rscreen
->chip_class
>= SI
)
746 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
748 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
751 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
752 struct r600_texture
*rtex
)
754 if (rtex
->cmask_buffer
)
757 assert(rtex
->cmask
.size
== 0);
759 if (rscreen
->chip_class
>= SI
) {
760 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
762 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
765 rtex
->cmask_buffer
= (struct r600_resource
*)
766 r600_aligned_buffer_create(&rscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
768 rtex
->cmask
.alignment
);
769 if (rtex
->cmask_buffer
== NULL
) {
770 rtex
->cmask
.size
= 0;
774 /* update colorbuffer state bits */
775 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
777 if (rscreen
->chip_class
>= SI
)
778 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
780 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
782 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
785 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
786 struct r600_texture
*rtex
)
788 unsigned cl_width
, cl_height
, width
, height
;
789 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
790 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
792 rtex
->surface
.htile_size
= 0;
794 if (rscreen
->chip_class
<= EVERGREEN
&&
795 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
798 /* HW bug on R6xx. */
799 if (rscreen
->chip_class
== R600
&&
800 (rtex
->resource
.b
.b
.width0
> 7680 ||
801 rtex
->resource
.b
.b
.height0
> 7680))
804 /* HTILE is broken with 1D tiling on old kernels and CIK. */
805 if (rscreen
->chip_class
>= CIK
&&
806 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
807 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
810 /* Overalign HTILE on P2 configs to work around GPU hangs in
811 * piglit/depthstencil-render-miplevels 585.
813 * This has been confirmed to help Kabini & Stoney, where the hangs
814 * are always reproducible. I think I have seen the test hang
815 * on Carrizo too, though it was very rare there.
817 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
846 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
847 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
849 slice_elements
= (width
* height
) / (8 * 8);
850 slice_bytes
= slice_elements
* 4;
852 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
853 base_align
= num_pipes
* pipe_interleave_bytes
;
855 rtex
->surface
.htile_alignment
= base_align
;
856 rtex
->surface
.htile_size
=
857 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
858 align(slice_bytes
, base_align
);
861 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
862 struct r600_texture
*rtex
)
864 uint32_t clear_value
;
866 if (rtex
->tc_compatible_htile
) {
867 clear_value
= 0x0000030F;
869 r600_texture_get_htile_size(rscreen
, rtex
);
873 if (!rtex
->surface
.htile_size
)
876 rtex
->htile_buffer
= (struct r600_resource
*)
877 r600_aligned_buffer_create(&rscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
878 rtex
->surface
.htile_size
,
879 rtex
->surface
.htile_alignment
);
880 if (rtex
->htile_buffer
== NULL
) {
881 /* this is not a fatal error as we can still keep rendering
882 * without htile buffer */
883 R600_ERR("Failed to create buffer object for htile buffer.\n");
885 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
886 0, rtex
->surface
.htile_size
,
891 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
895 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
896 "blk_h=%u, array_size=%u, last_level=%u, "
897 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
898 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
899 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
901 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
902 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
903 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
905 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
906 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
907 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.bankw
,
908 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
909 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
910 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
912 if (rtex
->fmask
.size
)
913 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
914 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
915 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
916 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
917 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
919 if (rtex
->cmask
.size
)
920 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
921 "slice_tile_max=%u\n",
922 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
923 rtex
->cmask
.slice_tile_max
);
925 if (rtex
->htile_buffer
)
926 fprintf(f
, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
927 rtex
->htile_buffer
->b
.b
.width0
,
928 rtex
->htile_buffer
->buf
->alignment
,
929 rtex
->tc_compatible_htile
);
931 if (rtex
->dcc_offset
) {
932 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
933 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
934 rtex
->surface
.dcc_alignment
);
935 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
936 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
937 "fast_clear_size=%"PRIu64
"\n",
938 i
, i
< rtex
->surface
.num_dcc_levels
,
939 rtex
->surface
.level
[i
].dcc_offset
,
940 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
943 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
944 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
945 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
946 "mode=%u, tiling_index = %u\n",
947 i
, rtex
->surface
.level
[i
].offset
,
948 rtex
->surface
.level
[i
].slice_size
,
949 u_minify(rtex
->resource
.b
.b
.width0
, i
),
950 u_minify(rtex
->resource
.b
.b
.height0
, i
),
951 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
952 rtex
->surface
.level
[i
].nblk_x
,
953 rtex
->surface
.level
[i
].nblk_y
,
954 rtex
->surface
.level
[i
].mode
,
955 rtex
->surface
.tiling_index
[i
]);
957 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
958 fprintf(f
, " StencilLayout: tilesplit=%u\n",
959 rtex
->surface
.stencil_tile_split
);
960 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
961 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
962 "slice_size=%"PRIu64
", npix_x=%u, "
963 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
964 "mode=%u, tiling_index = %u\n",
965 i
, rtex
->surface
.stencil_level
[i
].offset
,
966 rtex
->surface
.stencil_level
[i
].slice_size
,
967 u_minify(rtex
->resource
.b
.b
.width0
, i
),
968 u_minify(rtex
->resource
.b
.b
.height0
, i
),
969 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
970 rtex
->surface
.stencil_level
[i
].nblk_x
,
971 rtex
->surface
.stencil_level
[i
].nblk_y
,
972 rtex
->surface
.stencil_level
[i
].mode
,
973 rtex
->surface
.stencil_tiling_index
[i
]);
978 /* Common processing for r600_texture_create and r600_texture_from_handle */
979 static struct r600_texture
*
980 r600_texture_create_object(struct pipe_screen
*screen
,
981 const struct pipe_resource
*base
,
982 struct pb_buffer
*buf
,
983 struct radeon_surf
*surface
)
985 struct r600_texture
*rtex
;
986 struct r600_resource
*resource
;
987 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
989 rtex
= CALLOC_STRUCT(r600_texture
);
993 resource
= &rtex
->resource
;
994 resource
->b
.b
= *base
;
995 resource
->b
.b
.next
= NULL
;
996 resource
->b
.vtbl
= &r600_texture_vtbl
;
997 pipe_reference_init(&resource
->b
.b
.reference
, 1);
998 resource
->b
.b
.screen
= screen
;
1000 /* don't include stencil-only formats which we don't support for rendering */
1001 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1003 rtex
->surface
= *surface
;
1004 rtex
->size
= rtex
->surface
.surf_size
;
1006 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1007 (rtex
->surface
.flags
&
1008 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1010 /* TC-compatible HTILE only supports Z32_FLOAT. */
1011 if (rtex
->tc_compatible_htile
)
1012 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1014 rtex
->db_render_format
= base
->format
;
1016 /* Tiled depth textures utilize the non-displayable tile order.
1017 * This must be done after r600_setup_surface.
1018 * Applies to R600-Cayman. */
1019 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1020 /* Applies to GCN. */
1021 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1023 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1024 * between frames, so the only thing that can enable separate DCC
1025 * with DRI2 is multiple slow clears within a frame.
1027 rtex
->ps_draw_ratio
= 0;
1029 if (rtex
->is_depth
) {
1030 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1031 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1032 rscreen
->chip_class
>= EVERGREEN
) {
1033 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1034 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1036 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1037 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1038 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1039 rtex
->can_sample_z
= true;
1042 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1043 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1044 rtex
->db_compatible
= true;
1046 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1047 r600_texture_allocate_htile(rscreen
, rtex
);
1050 if (base
->nr_samples
> 1) {
1052 r600_texture_allocate_fmask(rscreen
, rtex
);
1053 r600_texture_allocate_cmask(rscreen
, rtex
);
1054 rtex
->cmask_buffer
= &rtex
->resource
;
1056 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1062 /* Shared textures must always set up DCC here.
1063 * If it's not present, it will be disabled by
1064 * apply_opaque_metadata later.
1066 if (rtex
->surface
.dcc_size
&&
1067 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1068 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1069 /* Reserve space for the DCC buffer. */
1070 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1071 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1075 /* Now create the backing buffer. */
1077 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1078 rtex
->surface
.surf_alignment
);
1080 resource
->flags
|= RADEON_FLAG_HANDLE
;
1082 if (!r600_alloc_resource(rscreen
, resource
)) {
1087 resource
->buf
= buf
;
1088 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1089 resource
->bo_size
= buf
->size
;
1090 resource
->bo_alignment
= buf
->alignment
;
1091 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1092 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1093 resource
->vram_usage
= buf
->size
;
1094 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1095 resource
->gart_usage
= buf
->size
;
1098 if (rtex
->cmask
.size
) {
1099 /* Initialize the cmask to 0xCC (= compressed state). */
1100 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1101 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1105 /* Initialize DCC only if the texture is not being imported. */
1106 if (!buf
&& rtex
->dcc_offset
) {
1107 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1109 rtex
->surface
.dcc_size
,
1113 /* Initialize the CMASK base register value. */
1114 rtex
->cmask
.base_address_reg
=
1115 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1117 if (rscreen
->debug_flags
& DBG_VM
) {
1118 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1119 rtex
->resource
.gpu_address
,
1120 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1121 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1122 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1125 if (rscreen
->debug_flags
& DBG_TEX
) {
1127 r600_print_texture_info(rtex
, stdout
);
1134 static enum radeon_surf_mode
1135 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1136 const struct pipe_resource
*templ
)
1138 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1139 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1141 /* MSAA resources must be 2D tiled. */
1142 if (templ
->nr_samples
> 1)
1143 return RADEON_SURF_MODE_2D
;
1145 /* Transfer resources should be linear. */
1146 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1147 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1149 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1150 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1151 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1152 (templ
->target
== PIPE_TEXTURE_2D
||
1153 templ
->target
== PIPE_TEXTURE_3D
))
1154 force_tiling
= true;
1156 /* Handle common candidates for the linear mode.
1157 * Compressed textures and DB surfaces must always be tiled.
1159 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1160 (!util_format_is_depth_or_stencil(templ
->format
) ||
1161 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1162 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1163 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1165 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1166 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1167 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1169 /* Cursors are linear on SI.
1170 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1171 if (rscreen
->chip_class
>= SI
&&
1172 (templ
->bind
& PIPE_BIND_CURSOR
))
1173 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1175 if (templ
->bind
& PIPE_BIND_LINEAR
)
1176 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1178 /* Textures with a very small height are recommended to be linear. */
1179 if (templ
->target
== PIPE_TEXTURE_1D
||
1180 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1181 /* Only very thin and long 2D textures should benefit from
1182 * linear_aligned. */
1183 (templ
->width0
> 8 && templ
->height0
<= 2))
1184 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1186 /* Textures likely to be mapped often. */
1187 if (templ
->usage
== PIPE_USAGE_STAGING
||
1188 templ
->usage
== PIPE_USAGE_STREAM
)
1189 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1192 /* Make small textures 1D tiled. */
1193 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1194 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1195 return RADEON_SURF_MODE_1D
;
1197 /* The allocator will switch to 1D if needed. */
1198 return RADEON_SURF_MODE_2D
;
1201 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1202 const struct pipe_resource
*templ
)
1204 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1205 struct radeon_surf surface
= {0};
1206 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1207 bool tc_compatible_htile
=
1208 rscreen
->chip_class
>= VI
&&
1209 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1210 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1211 !is_flushed_depth
&&
1212 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1213 util_format_is_depth_or_stencil(templ
->format
);
1217 r
= r600_init_surface(rscreen
, &surface
, templ
,
1218 r600_choose_tiling(rscreen
, templ
), 0, 0,
1219 false, false, is_flushed_depth
,
1220 tc_compatible_htile
);
1225 return (struct pipe_resource
*)
1226 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1229 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1230 const struct pipe_resource
*templ
,
1231 struct winsys_handle
*whandle
,
1234 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1235 struct pb_buffer
*buf
= NULL
;
1236 unsigned stride
= 0, offset
= 0;
1237 unsigned array_mode
;
1238 struct radeon_surf surface
;
1240 struct radeon_bo_metadata metadata
= {};
1241 struct r600_texture
*rtex
;
1243 /* Support only 2D textures without mipmaps */
1244 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1245 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1248 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1252 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1254 surface
.pipe_config
= metadata
.pipe_config
;
1255 surface
.bankw
= metadata
.bankw
;
1256 surface
.bankh
= metadata
.bankh
;
1257 surface
.tile_split
= metadata
.tile_split
;
1258 surface
.mtilea
= metadata
.mtilea
;
1259 surface
.num_banks
= metadata
.num_banks
;
1261 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1262 array_mode
= RADEON_SURF_MODE_2D
;
1263 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1264 array_mode
= RADEON_SURF_MODE_1D
;
1266 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1268 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1269 offset
, true, metadata
.scanout
, false, false);
1274 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1278 rtex
->resource
.is_shared
= true;
1279 rtex
->resource
.external_usage
= usage
;
1281 if (rscreen
->apply_opaque_metadata
)
1282 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1284 return &rtex
->resource
.b
.b
;
1287 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1288 struct pipe_resource
*texture
,
1289 struct r600_texture
**staging
)
1291 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1292 struct pipe_resource resource
;
1293 struct r600_texture
**flushed_depth_texture
= staging
?
1294 staging
: &rtex
->flushed_depth_texture
;
1295 enum pipe_format pipe_format
= texture
->format
;
1298 if (rtex
->flushed_depth_texture
)
1299 return true; /* it's ready */
1301 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1302 switch (pipe_format
) {
1303 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1304 /* Save memory by not allocating the S plane. */
1305 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1307 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1308 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1309 /* Save memory bandwidth by not copying the
1310 * stencil part during flush.
1312 * This potentially increases memory bandwidth
1313 * if an application uses both Z and S texturing
1314 * simultaneously (a flushed Z24S8 texture
1315 * would be stored compactly), but how often
1316 * does that really happen?
1318 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1322 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1323 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1325 /* DB->CB copies to an 8bpp surface don't work. */
1326 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1330 memset(&resource
, 0, sizeof(resource
));
1331 resource
.target
= texture
->target
;
1332 resource
.format
= pipe_format
;
1333 resource
.width0
= texture
->width0
;
1334 resource
.height0
= texture
->height0
;
1335 resource
.depth0
= texture
->depth0
;
1336 resource
.array_size
= texture
->array_size
;
1337 resource
.last_level
= texture
->last_level
;
1338 resource
.nr_samples
= texture
->nr_samples
;
1339 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1340 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1341 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1344 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1346 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1347 if (*flushed_depth_texture
== NULL
) {
1348 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1352 (*flushed_depth_texture
)->non_disp_tiling
= false;
1357 * Initialize the pipe_resource descriptor to be of the same size as the box,
1358 * which is supposed to hold a subregion of the texture "orig" at the given
1361 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1362 struct pipe_resource
*orig
,
1363 const struct pipe_box
*box
,
1364 unsigned level
, unsigned flags
)
1366 memset(res
, 0, sizeof(*res
));
1367 res
->format
= orig
->format
;
1368 res
->width0
= box
->width
;
1369 res
->height0
= box
->height
;
1371 res
->array_size
= 1;
1372 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1375 /* We must set the correct texture target and dimensions for a 3D box. */
1376 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1377 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1378 res
->array_size
= box
->depth
;
1380 res
->target
= PIPE_TEXTURE_2D
;
1384 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1385 struct r600_texture
*rtex
,
1386 unsigned transfer_usage
,
1387 const struct pipe_box
*box
)
1389 /* r600g doesn't react to dirty_tex_descriptor_counter */
1390 return rscreen
->chip_class
>= SI
&&
1391 !rtex
->resource
.is_shared
&&
1392 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1393 rtex
->resource
.b
.b
.last_level
== 0 &&
1394 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1395 box
->x
, box
->y
, box
->z
,
1396 box
->width
, box
->height
,
1400 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1401 struct r600_texture
*rtex
)
1403 struct r600_common_screen
*rscreen
= rctx
->screen
;
1405 /* There is no point in discarding depth and tiled buffers. */
1406 assert(!rtex
->is_depth
);
1407 assert(rtex
->surface
.is_linear
);
1409 /* Reallocate the buffer in the same pipe_resource. */
1410 r600_alloc_resource(rscreen
, &rtex
->resource
);
1412 /* Initialize the CMASK base address (needed even without CMASK). */
1413 rtex
->cmask
.base_address_reg
=
1414 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1416 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1418 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1421 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1422 struct pipe_resource
*texture
,
1425 const struct pipe_box
*box
,
1426 struct pipe_transfer
**ptransfer
)
1428 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1429 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1430 struct r600_transfer
*trans
;
1431 struct r600_resource
*buf
;
1432 unsigned offset
= 0;
1434 bool use_staging_texture
= false;
1436 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1438 /* Depth textures use staging unconditionally. */
1439 if (!rtex
->is_depth
) {
1440 /* Degrade the tile mode if we get too many transfers on APUs.
1441 * On dGPUs, the staging texture is always faster.
1442 * Only count uploads that are at least 4x4 pixels large.
1444 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1446 box
->width
>= 4 && box
->height
>= 4 &&
1447 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1448 bool can_invalidate
=
1449 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1452 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1456 /* Tiled textures need to be converted into a linear texture for CPU
1457 * access. The staging texture is always linear and is placed in GART.
1459 * Reading from VRAM is slow, always use the staging texture in
1462 * Use the staging texture for uploads if the underlying BO
1465 if (!rtex
->surface
.is_linear
)
1466 use_staging_texture
= true;
1467 else if (usage
& PIPE_TRANSFER_READ
)
1468 use_staging_texture
= (rtex
->resource
.domains
&
1469 RADEON_DOMAIN_VRAM
) != 0;
1470 /* Write & linear only: */
1471 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1472 RADEON_USAGE_READWRITE
) ||
1473 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1474 RADEON_USAGE_READWRITE
)) {
1476 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1478 r600_texture_invalidate_storage(rctx
, rtex
);
1480 use_staging_texture
= true;
1484 trans
= CALLOC_STRUCT(r600_transfer
);
1487 trans
->transfer
.resource
= texture
;
1488 trans
->transfer
.level
= level
;
1489 trans
->transfer
.usage
= usage
;
1490 trans
->transfer
.box
= *box
;
1492 if (rtex
->is_depth
) {
1493 struct r600_texture
*staging_depth
;
1495 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1496 /* MSAA depth buffers need to be converted to single sample buffers.
1498 * Mapping MSAA depth buffers can occur if ReadPixels is called
1499 * with a multisample GLX visual.
1501 * First downsample the depth buffer to a temporary texture,
1502 * then decompress the temporary one to staging.
1504 * Only the region being mapped is transfered.
1506 struct pipe_resource resource
;
1508 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1510 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1511 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1516 if (usage
& PIPE_TRANSFER_READ
) {
1517 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1519 R600_ERR("failed to create a temporary depth texture\n");
1524 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1525 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1526 0, 0, 0, box
->depth
, 0, 0);
1527 pipe_resource_reference(&temp
, NULL
);
1531 /* XXX: only readback the rectangle which is being mapped? */
1532 /* XXX: when discard is true, no need to read back from depth texture */
1533 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1534 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1539 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1541 box
->z
, box
->z
+ box
->depth
- 1,
1544 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1547 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].nblk_x
*
1548 staging_depth
->surface
.bpe
;
1549 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1550 trans
->staging
= (struct r600_resource
*)staging_depth
;
1551 buf
= trans
->staging
;
1552 } else if (use_staging_texture
) {
1553 struct pipe_resource resource
;
1554 struct r600_texture
*staging
;
1556 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1557 R600_RESOURCE_FLAG_TRANSFER
);
1558 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1559 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1561 /* Create the temporary texture. */
1562 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1564 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1568 trans
->staging
= &staging
->resource
;
1569 trans
->transfer
.stride
= staging
->surface
.level
[0].nblk_x
*
1570 staging
->surface
.bpe
;
1571 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1573 if (usage
& PIPE_TRANSFER_READ
)
1574 r600_copy_to_staging_texture(ctx
, trans
);
1576 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1578 buf
= trans
->staging
;
1580 /* the resource is mapped directly */
1581 trans
->transfer
.stride
= rtex
->surface
.level
[level
].nblk_x
*
1583 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1584 offset
= r600_texture_get_offset(rtex
, level
, box
);
1585 buf
= &rtex
->resource
;
1588 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1589 r600_resource_reference(&trans
->staging
, NULL
);
1594 *ptransfer
= &trans
->transfer
;
1595 return map
+ offset
;
1598 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1599 struct pipe_transfer
* transfer
)
1601 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1602 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1603 struct pipe_resource
*texture
= transfer
->resource
;
1604 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1606 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1607 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1608 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1609 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1610 &rtransfer
->staging
->b
.b
, transfer
->level
,
1613 r600_copy_from_staging_texture(ctx
, rtransfer
);
1617 if (rtransfer
->staging
) {
1618 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1619 r600_resource_reference(&rtransfer
->staging
, NULL
);
1622 /* Heuristic for {upload, draw, upload, draw, ..}:
1624 * Flush the gfx IB if we've allocated too much texture storage.
1626 * The idea is that we don't want to build IBs that use too much
1627 * memory and put pressure on the kernel memory manager and we also
1628 * want to make temporary and invalidated buffers go idle ASAP to
1629 * decrease the total memory usage or make them reusable. The memory
1630 * usage will be slightly higher than given here because of the buffer
1631 * cache in the winsys.
1633 * The result is that the kernel memory manager is never a bottleneck.
1635 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1636 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1637 rctx
->num_alloc_tex_transfer_bytes
= 0;
1643 static const struct u_resource_vtbl r600_texture_vtbl
=
1645 NULL
, /* get_handle */
1646 r600_texture_destroy
, /* resource_destroy */
1647 r600_texture_transfer_map
, /* transfer_map */
1648 u_default_transfer_flush_region
, /* transfer_flush_region */
1649 r600_texture_transfer_unmap
, /* transfer_unmap */
1652 /* DCC channel type categories within which formats can be reinterpreted
1653 * while keeping the same DCC encoding. The swizzle must also match. */
1654 enum dcc_channel_type
{
1655 dcc_channel_float32
,
1658 dcc_channel_float16
,
1661 dcc_channel_uint_10_10_10_2
,
1664 dcc_channel_incompatible
,
1667 /* Return the type of DCC encoding. */
1668 static enum dcc_channel_type
1669 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1673 /* Find the first non-void channel. */
1674 for (i
= 0; i
< desc
->nr_channels
; i
++)
1675 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1677 if (i
== desc
->nr_channels
)
1678 return dcc_channel_incompatible
;
1680 switch (desc
->channel
[i
].size
) {
1682 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1683 return dcc_channel_float32
;
1684 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1685 return dcc_channel_uint32
;
1686 return dcc_channel_sint32
;
1688 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1689 return dcc_channel_float16
;
1690 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1691 return dcc_channel_uint16
;
1692 return dcc_channel_sint16
;
1694 return dcc_channel_uint_10_10_10_2
;
1696 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1697 return dcc_channel_uint8
;
1698 return dcc_channel_sint8
;
1700 return dcc_channel_incompatible
;
1704 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1705 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1706 enum pipe_format format2
)
1708 const struct util_format_description
*desc1
, *desc2
;
1709 enum dcc_channel_type type1
, type2
;
1712 if (format1
== format2
)
1715 desc1
= util_format_description(format1
);
1716 desc2
= util_format_description(format2
);
1718 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1721 /* Swizzles must be the same. */
1722 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1723 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1724 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1725 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1728 type1
= vi_get_dcc_channel_type(desc1
);
1729 type2
= vi_get_dcc_channel_type(desc2
);
1731 return type1
!= dcc_channel_incompatible
&&
1732 type2
!= dcc_channel_incompatible
&&
1736 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1737 struct pipe_resource
*tex
,
1739 enum pipe_format view_format
)
1741 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1743 if (rtex
->dcc_offset
&&
1744 level
< rtex
->surface
.num_dcc_levels
&&
1745 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1746 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1747 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1750 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1751 struct pipe_resource
*texture
,
1752 const struct pipe_surface
*templ
,
1753 unsigned width
, unsigned height
)
1755 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1756 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1761 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1762 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1764 pipe_reference_init(&surface
->base
.reference
, 1);
1765 pipe_resource_reference(&surface
->base
.texture
, texture
);
1766 surface
->base
.context
= pipe
;
1767 surface
->base
.format
= templ
->format
;
1768 surface
->base
.width
= width
;
1769 surface
->base
.height
= height
;
1770 surface
->base
.u
= templ
->u
;
1772 if (texture
->target
!= PIPE_BUFFER
)
1773 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1777 return &surface
->base
;
1780 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1781 struct pipe_resource
*tex
,
1782 const struct pipe_surface
*templ
)
1784 unsigned level
= templ
->u
.tex
.level
;
1785 unsigned width
= u_minify(tex
->width0
, level
);
1786 unsigned height
= u_minify(tex
->height0
, level
);
1788 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1789 const struct util_format_description
*tex_desc
1790 = util_format_description(tex
->format
);
1791 const struct util_format_description
*templ_desc
1792 = util_format_description(templ
->format
);
1794 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1796 /* Adjust size of surface if and only if the block width or
1797 * height is changed. */
1798 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1799 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1800 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1801 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1803 width
= nblks_x
* templ_desc
->block
.width
;
1804 height
= nblks_y
* templ_desc
->block
.height
;
1808 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1811 static void r600_surface_destroy(struct pipe_context
*pipe
,
1812 struct pipe_surface
*surface
)
1814 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1815 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1816 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1817 pipe_resource_reference(&surface
->texture
, NULL
);
1821 static void r600_clear_texture(struct pipe_context
*pipe
,
1822 struct pipe_resource
*tex
,
1824 const struct pipe_box
*box
,
1827 struct pipe_screen
*screen
= pipe
->screen
;
1828 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1829 struct pipe_surface tmpl
= {{0}};
1830 struct pipe_surface
*sf
;
1831 const struct util_format_description
*desc
=
1832 util_format_description(tex
->format
);
1834 tmpl
.format
= tex
->format
;
1835 tmpl
.u
.tex
.first_layer
= box
->z
;
1836 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1837 tmpl
.u
.tex
.level
= level
;
1838 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1842 if (rtex
->is_depth
) {
1845 uint8_t stencil
= 0;
1847 /* Depth is always present. */
1848 clear
= PIPE_CLEAR_DEPTH
;
1849 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1851 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1852 clear
|= PIPE_CLEAR_STENCIL
;
1853 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1856 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1858 box
->width
, box
->height
, false);
1860 union pipe_color_union color
;
1862 /* pipe_color_union requires the full vec4 representation. */
1863 if (util_format_is_pure_uint(tex
->format
))
1864 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1865 else if (util_format_is_pure_sint(tex
->format
))
1866 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1868 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1870 if (screen
->is_format_supported(screen
, tex
->format
,
1872 PIPE_BIND_RENDER_TARGET
)) {
1873 pipe
->clear_render_target(pipe
, sf
, &color
,
1875 box
->width
, box
->height
, false);
1877 /* Software fallback - just for R9G9B9E5_FLOAT */
1878 util_clear_render_target(pipe
, sf
, &color
,
1880 box
->width
, box
->height
);
1883 pipe_surface_reference(&sf
, NULL
);
1886 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1888 const struct util_format_description
*desc
= util_format_description(format
);
1890 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1892 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1893 return V_0280A0_SWAP_STD
;
1895 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1898 switch (desc
->nr_channels
) {
1900 if (HAS_SWIZZLE(0,X
))
1901 return V_0280A0_SWAP_STD
; /* X___ */
1902 else if (HAS_SWIZZLE(3,X
))
1903 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1906 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1907 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1908 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1909 return V_0280A0_SWAP_STD
; /* XY__ */
1910 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1911 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1912 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1914 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1915 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1916 return V_0280A0_SWAP_ALT
; /* X__Y */
1917 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1918 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1921 if (HAS_SWIZZLE(0,X
))
1922 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1923 else if (HAS_SWIZZLE(0,Z
))
1924 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1927 /* check the middle channels, the 1st and 4th channel can be NONE */
1928 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1929 return V_0280A0_SWAP_STD
; /* XYZW */
1930 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1931 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1932 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1933 return V_0280A0_SWAP_ALT
; /* ZYXW */
1934 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1937 return V_0280A0_SWAP_ALT_REV
;
1939 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1946 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1948 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1953 if (rctx
->dcc_stats
[slot
].query_active
)
1954 vi_separate_dcc_stop_query(&rctx
->b
,
1955 rctx
->dcc_stats
[slot
].tex
);
1957 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1958 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1959 rctx
->b
.destroy_query(&rctx
->b
,
1960 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1961 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1964 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1968 * Return the per-context slot where DCC statistics queries for the texture live.
1970 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1971 struct r600_texture
*tex
)
1973 int i
, empty_slot
= -1;
1975 /* Remove zombie textures (textures kept alive by this array only). */
1976 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1977 if (rctx
->dcc_stats
[i
].tex
&&
1978 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
1979 vi_dcc_clean_up_context_slot(rctx
, i
);
1981 /* Find the texture. */
1982 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
1983 /* Return if found. */
1984 if (rctx
->dcc_stats
[i
].tex
== tex
) {
1985 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
1989 /* Record the first seen empty slot. */
1990 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
1994 /* Not found. Remove the oldest member to make space in the array. */
1995 if (empty_slot
== -1) {
1996 int oldest_slot
= 0;
1998 /* Find the oldest slot. */
1999 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2000 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2001 rctx
->dcc_stats
[i
].last_use_timestamp
)
2004 /* Clean up the oldest slot. */
2005 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2006 empty_slot
= oldest_slot
;
2009 /* Add the texture to the new slot. */
2010 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2011 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2015 static struct pipe_query
*
2016 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2018 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2019 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2021 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2022 return (struct pipe_query
*)query
;
2026 * Called when binding a color buffer.
2028 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2029 struct r600_texture
*tex
)
2031 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2032 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2034 assert(!rctx
->dcc_stats
[i
].query_active
);
2036 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2037 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2039 /* begin or resume the query */
2040 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2041 rctx
->dcc_stats
[i
].query_active
= true;
2045 * Called when unbinding a color buffer.
2047 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2048 struct r600_texture
*tex
)
2050 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2051 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2053 assert(rctx
->dcc_stats
[i
].query_active
);
2054 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2056 /* pause or end the query */
2057 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2058 rctx
->dcc_stats
[i
].query_active
= false;
2061 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2063 /* The minimum number of fullscreen draws per frame that is required
2065 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2068 /* Called by fast clear. */
2069 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2070 struct r600_texture
*tex
)
2072 /* The intent is to use this with shared displayable back buffers,
2073 * but it's not strictly limited only to them.
2075 if (!tex
->resource
.is_shared
||
2076 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2077 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2078 tex
->resource
.b
.b
.last_level
> 0 ||
2079 !tex
->surface
.dcc_size
)
2082 if (tex
->dcc_offset
)
2083 return; /* already enabled */
2085 /* Enable the DCC stat gathering. */
2086 if (!tex
->dcc_gather_statistics
) {
2087 tex
->dcc_gather_statistics
= true;
2088 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2091 if (!vi_should_enable_separate_dcc(tex
))
2092 return; /* stats show that DCC decompression is too expensive */
2094 assert(tex
->surface
.num_dcc_levels
);
2095 assert(!tex
->dcc_separate_buffer
);
2097 r600_texture_discard_cmask(rctx
->screen
, tex
);
2099 /* Get a DCC buffer. */
2100 if (tex
->last_dcc_separate_buffer
) {
2101 assert(tex
->dcc_gather_statistics
);
2102 assert(!tex
->dcc_separate_buffer
);
2103 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2104 tex
->last_dcc_separate_buffer
= NULL
;
2106 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2107 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
2109 tex
->surface
.dcc_size
,
2110 tex
->surface
.dcc_alignment
);
2111 if (!tex
->dcc_separate_buffer
)
2115 /* dcc_offset is the absolute GPUVM address. */
2116 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2118 /* no need to flag anything since this is called by fast clear that
2119 * flags framebuffer state
2124 * Called by pipe_context::flush_resource, the place where DCC decompression
2127 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2128 struct r600_texture
*tex
)
2130 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2131 struct pipe_query
*tmp
;
2132 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2133 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2134 bool disable
= false;
2136 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2137 union pipe_query_result result
;
2139 /* Read the results. */
2140 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2142 r600_query_hw_reset_buffers(rctx
,
2143 (struct r600_query_hw
*)
2144 rctx
->dcc_stats
[i
].ps_stats
[2]);
2146 /* Compute the approximate number of fullscreen draws. */
2147 tex
->ps_draw_ratio
=
2148 result
.pipeline_statistics
.ps_invocations
/
2149 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2150 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2152 disable
= tex
->dcc_separate_buffer
&&
2153 !vi_should_enable_separate_dcc(tex
);
2156 tex
->num_slow_clears
= 0;
2158 /* stop the statistics query for ps_stats[0] */
2160 vi_separate_dcc_stop_query(ctx
, tex
);
2162 /* Move the queries in the queue by one. */
2163 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2164 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2165 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2166 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2168 /* create and start a new query as ps_stats[0] */
2170 vi_separate_dcc_start_query(ctx
, tex
);
2173 assert(!tex
->last_dcc_separate_buffer
);
2174 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2175 tex
->dcc_separate_buffer
= NULL
;
2176 tex
->dcc_offset
= 0;
2177 /* no need to flag anything since this is called after
2178 * decompression that re-sets framebuffer state
2183 /* FAST COLOR CLEAR */
2185 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2186 enum pipe_format surface_format
,
2187 const union pipe_color_union
*color
)
2189 union util_color uc
;
2191 memset(&uc
, 0, sizeof(uc
));
2193 if (rtex
->surface
.bpe
== 16) {
2194 /* DCC fast clear only:
2195 * CLEAR_WORD0 = R = G = B
2198 assert(color
->ui
[0] == color
->ui
[1] &&
2199 color
->ui
[0] == color
->ui
[2]);
2200 uc
.ui
[0] = color
->ui
[0];
2201 uc
.ui
[1] = color
->ui
[3];
2202 } else if (util_format_is_pure_uint(surface_format
)) {
2203 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2204 } else if (util_format_is_pure_sint(surface_format
)) {
2205 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2207 util_pack_color(color
->f
, surface_format
, &uc
);
2210 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2213 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2214 const union pipe_color_union
*color
,
2215 uint32_t* reset_value
,
2216 bool* clear_words_needed
)
2218 bool values
[4] = {};
2220 bool main_value
= false;
2221 bool extra_value
= false;
2223 const struct util_format_description
*desc
= util_format_description(surface_format
);
2225 if (desc
->block
.bits
== 128 &&
2226 (color
->ui
[0] != color
->ui
[1] ||
2227 color
->ui
[0] != color
->ui
[2]))
2230 *clear_words_needed
= true;
2231 *reset_value
= 0x20202020U
;
2233 /* If we want to clear without needing a fast clear eliminate step, we
2234 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2235 * have two sets of flags, one for the last or first channel(extra) and
2236 * one for the other channels(main).
2239 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2240 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2241 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2243 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2244 if(r600_translate_colorswap(surface_format
, false) <= 1)
2245 extra_channel
= desc
->nr_channels
- 1;
2251 for (i
= 0; i
< 4; ++i
) {
2252 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2254 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2255 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2258 if (desc
->channel
[i
].pure_integer
&&
2259 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2260 /* Use the maximum value for clamping the clear color. */
2261 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2263 values
[i
] = color
->i
[i
] != 0;
2264 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2266 } else if (desc
->channel
[i
].pure_integer
&&
2267 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2268 /* Use the maximum value for clamping the clear color. */
2269 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2271 values
[i
] = color
->ui
[i
] != 0U;
2272 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2275 values
[i
] = color
->f
[i
] != 0.0F
;
2276 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2280 if (index
== extra_channel
)
2281 extra_value
= values
[i
];
2283 main_value
= values
[i
];
2286 for (int i
= 0; i
< 4; ++i
)
2287 if (values
[i
] != main_value
&&
2288 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2289 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2290 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2293 *clear_words_needed
= false;
2295 *reset_value
|= 0x80808080U
;
2298 *reset_value
|= 0x40404040U
;
2302 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2303 struct r600_texture
*rtex
,
2304 unsigned level
, unsigned clear_value
)
2306 struct pipe_resource
*dcc_buffer
;
2307 uint64_t dcc_offset
;
2309 assert(rtex
->dcc_offset
&& level
< rtex
->surface
.num_dcc_levels
);
2311 if (rtex
->dcc_separate_buffer
) {
2312 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2315 dcc_buffer
= &rtex
->resource
.b
.b
;
2316 dcc_offset
= rtex
->dcc_offset
;
2319 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2321 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2322 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2323 clear_value
, R600_COHERENCY_CB_META
);
2326 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2327 * This allows hitting the MSAA resolve fast path, which requires that both
2328 * src and dst micro tile modes match.
2330 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2331 struct r600_texture
*rtex
)
2333 if (rtex
->resource
.is_shared
||
2334 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2335 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2338 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2339 assert(rtex
->resource
.b
.b
.last_level
== 0);
2341 /* These magic numbers were copied from addrlib. It doesn't use any
2342 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2343 * different bpp and micro tile mode.
2345 if (rscreen
->chip_class
>= CIK
) {
2346 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2347 case RADEON_MICRO_MODE_DISPLAY
:
2348 rtex
->surface
.tiling_index
[0] = 10;
2350 case RADEON_MICRO_MODE_THIN
:
2351 rtex
->surface
.tiling_index
[0] = 14;
2353 case RADEON_MICRO_MODE_ROTATED
:
2354 rtex
->surface
.tiling_index
[0] = 28;
2356 default: /* depth, thick */
2357 assert(!"unexpected micro mode");
2361 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2362 case RADEON_MICRO_MODE_DISPLAY
:
2363 switch (rtex
->surface
.bpe
) {
2365 rtex
->surface
.tiling_index
[0] = 10;
2368 rtex
->surface
.tiling_index
[0] = 11;
2371 rtex
->surface
.tiling_index
[0] = 12;
2375 case RADEON_MICRO_MODE_THIN
:
2376 switch (rtex
->surface
.bpe
) {
2378 rtex
->surface
.tiling_index
[0] = 14;
2381 rtex
->surface
.tiling_index
[0] = 15;
2384 rtex
->surface
.tiling_index
[0] = 16;
2386 default: /* 8, 16 */
2387 rtex
->surface
.tiling_index
[0] = 17;
2391 default: /* depth, thick */
2392 assert(!"unexpected micro mode");
2397 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2399 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2402 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2403 struct pipe_framebuffer_state
*fb
,
2404 struct r600_atom
*fb_state
,
2405 unsigned *buffers
, unsigned *dirty_cbufs
,
2406 const union pipe_color_union
*color
)
2410 /* This function is broken in BE, so just disable this path for now */
2411 #ifdef PIPE_ARCH_BIG_ENDIAN
2415 if (rctx
->render_cond
)
2418 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2419 struct r600_texture
*tex
;
2420 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2425 /* if this colorbuffer is not being cleared */
2426 if (!(*buffers
& clear_bit
))
2429 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2431 /* the clear is allowed if all layers are bound */
2432 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2433 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2437 /* cannot clear mipmapped textures */
2438 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2442 /* only supported on tiled surfaces */
2443 if (tex
->surface
.is_linear
) {
2447 /* shared textures can't use fast clear without an explicit flush,
2448 * because there is no way to communicate the clear color among
2451 if (tex
->resource
.is_shared
&&
2452 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2455 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2456 if (rctx
->chip_class
== CIK
&&
2457 tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2458 rctx
->screen
->info
.drm_major
== 2 &&
2459 rctx
->screen
->info
.drm_minor
< 38) {
2463 /* Fast clear is the most appropriate place to enable DCC for
2464 * displayable surfaces.
2466 if (rctx
->chip_class
>= VI
&&
2467 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2468 vi_separate_dcc_try_enable(rctx
, tex
);
2470 /* Stoney can't do a CMASK-based clear, so all clears are
2471 * considered to be hypothetically slow clears, which
2472 * is weighed when determining to enable separate DCC.
2474 if (tex
->dcc_gather_statistics
&&
2475 rctx
->family
== CHIP_STONEY
)
2476 tex
->num_slow_clears
++;
2479 /* Try to clear DCC first, otherwise try CMASK. */
2480 if (tex
->dcc_offset
&& tex
->surface
.num_dcc_levels
) {
2481 uint32_t reset_value
;
2482 bool clear_words_needed
;
2484 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2487 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2488 color
, &reset_value
,
2489 &clear_words_needed
))
2492 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2494 if (clear_words_needed
)
2495 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2496 tex
->separate_dcc_dirty
= true;
2498 /* 128-bit formats are unusupported */
2499 if (tex
->surface
.bpe
> 8) {
2503 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2504 if (rctx
->family
== CHIP_STONEY
)
2507 /* ensure CMASK is enabled */
2508 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2509 if (tex
->cmask
.size
== 0) {
2513 /* Do the fast clear. */
2514 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2515 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2516 R600_COHERENCY_CB_META
);
2518 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2521 /* We can change the micro tile mode before a full clear. */
2522 if (rctx
->screen
->chip_class
>= SI
)
2523 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2525 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2528 *dirty_cbufs
|= 1 << i
;
2529 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2530 *buffers
&= ~clear_bit
;
2534 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2536 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2537 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2540 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2542 rctx
->b
.create_surface
= r600_create_surface
;
2543 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2544 rctx
->b
.clear_texture
= r600_clear_texture
;