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gallium/radeon: set texture metadata only once
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static void r600_texture_init_metadata(struct r600_texture *rtex,
232 struct radeon_bo_metadata *metadata)
233 {
234 struct radeon_surf *surface = &rtex->surface;
235
236 memset(metadata, 0, sizeof(*metadata));
237 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
238 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
239 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
240 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
241 metadata->pipe_config = surface->pipe_config;
242 metadata->bankw = surface->bankw;
243 metadata->bankh = surface->bankh;
244 metadata->tile_split = surface->tile_split;
245 metadata->stencil_tile_split = surface->stencil_tile_split;
246 metadata->mtilea = surface->mtilea;
247 metadata->num_banks = surface->num_banks;
248 metadata->stride = surface->level[0].pitch_bytes;
249 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
250 }
251
252 static boolean r600_texture_get_handle(struct pipe_screen* screen,
253 struct pipe_resource *resource,
254 struct winsys_handle *whandle,
255 unsigned usage)
256 {
257 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
258 struct r600_resource *res = (struct r600_resource*)resource;
259 struct r600_texture *rtex = (struct r600_texture*)resource;
260 struct radeon_bo_metadata metadata;
261
262 if (!res->is_shared) {
263 res->is_shared = true;
264 r600_texture_init_metadata(rtex, &metadata);
265 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
266 }
267
268 return rscreen->ws->buffer_get_handle(res->buf,
269 rtex->surface.level[0].pitch_bytes,
270 whandle);
271 }
272
273 static void r600_texture_destroy(struct pipe_screen *screen,
274 struct pipe_resource *ptex)
275 {
276 struct r600_texture *rtex = (struct r600_texture*)ptex;
277 struct r600_resource *resource = &rtex->resource;
278
279 if (rtex->flushed_depth_texture)
280 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
281
282 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
283 if (rtex->cmask_buffer != &rtex->resource) {
284 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
285 }
286 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
287 pb_reference(&resource->buf, NULL);
288 FREE(rtex);
289 }
290
291 static const struct u_resource_vtbl r600_texture_vtbl;
292
293 /* The number of samples can be specified independently of the texture. */
294 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
295 struct r600_texture *rtex,
296 unsigned nr_samples,
297 struct r600_fmask_info *out)
298 {
299 /* FMASK is allocated like an ordinary texture. */
300 struct radeon_surf fmask = rtex->surface;
301
302 memset(out, 0, sizeof(*out));
303
304 fmask.bo_alignment = 0;
305 fmask.bo_size = 0;
306 fmask.nsamples = 1;
307 fmask.flags |= RADEON_SURF_FMASK;
308
309 /* Force 2D tiling if it wasn't set. This may occur when creating
310 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
311 * destination buffer must have an FMASK too. */
312 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
313 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
314
315 if (rscreen->chip_class >= SI) {
316 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
317 }
318
319 switch (nr_samples) {
320 case 2:
321 case 4:
322 fmask.bpe = 1;
323 if (rscreen->chip_class <= CAYMAN) {
324 fmask.bankh = 4;
325 }
326 break;
327 case 8:
328 fmask.bpe = 4;
329 break;
330 default:
331 R600_ERR("Invalid sample count for FMASK allocation.\n");
332 return;
333 }
334
335 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
336 * This can be fixed by writing a separate FMASK allocator specifically
337 * for R600-R700 asics. */
338 if (rscreen->chip_class <= R700) {
339 fmask.bpe *= 2;
340 }
341
342 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
343 R600_ERR("Got error in surface_init while allocating FMASK.\n");
344 return;
345 }
346
347 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
348
349 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
350 if (out->slice_tile_max)
351 out->slice_tile_max -= 1;
352
353 out->tile_mode_index = fmask.tiling_index[0];
354 out->pitch_in_pixels = fmask.level[0].nblk_x;
355 out->bank_height = fmask.bankh;
356 out->alignment = MAX2(256, fmask.bo_alignment);
357 out->size = fmask.bo_size;
358 }
359
360 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
361 struct r600_texture *rtex)
362 {
363 r600_texture_get_fmask_info(rscreen, rtex,
364 rtex->resource.b.b.nr_samples, &rtex->fmask);
365
366 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
367 rtex->size = rtex->fmask.offset + rtex->fmask.size;
368 }
369
370 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
371 struct r600_texture *rtex,
372 struct r600_cmask_info *out)
373 {
374 unsigned cmask_tile_width = 8;
375 unsigned cmask_tile_height = 8;
376 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
377 unsigned element_bits = 4;
378 unsigned cmask_cache_bits = 1024;
379 unsigned num_pipes = rscreen->info.num_tile_pipes;
380 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
381
382 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
383 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
384 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
385 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
386 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
387
388 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
389 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
390
391 unsigned base_align = num_pipes * pipe_interleave_bytes;
392 unsigned slice_bytes =
393 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
394
395 assert(macro_tile_width % 128 == 0);
396 assert(macro_tile_height % 128 == 0);
397
398 out->pitch = pitch_elements;
399 out->height = height;
400 out->xalign = macro_tile_width;
401 out->yalign = macro_tile_height;
402 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
403 out->alignment = MAX2(256, base_align);
404 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
405 align(slice_bytes, base_align);
406 }
407
408 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
409 struct r600_texture *rtex,
410 struct r600_cmask_info *out)
411 {
412 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
413 unsigned num_pipes = rscreen->info.num_tile_pipes;
414 unsigned cl_width, cl_height;
415
416 switch (num_pipes) {
417 case 2:
418 cl_width = 32;
419 cl_height = 16;
420 break;
421 case 4:
422 cl_width = 32;
423 cl_height = 32;
424 break;
425 case 8:
426 cl_width = 64;
427 cl_height = 32;
428 break;
429 case 16: /* Hawaii */
430 cl_width = 64;
431 cl_height = 64;
432 break;
433 default:
434 assert(0);
435 return;
436 }
437
438 unsigned base_align = num_pipes * pipe_interleave_bytes;
439
440 unsigned width = align(rtex->surface.npix_x, cl_width*8);
441 unsigned height = align(rtex->surface.npix_y, cl_height*8);
442 unsigned slice_elements = (width * height) / (8*8);
443
444 /* Each element of CMASK is a nibble. */
445 unsigned slice_bytes = slice_elements / 2;
446
447 out->pitch = width;
448 out->height = height;
449 out->xalign = cl_width * 8;
450 out->yalign = cl_height * 8;
451 out->slice_tile_max = (width * height) / (128*128);
452 if (out->slice_tile_max)
453 out->slice_tile_max -= 1;
454
455 out->alignment = MAX2(256, base_align);
456 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
457 align(slice_bytes, base_align);
458 }
459
460 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
461 struct r600_texture *rtex)
462 {
463 if (rscreen->chip_class >= SI) {
464 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
465 } else {
466 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
467 }
468
469 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
470 rtex->size = rtex->cmask.offset + rtex->cmask.size;
471
472 if (rscreen->chip_class >= SI)
473 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
474 else
475 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
476 }
477
478 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
479 struct r600_texture *rtex)
480 {
481 if (rtex->cmask_buffer)
482 return;
483
484 assert(rtex->cmask.size == 0);
485
486 if (rscreen->chip_class >= SI) {
487 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
488 } else {
489 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
490 }
491
492 rtex->cmask_buffer = (struct r600_resource *)
493 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
494 PIPE_USAGE_DEFAULT, rtex->cmask.size);
495 if (rtex->cmask_buffer == NULL) {
496 rtex->cmask.size = 0;
497 return;
498 }
499
500 /* update colorbuffer state bits */
501 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
502
503 if (rscreen->chip_class >= SI)
504 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
505 else
506 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
507 }
508
509 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
510 struct r600_texture *rtex)
511 {
512 if (rscreen->debug_flags & DBG_NO_DCC)
513 return;
514
515 rtex->dcc_buffer = (struct r600_resource *)
516 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
517 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
518 if (rtex->dcc_buffer == NULL) {
519 return;
520 }
521
522 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
523 0xFFFFFFFF, true);
524
525 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
526 }
527
528 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
529 struct r600_texture *rtex)
530 {
531 unsigned cl_width, cl_height, width, height;
532 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
533 unsigned num_pipes = rscreen->info.num_tile_pipes;
534
535 if (rscreen->chip_class <= EVERGREEN &&
536 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
537 return 0;
538
539 /* HW bug on R6xx. */
540 if (rscreen->chip_class == R600 &&
541 (rtex->surface.level[0].npix_x > 7680 ||
542 rtex->surface.level[0].npix_y > 7680))
543 return 0;
544
545 /* HTILE is broken with 1D tiling on old kernels and CIK. */
546 if (rscreen->chip_class >= CIK &&
547 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
548 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
549 return 0;
550
551 /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
552 if (rscreen->family == CHIP_STONEY)
553 num_pipes = 4;
554
555 switch (num_pipes) {
556 case 1:
557 cl_width = 32;
558 cl_height = 16;
559 break;
560 case 2:
561 cl_width = 32;
562 cl_height = 32;
563 break;
564 case 4:
565 cl_width = 64;
566 cl_height = 32;
567 break;
568 case 8:
569 cl_width = 64;
570 cl_height = 64;
571 break;
572 case 16:
573 cl_width = 128;
574 cl_height = 64;
575 break;
576 default:
577 assert(0);
578 return 0;
579 }
580
581 width = align(rtex->surface.npix_x, cl_width * 8);
582 height = align(rtex->surface.npix_y, cl_height * 8);
583
584 slice_elements = (width * height) / (8 * 8);
585 slice_bytes = slice_elements * 4;
586
587 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
588 base_align = num_pipes * pipe_interleave_bytes;
589
590 rtex->htile.pitch = width;
591 rtex->htile.height = height;
592 rtex->htile.xalign = cl_width * 8;
593 rtex->htile.yalign = cl_height * 8;
594
595 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
596 align(slice_bytes, base_align);
597 }
598
599 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
600 struct r600_texture *rtex)
601 {
602 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
603
604 if (!htile_size)
605 return;
606
607 rtex->htile_buffer = (struct r600_resource*)
608 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
609 PIPE_USAGE_DEFAULT, htile_size);
610 if (rtex->htile_buffer == NULL) {
611 /* this is not a fatal error as we can still keep rendering
612 * without htile buffer */
613 R600_ERR("Failed to create buffer object for htile buffer.\n");
614 } else {
615 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
616 htile_size, 0, true);
617 }
618 }
619
620 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
621 {
622 int i;
623
624 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
625 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
626 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
627 rtex->surface.npix_x, rtex->surface.npix_y,
628 rtex->surface.npix_z, rtex->surface.blk_w,
629 rtex->surface.blk_h, rtex->surface.blk_d,
630 rtex->surface.array_size, rtex->surface.last_level,
631 rtex->surface.bpe, rtex->surface.nsamples,
632 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
633
634 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
635 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
636 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
637 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
638 rtex->surface.tile_split, rtex->surface.pipe_config,
639 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
640
641 if (rtex->fmask.size)
642 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
643 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
644 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
645 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
646 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
647
648 if (rtex->cmask.size)
649 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
650 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
651 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
652 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
653 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
654
655 if (rtex->htile_buffer)
656 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
657 "xalign=%u, yalign=%u\n",
658 rtex->htile_buffer->b.b.width0,
659 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
660 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
661
662 if (rtex->dcc_buffer) {
663 fprintf(f, " DCC: size=%u, alignment=%u\n",
664 rtex->dcc_buffer->b.b.width0,
665 rtex->dcc_buffer->buf->alignment);
666 for (i = 0; i <= rtex->surface.last_level; i++)
667 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
668 i, rtex->surface.level[i].dcc_offset);
669 }
670
671 for (i = 0; i <= rtex->surface.last_level; i++)
672 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
673 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
674 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
675 i, rtex->surface.level[i].offset,
676 rtex->surface.level[i].slice_size,
677 u_minify(rtex->resource.b.b.width0, i),
678 u_minify(rtex->resource.b.b.height0, i),
679 u_minify(rtex->resource.b.b.depth0, i),
680 rtex->surface.level[i].nblk_x,
681 rtex->surface.level[i].nblk_y,
682 rtex->surface.level[i].nblk_z,
683 rtex->surface.level[i].pitch_bytes,
684 rtex->surface.level[i].mode);
685
686 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
687 for (i = 0; i <= rtex->surface.last_level; i++) {
688 fprintf(f, " StencilLayout: tilesplit=%u\n",
689 rtex->surface.stencil_tile_split);
690 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
691 "slice_size=%"PRIu64", npix_x=%u, "
692 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
693 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
694 i, rtex->surface.stencil_level[i].offset,
695 rtex->surface.stencil_level[i].slice_size,
696 u_minify(rtex->resource.b.b.width0, i),
697 u_minify(rtex->resource.b.b.height0, i),
698 u_minify(rtex->resource.b.b.depth0, i),
699 rtex->surface.stencil_level[i].nblk_x,
700 rtex->surface.stencil_level[i].nblk_y,
701 rtex->surface.stencil_level[i].nblk_z,
702 rtex->surface.stencil_level[i].pitch_bytes,
703 rtex->surface.stencil_level[i].mode);
704 }
705 }
706 }
707
708 /* Common processing for r600_texture_create and r600_texture_from_handle */
709 static struct r600_texture *
710 r600_texture_create_object(struct pipe_screen *screen,
711 const struct pipe_resource *base,
712 unsigned pitch_in_bytes_override,
713 struct pb_buffer *buf,
714 struct radeon_surf *surface)
715 {
716 struct r600_texture *rtex;
717 struct r600_resource *resource;
718 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
719
720 rtex = CALLOC_STRUCT(r600_texture);
721 if (!rtex)
722 return NULL;
723
724 resource = &rtex->resource;
725 resource->b.b = *base;
726 resource->b.vtbl = &r600_texture_vtbl;
727 pipe_reference_init(&resource->b.b.reference, 1);
728 resource->b.b.screen = screen;
729
730 /* don't include stencil-only formats which we don't support for rendering */
731 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
732
733 rtex->surface = *surface;
734 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
735 FREE(rtex);
736 return NULL;
737 }
738
739 /* Tiled depth textures utilize the non-displayable tile order.
740 * This must be done after r600_setup_surface.
741 * Applies to R600-Cayman. */
742 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
743
744 if (rtex->is_depth) {
745 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
746 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
747 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
748
749 r600_texture_allocate_htile(rscreen, rtex);
750 }
751 } else {
752 if (base->nr_samples > 1) {
753 if (!buf) {
754 r600_texture_allocate_fmask(rscreen, rtex);
755 r600_texture_allocate_cmask(rscreen, rtex);
756 rtex->cmask_buffer = &rtex->resource;
757 }
758 if (!rtex->fmask.size || !rtex->cmask.size) {
759 FREE(rtex);
760 return NULL;
761 }
762 }
763 if (rtex->surface.dcc_size)
764 vi_texture_alloc_dcc_separate(rscreen, rtex);
765 }
766
767 /* Now create the backing buffer. */
768 if (!buf) {
769 if (!r600_init_resource(rscreen, resource, rtex->size,
770 rtex->surface.bo_alignment, TRUE)) {
771 FREE(rtex);
772 return NULL;
773 }
774 } else {
775 resource->buf = buf;
776 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
777 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
778 }
779
780 if (rtex->cmask.size) {
781 /* Initialize the cmask to 0xCC (= compressed state). */
782 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
783 rtex->cmask.offset, rtex->cmask.size,
784 0xCCCCCCCC, true);
785 }
786
787 /* Initialize the CMASK base register value. */
788 rtex->cmask.base_address_reg =
789 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
790
791 if (rscreen->debug_flags & DBG_VM) {
792 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
793 rtex->resource.gpu_address,
794 rtex->resource.gpu_address + rtex->resource.buf->size,
795 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
796 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
797 }
798
799 if (rscreen->debug_flags & DBG_TEX) {
800 puts("Texture:");
801 r600_print_texture_info(rtex, stdout);
802 }
803
804 return rtex;
805 }
806
807 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
808 const struct pipe_resource *templ)
809 {
810 const struct util_format_description *desc = util_format_description(templ->format);
811 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
812
813 /* MSAA resources must be 2D tiled. */
814 if (templ->nr_samples > 1)
815 return RADEON_SURF_MODE_2D;
816
817 /* Transfer resources should be linear. */
818 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
819 return RADEON_SURF_MODE_LINEAR_ALIGNED;
820
821 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
822 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
823 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
824 (templ->target == PIPE_TEXTURE_2D ||
825 templ->target == PIPE_TEXTURE_3D))
826 force_tiling = true;
827
828 /* Handle common candidates for the linear mode.
829 * Compressed textures must always be tiled. */
830 if (!force_tiling && !util_format_is_compressed(templ->format)) {
831 /* Not everything can be linear, so we cannot enforce it
832 * for all textures. */
833 if ((rscreen->debug_flags & DBG_NO_TILING) &&
834 (!util_format_is_depth_or_stencil(templ->format) ||
835 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
836 return RADEON_SURF_MODE_LINEAR_ALIGNED;
837
838 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
839 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
840 return RADEON_SURF_MODE_LINEAR_ALIGNED;
841
842 /* Cursors are linear on SI.
843 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
844 if (rscreen->chip_class >= SI &&
845 (templ->bind & PIPE_BIND_CURSOR))
846 return RADEON_SURF_MODE_LINEAR_ALIGNED;
847
848 if (templ->bind & PIPE_BIND_LINEAR)
849 return RADEON_SURF_MODE_LINEAR_ALIGNED;
850
851 /* Textures with a very small height are recommended to be linear. */
852 if (templ->target == PIPE_TEXTURE_1D ||
853 templ->target == PIPE_TEXTURE_1D_ARRAY ||
854 templ->height0 <= 4)
855 return RADEON_SURF_MODE_LINEAR_ALIGNED;
856
857 /* Textures likely to be mapped often. */
858 if (templ->usage == PIPE_USAGE_STAGING ||
859 templ->usage == PIPE_USAGE_STREAM)
860 return RADEON_SURF_MODE_LINEAR_ALIGNED;
861 }
862
863 /* Make small textures 1D tiled. */
864 if (templ->width0 <= 16 || templ->height0 <= 16 ||
865 (rscreen->debug_flags & DBG_NO_2D_TILING))
866 return RADEON_SURF_MODE_1D;
867
868 /* The allocator will switch to 1D if needed. */
869 return RADEON_SURF_MODE_2D;
870 }
871
872 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
873 const struct pipe_resource *templ)
874 {
875 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
876 struct radeon_surf surface = {0};
877 int r;
878
879 r = r600_init_surface(rscreen, &surface, templ,
880 r600_choose_tiling(rscreen, templ),
881 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
882 if (r) {
883 return NULL;
884 }
885 r = rscreen->ws->surface_best(rscreen->ws, &surface);
886 if (r) {
887 return NULL;
888 }
889 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
890 0, NULL, &surface);
891 }
892
893 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
894 const struct pipe_resource *templ,
895 struct winsys_handle *whandle,
896 unsigned usage)
897 {
898 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
899 struct pb_buffer *buf = NULL;
900 unsigned stride = 0;
901 unsigned array_mode;
902 struct radeon_surf surface;
903 int r;
904 struct radeon_bo_metadata metadata = {};
905
906 /* Support only 2D textures without mipmaps */
907 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
908 templ->depth0 != 1 || templ->last_level != 0)
909 return NULL;
910
911 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
912 if (!buf)
913 return NULL;
914
915 rscreen->ws->buffer_get_metadata(buf, &metadata);
916
917 surface.bankw = metadata.bankw;
918 surface.bankh = metadata.bankh;
919 surface.tile_split = metadata.tile_split;
920 surface.stencil_tile_split = metadata.stencil_tile_split;
921 surface.mtilea = metadata.mtilea;
922
923 if (metadata.macrotile == RADEON_LAYOUT_TILED)
924 array_mode = RADEON_SURF_MODE_2D;
925 else if (metadata.microtile == RADEON_LAYOUT_TILED)
926 array_mode = RADEON_SURF_MODE_1D;
927 else
928 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
929
930 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
931 if (r) {
932 return NULL;
933 }
934
935 if (metadata.scanout)
936 surface.flags |= RADEON_SURF_SCANOUT;
937
938 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
939 stride, buf, &surface);
940 }
941
942 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
943 struct pipe_resource *texture,
944 struct r600_texture **staging)
945 {
946 struct r600_texture *rtex = (struct r600_texture*)texture;
947 struct pipe_resource resource;
948 struct r600_texture **flushed_depth_texture = staging ?
949 staging : &rtex->flushed_depth_texture;
950
951 if (!staging && rtex->flushed_depth_texture)
952 return true; /* it's ready */
953
954 resource.target = texture->target;
955 resource.format = texture->format;
956 resource.width0 = texture->width0;
957 resource.height0 = texture->height0;
958 resource.depth0 = texture->depth0;
959 resource.array_size = texture->array_size;
960 resource.last_level = texture->last_level;
961 resource.nr_samples = texture->nr_samples;
962 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
963 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
964 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
965
966 if (staging)
967 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
968
969 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
970 if (*flushed_depth_texture == NULL) {
971 R600_ERR("failed to create temporary texture to hold flushed depth\n");
972 return false;
973 }
974
975 (*flushed_depth_texture)->is_flushing_texture = TRUE;
976 (*flushed_depth_texture)->non_disp_tiling = false;
977 return true;
978 }
979
980 /**
981 * Initialize the pipe_resource descriptor to be of the same size as the box,
982 * which is supposed to hold a subregion of the texture "orig" at the given
983 * mipmap level.
984 */
985 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
986 struct pipe_resource *orig,
987 const struct pipe_box *box,
988 unsigned level, unsigned flags)
989 {
990 memset(res, 0, sizeof(*res));
991 res->format = orig->format;
992 res->width0 = box->width;
993 res->height0 = box->height;
994 res->depth0 = 1;
995 res->array_size = 1;
996 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
997 res->flags = flags;
998
999 /* We must set the correct texture target and dimensions for a 3D box. */
1000 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1001 res->target = orig->target;
1002 else
1003 res->target = PIPE_TEXTURE_2D;
1004
1005 switch (res->target) {
1006 case PIPE_TEXTURE_1D_ARRAY:
1007 case PIPE_TEXTURE_2D_ARRAY:
1008 case PIPE_TEXTURE_CUBE_ARRAY:
1009 res->array_size = box->depth;
1010 break;
1011 case PIPE_TEXTURE_3D:
1012 res->depth0 = box->depth;
1013 break;
1014 default:;
1015 }
1016 }
1017
1018 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1019 struct pipe_resource *texture,
1020 unsigned level,
1021 unsigned usage,
1022 const struct pipe_box *box,
1023 struct pipe_transfer **ptransfer)
1024 {
1025 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1026 struct r600_texture *rtex = (struct r600_texture*)texture;
1027 struct r600_transfer *trans;
1028 boolean use_staging_texture = FALSE;
1029 struct r600_resource *buf;
1030 unsigned offset = 0;
1031 char *map;
1032
1033 /* We cannot map a tiled texture directly because the data is
1034 * in a different order, therefore we do detiling using a blit.
1035 *
1036 * Also, use a temporary in GTT memory for read transfers, as
1037 * the CPU is much happier reading out of cached system memory
1038 * than uncached VRAM.
1039 */
1040 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1041 use_staging_texture = TRUE;
1042 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1043 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1044 /* Untiled buffers in VRAM, which is slow for CPU reads */
1045 use_staging_texture = TRUE;
1046 } else if (!(usage & PIPE_TRANSFER_READ) &&
1047 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1048 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1049 /* Use a staging texture for uploads if the underlying BO is busy. */
1050 use_staging_texture = TRUE;
1051 }
1052
1053 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1054 use_staging_texture = FALSE;
1055 }
1056
1057 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1058 return NULL;
1059 }
1060
1061 trans = CALLOC_STRUCT(r600_transfer);
1062 if (!trans)
1063 return NULL;
1064 trans->transfer.resource = texture;
1065 trans->transfer.level = level;
1066 trans->transfer.usage = usage;
1067 trans->transfer.box = *box;
1068
1069 if (rtex->is_depth) {
1070 struct r600_texture *staging_depth;
1071
1072 if (rtex->resource.b.b.nr_samples > 1) {
1073 /* MSAA depth buffers need to be converted to single sample buffers.
1074 *
1075 * Mapping MSAA depth buffers can occur if ReadPixels is called
1076 * with a multisample GLX visual.
1077 *
1078 * First downsample the depth buffer to a temporary texture,
1079 * then decompress the temporary one to staging.
1080 *
1081 * Only the region being mapped is transfered.
1082 */
1083 struct pipe_resource resource;
1084
1085 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1086
1087 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1088 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1089 FREE(trans);
1090 return NULL;
1091 }
1092
1093 if (usage & PIPE_TRANSFER_READ) {
1094 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1095 if (!temp) {
1096 R600_ERR("failed to create a temporary depth texture\n");
1097 FREE(trans);
1098 return NULL;
1099 }
1100
1101 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1102 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1103 0, 0, 0, box->depth, 0, 0);
1104 pipe_resource_reference(&temp, NULL);
1105 }
1106 }
1107 else {
1108 /* XXX: only readback the rectangle which is being mapped? */
1109 /* XXX: when discard is true, no need to read back from depth texture */
1110 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1111 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1112 FREE(trans);
1113 return NULL;
1114 }
1115
1116 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1117 level, level,
1118 box->z, box->z + box->depth - 1,
1119 0, 0);
1120
1121 offset = r600_texture_get_offset(staging_depth, level, box);
1122 }
1123
1124 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1125 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1126 trans->staging = (struct r600_resource*)staging_depth;
1127 } else if (use_staging_texture) {
1128 struct pipe_resource resource;
1129 struct r600_texture *staging;
1130
1131 r600_init_temp_resource_from_box(&resource, texture, box, level,
1132 R600_RESOURCE_FLAG_TRANSFER);
1133 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1134 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1135
1136 /* Create the temporary texture. */
1137 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1138 if (!staging) {
1139 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1140 FREE(trans);
1141 return NULL;
1142 }
1143 trans->staging = &staging->resource;
1144 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1145 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1146 if (usage & PIPE_TRANSFER_READ) {
1147 r600_copy_to_staging_texture(ctx, trans);
1148 }
1149 } else {
1150 /* the resource is mapped directly */
1151 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1152 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1153 offset = r600_texture_get_offset(rtex, level, box);
1154 }
1155
1156 if (trans->staging) {
1157 buf = trans->staging;
1158 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1159 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1160 } else {
1161 buf = &rtex->resource;
1162 }
1163
1164 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1165 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1166 FREE(trans);
1167 return NULL;
1168 }
1169
1170 *ptransfer = &trans->transfer;
1171 return map + offset;
1172 }
1173
1174 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1175 struct pipe_transfer* transfer)
1176 {
1177 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1178 struct pipe_resource *texture = transfer->resource;
1179 struct r600_texture *rtex = (struct r600_texture*)texture;
1180
1181 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1182 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1183 ctx->resource_copy_region(ctx, texture, transfer->level,
1184 transfer->box.x, transfer->box.y, transfer->box.z,
1185 &rtransfer->staging->b.b, transfer->level,
1186 &transfer->box);
1187 } else {
1188 r600_copy_from_staging_texture(ctx, rtransfer);
1189 }
1190 }
1191
1192 if (rtransfer->staging)
1193 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1194
1195 FREE(transfer);
1196 }
1197
1198 static const struct u_resource_vtbl r600_texture_vtbl =
1199 {
1200 NULL, /* get_handle */
1201 r600_texture_destroy, /* resource_destroy */
1202 r600_texture_transfer_map, /* transfer_map */
1203 u_default_transfer_flush_region, /* transfer_flush_region */
1204 r600_texture_transfer_unmap, /* transfer_unmap */
1205 NULL /* transfer_inline_write */
1206 };
1207
1208 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1209 struct pipe_resource *texture,
1210 const struct pipe_surface *templ,
1211 unsigned width, unsigned height)
1212 {
1213 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1214
1215 if (!surface)
1216 return NULL;
1217
1218 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1219 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1220
1221 pipe_reference_init(&surface->base.reference, 1);
1222 pipe_resource_reference(&surface->base.texture, texture);
1223 surface->base.context = pipe;
1224 surface->base.format = templ->format;
1225 surface->base.width = width;
1226 surface->base.height = height;
1227 surface->base.u = templ->u;
1228 return &surface->base;
1229 }
1230
1231 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1232 struct pipe_resource *tex,
1233 const struct pipe_surface *templ)
1234 {
1235 unsigned level = templ->u.tex.level;
1236 unsigned width = u_minify(tex->width0, level);
1237 unsigned height = u_minify(tex->height0, level);
1238
1239 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1240 const struct util_format_description *tex_desc
1241 = util_format_description(tex->format);
1242 const struct util_format_description *templ_desc
1243 = util_format_description(templ->format);
1244
1245 assert(tex_desc->block.bits == templ_desc->block.bits);
1246
1247 /* Adjust size of surface if and only if the block width or
1248 * height is changed. */
1249 if (tex_desc->block.width != templ_desc->block.width ||
1250 tex_desc->block.height != templ_desc->block.height) {
1251 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1252 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1253
1254 width = nblks_x * templ_desc->block.width;
1255 height = nblks_y * templ_desc->block.height;
1256 }
1257 }
1258
1259 return r600_create_surface_custom(pipe, tex, templ, width, height);
1260 }
1261
1262 static void r600_surface_destroy(struct pipe_context *pipe,
1263 struct pipe_surface *surface)
1264 {
1265 struct r600_surface *surf = (struct r600_surface*)surface;
1266 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1267 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1268 pipe_resource_reference(&surface->texture, NULL);
1269 FREE(surface);
1270 }
1271
1272 unsigned r600_translate_colorswap(enum pipe_format format)
1273 {
1274 const struct util_format_description *desc = util_format_description(format);
1275
1276 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1277
1278 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1279 return V_0280A0_SWAP_STD;
1280
1281 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1282 return ~0U;
1283
1284 switch (desc->nr_channels) {
1285 case 1:
1286 if (HAS_SWIZZLE(0,X))
1287 return V_0280A0_SWAP_STD; /* X___ */
1288 else if (HAS_SWIZZLE(3,X))
1289 return V_0280A0_SWAP_ALT_REV; /* ___X */
1290 break;
1291 case 2:
1292 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1293 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1294 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1295 return V_0280A0_SWAP_STD; /* XY__ */
1296 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1297 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1298 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1299 return V_0280A0_SWAP_STD_REV; /* YX__ */
1300 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1301 return V_0280A0_SWAP_ALT; /* X__Y */
1302 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1303 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1304 break;
1305 case 3:
1306 if (HAS_SWIZZLE(0,X))
1307 return V_0280A0_SWAP_STD; /* XYZ */
1308 else if (HAS_SWIZZLE(0,Z))
1309 return V_0280A0_SWAP_STD_REV; /* ZYX */
1310 break;
1311 case 4:
1312 /* check the middle channels, the 1st and 4th channel can be NONE */
1313 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1314 return V_0280A0_SWAP_STD; /* XYZW */
1315 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1316 return V_0280A0_SWAP_STD_REV; /* WZYX */
1317 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1318 return V_0280A0_SWAP_ALT; /* ZYXW */
1319 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
1320 return V_0280A0_SWAP_ALT_REV; /* YZWX */
1321 break;
1322 }
1323 return ~0U;
1324 }
1325
1326 static void evergreen_set_clear_color(struct r600_texture *rtex,
1327 enum pipe_format surface_format,
1328 const union pipe_color_union *color)
1329 {
1330 union util_color uc;
1331
1332 memset(&uc, 0, sizeof(uc));
1333
1334 if (util_format_is_pure_uint(surface_format)) {
1335 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1336 } else if (util_format_is_pure_sint(surface_format)) {
1337 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1338 } else {
1339 util_pack_color(color->f, surface_format, &uc);
1340 }
1341
1342 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1343 }
1344
1345 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1346 const union pipe_color_union *color,
1347 uint32_t* reset_value,
1348 bool* clear_words_needed)
1349 {
1350 bool values[4] = {};
1351 int i;
1352 bool main_value = false;
1353 bool extra_value = false;
1354 int extra_channel;
1355 const struct util_format_description *desc = util_format_description(surface_format);
1356
1357 *clear_words_needed = true;
1358 *reset_value = 0x20202020U;
1359
1360 /* If we want to clear without needing a fast clear eliminate step, we
1361 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1362 * have two sets of flags, one for the last or first channel(extra) and
1363 * one for the other channels(main).
1364 */
1365
1366 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1367 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1368 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1369 extra_channel = -1;
1370 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1371 if(r600_translate_colorswap(surface_format) <= 1)
1372 extra_channel = desc->nr_channels - 1;
1373 else
1374 extra_channel = 0;
1375 } else
1376 return;
1377
1378 for (i = 0; i < 4; ++i) {
1379 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1380
1381 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1382 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1383 continue;
1384
1385 if (util_format_is_pure_sint(surface_format)) {
1386 values[i] = color->i[i] != 0;
1387 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1388 return;
1389 } else if (util_format_is_pure_uint(surface_format)) {
1390 values[i] = color->ui[i] != 0U;
1391 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1392 return;
1393 } else {
1394 values[i] = color->f[i] != 0.0F;
1395 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1396 return;
1397 }
1398
1399 if (index == extra_channel)
1400 extra_value = values[i];
1401 else
1402 main_value = values[i];
1403 }
1404
1405 for (int i = 0; i < 4; ++i)
1406 if (values[i] != main_value &&
1407 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1408 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1409 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1410 return;
1411
1412 *clear_words_needed = false;
1413 if (main_value)
1414 *reset_value |= 0x80808080U;
1415
1416 if (extra_value)
1417 *reset_value |= 0x40404040U;
1418 }
1419
1420 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1421 struct pipe_framebuffer_state *fb,
1422 struct r600_atom *fb_state,
1423 unsigned *buffers, unsigned *dirty_cbufs,
1424 const union pipe_color_union *color)
1425 {
1426 int i;
1427
1428 /* This function is broken in BE, so just disable this path for now */
1429 #ifdef PIPE_ARCH_BIG_ENDIAN
1430 return;
1431 #endif
1432
1433 if (rctx->render_cond)
1434 return;
1435
1436 for (i = 0; i < fb->nr_cbufs; i++) {
1437 struct r600_texture *tex;
1438 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1439
1440 if (!fb->cbufs[i])
1441 continue;
1442
1443 /* if this colorbuffer is not being cleared */
1444 if (!(*buffers & clear_bit))
1445 continue;
1446
1447 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1448
1449 /* 128-bit formats are unusupported */
1450 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1451 continue;
1452 }
1453
1454 /* the clear is allowed if all layers are bound */
1455 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1456 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1457 continue;
1458 }
1459
1460 /* cannot clear mipmapped textures */
1461 if (fb->cbufs[i]->texture->last_level != 0) {
1462 continue;
1463 }
1464
1465 /* only supported on tiled surfaces */
1466 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1467 continue;
1468 }
1469
1470 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1471 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1472 rctx->chip_class >= CIK &&
1473 rctx->screen->info.drm_major == 2 &&
1474 rctx->screen->info.drm_minor < 38) {
1475 continue;
1476 }
1477
1478 if (tex->dcc_buffer) {
1479 uint32_t reset_value;
1480 bool clear_words_needed;
1481
1482 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1483 continue;
1484
1485 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1486
1487 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1488 0, tex->surface.dcc_size, reset_value, true);
1489
1490 if (clear_words_needed)
1491 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1492 } else {
1493 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1494 if (rctx->family == CHIP_STONEY)
1495 continue;
1496
1497 /* ensure CMASK is enabled */
1498 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1499 if (tex->cmask.size == 0) {
1500 continue;
1501 }
1502
1503 /* Do the fast clear. */
1504 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1505 tex->cmask.offset, tex->cmask.size, 0, true);
1506
1507 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1508 }
1509
1510 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1511
1512 if (dirty_cbufs)
1513 *dirty_cbufs |= 1 << i;
1514 rctx->set_atom_dirty(rctx, fb_state, true);
1515 *buffers &= ~clear_bit;
1516 }
1517 }
1518
1519 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1520 {
1521 rscreen->b.resource_from_handle = r600_texture_from_handle;
1522 rscreen->b.resource_get_handle = r600_texture_get_handle;
1523 }
1524
1525 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1526 {
1527 rctx->b.create_surface = r600_create_surface;
1528 rctx->b.surface_destroy = r600_surface_destroy;
1529 }