src/gallium/drivers/radeon/radeon_llvm.h

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Tom Stellard <thomas.stellard@amd.com>
  24  *
  25  */
  26
  27 #ifndef RADEON_LLVM_H
  28 #define RADEON_LLVM_H
  29
  30 #include <llvm-c/Core.h>
  31 #include "gallivm/lp_bld_init.h"
  32 #include "gallivm/lp_bld_tgsi.h"
  33
  34 #define RADEON_LLVM_MAX_INPUTS 16 * 4
  35 #define RADEON_LLVM_MAX_OUTPUTS 16 * 4
  36 #define RADEON_LLVM_MAX_BRANCH_DEPTH 16
  37 #define RADEON_LLVM_MAX_LOOP_DEPTH 16
  38
  39 #define RADEON_LLVM_MAX_SYSTEM_VALUES 4
  40
  41 struct radeon_llvm_branch {
  42         LLVMBasicBlockRef endif_block;
  43         LLVMBasicBlockRef if_block;
  44         LLVMBasicBlockRef else_block;
  45         unsigned has_else;
  46 };
  47
  48 struct radeon_llvm_loop {
  49         LLVMBasicBlockRef loop_block;
  50         LLVMBasicBlockRef endloop_block;
  51 };
  52
  53 struct radeon_llvm_context {
  54
  55         struct lp_build_tgsi_soa_context soa;
  56
  57         unsigned chip_class;
  58         unsigned type;
  59         unsigned face_input;
  60         unsigned two_side;
  61         unsigned clip_vertex;
  62         struct r600_shader_io * r600_inputs;
  63         struct r600_shader_io * r600_outputs;
  64         struct pipe_stream_output_info *stream_outputs;
  65         unsigned color_buffer_count;
  66         unsigned fs_color_all;
  67
  68         /*=== Front end configuration ===*/
  69
  70         /* Special Intrinsics */
  71
  72         /** Write to an output register: float store_output(float, i32) */
  73         const char * store_output_intr;
  74
  75         /** Swizzle a vector value: <4 x float> swizzle(<4 x float>, i32)
  76          * The swizzle is an unsigned integer that encodes a TGSI_SWIZZLE_* value
  77          * in 2-bits.
  78          * Swizzle{0-1} = X Channel
  79          * Swizzle{2-3} = Y Channel
  80          * Swizzle{4-5} = Z Channel
  81          * Swizzle{6-7} = W Channel
  82          */
  83         const char * swizzle_intr;
  84
  85         /* Instructions that are not described by any of the TGSI opcodes. */
  86
  87         /** This function is responsible for initilizing the inputs array and will be
  88           * called once for each input declared in the TGSI shader.
  89           */
  90         void (*load_input)(struct radeon_llvm_context *,
  91                         unsigned input_index,
  92                         const struct tgsi_full_declaration *decl);
  93
  94         void (*load_system_value)(struct radeon_llvm_context *,
  95                         unsigned index,
  96                         const struct tgsi_full_declaration *decl);
  97
  98         /** User data to use with the callbacks */
  99         void * userdata;
 100
 101         /** This array contains the input values for the shader.  Typically these
 102           * values will be in the form of a target intrinsic that will inform the
 103           * backend how to load the actual inputs to the shader.
 104           */
 105         LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
 106         LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
 107         unsigned output_reg_count;
 108
 109         LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
 110
 111         unsigned reserved_reg_count;
 112         /*=== Private Members ===*/
 113
 114         struct radeon_llvm_branch branch[RADEON_LLVM_MAX_BRANCH_DEPTH];
 115         struct radeon_llvm_loop loop[RADEON_LLVM_MAX_LOOP_DEPTH];
 116
 117         unsigned branch_depth;
 118         unsigned loop_depth;
 119
 120
 121         LLVMValueRef main_fn;
 122
 123         struct gallivm_state gallivm;
 124 };
 125
 126 static inline LLVMValueRef bitcast(
 127                 struct lp_build_tgsi_context * bld_base,
 128                 enum tgsi_opcode_type type,
 129                 LLVMValueRef value
 130 )
 131 {
 132         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 133         LLVMContextRef ctx = bld_base->base.gallivm->context;
 134         LLVMTypeRef dst_type;
 135
 136         switch (type) {
 137         case TGSI_TYPE_UNSIGNED:
 138         case TGSI_TYPE_SIGNED:
 139                 dst_type = LLVMInt32TypeInContext(ctx);
 140                 break;
 141         case TGSI_TYPE_UNTYPED:
 142         case TGSI_TYPE_FLOAT:
 143                 dst_type = LLVMFloatTypeInContext(ctx);
 144                 break;
 145         default:
 146                 dst_type = 0;
 147                 break;
 148         }
 149
 150         if (dst_type)
 151                 return LLVMBuildBitCast(builder, value, dst_type, "");
 152         else
 153                 return value;
 154 }
 155
 156
 157 void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base,
 158                                           struct lp_build_emit_data * emit_data,
 159                                           unsigned coord_arg);
 160
 161 void radeon_llvm_context_init(struct radeon_llvm_context * ctx);
 162
 163 void radeon_llvm_dispose(struct radeon_llvm_context * ctx);
 164
 165 inline static struct radeon_llvm_context * radeon_llvm_context(
 166         struct lp_build_tgsi_context * bld_base)
 167 {
 168         return (struct radeon_llvm_context*)bld_base;
 169 }
 170
 171 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan);
 172
 173 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx);
 174
 175 LLVMValueRef
 176 build_intrinsic(LLVMBuilderRef builder,
 177                 const char *name,
 178                 LLVMTypeRef ret_type,
 179                 LLVMValueRef *args,
 180                 unsigned num_args,
 181                 LLVMAttribute attr);
 182
 183 void
 184 build_tgsi_intrinsic_nomem(
 185                 const struct lp_build_tgsi_action * action,
 186                 struct lp_build_tgsi_context * bld_base,
 187                 struct lp_build_emit_data * emit_data);
 188
 189
 190
 191 #endif /* RADEON_LLVM_H */