2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
30 #include <llvm-c/Core.h>
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_tgsi.h"
34 #define RADEON_LLVM_MAX_INPUTS 32 * 4
35 #define RADEON_LLVM_MAX_OUTPUTS 32 * 4
36 #define RADEON_LLVM_MAX_BRANCH_DEPTH 16
37 #define RADEON_LLVM_MAX_LOOP_DEPTH 16
38 #define RADEON_LLVM_MAX_ARRAYS 16
40 #define RADEON_LLVM_MAX_SYSTEM_VALUES 4
42 struct radeon_llvm_branch
{
43 LLVMBasicBlockRef endif_block
;
44 LLVMBasicBlockRef if_block
;
45 LLVMBasicBlockRef else_block
;
49 struct radeon_llvm_loop
{
50 LLVMBasicBlockRef loop_block
;
51 LLVMBasicBlockRef endloop_block
;
54 struct radeon_llvm_context
{
56 struct lp_build_tgsi_soa_context soa
;
63 struct r600_shader_io
* r600_inputs
;
64 struct r600_shader_io
* r600_outputs
;
65 struct pipe_stream_output_info
*stream_outputs
;
66 unsigned color_buffer_count
;
67 unsigned fs_color_all
;
68 unsigned alpha_to_one
;
69 unsigned has_txq_cube_array_z_comp
;
70 unsigned uses_tex_buffers
;
72 /*=== Front end configuration ===*/
74 /* Special Intrinsics */
76 /** Write to an output register: float store_output(float, i32) */
77 const char * store_output_intr
;
79 /** Swizzle a vector value: <4 x float> swizzle(<4 x float>, i32)
80 * The swizzle is an unsigned integer that encodes a TGSI_SWIZZLE_* value
82 * Swizzle{0-1} = X Channel
83 * Swizzle{2-3} = Y Channel
84 * Swizzle{4-5} = Z Channel
85 * Swizzle{6-7} = W Channel
87 const char * swizzle_intr
;
89 /* Instructions that are not described by any of the TGSI opcodes. */
91 /** This function is responsible for initilizing the inputs array and will be
92 * called once for each input declared in the TGSI shader.
94 void (*load_input
)(struct radeon_llvm_context
*,
96 const struct tgsi_full_declaration
*decl
);
98 void (*load_system_value
)(struct radeon_llvm_context
*,
100 const struct tgsi_full_declaration
*decl
);
102 /** User data to use with the callbacks */
105 /** This array contains the input values for the shader. Typically these
106 * values will be in the form of a target intrinsic that will inform the
107 * backend how to load the actual inputs to the shader.
109 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
];
110 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
][TGSI_NUM_CHANNELS
];
111 unsigned output_reg_count
;
113 LLVMValueRef system_values
[RADEON_LLVM_MAX_SYSTEM_VALUES
];
115 /*=== Private Members ===*/
117 struct radeon_llvm_branch branch
[RADEON_LLVM_MAX_BRANCH_DEPTH
];
118 struct radeon_llvm_loop loop
[RADEON_LLVM_MAX_LOOP_DEPTH
];
120 unsigned branch_depth
;
123 struct tgsi_declaration_range arrays
[RADEON_LLVM_MAX_ARRAYS
];
126 LLVMValueRef main_fn
;
128 struct gallivm_state gallivm
;
131 static inline LLVMTypeRef
tgsi2llvmtype(
132 struct lp_build_tgsi_context
* bld_base
,
133 enum tgsi_opcode_type type
)
135 LLVMContextRef ctx
= bld_base
->base
.gallivm
->context
;
138 case TGSI_TYPE_UNSIGNED
:
139 case TGSI_TYPE_SIGNED
:
140 return LLVMInt32TypeInContext(ctx
);
141 case TGSI_TYPE_UNTYPED
:
142 case TGSI_TYPE_FLOAT
:
143 return LLVMFloatTypeInContext(ctx
);
149 static inline LLVMValueRef
bitcast(
150 struct lp_build_tgsi_context
* bld_base
,
151 enum tgsi_opcode_type type
,
155 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
156 LLVMTypeRef dst_type
= tgsi2llvmtype(bld_base
, type
);
159 return LLVMBuildBitCast(builder
, value
, dst_type
, "");
165 void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context
* bld_base
,
166 struct lp_build_emit_data
* emit_data
,
167 LLVMValueRef
*coords_arg
);
169 void radeon_llvm_context_init(struct radeon_llvm_context
* ctx
);
171 void radeon_llvm_create_func(struct radeon_llvm_context
* ctx
,
172 LLVMTypeRef
*ParamTypes
, unsigned ParamCount
);
174 void radeon_llvm_dispose(struct radeon_llvm_context
* ctx
);
176 inline static struct radeon_llvm_context
* radeon_llvm_context(
177 struct lp_build_tgsi_context
* bld_base
)
179 return (struct radeon_llvm_context
*)bld_base
;
182 unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
);
184 void radeon_llvm_finalize_module(struct radeon_llvm_context
* ctx
);
187 build_intrinsic(LLVMBuilderRef builder
,
189 LLVMTypeRef ret_type
,
195 build_tgsi_intrinsic_nomem(
196 const struct lp_build_tgsi_action
* action
,
197 struct lp_build_tgsi_context
* bld_base
,
198 struct lp_build_emit_data
* emit_data
);
202 #endif /* RADEON_LLVM_H */