src/gallium/drivers/radeon/radeon_llvm.h

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Tom Stellard <thomas.stellard@amd.com>
  24  *
  25  */
  26
  27 #ifndef RADEON_LLVM_H
  28 #define RADEON_LLVM_H
  29
  30 #include <llvm-c/Core.h>
  31 #include "gallivm/lp_bld_init.h"
  32 #include "gallivm/lp_bld_tgsi.h"
  33
  34 #define RADEON_LLVM_MAX_INPUTS 32 * 4
  35 #define RADEON_LLVM_MAX_OUTPUTS 32 * 4
  36
  37 #define RADEON_LLVM_INITIAL_CF_DEPTH 4
  38
  39 #define RADEON_LLVM_MAX_SYSTEM_VALUES 4
  40
  41 struct radeon_llvm_branch {
  42         LLVMBasicBlockRef endif_block;
  43         LLVMBasicBlockRef if_block;
  44         LLVMBasicBlockRef else_block;
  45         unsigned has_else;
  46 };
  47
  48 struct radeon_llvm_loop {
  49         LLVMBasicBlockRef loop_block;
  50         LLVMBasicBlockRef endloop_block;
  51 };
  52
  53 struct radeon_llvm_context {
  54
  55         struct lp_build_tgsi_soa_context soa;
  56
  57         unsigned chip_class;
  58         unsigned type;
  59         unsigned face_gpr;
  60         unsigned two_side;
  61         unsigned clip_vertex;
  62         unsigned inputs_count;
  63         struct r600_shader_io * r600_inputs;
  64         struct r600_shader_io * r600_outputs;
  65         struct pipe_stream_output_info *stream_outputs;
  66         unsigned color_buffer_count;
  67         unsigned fs_color_all;
  68         unsigned alpha_to_one;
  69         unsigned has_txq_cube_array_z_comp;
  70         unsigned uses_tex_buffers;
  71         unsigned has_compressed_msaa_texturing;
  72
  73         /*=== Front end configuration ===*/
  74
  75         /* Special Intrinsics */
  76
  77         /** Write to an output register: float store_output(float, i32) */
  78         const char * store_output_intr;
  79
  80         /** Swizzle a vector value: <4 x float> swizzle(<4 x float>, i32)
  81          * The swizzle is an unsigned integer that encodes a TGSI_SWIZZLE_* value
  82          * in 2-bits.
  83          * Swizzle{0-1} = X Channel
  84          * Swizzle{2-3} = Y Channel
  85          * Swizzle{4-5} = Z Channel
  86          * Swizzle{6-7} = W Channel
  87          */
  88         const char * swizzle_intr;
  89
  90         /* Instructions that are not described by any of the TGSI opcodes. */
  91
  92         /** This function is responsible for initilizing the inputs array and will be
  93           * called once for each input declared in the TGSI shader.
  94           */
  95         void (*load_input)(struct radeon_llvm_context *,
  96                         unsigned input_index,
  97                         const struct tgsi_full_declaration *decl);
  98
  99         void (*load_system_value)(struct radeon_llvm_context *,
 100                         unsigned index,
 101                         const struct tgsi_full_declaration *decl);
 102
 103         /** User data to use with the callbacks */
 104         void * userdata;
 105
 106         /** This array contains the input values for the shader.  Typically these
 107           * values will be in the form of a target intrinsic that will inform the
 108           * backend how to load the actual inputs to the shader.
 109           */
 110         LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
 111         LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
 112         unsigned output_reg_count;
 113
 114         /** This pointer is used to contain the temporary values.
 115           * The amount of temporary used in tgsi can't be bound to a max value and
 116           * thus we must allocate this array at runtime.
 117           */
 118         LLVMValueRef *temps;
 119         unsigned temps_count;
 120         LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
 121
 122         /*=== Private Members ===*/
 123
 124         struct radeon_llvm_branch *branch;
 125         struct radeon_llvm_loop *loop;
 126
 127         unsigned branch_depth;
 128         unsigned branch_depth_max;
 129         unsigned loop_depth;
 130         unsigned loop_depth_max;
 131
 132         struct tgsi_declaration_range *arrays;
 133
 134         LLVMValueRef main_fn;
 135
 136         struct gallivm_state gallivm;
 137 };
 138
 139 static inline LLVMTypeRef tgsi2llvmtype(
 140                 struct lp_build_tgsi_context * bld_base,
 141                 enum tgsi_opcode_type type)
 142 {
 143         LLVMContextRef ctx = bld_base->base.gallivm->context;
 144
 145         switch (type) {
 146         case TGSI_TYPE_UNSIGNED:
 147         case TGSI_TYPE_SIGNED:
 148                 return LLVMInt32TypeInContext(ctx);
 149         case TGSI_TYPE_DOUBLE:
 150                 return LLVMDoubleTypeInContext(ctx);
 151         case TGSI_TYPE_UNTYPED:
 152         case TGSI_TYPE_FLOAT:
 153                 return LLVMFloatTypeInContext(ctx);
 154         default: break;
 155         }
 156         return 0;
 157 }
 158
 159 static inline LLVMValueRef bitcast(
 160                 struct lp_build_tgsi_context * bld_base,
 161                 enum tgsi_opcode_type type,
 162                 LLVMValueRef value
 163 )
 164 {
 165         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 166         LLVMTypeRef dst_type = tgsi2llvmtype(bld_base, type);
 167
 168         if (dst_type)
 169                 return LLVMBuildBitCast(builder, value, dst_type, "");
 170         else
 171                 return value;
 172 }
 173
 174
 175 void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base,
 176                                           struct lp_build_emit_data * emit_data,
 177                                           LLVMValueRef *coords_arg);
 178
 179 void radeon_llvm_context_init(struct radeon_llvm_context * ctx);
 180
 181 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
 182                              LLVMTypeRef *ParamTypes, unsigned ParamCount);
 183
 184 void radeon_llvm_dispose(struct radeon_llvm_context * ctx);
 185
 186 inline static struct radeon_llvm_context * radeon_llvm_context(
 187         struct lp_build_tgsi_context * bld_base)
 188 {
 189         return (struct radeon_llvm_context*)bld_base;
 190 }
 191
 192 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan);
 193
 194 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx);
 195
 196 LLVMValueRef
 197 build_intrinsic(LLVMBuilderRef builder,
 198                 const char *name,
 199                 LLVMTypeRef ret_type,
 200                 LLVMValueRef *args,
 201                 unsigned num_args,
 202                 LLVMAttribute attr);
 203
 204 void
 205 build_tgsi_intrinsic_nomem(
 206                 const struct lp_build_tgsi_action * action,
 207                 struct lp_build_tgsi_context * bld_base,
 208                 struct lp_build_emit_data * emit_data);
 209
 210 LLVMValueRef
 211 radeon_llvm_emit_fetch_double(struct lp_build_tgsi_context *bld_base,
 212                               LLVMValueRef ptr,
 213                               LLVMValueRef ptr2);
 214
 215 LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base,
 216                                   LLVMValueRef value);
 217
 218 LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
 219                                     const struct tgsi_full_src_register *reg,
 220                                     enum tgsi_opcode_type type,
 221                                     unsigned swizzle);
 222
 223 void radeon_llvm_emit_store(
 224         struct lp_build_tgsi_context * bld_base,
 225         const struct tgsi_full_instruction * inst,
 226         const struct tgsi_opcode_info * info,
 227         LLVMValueRef dst[4]);
 228
 229 #endif /* RADEON_LLVM_H */