src/gallium/drivers/radeon/radeon_llvm.h

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Tom Stellard <thomas.stellard@amd.com>
  24  *
  25  */
  26
  27 #ifndef RADEON_LLVM_H
  28 #define RADEON_LLVM_H
  29
  30 #include <llvm-c/Core.h>
  31 #include "gallivm/lp_bld_init.h"
  32 #include "gallivm/lp_bld_tgsi.h"
  33
  34 #define RADEON_LLVM_MAX_INPUTS 32 * 4
  35 #define RADEON_LLVM_MAX_OUTPUTS 32 * 4
  36 #define RADEON_LLVM_MAX_BRANCH_DEPTH 16
  37 #define RADEON_LLVM_MAX_LOOP_DEPTH 16
  38 #define RADEON_LLVM_MAX_ARRAYS 16
  39
  40 #define RADEON_LLVM_MAX_SYSTEM_VALUES 4
  41
  42 struct radeon_llvm_branch {
  43         LLVMBasicBlockRef endif_block;
  44         LLVMBasicBlockRef if_block;
  45         LLVMBasicBlockRef else_block;
  46         unsigned has_else;
  47 };
  48
  49 struct radeon_llvm_loop {
  50         LLVMBasicBlockRef loop_block;
  51         LLVMBasicBlockRef endloop_block;
  52 };
  53
  54 struct radeon_llvm_context {
  55
  56         struct lp_build_tgsi_soa_context soa;
  57
  58         unsigned chip_class;
  59         unsigned type;
  60         unsigned face_gpr;
  61         unsigned two_side;
  62         unsigned clip_vertex;
  63         struct r600_shader_io * r600_inputs;
  64         struct r600_shader_io * r600_outputs;
  65         struct pipe_stream_output_info *stream_outputs;
  66         unsigned color_buffer_count;
  67         unsigned fs_color_all;
  68         unsigned alpha_to_one;
  69         unsigned has_txq_cube_array_z_comp;
  70         unsigned uses_tex_buffers;
  71         unsigned has_compressed_msaa_texturing;
  72
  73         /*=== Front end configuration ===*/
  74
  75         /* Special Intrinsics */
  76
  77         /** Write to an output register: float store_output(float, i32) */
  78         const char * store_output_intr;
  79
  80         /** Swizzle a vector value: <4 x float> swizzle(<4 x float>, i32)
  81          * The swizzle is an unsigned integer that encodes a TGSI_SWIZZLE_* value
  82          * in 2-bits.
  83          * Swizzle{0-1} = X Channel
  84          * Swizzle{2-3} = Y Channel
  85          * Swizzle{4-5} = Z Channel
  86          * Swizzle{6-7} = W Channel
  87          */
  88         const char * swizzle_intr;
  89
  90         /* Instructions that are not described by any of the TGSI opcodes. */
  91
  92         /** This function is responsible for initilizing the inputs array and will be
  93           * called once for each input declared in the TGSI shader.
  94           */
  95         void (*load_input)(struct radeon_llvm_context *,
  96                         unsigned input_index,
  97                         const struct tgsi_full_declaration *decl);
  98
  99         void (*load_system_value)(struct radeon_llvm_context *,
 100                         unsigned index,
 101                         const struct tgsi_full_declaration *decl);
 102
 103         /** User data to use with the callbacks */
 104         void * userdata;
 105
 106         /** This array contains the input values for the shader.  Typically these
 107           * values will be in the form of a target intrinsic that will inform the
 108           * backend how to load the actual inputs to the shader.
 109           */
 110         LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
 111         LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
 112         unsigned output_reg_count;
 113
 114         LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
 115
 116         /*=== Private Members ===*/
 117
 118         struct radeon_llvm_branch branch[RADEON_LLVM_MAX_BRANCH_DEPTH];
 119         struct radeon_llvm_loop loop[RADEON_LLVM_MAX_LOOP_DEPTH];
 120
 121         unsigned branch_depth;
 122         unsigned loop_depth;
 123
 124         struct tgsi_declaration_range arrays[RADEON_LLVM_MAX_ARRAYS];
 125         unsigned num_arrays;
 126
 127         LLVMValueRef main_fn;
 128
 129         struct gallivm_state gallivm;
 130 };
 131
 132 static inline LLVMTypeRef tgsi2llvmtype(
 133                 struct lp_build_tgsi_context * bld_base,
 134                 enum tgsi_opcode_type type)
 135 {
 136         LLVMContextRef ctx = bld_base->base.gallivm->context;
 137
 138         switch (type) {
 139         case TGSI_TYPE_UNSIGNED:
 140         case TGSI_TYPE_SIGNED:
 141                 return LLVMInt32TypeInContext(ctx);
 142         case TGSI_TYPE_UNTYPED:
 143         case TGSI_TYPE_FLOAT:
 144                 return LLVMFloatTypeInContext(ctx);
 145         default: break;
 146         }
 147         return 0;
 148 }
 149
 150 static inline LLVMValueRef bitcast(
 151                 struct lp_build_tgsi_context * bld_base,
 152                 enum tgsi_opcode_type type,
 153                 LLVMValueRef value
 154 )
 155 {
 156         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 157         LLVMTypeRef dst_type = tgsi2llvmtype(bld_base, type);
 158
 159         if (dst_type)
 160                 return LLVMBuildBitCast(builder, value, dst_type, "");
 161         else
 162                 return value;
 163 }
 164
 165
 166 void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base,
 167                                           struct lp_build_emit_data * emit_data,
 168                                           LLVMValueRef *coords_arg);
 169
 170 void radeon_llvm_context_init(struct radeon_llvm_context * ctx);
 171
 172 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
 173                              LLVMTypeRef *ParamTypes, unsigned ParamCount);
 174
 175 void radeon_llvm_dispose(struct radeon_llvm_context * ctx);
 176
 177 inline static struct radeon_llvm_context * radeon_llvm_context(
 178         struct lp_build_tgsi_context * bld_base)
 179 {
 180         return (struct radeon_llvm_context*)bld_base;
 181 }
 182
 183 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan);
 184
 185 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx);
 186
 187 LLVMValueRef
 188 build_intrinsic(LLVMBuilderRef builder,
 189                 const char *name,
 190                 LLVMTypeRef ret_type,
 191                 LLVMValueRef *args,
 192                 unsigned num_args,
 193                 LLVMAttribute attr);
 194
 195 void
 196 build_tgsi_intrinsic_nomem(
 197                 const struct lp_build_tgsi_action * action,
 198                 struct lp_build_tgsi_context * bld_base,
 199                 struct lp_build_emit_data * emit_data);
 200
 201
 202
 203 #endif /* RADEON_LLVM_H */