2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
26 #include "radeon_llvm.h"
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
43 static struct radeon_llvm_loop
* get_current_loop(struct radeon_llvm_context
* ctx
)
45 return ctx
->loop_depth
> 0 ? ctx
->loop
+ (ctx
->loop_depth
- 1) : NULL
;
48 static struct radeon_llvm_branch
* get_current_branch(
49 struct radeon_llvm_context
* ctx
)
51 return ctx
->branch_depth
> 0 ?
52 ctx
->branch
+ (ctx
->branch_depth
- 1) : NULL
;
55 unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
57 return (index
* 4) + chan
;
60 static LLVMValueRef
emit_swizzle(
61 struct lp_build_tgsi_context
* bld_base
,
68 LLVMValueRef swizzles
[4];
70 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
);
72 swizzles
[0] = LLVMConstInt(i32t
, swizzle_x
, 0);
73 swizzles
[1] = LLVMConstInt(i32t
, swizzle_y
, 0);
74 swizzles
[2] = LLVMConstInt(i32t
, swizzle_z
, 0);
75 swizzles
[3] = LLVMConstInt(i32t
, swizzle_w
, 0);
77 return LLVMBuildShuffleVector(bld_base
->base
.gallivm
->builder
,
79 LLVMGetUndef(LLVMTypeOf(value
)),
80 LLVMConstVector(swizzles
, 4), "");
83 static struct tgsi_declaration_range
84 get_array_range(struct lp_build_tgsi_context
*bld_base
,
85 unsigned File
, const struct tgsi_ind_register
*reg
)
87 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
88 if (File
!= TGSI_FILE_TEMPORARY
|| reg
->ArrayID
== 0 ||
89 reg
->ArrayID
> RADEON_LLVM_MAX_ARRAYS
) {
90 struct tgsi_declaration_range range
;
92 range
.Last
= bld_base
->info
->file_max
[File
];
96 return ctx
->arrays
[reg
->ArrayID
- 1];
101 struct lp_build_tgsi_soa_context
*bld
,
102 const struct tgsi_ind_register
*reg
,
105 struct gallivm_state
* gallivm
= bld
->bld_base
.base
.gallivm
;
107 LLVMValueRef addr
= LLVMBuildLoad(gallivm
->builder
, bld
->addr
[reg
->Index
][reg
->Swizzle
], "");
108 return LLVMBuildAdd(gallivm
->builder
, addr
, lp_build_const_int32(gallivm
, offset
), "");
113 struct lp_build_tgsi_context
*bld_base
,
114 const struct tgsi_full_src_register
*reg
,
115 enum tgsi_opcode_type type
,
120 struct lp_build_tgsi_context
*bld_base
,
121 unsigned File
, enum tgsi_opcode_type type
,
122 struct tgsi_declaration_range range
,
125 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
126 struct gallivm_state
* gallivm
= bld
->bld_base
.base
.gallivm
;
127 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
129 unsigned i
, size
= range
.Last
- range
.First
+ 1;
130 LLVMTypeRef vec
= LLVMVectorType(tgsi2llvmtype(bld_base
, type
), size
);
131 LLVMValueRef result
= LLVMGetUndef(vec
);
133 struct tgsi_full_src_register tmp_reg
= {};
134 tmp_reg
.Register
.File
= File
;
136 for (i
= 0; i
< size
; ++i
) {
137 tmp_reg
.Register
.Index
= i
+ range
.First
;
138 LLVMValueRef temp
= emit_fetch(bld_base
, &tmp_reg
, type
, swizzle
);
139 result
= LLVMBuildInsertElement(builder
, result
, temp
,
140 lp_build_const_int32(gallivm
, i
), "");
145 static bool uses_temp_indirect_addressing(
146 struct lp_build_tgsi_context
*bld_base
)
148 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
149 return (bld
->indirect_files
& (1 << TGSI_FILE_TEMPORARY
));
154 struct lp_build_tgsi_context
*bld_base
,
155 const struct tgsi_full_src_register
*reg
,
156 enum tgsi_opcode_type type
,
159 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
160 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
161 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
162 LLVMValueRef result
= NULL
, ptr
;
165 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
167 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
168 values
[chan
] = emit_fetch(bld_base
, reg
, type
, chan
);
170 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
174 if (reg
->Register
.Indirect
) {
175 struct tgsi_declaration_range range
= get_array_range(bld_base
,
176 reg
->Register
.File
, ®
->Indirect
);
177 return LLVMBuildExtractElement(builder
,
178 emit_array_fetch(bld_base
, reg
->Register
.File
, type
, range
, swizzle
),
179 emit_array_index(bld
, ®
->Indirect
, reg
->Register
.Index
- range
.First
),
183 switch(reg
->Register
.File
) {
184 case TGSI_FILE_IMMEDIATE
: {
185 LLVMTypeRef ctype
= tgsi2llvmtype(bld_base
, type
);
186 return LLVMConstBitCast(bld
->immediates
[reg
->Register
.Index
][swizzle
], ctype
);
189 case TGSI_FILE_INPUT
:
190 result
= ctx
->inputs
[radeon_llvm_reg_index_soa(reg
->Register
.Index
, swizzle
)];
193 case TGSI_FILE_TEMPORARY
:
194 if (uses_temp_indirect_addressing(bld_base
)) {
195 ptr
= lp_get_temp_ptr_soa(bld
, reg
->Register
.Index
, swizzle
);
198 ptr
= ctx
->temps
[reg
->Register
.Index
* TGSI_NUM_CHANNELS
+ swizzle
];
199 result
= LLVMBuildLoad(builder
, ptr
, "");
202 case TGSI_FILE_OUTPUT
:
203 ptr
= lp_get_output_ptr(bld
, reg
->Register
.Index
, swizzle
);
204 result
= LLVMBuildLoad(builder
, ptr
, "");
208 return LLVMGetUndef(tgsi2llvmtype(bld_base
, type
));
211 return bitcast(bld_base
, type
, result
);
214 static LLVMValueRef
fetch_system_value(
215 struct lp_build_tgsi_context
* bld_base
,
216 const struct tgsi_full_src_register
*reg
,
217 enum tgsi_opcode_type type
,
220 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
221 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
223 LLVMValueRef cval
= ctx
->system_values
[reg
->Register
.Index
];
224 if (LLVMGetTypeKind(LLVMTypeOf(cval
)) == LLVMVectorTypeKind
) {
225 cval
= LLVMBuildExtractElement(gallivm
->builder
, cval
,
226 lp_build_const_int32(gallivm
, swizzle
), "");
228 return bitcast(bld_base
, type
, cval
);
231 static void emit_declaration(
232 struct lp_build_tgsi_context
* bld_base
,
233 const struct tgsi_full_declaration
*decl
)
235 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
236 unsigned first
, last
, i
, idx
;
237 switch(decl
->Declaration
.File
) {
238 case TGSI_FILE_ADDRESS
:
241 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
243 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
244 ctx
->soa
.addr
[idx
][chan
] = lp_build_alloca(
246 ctx
->soa
.bld_base
.uint_bld
.elem_type
, "");
252 case TGSI_FILE_TEMPORARY
:
253 if (decl
->Declaration
.Array
&& decl
->Array
.ArrayID
<= RADEON_LLVM_MAX_ARRAYS
)
254 ctx
->arrays
[decl
->Array
.ArrayID
- 1] = decl
->Range
;
255 if (uses_temp_indirect_addressing(bld_base
)) {
256 lp_emit_declaration_soa(bld_base
, decl
);
259 first
= decl
->Range
.First
;
260 last
= decl
->Range
.Last
;
261 if (!ctx
->temps_count
) {
262 ctx
->temps_count
= bld_base
->info
->file_max
[TGSI_FILE_TEMPORARY
] + 1;
263 ctx
->temps
= MALLOC(TGSI_NUM_CHANNELS
* ctx
->temps_count
* sizeof(LLVMValueRef
));
265 for (idx
= first
; idx
<= last
; idx
++) {
266 for (i
= 0; i
< TGSI_NUM_CHANNELS
; i
++) {
267 ctx
->temps
[idx
* TGSI_NUM_CHANNELS
+ i
] =
268 lp_build_alloca(bld_base
->base
.gallivm
, bld_base
->base
.vec_type
,
274 case TGSI_FILE_INPUT
:
277 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
279 ctx
->load_input(ctx
, idx
, decl
);
284 case TGSI_FILE_SYSTEM_VALUE
:
287 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
288 ctx
->load_system_value(ctx
, idx
, decl
);
293 case TGSI_FILE_OUTPUT
:
296 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
298 assert(idx
< RADEON_LLVM_MAX_OUTPUTS
);
299 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
300 ctx
->soa
.outputs
[idx
][chan
] = lp_build_alloca(&ctx
->gallivm
,
301 ctx
->soa
.bld_base
.base
.elem_type
, "");
305 ctx
->output_reg_count
= MAX2(ctx
->output_reg_count
,
306 decl
->Range
.Last
+ 1);
317 struct lp_build_tgsi_context
* bld_base
,
318 const struct tgsi_full_instruction
* inst
,
319 const struct tgsi_opcode_info
* info
,
322 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
323 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
324 struct gallivm_state
*gallivm
= bld
->bld_base
.base
.gallivm
;
325 struct lp_build_context base
= bld
->bld_base
.base
;
326 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[0];
327 LLVMBuilderRef builder
= bld
->bld_base
.base
.gallivm
->builder
;
328 LLVMValueRef temp_ptr
;
329 unsigned chan
, chan_index
;
330 boolean is_vec_store
= FALSE
;
333 LLVMTypeKind k
= LLVMGetTypeKind(LLVMTypeOf(dst
[0]));
334 is_vec_store
= (k
== LLVMVectorTypeKind
);
338 LLVMValueRef values
[4] = {};
339 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst
, chan
) {
340 LLVMValueRef index
= lp_build_const_int32(gallivm
, chan
);
341 values
[chan
] = LLVMBuildExtractElement(gallivm
->builder
,
344 bld_base
->emit_store(bld_base
, inst
, info
, values
);
348 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst
, chan_index
) {
349 LLVMValueRef value
= dst
[chan_index
];
351 if (inst
->Instruction
.Saturate
!= TGSI_SAT_NONE
) {
352 struct lp_build_emit_data clamp_emit_data
;
354 memset(&clamp_emit_data
, 0, sizeof(clamp_emit_data
));
355 clamp_emit_data
.arg_count
= 3;
356 clamp_emit_data
.args
[0] = value
;
357 clamp_emit_data
.args
[2] = base
.one
;
359 switch(inst
->Instruction
.Saturate
) {
360 case TGSI_SAT_ZERO_ONE
:
361 clamp_emit_data
.args
[1] = base
.zero
;
363 case TGSI_SAT_MINUS_PLUS_ONE
:
364 clamp_emit_data
.args
[1] = LLVMConstReal(
365 base
.elem_type
, -1.0f
);
370 value
= lp_build_emit_llvm(bld_base
, TGSI_OPCODE_CLAMP
,
374 if (reg
->Register
.File
== TGSI_FILE_ADDRESS
) {
375 temp_ptr
= bld
->addr
[reg
->Register
.Index
][chan_index
];
376 LLVMBuildStore(builder
, value
, temp_ptr
);
380 value
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, value
);
382 if (reg
->Register
.Indirect
) {
383 struct tgsi_declaration_range range
= get_array_range(bld_base
,
384 reg
->Register
.File
, ®
->Indirect
);
386 unsigned i
, size
= range
.Last
- range
.First
+ 1;
387 LLVMValueRef array
= LLVMBuildInsertElement(builder
,
388 emit_array_fetch(bld_base
, reg
->Register
.File
, TGSI_TYPE_FLOAT
, range
, chan_index
),
389 value
, emit_array_index(bld
, ®
->Indirect
, reg
->Register
.Index
- range
.First
), "");
391 for (i
= 0; i
< size
; ++i
) {
392 switch(reg
->Register
.File
) {
393 case TGSI_FILE_OUTPUT
:
394 temp_ptr
= bld
->outputs
[i
+ range
.First
][chan_index
];
397 case TGSI_FILE_TEMPORARY
:
398 if (uses_temp_indirect_addressing(bld_base
))
399 temp_ptr
= lp_get_temp_ptr_soa(bld
, i
+ range
.First
, chan_index
);
401 temp_ptr
= ctx
->temps
[(i
+ range
.First
) * TGSI_NUM_CHANNELS
+ chan_index
];
407 value
= LLVMBuildExtractElement(builder
, array
,
408 lp_build_const_int32(gallivm
, i
), "");
409 LLVMBuildStore(builder
, value
, temp_ptr
);
413 switch(reg
->Register
.File
) {
414 case TGSI_FILE_OUTPUT
:
415 temp_ptr
= bld
->outputs
[reg
->Register
.Index
][chan_index
];
418 case TGSI_FILE_TEMPORARY
:
419 if (uses_temp_indirect_addressing(bld_base
)) {
423 temp_ptr
= ctx
->temps
[ TGSI_NUM_CHANNELS
* reg
->Register
.Index
+ chan_index
];
429 LLVMBuildStore(builder
, value
, temp_ptr
);
434 static void bgnloop_emit(
435 const struct lp_build_tgsi_action
* action
,
436 struct lp_build_tgsi_context
* bld_base
,
437 struct lp_build_emit_data
* emit_data
)
439 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
440 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
441 LLVMBasicBlockRef loop_block
;
442 LLVMBasicBlockRef endloop_block
;
443 endloop_block
= LLVMAppendBasicBlockInContext(gallivm
->context
,
444 ctx
->main_fn
, "ENDLOOP");
445 loop_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
446 endloop_block
, "LOOP");
447 LLVMBuildBr(gallivm
->builder
, loop_block
);
448 LLVMPositionBuilderAtEnd(gallivm
->builder
, loop_block
);
450 ctx
->loop
[ctx
->loop_depth
- 1].loop_block
= loop_block
;
451 ctx
->loop
[ctx
->loop_depth
- 1].endloop_block
= endloop_block
;
454 static void brk_emit(
455 const struct lp_build_tgsi_action
* action
,
456 struct lp_build_tgsi_context
* bld_base
,
457 struct lp_build_emit_data
* emit_data
)
459 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
460 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
461 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
463 LLVMBuildBr(gallivm
->builder
, current_loop
->endloop_block
);
466 static void cont_emit(
467 const struct lp_build_tgsi_action
* action
,
468 struct lp_build_tgsi_context
* bld_base
,
469 struct lp_build_emit_data
* emit_data
)
471 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
472 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
473 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
475 LLVMBuildBr(gallivm
->builder
, current_loop
->loop_block
);
478 static void else_emit(
479 const struct lp_build_tgsi_action
* action
,
480 struct lp_build_tgsi_context
* bld_base
,
481 struct lp_build_emit_data
* emit_data
)
483 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
484 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
485 struct radeon_llvm_branch
* current_branch
= get_current_branch(ctx
);
486 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(gallivm
->builder
);
488 /* We need to add a terminator to the current block if the previous
489 * instruction was an ENDIF.Example:
502 if (current_block
!= current_branch
->if_block
) {
503 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
505 if (!LLVMGetBasicBlockTerminator(current_branch
->if_block
)) {
506 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
508 current_branch
->has_else
= 1;
509 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->else_block
);
512 static void endif_emit(
513 const struct lp_build_tgsi_action
* action
,
514 struct lp_build_tgsi_context
* bld_base
,
515 struct lp_build_emit_data
* emit_data
)
517 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
518 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
519 struct radeon_llvm_branch
* current_branch
= get_current_branch(ctx
);
520 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(gallivm
->builder
);
522 /* If we have consecutive ENDIF instructions, then the first ENDIF
523 * will not have a terminator, so we need to add one. */
524 if (current_block
!= current_branch
->if_block
525 && current_block
!= current_branch
->else_block
526 && !LLVMGetBasicBlockTerminator(current_block
)) {
528 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
530 if (!LLVMGetBasicBlockTerminator(current_branch
->else_block
)) {
531 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->else_block
);
532 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
535 if (!LLVMGetBasicBlockTerminator(current_branch
->if_block
)) {
536 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->if_block
);
537 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
540 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->endif_block
);
544 static void endloop_emit(
545 const struct lp_build_tgsi_action
* action
,
546 struct lp_build_tgsi_context
* bld_base
,
547 struct lp_build_emit_data
* emit_data
)
549 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
550 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
551 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
553 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm
->builder
))) {
554 LLVMBuildBr(gallivm
->builder
, current_loop
->loop_block
);
557 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_loop
->endloop_block
);
561 static void if_cond_emit(
562 const struct lp_build_tgsi_action
* action
,
563 struct lp_build_tgsi_context
* bld_base
,
564 struct lp_build_emit_data
* emit_data
,
567 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
568 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
569 LLVMBasicBlockRef if_block
, else_block
, endif_block
;
571 endif_block
= LLVMAppendBasicBlockInContext(gallivm
->context
,
572 ctx
->main_fn
, "ENDIF");
573 if_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
575 else_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
576 endif_block
, "ELSE");
577 LLVMBuildCondBr(gallivm
->builder
, cond
, if_block
, else_block
);
578 LLVMPositionBuilderAtEnd(gallivm
->builder
, if_block
);
581 ctx
->branch
[ctx
->branch_depth
- 1].endif_block
= endif_block
;
582 ctx
->branch
[ctx
->branch_depth
- 1].if_block
= if_block
;
583 ctx
->branch
[ctx
->branch_depth
- 1].else_block
= else_block
;
584 ctx
->branch
[ctx
->branch_depth
- 1].has_else
= 0;
588 const struct lp_build_tgsi_action
* action
,
589 struct lp_build_tgsi_context
* bld_base
,
590 struct lp_build_emit_data
* emit_data
)
592 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
595 cond
= LLVMBuildFCmp(gallivm
->builder
, LLVMRealUNE
,
597 bld_base
->base
.zero
, "");
599 if_cond_emit(action
, bld_base
, emit_data
, cond
);
602 static void uif_emit(
603 const struct lp_build_tgsi_action
* action
,
604 struct lp_build_tgsi_context
* bld_base
,
605 struct lp_build_emit_data
* emit_data
)
607 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
610 cond
= LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
611 bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, emit_data
->args
[0]),
612 bld_base
->int_bld
.zero
, "");
614 if_cond_emit(action
, bld_base
, emit_data
, cond
);
617 static void kil_emit(
618 const struct lp_build_tgsi_action
* action
,
619 struct lp_build_tgsi_context
* bld_base
,
620 struct lp_build_emit_data
* emit_data
)
623 for (i
= 0; i
< emit_data
->arg_count
; i
++) {
624 emit_data
->output
[i
] = lp_build_intrinsic_unary(
625 bld_base
->base
.gallivm
->builder
,
627 emit_data
->dst_type
, emit_data
->args
[i
]);
631 void radeon_llvm_emit_prepare_cube_coords(
632 struct lp_build_tgsi_context
* bld_base
,
633 struct lp_build_emit_data
* emit_data
,
634 LLVMValueRef
*coords_arg
)
637 unsigned target
= emit_data
->inst
->Texture
.Texture
;
638 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
639 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
640 LLVMBuilderRef builder
= gallivm
->builder
;
641 LLVMTypeRef type
= bld_base
->base
.elem_type
;
642 LLVMValueRef coords
[4];
643 LLVMValueRef mad_args
[3];
645 struct LLVMOpaqueValue
*cube_vec
;
649 cube_vec
= lp_build_gather_values(bld_base
->base
.gallivm
, coords_arg
, 4);
650 v
= build_intrinsic(builder
, "llvm.AMDGPU.cube", LLVMVectorType(type
, 4),
651 &cube_vec
, 1, LLVMReadNoneAttribute
);
653 for (i
= 0; i
< 4; ++i
) {
654 idx
= lp_build_const_int32(gallivm
, i
);
655 coords
[i
] = LLVMBuildExtractElement(builder
, v
, idx
, "");
658 coords
[2] = build_intrinsic(builder
, "fabs",
659 type
, &coords
[2], 1, LLVMReadNoneAttribute
);
660 coords
[2] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_RCP
, coords
[2]);
662 mad_args
[1] = coords
[2];
663 mad_args
[2] = LLVMConstReal(type
, 1.5);
665 mad_args
[0] = coords
[0];
666 coords
[0] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
667 mad_args
[0], mad_args
[1], mad_args
[2]);
669 mad_args
[0] = coords
[1];
670 coords
[1] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
671 mad_args
[0], mad_args
[1], mad_args
[2]);
673 /* apply xyz = yxw swizzle to cooords */
674 coords
[2] = coords
[3];
675 coords
[3] = coords
[1];
676 coords
[1] = coords
[0];
677 coords
[0] = coords
[3];
679 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
680 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
681 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
682 /* coords_arg.w component - array_index for cube arrays */
683 coords
[2] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
684 coords_arg
[3], lp_build_const_float(gallivm
, 8.0), coords
[2]);
687 /* Preserve compare/lod/bias. Put it in coords.w. */
688 if (opcode
== TGSI_OPCODE_TEX2
||
689 opcode
== TGSI_OPCODE_TXB2
||
690 opcode
== TGSI_OPCODE_TXL2
) {
691 coords
[3] = coords_arg
[4];
692 } else if (opcode
== TGSI_OPCODE_TXB
||
693 opcode
== TGSI_OPCODE_TXL
||
694 target
== TGSI_TEXTURE_SHADOWCUBE
) {
695 coords
[3] = coords_arg
[3];
698 memcpy(coords_arg
, coords
, sizeof(coords
));
701 static void txd_fetch_args(
702 struct lp_build_tgsi_context
* bld_base
,
703 struct lp_build_emit_data
* emit_data
)
705 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
707 LLVMValueRef coords
[4];
709 for (src
= 0; src
< 3; src
++) {
710 for (chan
= 0; chan
< 4; chan
++)
711 coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
713 emit_data
->args
[src
] = lp_build_gather_values(bld_base
->base
.gallivm
,
716 emit_data
->arg_count
= 3;
717 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
721 static void txp_fetch_args(
722 struct lp_build_tgsi_context
* bld_base
,
723 struct lp_build_emit_data
* emit_data
)
725 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
728 LLVMValueRef coords
[4];
730 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
731 src_w
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
733 for (chan
= 0; chan
< 3; chan
++ ) {
734 LLVMValueRef arg
= lp_build_emit_fetch(bld_base
,
735 emit_data
->inst
, 0, chan
);
736 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
737 TGSI_OPCODE_DIV
, arg
, src_w
);
739 coords
[3] = bld_base
->base
.one
;
741 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
742 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
743 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
744 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
745 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
746 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
747 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
);
750 emit_data
->args
[0] = lp_build_gather_values(bld_base
->base
.gallivm
,
752 emit_data
->arg_count
= 1;
755 static void tex_fetch_args(
756 struct lp_build_tgsi_context
* bld_base
,
757 struct lp_build_emit_data
* emit_data
)
759 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
760 * when we used CHAN_ALL. We should be able to get this to work,
761 * but for now we will swizzle it ourselves
762 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
767 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
769 LLVMValueRef coords
[5];
771 for (chan
= 0; chan
< 4; chan
++) {
772 coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 0, chan
);
775 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
776 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
777 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
778 /* These instructions have additional operand that should be packed
779 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
780 * That operand should be passed as a float value in the args array
781 * right after the coord vector. After packing it's not used anymore,
782 * that's why arg_count is not increased */
783 coords
[4] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
786 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
787 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
788 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
789 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
790 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
791 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
792 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
);
795 emit_data
->arg_count
= 1;
796 emit_data
->args
[0] = lp_build_gather_values(bld_base
->base
.gallivm
,
798 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
801 static void txf_fetch_args(
802 struct lp_build_tgsi_context
* bld_base
,
803 struct lp_build_emit_data
* emit_data
)
805 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
806 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
807 const struct tgsi_texture_offset
* off
= inst
->TexOffsets
;
808 LLVMTypeRef offset_type
= bld_base
->int_bld
.elem_type
;
810 /* fetch tex coords */
811 tex_fetch_args(bld_base
, emit_data
);
813 /* fetch tex offsets */
814 if (inst
->Texture
.NumOffsets
) {
815 assert(inst
->Texture
.NumOffsets
== 1);
817 emit_data
->args
[1] = LLVMConstBitCast(
818 bld
->immediates
[off
->Index
][off
->SwizzleX
],
820 emit_data
->args
[2] = LLVMConstBitCast(
821 bld
->immediates
[off
->Index
][off
->SwizzleY
],
823 emit_data
->args
[3] = LLVMConstBitCast(
824 bld
->immediates
[off
->Index
][off
->SwizzleZ
],
827 emit_data
->args
[1] = bld_base
->int_bld
.zero
;
828 emit_data
->args
[2] = bld_base
->int_bld
.zero
;
829 emit_data
->args
[3] = bld_base
->int_bld
.zero
;
832 emit_data
->arg_count
= 4;
835 static void emit_icmp(
836 const struct lp_build_tgsi_action
* action
,
837 struct lp_build_tgsi_context
* bld_base
,
838 struct lp_build_emit_data
* emit_data
)
841 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
842 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
844 switch (emit_data
->inst
->Instruction
.Opcode
) {
845 case TGSI_OPCODE_USEQ
: pred
= LLVMIntEQ
; break;
846 case TGSI_OPCODE_USNE
: pred
= LLVMIntNE
; break;
847 case TGSI_OPCODE_USGE
: pred
= LLVMIntUGE
; break;
848 case TGSI_OPCODE_USLT
: pred
= LLVMIntULT
; break;
849 case TGSI_OPCODE_ISGE
: pred
= LLVMIntSGE
; break;
850 case TGSI_OPCODE_ISLT
: pred
= LLVMIntSLT
; break;
852 assert(!"unknown instruction");
857 LLVMValueRef v
= LLVMBuildICmp(builder
, pred
,
858 emit_data
->args
[0], emit_data
->args
[1],"");
860 v
= LLVMBuildSExtOrBitCast(builder
, v
,
861 LLVMInt32TypeInContext(context
), "");
863 emit_data
->output
[emit_data
->chan
] = v
;
866 static void emit_ucmp(
867 const struct lp_build_tgsi_action
* action
,
868 struct lp_build_tgsi_context
* bld_base
,
869 struct lp_build_emit_data
* emit_data
)
871 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
873 LLVMValueRef arg0
= LLVMBuildBitCast(builder
, emit_data
->args
[0],
874 bld_base
->uint_bld
.elem_type
, "");
876 LLVMValueRef v
= LLVMBuildICmp(builder
, LLVMIntNE
, arg0
,
877 bld_base
->uint_bld
.zero
, "");
879 emit_data
->output
[emit_data
->chan
] =
880 LLVMBuildSelect(builder
, v
, emit_data
->args
[1], emit_data
->args
[2], "");
883 static void emit_cmp(
884 const struct lp_build_tgsi_action
*action
,
885 struct lp_build_tgsi_context
* bld_base
,
886 struct lp_build_emit_data
* emit_data
)
888 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
889 LLVMRealPredicate pred
;
892 /* Use ordered for everything but NE (which is usual for
895 switch (emit_data
->inst
->Instruction
.Opcode
) {
896 case TGSI_OPCODE_SGE
: pred
= LLVMRealOGE
; break;
897 case TGSI_OPCODE_SEQ
: pred
= LLVMRealOEQ
; break;
898 case TGSI_OPCODE_SLE
: pred
= LLVMRealOLE
; break;
899 case TGSI_OPCODE_SLT
: pred
= LLVMRealOLT
; break;
900 case TGSI_OPCODE_SNE
: pred
= LLVMRealUNE
; break;
901 case TGSI_OPCODE_SGT
: pred
= LLVMRealOGT
; break;
902 default: assert(!"unknown instruction"); pred
= 0; break;
905 cond
= LLVMBuildFCmp(builder
,
906 pred
, emit_data
->args
[0], emit_data
->args
[1], "");
908 emit_data
->output
[emit_data
->chan
] = LLVMBuildSelect(builder
,
909 cond
, bld_base
->base
.one
, bld_base
->base
.zero
, "");
912 static void emit_fcmp(
913 const struct lp_build_tgsi_action
*action
,
914 struct lp_build_tgsi_context
* bld_base
,
915 struct lp_build_emit_data
* emit_data
)
917 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
918 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
919 LLVMRealPredicate pred
;
921 /* Use ordered for everything but NE (which is usual for
924 switch (emit_data
->inst
->Instruction
.Opcode
) {
925 case TGSI_OPCODE_FSEQ
: pred
= LLVMRealOEQ
; break;
926 case TGSI_OPCODE_FSGE
: pred
= LLVMRealOGE
; break;
927 case TGSI_OPCODE_FSLT
: pred
= LLVMRealOLT
; break;
928 case TGSI_OPCODE_FSNE
: pred
= LLVMRealUNE
; break;
929 default: assert(!"unknown instruction"); pred
= 0; break;
932 LLVMValueRef v
= LLVMBuildFCmp(builder
, pred
,
933 emit_data
->args
[0], emit_data
->args
[1],"");
935 v
= LLVMBuildSExtOrBitCast(builder
, v
,
936 LLVMInt32TypeInContext(context
), "");
938 emit_data
->output
[emit_data
->chan
] = v
;
941 static void emit_not(
942 const struct lp_build_tgsi_action
* action
,
943 struct lp_build_tgsi_context
* bld_base
,
944 struct lp_build_emit_data
* emit_data
)
946 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
947 LLVMValueRef v
= bitcast(bld_base
, TGSI_TYPE_UNSIGNED
,
949 emit_data
->output
[emit_data
->chan
] = LLVMBuildNot(builder
, v
, "");
952 static void emit_arl(
953 const struct lp_build_tgsi_action
* action
,
954 struct lp_build_tgsi_context
* bld_base
,
955 struct lp_build_emit_data
* emit_data
)
957 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
958 LLVMValueRef floor_index
= lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_FLR
, emit_data
->args
[0]);
959 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToSI(builder
,
960 floor_index
, bld_base
->base
.int_elem_type
, "");
963 static void emit_and(
964 const struct lp_build_tgsi_action
* action
,
965 struct lp_build_tgsi_context
* bld_base
,
966 struct lp_build_emit_data
* emit_data
)
968 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
969 emit_data
->output
[emit_data
->chan
] = LLVMBuildAnd(builder
,
970 emit_data
->args
[0], emit_data
->args
[1], "");
974 const struct lp_build_tgsi_action
* action
,
975 struct lp_build_tgsi_context
* bld_base
,
976 struct lp_build_emit_data
* emit_data
)
978 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
979 emit_data
->output
[emit_data
->chan
] = LLVMBuildOr(builder
,
980 emit_data
->args
[0], emit_data
->args
[1], "");
983 static void emit_uadd(
984 const struct lp_build_tgsi_action
* action
,
985 struct lp_build_tgsi_context
* bld_base
,
986 struct lp_build_emit_data
* emit_data
)
988 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
989 emit_data
->output
[emit_data
->chan
] = LLVMBuildAdd(builder
,
990 emit_data
->args
[0], emit_data
->args
[1], "");
993 static void emit_udiv(
994 const struct lp_build_tgsi_action
* action
,
995 struct lp_build_tgsi_context
* bld_base
,
996 struct lp_build_emit_data
* emit_data
)
998 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
999 emit_data
->output
[emit_data
->chan
] = LLVMBuildUDiv(builder
,
1000 emit_data
->args
[0], emit_data
->args
[1], "");
1003 static void emit_idiv(
1004 const struct lp_build_tgsi_action
* action
,
1005 struct lp_build_tgsi_context
* bld_base
,
1006 struct lp_build_emit_data
* emit_data
)
1008 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1009 emit_data
->output
[emit_data
->chan
] = LLVMBuildSDiv(builder
,
1010 emit_data
->args
[0], emit_data
->args
[1], "");
1013 static void emit_mod(
1014 const struct lp_build_tgsi_action
* action
,
1015 struct lp_build_tgsi_context
* bld_base
,
1016 struct lp_build_emit_data
* emit_data
)
1018 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1019 emit_data
->output
[emit_data
->chan
] = LLVMBuildSRem(builder
,
1020 emit_data
->args
[0], emit_data
->args
[1], "");
1023 static void emit_umod(
1024 const struct lp_build_tgsi_action
* action
,
1025 struct lp_build_tgsi_context
* bld_base
,
1026 struct lp_build_emit_data
* emit_data
)
1028 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1029 emit_data
->output
[emit_data
->chan
] = LLVMBuildURem(builder
,
1030 emit_data
->args
[0], emit_data
->args
[1], "");
1033 static void emit_shl(
1034 const struct lp_build_tgsi_action
* action
,
1035 struct lp_build_tgsi_context
* bld_base
,
1036 struct lp_build_emit_data
* emit_data
)
1038 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1039 emit_data
->output
[emit_data
->chan
] = LLVMBuildShl(builder
,
1040 emit_data
->args
[0], emit_data
->args
[1], "");
1043 static void emit_ushr(
1044 const struct lp_build_tgsi_action
* action
,
1045 struct lp_build_tgsi_context
* bld_base
,
1046 struct lp_build_emit_data
* emit_data
)
1048 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1049 emit_data
->output
[emit_data
->chan
] = LLVMBuildLShr(builder
,
1050 emit_data
->args
[0], emit_data
->args
[1], "");
1052 static void emit_ishr(
1053 const struct lp_build_tgsi_action
* action
,
1054 struct lp_build_tgsi_context
* bld_base
,
1055 struct lp_build_emit_data
* emit_data
)
1057 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1058 emit_data
->output
[emit_data
->chan
] = LLVMBuildAShr(builder
,
1059 emit_data
->args
[0], emit_data
->args
[1], "");
1062 static void emit_xor(
1063 const struct lp_build_tgsi_action
* action
,
1064 struct lp_build_tgsi_context
* bld_base
,
1065 struct lp_build_emit_data
* emit_data
)
1067 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1068 emit_data
->output
[emit_data
->chan
] = LLVMBuildXor(builder
,
1069 emit_data
->args
[0], emit_data
->args
[1], "");
1072 static void emit_ssg(
1073 const struct lp_build_tgsi_action
* action
,
1074 struct lp_build_tgsi_context
* bld_base
,
1075 struct lp_build_emit_data
* emit_data
)
1077 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1079 LLVMValueRef cmp
, val
;
1081 if (emit_data
->inst
->Instruction
.Opcode
== TGSI_OPCODE_ISSG
) {
1082 cmp
= LLVMBuildICmp(builder
, LLVMIntSGT
, emit_data
->args
[0], bld_base
->int_bld
.zero
, "");
1083 val
= LLVMBuildSelect(builder
, cmp
, bld_base
->int_bld
.one
, emit_data
->args
[0], "");
1084 cmp
= LLVMBuildICmp(builder
, LLVMIntSGE
, val
, bld_base
->int_bld
.zero
, "");
1085 val
= LLVMBuildSelect(builder
, cmp
, val
, LLVMConstInt(bld_base
->int_bld
.elem_type
, -1, true), "");
1086 } else { // float SSG
1087 cmp
= LLVMBuildFCmp(builder
, LLVMRealUGT
, emit_data
->args
[0], bld_base
->base
.zero
, "");
1088 val
= LLVMBuildSelect(builder
, cmp
, bld_base
->base
.one
, emit_data
->args
[0], "");
1089 cmp
= LLVMBuildFCmp(builder
, LLVMRealUGE
, val
, bld_base
->base
.zero
, "");
1090 val
= LLVMBuildSelect(builder
, cmp
, val
, LLVMConstReal(bld_base
->base
.elem_type
, -1), "");
1093 emit_data
->output
[emit_data
->chan
] = val
;
1096 static void emit_ineg(
1097 const struct lp_build_tgsi_action
* action
,
1098 struct lp_build_tgsi_context
* bld_base
,
1099 struct lp_build_emit_data
* emit_data
)
1101 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1102 emit_data
->output
[emit_data
->chan
] = LLVMBuildNeg(builder
,
1103 emit_data
->args
[0], "");
1106 static void emit_f2i(
1107 const struct lp_build_tgsi_action
* action
,
1108 struct lp_build_tgsi_context
* bld_base
,
1109 struct lp_build_emit_data
* emit_data
)
1111 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1112 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToSI(builder
,
1113 emit_data
->args
[0], bld_base
->int_bld
.elem_type
, "");
1116 static void emit_f2u(
1117 const struct lp_build_tgsi_action
* action
,
1118 struct lp_build_tgsi_context
* bld_base
,
1119 struct lp_build_emit_data
* emit_data
)
1121 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1122 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToUI(builder
,
1123 emit_data
->args
[0], bld_base
->uint_bld
.elem_type
, "");
1126 static void emit_i2f(
1127 const struct lp_build_tgsi_action
* action
,
1128 struct lp_build_tgsi_context
* bld_base
,
1129 struct lp_build_emit_data
* emit_data
)
1131 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1132 emit_data
->output
[emit_data
->chan
] = LLVMBuildSIToFP(builder
,
1133 emit_data
->args
[0], bld_base
->base
.elem_type
, "");
1136 static void emit_u2f(
1137 const struct lp_build_tgsi_action
* action
,
1138 struct lp_build_tgsi_context
* bld_base
,
1139 struct lp_build_emit_data
* emit_data
)
1141 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1142 emit_data
->output
[emit_data
->chan
] = LLVMBuildUIToFP(builder
,
1143 emit_data
->args
[0], bld_base
->base
.elem_type
, "");
1146 static void emit_immediate(struct lp_build_tgsi_context
* bld_base
,
1147 const struct tgsi_full_immediate
*imm
)
1150 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
1152 for (i
= 0; i
< 4; ++i
) {
1153 ctx
->soa
.immediates
[ctx
->soa
.num_immediates
][i
] =
1154 LLVMConstInt(bld_base
->uint_bld
.elem_type
, imm
->u
[i
].Uint
, false );
1157 ctx
->soa
.num_immediates
++;
1161 build_intrinsic(LLVMBuilderRef builder
,
1163 LLVMTypeRef ret_type
,
1168 LLVMModuleRef module
= LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder
)));
1169 LLVMValueRef function
;
1171 function
= LLVMGetNamedFunction(module
, name
);
1173 LLVMTypeRef arg_types
[LP_MAX_FUNC_ARGS
];
1176 assert(num_args
<= LP_MAX_FUNC_ARGS
);
1178 for(i
= 0; i
< num_args
; ++i
) {
1180 arg_types
[i
] = LLVMTypeOf(args
[i
]);
1183 function
= lp_declare_intrinsic(module
, name
, ret_type
, arg_types
, num_args
);
1186 LLVMAddFunctionAttr(function
, attr
);
1189 return LLVMBuildCall(builder
, function
, args
, num_args
, "");
1192 static void build_tgsi_intrinsic(
1193 const struct lp_build_tgsi_action
* action
,
1194 struct lp_build_tgsi_context
* bld_base
,
1195 struct lp_build_emit_data
* emit_data
,
1198 struct lp_build_context
* base
= &bld_base
->base
;
1199 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1200 base
->gallivm
->builder
, action
->intr_name
,
1201 emit_data
->dst_type
, emit_data
->args
,
1202 emit_data
->arg_count
, attr
);
1205 build_tgsi_intrinsic_nomem(
1206 const struct lp_build_tgsi_action
* action
,
1207 struct lp_build_tgsi_context
* bld_base
,
1208 struct lp_build_emit_data
* emit_data
)
1210 build_tgsi_intrinsic(action
, bld_base
, emit_data
, LLVMReadNoneAttribute
);
1213 static void build_tgsi_intrinsic_readonly(
1214 const struct lp_build_tgsi_action
* action
,
1215 struct lp_build_tgsi_context
* bld_base
,
1216 struct lp_build_emit_data
* emit_data
)
1218 build_tgsi_intrinsic(action
, bld_base
, emit_data
, LLVMReadOnlyAttribute
);
1221 void radeon_llvm_context_init(struct radeon_llvm_context
* ctx
)
1223 struct lp_type type
;
1225 /* Initialize the gallivm object:
1226 * We are only using the module, context, and builder fields of this struct.
1227 * This should be enough for us to be able to pass our gallivm struct to the
1228 * helper functions in the gallivm module.
1230 memset(&ctx
->gallivm
, 0, sizeof (ctx
->gallivm
));
1231 memset(&ctx
->soa
, 0, sizeof(ctx
->soa
));
1232 ctx
->gallivm
.context
= LLVMContextCreate();
1233 ctx
->gallivm
.module
= LLVMModuleCreateWithNameInContext("tgsi",
1234 ctx
->gallivm
.context
);
1235 ctx
->gallivm
.builder
= LLVMCreateBuilderInContext(ctx
->gallivm
.context
);
1237 ctx
->store_output_intr
= "llvm.AMDGPU.store.output.";
1238 ctx
->swizzle_intr
= "llvm.AMDGPU.swizzle";
1239 struct lp_build_tgsi_context
* bld_base
= &ctx
->soa
.bld_base
;
1241 /* XXX: We need to revisit this.I think the correct way to do this is
1242 * to use length = 4 here and use the elem_bld for everything. */
1243 type
.floating
= TRUE
;
1250 lp_build_context_init(&bld_base
->base
, &ctx
->gallivm
, type
);
1251 lp_build_context_init(&ctx
->soa
.bld_base
.uint_bld
, &ctx
->gallivm
, lp_uint_type(type
));
1252 lp_build_context_init(&ctx
->soa
.bld_base
.int_bld
, &ctx
->gallivm
, lp_int_type(type
));
1255 bld_base
->emit_store
= emit_store
;
1256 bld_base
->emit_swizzle
= emit_swizzle
;
1257 bld_base
->emit_declaration
= emit_declaration
;
1258 bld_base
->emit_immediate
= emit_immediate
;
1260 bld_base
->emit_fetch_funcs
[TGSI_FILE_IMMEDIATE
] = emit_fetch
;
1261 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = emit_fetch
;
1262 bld_base
->emit_fetch_funcs
[TGSI_FILE_TEMPORARY
] = emit_fetch
;
1263 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = emit_fetch
;
1264 bld_base
->emit_fetch_funcs
[TGSI_FILE_SYSTEM_VALUE
] = fetch_system_value
;
1266 /* Allocate outputs */
1267 ctx
->soa
.outputs
= ctx
->outputs
;
1269 ctx
->num_arrays
= 0;
1271 /* XXX: Is there a better way to initialize all this ? */
1273 lp_set_default_actions(bld_base
);
1275 bld_base
->op_actions
[TGSI_OPCODE_ABS
].emit
= build_tgsi_intrinsic_readonly
;
1276 bld_base
->op_actions
[TGSI_OPCODE_ABS
].intr_name
= "fabs";
1277 bld_base
->op_actions
[TGSI_OPCODE_ARL
].emit
= emit_arl
;
1278 bld_base
->op_actions
[TGSI_OPCODE_AND
].emit
= emit_and
;
1279 bld_base
->op_actions
[TGSI_OPCODE_BGNLOOP
].emit
= bgnloop_emit
;
1280 bld_base
->op_actions
[TGSI_OPCODE_BRK
].emit
= brk_emit
;
1281 bld_base
->op_actions
[TGSI_OPCODE_CEIL
].emit
= build_tgsi_intrinsic_readonly
;
1282 bld_base
->op_actions
[TGSI_OPCODE_CEIL
].intr_name
= "ceil";
1283 bld_base
->op_actions
[TGSI_OPCODE_CLAMP
].emit
= build_tgsi_intrinsic_nomem
;
1284 bld_base
->op_actions
[TGSI_OPCODE_CLAMP
].intr_name
= "llvm.AMDIL.clamp.";
1285 bld_base
->op_actions
[TGSI_OPCODE_CMP
].emit
= build_tgsi_intrinsic_nomem
;
1286 bld_base
->op_actions
[TGSI_OPCODE_CMP
].intr_name
= "llvm.AMDGPU.cndlt";
1287 bld_base
->op_actions
[TGSI_OPCODE_CONT
].emit
= cont_emit
;
1288 bld_base
->op_actions
[TGSI_OPCODE_COS
].emit
= build_tgsi_intrinsic_readonly
;
1289 bld_base
->op_actions
[TGSI_OPCODE_COS
].intr_name
= "llvm.cos.f32";
1290 bld_base
->op_actions
[TGSI_OPCODE_DDX
].intr_name
= "llvm.AMDGPU.ddx";
1291 bld_base
->op_actions
[TGSI_OPCODE_DDX
].fetch_args
= tex_fetch_args
;
1292 bld_base
->op_actions
[TGSI_OPCODE_DDY
].intr_name
= "llvm.AMDGPU.ddy";
1293 bld_base
->op_actions
[TGSI_OPCODE_DDY
].fetch_args
= tex_fetch_args
;
1294 bld_base
->op_actions
[TGSI_OPCODE_ELSE
].emit
= else_emit
;
1295 bld_base
->op_actions
[TGSI_OPCODE_ENDIF
].emit
= endif_emit
;
1296 bld_base
->op_actions
[TGSI_OPCODE_ENDLOOP
].emit
= endloop_emit
;
1297 bld_base
->op_actions
[TGSI_OPCODE_EX2
].emit
= build_tgsi_intrinsic_nomem
;
1298 bld_base
->op_actions
[TGSI_OPCODE_EX2
].intr_name
= "llvm.AMDIL.exp.";
1299 bld_base
->op_actions
[TGSI_OPCODE_FLR
].emit
= build_tgsi_intrinsic_readonly
;
1300 bld_base
->op_actions
[TGSI_OPCODE_FLR
].intr_name
= "floor";
1301 bld_base
->op_actions
[TGSI_OPCODE_FRC
].emit
= build_tgsi_intrinsic_nomem
;
1302 bld_base
->op_actions
[TGSI_OPCODE_FRC
].intr_name
= "llvm.AMDIL.fraction.";
1303 bld_base
->op_actions
[TGSI_OPCODE_F2I
].emit
= emit_f2i
;
1304 bld_base
->op_actions
[TGSI_OPCODE_F2U
].emit
= emit_f2u
;
1305 bld_base
->op_actions
[TGSI_OPCODE_FSEQ
].emit
= emit_fcmp
;
1306 bld_base
->op_actions
[TGSI_OPCODE_FSGE
].emit
= emit_fcmp
;
1307 bld_base
->op_actions
[TGSI_OPCODE_FSLT
].emit
= emit_fcmp
;
1308 bld_base
->op_actions
[TGSI_OPCODE_FSNE
].emit
= emit_fcmp
;
1309 bld_base
->op_actions
[TGSI_OPCODE_IABS
].emit
= build_tgsi_intrinsic_nomem
;
1310 bld_base
->op_actions
[TGSI_OPCODE_IABS
].intr_name
= "llvm.AMDIL.abs.";
1311 bld_base
->op_actions
[TGSI_OPCODE_IDIV
].emit
= emit_idiv
;
1312 bld_base
->op_actions
[TGSI_OPCODE_IF
].emit
= if_emit
;
1313 bld_base
->op_actions
[TGSI_OPCODE_UIF
].emit
= uif_emit
;
1314 bld_base
->op_actions
[TGSI_OPCODE_IMAX
].emit
= build_tgsi_intrinsic_nomem
;
1315 bld_base
->op_actions
[TGSI_OPCODE_IMAX
].intr_name
= "llvm.AMDGPU.imax";
1316 bld_base
->op_actions
[TGSI_OPCODE_IMIN
].emit
= build_tgsi_intrinsic_nomem
;
1317 bld_base
->op_actions
[TGSI_OPCODE_IMIN
].intr_name
= "llvm.AMDGPU.imin";
1318 bld_base
->op_actions
[TGSI_OPCODE_INEG
].emit
= emit_ineg
;
1319 bld_base
->op_actions
[TGSI_OPCODE_ISHR
].emit
= emit_ishr
;
1320 bld_base
->op_actions
[TGSI_OPCODE_ISGE
].emit
= emit_icmp
;
1321 bld_base
->op_actions
[TGSI_OPCODE_ISLT
].emit
= emit_icmp
;
1322 bld_base
->op_actions
[TGSI_OPCODE_ISSG
].emit
= emit_ssg
;
1323 bld_base
->op_actions
[TGSI_OPCODE_I2F
].emit
= emit_i2f
;
1324 bld_base
->op_actions
[TGSI_OPCODE_KILL_IF
].emit
= kil_emit
;
1325 bld_base
->op_actions
[TGSI_OPCODE_KILL_IF
].intr_name
= "llvm.AMDGPU.kill";
1326 bld_base
->op_actions
[TGSI_OPCODE_KILL
].emit
= lp_build_tgsi_intrinsic
;
1327 bld_base
->op_actions
[TGSI_OPCODE_KILL
].intr_name
= "llvm.AMDGPU.kilp";
1328 bld_base
->op_actions
[TGSI_OPCODE_LG2
].emit
= build_tgsi_intrinsic_readonly
;
1329 bld_base
->op_actions
[TGSI_OPCODE_LG2
].intr_name
= "llvm.log2.f32";
1330 bld_base
->op_actions
[TGSI_OPCODE_LRP
].emit
= build_tgsi_intrinsic_nomem
;
1331 bld_base
->op_actions
[TGSI_OPCODE_LRP
].intr_name
= "llvm.AMDGPU.lrp";
1332 bld_base
->op_actions
[TGSI_OPCODE_MOD
].emit
= emit_mod
;
1333 bld_base
->op_actions
[TGSI_OPCODE_NOT
].emit
= emit_not
;
1334 bld_base
->op_actions
[TGSI_OPCODE_OR
].emit
= emit_or
;
1335 bld_base
->op_actions
[TGSI_OPCODE_POW
].emit
= build_tgsi_intrinsic_readonly
;
1336 bld_base
->op_actions
[TGSI_OPCODE_POW
].intr_name
= "llvm.pow.f32";
1337 bld_base
->op_actions
[TGSI_OPCODE_ROUND
].emit
= build_tgsi_intrinsic_nomem
;
1338 bld_base
->op_actions
[TGSI_OPCODE_ROUND
].intr_name
= "llvm.AMDIL.round.nearest.";
1339 bld_base
->op_actions
[TGSI_OPCODE_SGE
].emit
= emit_cmp
;
1340 bld_base
->op_actions
[TGSI_OPCODE_SEQ
].emit
= emit_cmp
;
1341 bld_base
->op_actions
[TGSI_OPCODE_SHL
].emit
= emit_shl
;
1342 bld_base
->op_actions
[TGSI_OPCODE_SLE
].emit
= emit_cmp
;
1343 bld_base
->op_actions
[TGSI_OPCODE_SLT
].emit
= emit_cmp
;
1344 bld_base
->op_actions
[TGSI_OPCODE_SNE
].emit
= emit_cmp
;
1345 bld_base
->op_actions
[TGSI_OPCODE_SGT
].emit
= emit_cmp
;
1346 bld_base
->op_actions
[TGSI_OPCODE_SIN
].emit
= build_tgsi_intrinsic_readonly
;
1347 bld_base
->op_actions
[TGSI_OPCODE_SIN
].intr_name
= "llvm.sin.f32";
1348 bld_base
->op_actions
[TGSI_OPCODE_SSG
].emit
= emit_ssg
;
1349 bld_base
->op_actions
[TGSI_OPCODE_TEX
].fetch_args
= tex_fetch_args
;
1350 bld_base
->op_actions
[TGSI_OPCODE_TEX
].intr_name
= "llvm.AMDGPU.tex";
1351 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].fetch_args
= tex_fetch_args
;
1352 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].intr_name
= "llvm.AMDGPU.tex";
1353 bld_base
->op_actions
[TGSI_OPCODE_TXB
].fetch_args
= tex_fetch_args
;
1354 bld_base
->op_actions
[TGSI_OPCODE_TXB
].intr_name
= "llvm.AMDGPU.txb";
1355 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].fetch_args
= tex_fetch_args
;
1356 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].intr_name
= "llvm.AMDGPU.txb";
1357 bld_base
->op_actions
[TGSI_OPCODE_TXD
].fetch_args
= txd_fetch_args
;
1358 bld_base
->op_actions
[TGSI_OPCODE_TXD
].intr_name
= "llvm.AMDGPU.txd";
1359 bld_base
->op_actions
[TGSI_OPCODE_TXF
].fetch_args
= txf_fetch_args
;
1360 bld_base
->op_actions
[TGSI_OPCODE_TXF
].intr_name
= "llvm.AMDGPU.txf";
1361 bld_base
->op_actions
[TGSI_OPCODE_TXL
].fetch_args
= tex_fetch_args
;
1362 bld_base
->op_actions
[TGSI_OPCODE_TXL
].intr_name
= "llvm.AMDGPU.txl";
1363 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].fetch_args
= tex_fetch_args
;
1364 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].intr_name
= "llvm.AMDGPU.txl";
1365 bld_base
->op_actions
[TGSI_OPCODE_TXP
].fetch_args
= txp_fetch_args
;
1366 bld_base
->op_actions
[TGSI_OPCODE_TXP
].intr_name
= "llvm.AMDGPU.tex";
1367 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= tex_fetch_args
;
1368 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].intr_name
= "llvm.AMDGPU.txq";
1369 bld_base
->op_actions
[TGSI_OPCODE_TRUNC
].emit
= build_tgsi_intrinsic_nomem
;
1370 bld_base
->op_actions
[TGSI_OPCODE_TRUNC
].intr_name
= "llvm.AMDGPU.trunc";
1371 bld_base
->op_actions
[TGSI_OPCODE_UADD
].emit
= emit_uadd
;
1372 bld_base
->op_actions
[TGSI_OPCODE_UDIV
].emit
= emit_udiv
;
1373 bld_base
->op_actions
[TGSI_OPCODE_UMAX
].emit
= build_tgsi_intrinsic_nomem
;
1374 bld_base
->op_actions
[TGSI_OPCODE_UMAX
].intr_name
= "llvm.AMDGPU.umax";
1375 bld_base
->op_actions
[TGSI_OPCODE_UMIN
].emit
= build_tgsi_intrinsic_nomem
;
1376 bld_base
->op_actions
[TGSI_OPCODE_UMIN
].intr_name
= "llvm.AMDGPU.umin";
1377 bld_base
->op_actions
[TGSI_OPCODE_UMOD
].emit
= emit_umod
;
1378 bld_base
->op_actions
[TGSI_OPCODE_USEQ
].emit
= emit_icmp
;
1379 bld_base
->op_actions
[TGSI_OPCODE_USGE
].emit
= emit_icmp
;
1380 bld_base
->op_actions
[TGSI_OPCODE_USHR
].emit
= emit_ushr
;
1381 bld_base
->op_actions
[TGSI_OPCODE_USLT
].emit
= emit_icmp
;
1382 bld_base
->op_actions
[TGSI_OPCODE_USNE
].emit
= emit_icmp
;
1383 bld_base
->op_actions
[TGSI_OPCODE_U2F
].emit
= emit_u2f
;
1384 bld_base
->op_actions
[TGSI_OPCODE_XOR
].emit
= emit_xor
;
1385 bld_base
->op_actions
[TGSI_OPCODE_UCMP
].emit
= emit_ucmp
;
1387 bld_base
->rsq_action
.emit
= build_tgsi_intrinsic_nomem
;
1388 #if HAVE_LLVM >= 0x0305
1389 bld_base
->rsq_action
.intr_name
= "llvm.AMDGPU.rsq.clamped.f32";
1391 bld_base
->rsq_action
.intr_name
= "llvm.AMDGPU.rsq";
1395 void radeon_llvm_create_func(struct radeon_llvm_context
* ctx
,
1396 LLVMTypeRef
*ParamTypes
, unsigned ParamCount
)
1398 LLVMTypeRef main_fn_type
;
1399 LLVMBasicBlockRef main_fn_body
;
1401 /* Setup the function */
1402 main_fn_type
= LLVMFunctionType(LLVMVoidTypeInContext(ctx
->gallivm
.context
),
1403 ParamTypes
, ParamCount
, 0);
1404 ctx
->main_fn
= LLVMAddFunction(ctx
->gallivm
.module
, "main", main_fn_type
);
1405 main_fn_body
= LLVMAppendBasicBlockInContext(ctx
->gallivm
.context
,
1406 ctx
->main_fn
, "main_body");
1407 LLVMPositionBuilderAtEnd(ctx
->gallivm
.builder
, main_fn_body
);
1410 void radeon_llvm_finalize_module(struct radeon_llvm_context
* ctx
)
1412 struct gallivm_state
* gallivm
= ctx
->soa
.bld_base
.base
.gallivm
;
1413 /* End the main function with Return*/
1414 LLVMBuildRetVoid(gallivm
->builder
);
1416 /* Create the pass manager */
1417 ctx
->gallivm
.passmgr
= LLVMCreateFunctionPassManagerForModule(
1420 /* This pass should eliminate all the load and store instructions */
1421 LLVMAddPromoteMemoryToRegisterPass(gallivm
->passmgr
);
1423 /* Add some optimization passes */
1424 LLVMAddScalarReplAggregatesPass(gallivm
->passmgr
);
1425 LLVMAddLICMPass(gallivm
->passmgr
);
1426 LLVMAddAggressiveDCEPass(gallivm
->passmgr
);
1427 LLVMAddCFGSimplificationPass(gallivm
->passmgr
);
1430 LLVMRunFunctionPassManager(gallivm
->passmgr
, ctx
->main_fn
);
1432 LLVMDisposeBuilder(gallivm
->builder
);
1433 LLVMDisposePassManager(gallivm
->passmgr
);
1437 void radeon_llvm_dispose(struct radeon_llvm_context
* ctx
)
1439 LLVMDisposeModule(ctx
->soa
.bld_base
.base
.gallivm
->module
);
1440 LLVMContextDispose(ctx
->soa
.bld_base
.base
.gallivm
->context
);