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radeon/llvm: move system value fetching to common code
[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26 #include "radeon_llvm.h"
27
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
42
43 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
44 {
45 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
46 }
47
48 static struct radeon_llvm_branch * get_current_branch(
49 struct radeon_llvm_context * ctx)
50 {
51 return ctx->branch_depth > 0 ?
52 ctx->branch + (ctx->branch_depth - 1) : NULL;
53 }
54
55 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
56 {
57 return (index * 4) + chan;
58 }
59
60 static LLVMValueRef emit_swizzle(
61 struct lp_build_tgsi_context * bld_base,
62 LLVMValueRef value,
63 unsigned swizzle_x,
64 unsigned swizzle_y,
65 unsigned swizzle_z,
66 unsigned swizzle_w)
67 {
68 LLVMValueRef swizzles[4];
69 LLVMTypeRef i32t =
70 LLVMInt32TypeInContext(bld_base->base.gallivm->context);
71
72 swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0);
73 swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0);
74 swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0);
75 swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0);
76
77 return LLVMBuildShuffleVector(bld_base->base.gallivm->builder,
78 value,
79 LLVMGetUndef(LLVMTypeOf(value)),
80 LLVMConstVector(swizzles, 4), "");
81 }
82
83 static struct tgsi_declaration_range
84 get_array_range(struct lp_build_tgsi_context *bld_base,
85 unsigned File, const struct tgsi_ind_register *reg)
86 {
87 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
88 if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 ||
89 reg->ArrayID > RADEON_LLVM_MAX_ARRAYS) {
90 struct tgsi_declaration_range range;
91 range.First = 0;
92 range.Last = bld_base->info->file_max[File];
93 return range;
94 }
95
96 return ctx->arrays[reg->ArrayID - 1];
97 }
98
99 static LLVMValueRef
100 emit_array_index(
101 struct lp_build_tgsi_soa_context *bld,
102 const struct tgsi_ind_register *reg,
103 unsigned offset)
104 {
105 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
106
107 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, bld->addr[reg->Index][reg->Swizzle], "");
108 return LLVMBuildAdd(gallivm->builder, addr, lp_build_const_int32(gallivm, offset), "");
109 }
110
111 static LLVMValueRef
112 emit_fetch(
113 struct lp_build_tgsi_context *bld_base,
114 const struct tgsi_full_src_register *reg,
115 enum tgsi_opcode_type type,
116 unsigned swizzle);
117
118 static LLVMValueRef
119 emit_array_fetch(
120 struct lp_build_tgsi_context *bld_base,
121 unsigned File, enum tgsi_opcode_type type,
122 struct tgsi_declaration_range range,
123 unsigned swizzle)
124 {
125 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
126 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
127 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
128
129 unsigned i, size = range.Last - range.First + 1;
130 LLVMTypeRef vec = LLVMVectorType(tgsi2llvmtype(bld_base, type), size);
131 LLVMValueRef result = LLVMGetUndef(vec);
132
133 struct tgsi_full_src_register tmp_reg = {};
134 tmp_reg.Register.File = File;
135
136 for (i = 0; i < size; ++i) {
137 tmp_reg.Register.Index = i + range.First;
138 LLVMValueRef temp = emit_fetch(bld_base, &tmp_reg, type, swizzle);
139 result = LLVMBuildInsertElement(builder, result, temp,
140 lp_build_const_int32(gallivm, i), "");
141 }
142 return result;
143 }
144
145 static LLVMValueRef
146 emit_fetch(
147 struct lp_build_tgsi_context *bld_base,
148 const struct tgsi_full_src_register *reg,
149 enum tgsi_opcode_type type,
150 unsigned swizzle)
151 {
152 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
153 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
154 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
155 LLVMValueRef result, ptr;
156
157 if (swizzle == ~0) {
158 LLVMValueRef values[TGSI_NUM_CHANNELS];
159 unsigned chan;
160 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
161 values[chan] = emit_fetch(bld_base, reg, type, chan);
162 }
163 return lp_build_gather_values(bld_base->base.gallivm, values,
164 TGSI_NUM_CHANNELS);
165 }
166
167 if (reg->Register.Indirect) {
168 struct tgsi_declaration_range range = get_array_range(bld_base,
169 reg->Register.File, &reg->Indirect);
170 return LLVMBuildExtractElement(builder,
171 emit_array_fetch(bld_base, reg->Register.File, type, range, swizzle),
172 emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First),
173 "");
174 }
175
176 switch(reg->Register.File) {
177 case TGSI_FILE_IMMEDIATE: {
178 LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type);
179 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
180 }
181
182 case TGSI_FILE_INPUT:
183 result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)];
184 break;
185
186 case TGSI_FILE_TEMPORARY:
187 ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
188 result = LLVMBuildLoad(builder, ptr, "");
189 break;
190
191 case TGSI_FILE_OUTPUT:
192 ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
193 result = LLVMBuildLoad(builder, ptr, "");
194 break;
195
196 default:
197 return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
198 }
199
200 return bitcast(bld_base, type, result);
201 }
202
203 static LLVMValueRef fetch_system_value(
204 struct lp_build_tgsi_context * bld_base,
205 const struct tgsi_full_src_register *reg,
206 enum tgsi_opcode_type type,
207 unsigned swizzle)
208 {
209 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
210 LLVMValueRef cval = ctx->system_values[reg->Register.Index];
211 return bitcast(bld_base, type, cval);
212 }
213
214 static void emit_declaration(
215 struct lp_build_tgsi_context * bld_base,
216 const struct tgsi_full_declaration *decl)
217 {
218 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
219 switch(decl->Declaration.File) {
220 case TGSI_FILE_ADDRESS:
221 {
222 unsigned idx;
223 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
224 unsigned chan;
225 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
226 ctx->soa.addr[idx][chan] = lp_build_alloca(
227 &ctx->gallivm,
228 ctx->soa.bld_base.uint_bld.elem_type, "");
229 }
230 }
231 break;
232 }
233
234 case TGSI_FILE_TEMPORARY:
235 if (decl->Declaration.Array && decl->Array.ArrayID <= RADEON_LLVM_MAX_ARRAYS)
236 ctx->arrays[decl->Array.ArrayID - 1] = decl->Range;
237 lp_emit_declaration_soa(bld_base, decl);
238 break;
239
240 case TGSI_FILE_INPUT:
241 {
242 unsigned idx;
243 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
244 ctx->load_input(ctx, idx, decl);
245 }
246 }
247 break;
248
249 case TGSI_FILE_SYSTEM_VALUE:
250 {
251 unsigned idx;
252 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
253 ctx->load_system_value(ctx, idx, decl);
254 }
255 }
256 break;
257
258 case TGSI_FILE_OUTPUT:
259 {
260 unsigned idx;
261 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
262 unsigned chan;
263 assert(idx < RADEON_LLVM_MAX_OUTPUTS);
264 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
265 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm,
266 ctx->soa.bld_base.base.elem_type, "");
267 }
268 }
269
270 ctx->output_reg_count = MAX2(ctx->output_reg_count,
271 decl->Range.Last + 1);
272 break;
273 }
274
275 default:
276 break;
277 }
278 }
279
280 static void
281 emit_store(
282 struct lp_build_tgsi_context * bld_base,
283 const struct tgsi_full_instruction * inst,
284 const struct tgsi_opcode_info * info,
285 LLVMValueRef dst[4])
286 {
287 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
288 struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
289 struct lp_build_context base = bld->bld_base.base;
290 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
291 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
292 LLVMValueRef temp_ptr;
293 unsigned chan, chan_index;
294 boolean is_vec_store = FALSE;
295
296 if (dst[0]) {
297 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
298 is_vec_store = (k == LLVMVectorTypeKind);
299 }
300
301 if (is_vec_store) {
302 LLVMValueRef values[4] = {};
303 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
304 LLVMValueRef index = lp_build_const_int32(gallivm, chan);
305 values[chan] = LLVMBuildExtractElement(gallivm->builder,
306 dst[0], index, "");
307 }
308 bld_base->emit_store(bld_base, inst, info, values);
309 return;
310 }
311
312 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
313 LLVMValueRef value = dst[chan_index];
314
315 if (inst->Instruction.Saturate != TGSI_SAT_NONE) {
316 struct lp_build_emit_data clamp_emit_data;
317
318 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
319 clamp_emit_data.arg_count = 3;
320 clamp_emit_data.args[0] = value;
321 clamp_emit_data.args[2] = base.one;
322
323 switch(inst->Instruction.Saturate) {
324 case TGSI_SAT_ZERO_ONE:
325 clamp_emit_data.args[1] = base.zero;
326 break;
327 case TGSI_SAT_MINUS_PLUS_ONE:
328 clamp_emit_data.args[1] = LLVMConstReal(
329 base.elem_type, -1.0f);
330 break;
331 default:
332 assert(0);
333 }
334 value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
335 &clamp_emit_data);
336 }
337
338 if (reg->Register.File == TGSI_FILE_ADDRESS) {
339 temp_ptr = bld->addr[reg->Register.Index][chan_index];
340 LLVMBuildStore(builder, value, temp_ptr);
341 continue;
342 }
343
344 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
345
346 if (reg->Register.Indirect) {
347 struct tgsi_declaration_range range = get_array_range(bld_base,
348 reg->Register.File, &reg->Indirect);
349
350 unsigned i, size = range.Last - range.First + 1;
351 LLVMValueRef array = LLVMBuildInsertElement(builder,
352 emit_array_fetch(bld_base, reg->Register.File, TGSI_TYPE_FLOAT, range, chan_index),
353 value, emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First), "");
354
355 for (i = 0; i < size; ++i) {
356 switch(reg->Register.File) {
357 case TGSI_FILE_OUTPUT:
358 temp_ptr = bld->outputs[i + range.First][chan_index];
359 break;
360
361 case TGSI_FILE_TEMPORARY:
362 temp_ptr = lp_get_temp_ptr_soa(bld, i + range.First, chan_index);
363 break;
364
365 default:
366 return;
367 }
368 value = LLVMBuildExtractElement(builder, array,
369 lp_build_const_int32(gallivm, i), "");
370 LLVMBuildStore(builder, value, temp_ptr);
371 }
372
373 } else {
374 switch(reg->Register.File) {
375 case TGSI_FILE_OUTPUT:
376 temp_ptr = bld->outputs[reg->Register.Index][chan_index];
377 break;
378
379 case TGSI_FILE_TEMPORARY:
380 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, chan_index);
381 break;
382
383 default:
384 return;
385 }
386 LLVMBuildStore(builder, value, temp_ptr);
387 }
388 }
389 }
390
391 static void bgnloop_emit(
392 const struct lp_build_tgsi_action * action,
393 struct lp_build_tgsi_context * bld_base,
394 struct lp_build_emit_data * emit_data)
395 {
396 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
397 struct gallivm_state * gallivm = bld_base->base.gallivm;
398 LLVMBasicBlockRef loop_block;
399 LLVMBasicBlockRef endloop_block;
400 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
401 ctx->main_fn, "ENDLOOP");
402 loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
403 endloop_block, "LOOP");
404 LLVMBuildBr(gallivm->builder, loop_block);
405 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
406 ctx->loop_depth++;
407 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
408 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
409 }
410
411 static void brk_emit(
412 const struct lp_build_tgsi_action * action,
413 struct lp_build_tgsi_context * bld_base,
414 struct lp_build_emit_data * emit_data)
415 {
416 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
417 struct gallivm_state * gallivm = bld_base->base.gallivm;
418 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
419
420 LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
421 }
422
423 static void cont_emit(
424 const struct lp_build_tgsi_action * action,
425 struct lp_build_tgsi_context * bld_base,
426 struct lp_build_emit_data * emit_data)
427 {
428 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
429 struct gallivm_state * gallivm = bld_base->base.gallivm;
430 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
431
432 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
433 }
434
435 static void else_emit(
436 const struct lp_build_tgsi_action * action,
437 struct lp_build_tgsi_context * bld_base,
438 struct lp_build_emit_data * emit_data)
439 {
440 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
441 struct gallivm_state * gallivm = bld_base->base.gallivm;
442 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
443 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
444
445 /* We need to add a terminator to the current block if the previous
446 * instruction was an ENDIF.Example:
447 * IF
448 * [code]
449 * IF
450 * [code]
451 * ELSE
452 * [code]
453 * ENDIF <--
454 * ELSE<--
455 * [code]
456 * ENDIF
457 */
458
459 if (current_block != current_branch->if_block) {
460 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
461 }
462 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
463 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
464 }
465 current_branch->has_else = 1;
466 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
467 }
468
469 static void endif_emit(
470 const struct lp_build_tgsi_action * action,
471 struct lp_build_tgsi_context * bld_base,
472 struct lp_build_emit_data * emit_data)
473 {
474 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
475 struct gallivm_state * gallivm = bld_base->base.gallivm;
476 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
477 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
478
479 /* If we have consecutive ENDIF instructions, then the first ENDIF
480 * will not have a terminator, so we need to add one. */
481 if (current_block != current_branch->if_block
482 && current_block != current_branch->else_block
483 && !LLVMGetBasicBlockTerminator(current_block)) {
484
485 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
486 }
487 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
488 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
489 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
490 }
491
492 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
493 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
494 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
495 }
496
497 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
498 ctx->branch_depth--;
499 }
500
501 static void endloop_emit(
502 const struct lp_build_tgsi_action * action,
503 struct lp_build_tgsi_context * bld_base,
504 struct lp_build_emit_data * emit_data)
505 {
506 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
507 struct gallivm_state * gallivm = bld_base->base.gallivm;
508 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
509
510 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
511 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
512 }
513
514 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
515 ctx->loop_depth--;
516 }
517
518 static void if_emit(
519 const struct lp_build_tgsi_action * action,
520 struct lp_build_tgsi_context * bld_base,
521 struct lp_build_emit_data * emit_data)
522 {
523 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
524 struct gallivm_state * gallivm = bld_base->base.gallivm;
525 LLVMValueRef cond;
526 LLVMBasicBlockRef if_block, else_block, endif_block;
527
528 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
529 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
530 bld_base->int_bld.zero, "");
531
532 endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
533 ctx->main_fn, "ENDIF");
534 if_block = LLVMInsertBasicBlockInContext(gallivm->context,
535 endif_block, "IF");
536 else_block = LLVMInsertBasicBlockInContext(gallivm->context,
537 endif_block, "ELSE");
538 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
539 LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
540
541 ctx->branch_depth++;
542 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
543 ctx->branch[ctx->branch_depth - 1].if_block = if_block;
544 ctx->branch[ctx->branch_depth - 1].else_block = else_block;
545 ctx->branch[ctx->branch_depth - 1].has_else = 0;
546 }
547
548 static void kil_emit(
549 const struct lp_build_tgsi_action * action,
550 struct lp_build_tgsi_context * bld_base,
551 struct lp_build_emit_data * emit_data)
552 {
553 unsigned i;
554 for (i = 0; i < emit_data->arg_count; i++) {
555 emit_data->output[i] = lp_build_intrinsic_unary(
556 bld_base->base.gallivm->builder,
557 action->intr_name,
558 emit_data->dst_type, emit_data->args[i]);
559 }
560 }
561
562 void radeon_llvm_emit_prepare_cube_coords(
563 struct lp_build_tgsi_context * bld_base,
564 struct lp_build_emit_data * emit_data,
565 LLVMValueRef *coords_arg)
566 {
567
568 unsigned target = emit_data->inst->Texture.Texture;
569 unsigned opcode = emit_data->inst->Instruction.Opcode;
570 struct gallivm_state * gallivm = bld_base->base.gallivm;
571 LLVMBuilderRef builder = gallivm->builder;
572 LLVMTypeRef type = bld_base->base.elem_type;
573 LLVMValueRef coords[4];
574 LLVMValueRef mad_args[3];
575 LLVMValueRef idx;
576 struct LLVMOpaqueValue *cube_vec;
577 LLVMValueRef v;
578 unsigned i;
579
580 cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
581 v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
582 &cube_vec, 1, LLVMReadNoneAttribute);
583
584 for (i = 0; i < 4; ++i) {
585 idx = lp_build_const_int32(gallivm, i);
586 coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
587 }
588
589 coords[2] = build_intrinsic(builder, "fabs",
590 type, &coords[2], 1, LLVMReadNoneAttribute);
591 coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]);
592
593 mad_args[1] = coords[2];
594 mad_args[2] = LLVMConstReal(type, 1.5);
595
596 mad_args[0] = coords[0];
597 coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
598 mad_args[0], mad_args[1], mad_args[2]);
599
600 mad_args[0] = coords[1];
601 coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
602 mad_args[0], mad_args[1], mad_args[2]);
603
604 /* apply xyz = yxw swizzle to cooords */
605 coords[2] = coords[3];
606 coords[3] = coords[1];
607 coords[1] = coords[0];
608 coords[0] = coords[3];
609
610 /* all cases except simple cube map sampling require special handling
611 * for coord vector */
612 if (target != TGSI_TEXTURE_CUBE ||
613 opcode != TGSI_OPCODE_TEX) {
614
615 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
616 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
617 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
618
619 /* coords_arg.w component - array_index for cube arrays or
620 * compare value for SHADOWCUBE */
621 coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
622 coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
623 }
624
625 /* for instructions that need additional src (compare/lod/bias),
626 * put it in coord.w */
627 if (opcode == TGSI_OPCODE_TEX2 ||
628 opcode == TGSI_OPCODE_TXB2 ||
629 opcode == TGSI_OPCODE_TXL2) {
630 coords[3] = coords_arg[4];
631 }
632 }
633
634 memcpy(coords_arg, coords, sizeof(coords));
635 }
636
637 static void txd_fetch_args(
638 struct lp_build_tgsi_context * bld_base,
639 struct lp_build_emit_data * emit_data)
640 {
641 const struct tgsi_full_instruction * inst = emit_data->inst;
642
643 LLVMValueRef coords[4];
644 unsigned chan, src;
645 for (src = 0; src < 3; src++) {
646 for (chan = 0; chan < 4; chan++)
647 coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan);
648
649 emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm,
650 coords, 4);
651 }
652 emit_data->arg_count = 3;
653 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
654 }
655
656
657 static void txp_fetch_args(
658 struct lp_build_tgsi_context * bld_base,
659 struct lp_build_emit_data * emit_data)
660 {
661 const struct tgsi_full_instruction * inst = emit_data->inst;
662 LLVMValueRef src_w;
663 unsigned chan;
664 LLVMValueRef coords[4];
665
666 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
667 src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
668
669 for (chan = 0; chan < 3; chan++ ) {
670 LLVMValueRef arg = lp_build_emit_fetch(bld_base,
671 emit_data->inst, 0, chan);
672 coords[chan] = lp_build_emit_llvm_binary(bld_base,
673 TGSI_OPCODE_DIV, arg, src_w);
674 }
675 coords[3] = bld_base->base.one;
676
677 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
678 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
679 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
680 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
681 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
682 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
683 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
684 }
685
686 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
687 coords, 4);
688 emit_data->arg_count = 1;
689 }
690
691 static void tex_fetch_args(
692 struct lp_build_tgsi_context * bld_base,
693 struct lp_build_emit_data * emit_data)
694 {
695 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
696 * when we used CHAN_ALL. We should be able to get this to work,
697 * but for now we will swizzle it ourselves
698 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
699 0, CHAN_ALL);
700
701 */
702
703 const struct tgsi_full_instruction * inst = emit_data->inst;
704
705 LLVMValueRef coords[5];
706 unsigned chan;
707 for (chan = 0; chan < 4; chan++) {
708 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
709 }
710
711 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
712 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
713 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
714 /* These instructions have additional operand that should be packed
715 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
716 * That operand should be passed as a float value in the args array
717 * right after the coord vector. After packing it's not used anymore,
718 * that's why arg_count is not increased */
719 coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
720 }
721
722 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
723 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
724 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
725 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
726 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
727 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
728 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
729 }
730
731 emit_data->arg_count = 1;
732 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
733 coords, 4);
734 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
735 }
736
737 static void txf_fetch_args(
738 struct lp_build_tgsi_context * bld_base,
739 struct lp_build_emit_data * emit_data)
740 {
741 const struct tgsi_full_instruction * inst = emit_data->inst;
742 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
743 const struct tgsi_texture_offset * off = inst->TexOffsets;
744 LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
745
746 /* fetch tex coords */
747 tex_fetch_args(bld_base, emit_data);
748
749 /* fetch tex offsets */
750 if (inst->Texture.NumOffsets) {
751 assert(inst->Texture.NumOffsets == 1);
752
753 emit_data->args[1] = LLVMConstBitCast(
754 bld->immediates[off->Index][off->SwizzleX],
755 offset_type);
756 emit_data->args[2] = LLVMConstBitCast(
757 bld->immediates[off->Index][off->SwizzleY],
758 offset_type);
759 emit_data->args[3] = LLVMConstBitCast(
760 bld->immediates[off->Index][off->SwizzleZ],
761 offset_type);
762 } else {
763 emit_data->args[1] = bld_base->int_bld.zero;
764 emit_data->args[2] = bld_base->int_bld.zero;
765 emit_data->args[3] = bld_base->int_bld.zero;
766 }
767
768 emit_data->arg_count = 4;
769 }
770
771 static void emit_icmp(
772 const struct lp_build_tgsi_action * action,
773 struct lp_build_tgsi_context * bld_base,
774 struct lp_build_emit_data * emit_data)
775 {
776 unsigned pred;
777 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
778 LLVMContextRef context = bld_base->base.gallivm->context;
779
780 switch (emit_data->inst->Instruction.Opcode) {
781 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
782 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
783 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
784 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
785 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
786 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
787 default:
788 assert(!"unknown instruction");
789 pred = 0;
790 break;
791 }
792
793 LLVMValueRef v = LLVMBuildICmp(builder, pred,
794 emit_data->args[0], emit_data->args[1],"");
795
796 v = LLVMBuildSExtOrBitCast(builder, v,
797 LLVMInt32TypeInContext(context), "");
798
799 emit_data->output[emit_data->chan] = v;
800 }
801
802 static void emit_ucmp(
803 const struct lp_build_tgsi_action * action,
804 struct lp_build_tgsi_context * bld_base,
805 struct lp_build_emit_data * emit_data)
806 {
807 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
808
809 LLVMValueRef v = LLVMBuildFCmp(builder, LLVMRealUGE,
810 emit_data->args[0], lp_build_const_float(bld_base->base.gallivm, 0.), "");
811
812 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, v, emit_data->args[2], emit_data->args[1], "");
813 }
814
815 static void emit_cmp(
816 const struct lp_build_tgsi_action *action,
817 struct lp_build_tgsi_context * bld_base,
818 struct lp_build_emit_data * emit_data)
819 {
820 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
821 LLVMRealPredicate pred;
822 LLVMValueRef cond;
823
824 /* XXX I'm not sure whether to do unordered or ordered comparisons,
825 * but llvmpipe uses unordered comparisons, so for consistency we use
826 * unordered. (The authors of llvmpipe aren't sure about using
827 * unordered vs ordered comparisons either.
828 */
829 switch (emit_data->inst->Instruction.Opcode) {
830 case TGSI_OPCODE_SGE: pred = LLVMRealUGE; break;
831 case TGSI_OPCODE_SEQ: pred = LLVMRealUEQ; break;
832 case TGSI_OPCODE_SLE: pred = LLVMRealULE; break;
833 case TGSI_OPCODE_SLT: pred = LLVMRealULT; break;
834 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
835 case TGSI_OPCODE_SGT: pred = LLVMRealUGT; break;
836 default: assert(!"unknown instruction"); pred = 0; break;
837 }
838
839 cond = LLVMBuildFCmp(builder,
840 pred, emit_data->args[0], emit_data->args[1], "");
841
842 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
843 cond, bld_base->base.one, bld_base->base.zero, "");
844 }
845
846 static void emit_not(
847 const struct lp_build_tgsi_action * action,
848 struct lp_build_tgsi_context * bld_base,
849 struct lp_build_emit_data * emit_data)
850 {
851 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
852 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
853 emit_data->args[0]);
854 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
855 }
856
857 static void emit_arl(
858 const struct lp_build_tgsi_action * action,
859 struct lp_build_tgsi_context * bld_base,
860 struct lp_build_emit_data * emit_data)
861 {
862 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
863 LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
864 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
865 floor_index, bld_base->base.int_elem_type , "");
866 }
867
868 static void emit_and(
869 const struct lp_build_tgsi_action * action,
870 struct lp_build_tgsi_context * bld_base,
871 struct lp_build_emit_data * emit_data)
872 {
873 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
874 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
875 emit_data->args[0], emit_data->args[1], "");
876 }
877
878 static void emit_or(
879 const struct lp_build_tgsi_action * action,
880 struct lp_build_tgsi_context * bld_base,
881 struct lp_build_emit_data * emit_data)
882 {
883 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
884 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
885 emit_data->args[0], emit_data->args[1], "");
886 }
887
888 static void emit_uadd(
889 const struct lp_build_tgsi_action * action,
890 struct lp_build_tgsi_context * bld_base,
891 struct lp_build_emit_data * emit_data)
892 {
893 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
894 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
895 emit_data->args[0], emit_data->args[1], "");
896 }
897
898 static void emit_udiv(
899 const struct lp_build_tgsi_action * action,
900 struct lp_build_tgsi_context * bld_base,
901 struct lp_build_emit_data * emit_data)
902 {
903 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
904 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
905 emit_data->args[0], emit_data->args[1], "");
906 }
907
908 static void emit_idiv(
909 const struct lp_build_tgsi_action * action,
910 struct lp_build_tgsi_context * bld_base,
911 struct lp_build_emit_data * emit_data)
912 {
913 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
914 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
915 emit_data->args[0], emit_data->args[1], "");
916 }
917
918 static void emit_mod(
919 const struct lp_build_tgsi_action * action,
920 struct lp_build_tgsi_context * bld_base,
921 struct lp_build_emit_data * emit_data)
922 {
923 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
924 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
925 emit_data->args[0], emit_data->args[1], "");
926 }
927
928 static void emit_umod(
929 const struct lp_build_tgsi_action * action,
930 struct lp_build_tgsi_context * bld_base,
931 struct lp_build_emit_data * emit_data)
932 {
933 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
934 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
935 emit_data->args[0], emit_data->args[1], "");
936 }
937
938 static void emit_shl(
939 const struct lp_build_tgsi_action * action,
940 struct lp_build_tgsi_context * bld_base,
941 struct lp_build_emit_data * emit_data)
942 {
943 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
944 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
945 emit_data->args[0], emit_data->args[1], "");
946 }
947
948 static void emit_ushr(
949 const struct lp_build_tgsi_action * action,
950 struct lp_build_tgsi_context * bld_base,
951 struct lp_build_emit_data * emit_data)
952 {
953 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
954 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
955 emit_data->args[0], emit_data->args[1], "");
956 }
957 static void emit_ishr(
958 const struct lp_build_tgsi_action * action,
959 struct lp_build_tgsi_context * bld_base,
960 struct lp_build_emit_data * emit_data)
961 {
962 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
963 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
964 emit_data->args[0], emit_data->args[1], "");
965 }
966
967 static void emit_xor(
968 const struct lp_build_tgsi_action * action,
969 struct lp_build_tgsi_context * bld_base,
970 struct lp_build_emit_data * emit_data)
971 {
972 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
973 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
974 emit_data->args[0], emit_data->args[1], "");
975 }
976
977 static void emit_ssg(
978 const struct lp_build_tgsi_action * action,
979 struct lp_build_tgsi_context * bld_base,
980 struct lp_build_emit_data * emit_data)
981 {
982 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
983
984 LLVMValueRef cmp, val;
985
986 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
987 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
988 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
989 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
990 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
991 } else { // float SSG
992 cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->base.zero, "");
993 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
994 cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, "");
995 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
996 }
997
998 emit_data->output[emit_data->chan] = val;
999 }
1000
1001 static void emit_ineg(
1002 const struct lp_build_tgsi_action * action,
1003 struct lp_build_tgsi_context * bld_base,
1004 struct lp_build_emit_data * emit_data)
1005 {
1006 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1007 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
1008 emit_data->args[0], "");
1009 }
1010
1011 static void emit_f2i(
1012 const struct lp_build_tgsi_action * action,
1013 struct lp_build_tgsi_context * bld_base,
1014 struct lp_build_emit_data * emit_data)
1015 {
1016 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1017 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
1018 emit_data->args[0], bld_base->int_bld.elem_type, "");
1019 }
1020
1021 static void emit_f2u(
1022 const struct lp_build_tgsi_action * action,
1023 struct lp_build_tgsi_context * bld_base,
1024 struct lp_build_emit_data * emit_data)
1025 {
1026 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1027 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
1028 emit_data->args[0], bld_base->uint_bld.elem_type, "");
1029 }
1030
1031 static void emit_i2f(
1032 const struct lp_build_tgsi_action * action,
1033 struct lp_build_tgsi_context * bld_base,
1034 struct lp_build_emit_data * emit_data)
1035 {
1036 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1037 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
1038 emit_data->args[0], bld_base->base.elem_type, "");
1039 }
1040
1041 static void emit_u2f(
1042 const struct lp_build_tgsi_action * action,
1043 struct lp_build_tgsi_context * bld_base,
1044 struct lp_build_emit_data * emit_data)
1045 {
1046 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1047 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
1048 emit_data->args[0], bld_base->base.elem_type, "");
1049 }
1050
1051 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
1052 const struct tgsi_full_immediate *imm)
1053 {
1054 unsigned i;
1055 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
1056
1057 for (i = 0; i < 4; ++i) {
1058 ctx->soa.immediates[ctx->soa.num_immediates][i] =
1059 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false );
1060 }
1061
1062 ctx->soa.num_immediates++;
1063 }
1064
1065 LLVMValueRef
1066 build_intrinsic(LLVMBuilderRef builder,
1067 const char *name,
1068 LLVMTypeRef ret_type,
1069 LLVMValueRef *args,
1070 unsigned num_args,
1071 LLVMAttribute attr)
1072 {
1073 LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
1074 LLVMValueRef function;
1075
1076 function = LLVMGetNamedFunction(module, name);
1077 if(!function) {
1078 LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
1079 unsigned i;
1080
1081 assert(num_args <= LP_MAX_FUNC_ARGS);
1082
1083 for(i = 0; i < num_args; ++i) {
1084 assert(args[i]);
1085 arg_types[i] = LLVMTypeOf(args[i]);
1086 }
1087
1088 function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
1089
1090 if (attr)
1091 LLVMAddFunctionAttr(function, attr);
1092 }
1093
1094 return LLVMBuildCall(builder, function, args, num_args, "");
1095 }
1096
1097 static void build_tgsi_intrinsic(
1098 const struct lp_build_tgsi_action * action,
1099 struct lp_build_tgsi_context * bld_base,
1100 struct lp_build_emit_data * emit_data,
1101 LLVMAttribute attr)
1102 {
1103 struct lp_build_context * base = &bld_base->base;
1104 emit_data->output[emit_data->chan] = build_intrinsic(
1105 base->gallivm->builder, action->intr_name,
1106 emit_data->dst_type, emit_data->args,
1107 emit_data->arg_count, attr);
1108 }
1109 void
1110 build_tgsi_intrinsic_nomem(
1111 const struct lp_build_tgsi_action * action,
1112 struct lp_build_tgsi_context * bld_base,
1113 struct lp_build_emit_data * emit_data)
1114 {
1115 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadNoneAttribute);
1116 }
1117
1118 static void build_tgsi_intrinsic_readonly(
1119 const struct lp_build_tgsi_action * action,
1120 struct lp_build_tgsi_context * bld_base,
1121 struct lp_build_emit_data * emit_data)
1122 {
1123 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadOnlyAttribute);
1124 }
1125
1126 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
1127 {
1128 struct lp_type type;
1129
1130 /* Initialize the gallivm object:
1131 * We are only using the module, context, and builder fields of this struct.
1132 * This should be enough for us to be able to pass our gallivm struct to the
1133 * helper functions in the gallivm module.
1134 */
1135 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
1136 memset(&ctx->soa, 0, sizeof(ctx->soa));
1137 ctx->gallivm.context = LLVMContextCreate();
1138 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
1139 ctx->gallivm.context);
1140 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
1141
1142 ctx->store_output_intr = "llvm.AMDGPU.store.output.";
1143 ctx->swizzle_intr = "llvm.AMDGPU.swizzle";
1144 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1145
1146 /* XXX: We need to revisit this.I think the correct way to do this is
1147 * to use length = 4 here and use the elem_bld for everything. */
1148 type.floating = TRUE;
1149 type.sign = TRUE;
1150 type.width = 32;
1151 type.length = 1;
1152
1153 lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1154 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1155 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1156
1157 bld_base->soa = 1;
1158 bld_base->emit_store = emit_store;
1159 bld_base->emit_swizzle = emit_swizzle;
1160 bld_base->emit_declaration = emit_declaration;
1161 bld_base->emit_immediate = emit_immediate;
1162
1163 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch;
1164 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch;
1165 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch;
1166 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch;
1167 bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = fetch_system_value;
1168
1169 /* Allocate outputs */
1170 ctx->soa.outputs = ctx->outputs;
1171
1172 ctx->num_arrays = 0;
1173
1174 /* XXX: Is there a better way to initialize all this ? */
1175
1176 lp_set_default_actions(bld_base);
1177
1178 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
1179 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
1180 bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
1181 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1182 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1183 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1184 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
1185 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
1186 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1187 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
1188 bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
1189 bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
1190 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1191 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly;
1192 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
1193 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
1194 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
1195 bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
1196 bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
1197 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1198 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1199 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1200 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1201 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
1202 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_readonly;
1203 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
1204 bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
1205 bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
1206 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1207 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1208 bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
1209 bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
1210 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1211 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1212 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1213 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
1214 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
1215 bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
1216 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1217 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1218 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1219 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1220 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1221 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1222 bld_base->op_actions[TGSI_OPCODE_KIL].emit = kil_emit;
1223 bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill";
1224 bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic;
1225 bld_base->op_actions[TGSI_OPCODE_KILP].intr_name = "llvm.AMDGPU.kilp";
1226 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_readonly;
1227 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
1228 bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
1229 bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
1230 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1231 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1232 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1233 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly;
1234 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
1235 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1236 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
1237 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
1238 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
1239 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1240 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
1241 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
1242 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
1243 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
1244 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly;
1245 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
1246 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1247 bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
1248 bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
1249 bld_base->op_actions[TGSI_OPCODE_TEX2].fetch_args = tex_fetch_args;
1250 bld_base->op_actions[TGSI_OPCODE_TEX2].intr_name = "llvm.AMDGPU.tex";
1251 bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
1252 bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
1253 bld_base->op_actions[TGSI_OPCODE_TXB2].fetch_args = tex_fetch_args;
1254 bld_base->op_actions[TGSI_OPCODE_TXB2].intr_name = "llvm.AMDGPU.txb";
1255 bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
1256 bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
1257 bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
1258 bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
1259 bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
1260 bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
1261 bld_base->op_actions[TGSI_OPCODE_TXL2].fetch_args = tex_fetch_args;
1262 bld_base->op_actions[TGSI_OPCODE_TXL2].intr_name = "llvm.AMDGPU.txl";
1263 bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
1264 bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
1265 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
1266 bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
1267 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1268 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
1269 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1270 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1271 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
1272 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
1273 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
1274 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
1275 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1276 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1277 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1278 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1279 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1280 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1281 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1282 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1283 bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
1284
1285 bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
1286 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
1287 }
1288
1289 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
1290 LLVMTypeRef *ParamTypes, unsigned ParamCount)
1291 {
1292 LLVMTypeRef main_fn_type;
1293 LLVMBasicBlockRef main_fn_body;
1294
1295 /* Setup the function */
1296 main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context),
1297 ParamTypes, ParamCount, 0);
1298 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1299 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1300 ctx->main_fn, "main_body");
1301 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1302 }
1303
1304 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1305 {
1306 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1307 /* End the main function with Return*/
1308 LLVMBuildRetVoid(gallivm->builder);
1309
1310 /* Create the pass manager */
1311 ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule(
1312 gallivm->module);
1313
1314 /* This pass should eliminate all the load and store instructions */
1315 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1316
1317 /* Add some optimization passes */
1318 LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1319 LLVMAddLICMPass(gallivm->passmgr);
1320 LLVMAddAggressiveDCEPass(gallivm->passmgr);
1321 LLVMAddCFGSimplificationPass(gallivm->passmgr);
1322
1323 /* Run the passs */
1324 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1325
1326 LLVMDisposeBuilder(gallivm->builder);
1327 LLVMDisposePassManager(gallivm->passmgr);
1328
1329 }
1330
1331 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1332 {
1333 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1334 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1335 }