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[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26 #include "radeon_llvm.h"
27
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
42
43 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
44 {
45 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
46 }
47
48 static struct radeon_llvm_branch * get_current_branch(
49 struct radeon_llvm_context * ctx)
50 {
51 return ctx->branch_depth > 0 ?
52 ctx->branch + (ctx->branch_depth - 1) : NULL;
53 }
54
55 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
56 {
57 return (index * 4) + chan;
58 }
59
60 static LLVMValueRef emit_swizzle(
61 struct lp_build_tgsi_context * bld_base,
62 LLVMValueRef value,
63 unsigned swizzle_x,
64 unsigned swizzle_y,
65 unsigned swizzle_z,
66 unsigned swizzle_w)
67 {
68 LLVMValueRef swizzles[4];
69 LLVMTypeRef i32t =
70 LLVMInt32TypeInContext(bld_base->base.gallivm->context);
71
72 swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0);
73 swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0);
74 swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0);
75 swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0);
76
77 return LLVMBuildShuffleVector(bld_base->base.gallivm->builder,
78 value,
79 LLVMGetUndef(LLVMTypeOf(value)),
80 LLVMConstVector(swizzles, 4), "");
81 }
82
83 static struct tgsi_declaration_range
84 get_array_range(struct lp_build_tgsi_context *bld_base,
85 unsigned File, const struct tgsi_ind_register *reg)
86 {
87 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
88 if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 ||
89 reg->ArrayID > RADEON_LLVM_MAX_ARRAYS) {
90 struct tgsi_declaration_range range;
91 range.First = 0;
92 range.Last = bld_base->info->file_max[File];
93 return range;
94 }
95
96 return ctx->arrays[reg->ArrayID - 1];
97 }
98
99 static LLVMValueRef
100 emit_array_index(
101 struct lp_build_tgsi_soa_context *bld,
102 const struct tgsi_ind_register *reg,
103 unsigned offset)
104 {
105 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
106
107 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, bld->addr[reg->Index][reg->Swizzle], "");
108 return LLVMBuildAdd(gallivm->builder, addr, lp_build_const_int32(gallivm, offset), "");
109 }
110
111 static LLVMValueRef
112 emit_fetch(
113 struct lp_build_tgsi_context *bld_base,
114 const struct tgsi_full_src_register *reg,
115 enum tgsi_opcode_type type,
116 unsigned swizzle);
117
118 static LLVMValueRef
119 emit_array_fetch(
120 struct lp_build_tgsi_context *bld_base,
121 unsigned File, enum tgsi_opcode_type type,
122 struct tgsi_declaration_range range,
123 unsigned swizzle)
124 {
125 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
126 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
127 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
128
129 unsigned i, size = range.Last - range.First + 1;
130 LLVMTypeRef vec = LLVMVectorType(tgsi2llvmtype(bld_base, type), size);
131 LLVMValueRef result = LLVMGetUndef(vec);
132
133 struct tgsi_full_src_register tmp_reg = {};
134 tmp_reg.Register.File = File;
135
136 for (i = 0; i < size; ++i) {
137 tmp_reg.Register.Index = i + range.First;
138 LLVMValueRef temp = emit_fetch(bld_base, &tmp_reg, type, swizzle);
139 result = LLVMBuildInsertElement(builder, result, temp,
140 lp_build_const_int32(gallivm, i), "");
141 }
142 return result;
143 }
144
145 static bool uses_temp_indirect_addressing(
146 struct lp_build_tgsi_context *bld_base)
147 {
148 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
149 return (bld->indirect_files & (1 << TGSI_FILE_TEMPORARY));
150 }
151
152 static LLVMValueRef
153 emit_fetch(
154 struct lp_build_tgsi_context *bld_base,
155 const struct tgsi_full_src_register *reg,
156 enum tgsi_opcode_type type,
157 unsigned swizzle)
158 {
159 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
160 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
161 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
162 LLVMValueRef result, ptr;
163
164 if (swizzle == ~0) {
165 LLVMValueRef values[TGSI_NUM_CHANNELS];
166 unsigned chan;
167 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
168 values[chan] = emit_fetch(bld_base, reg, type, chan);
169 }
170 return lp_build_gather_values(bld_base->base.gallivm, values,
171 TGSI_NUM_CHANNELS);
172 }
173
174 if (reg->Register.Indirect) {
175 struct tgsi_declaration_range range = get_array_range(bld_base,
176 reg->Register.File, &reg->Indirect);
177 return LLVMBuildExtractElement(builder,
178 emit_array_fetch(bld_base, reg->Register.File, type, range, swizzle),
179 emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First),
180 "");
181 }
182
183 switch(reg->Register.File) {
184 case TGSI_FILE_IMMEDIATE: {
185 LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type);
186 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
187 }
188
189 case TGSI_FILE_INPUT:
190 result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)];
191 break;
192
193 case TGSI_FILE_TEMPORARY:
194 if (uses_temp_indirect_addressing(bld_base)) {
195 ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
196 break;
197 }
198 ptr = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle];
199 result = LLVMBuildLoad(builder, ptr, "");
200 break;
201
202 case TGSI_FILE_OUTPUT:
203 ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
204 result = LLVMBuildLoad(builder, ptr, "");
205 break;
206
207 default:
208 return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
209 }
210
211 return bitcast(bld_base, type, result);
212 }
213
214 static LLVMValueRef fetch_system_value(
215 struct lp_build_tgsi_context * bld_base,
216 const struct tgsi_full_src_register *reg,
217 enum tgsi_opcode_type type,
218 unsigned swizzle)
219 {
220 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
221 LLVMValueRef cval = ctx->system_values[reg->Register.Index];
222 return bitcast(bld_base, type, cval);
223 }
224
225 static void emit_declaration(
226 struct lp_build_tgsi_context * bld_base,
227 const struct tgsi_full_declaration *decl)
228 {
229 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
230 unsigned first, last, i, idx;
231 switch(decl->Declaration.File) {
232 case TGSI_FILE_ADDRESS:
233 {
234 unsigned idx;
235 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
236 unsigned chan;
237 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
238 ctx->soa.addr[idx][chan] = lp_build_alloca(
239 &ctx->gallivm,
240 ctx->soa.bld_base.uint_bld.elem_type, "");
241 }
242 }
243 break;
244 }
245
246 case TGSI_FILE_TEMPORARY:
247 if (decl->Declaration.Array && decl->Array.ArrayID <= RADEON_LLVM_MAX_ARRAYS)
248 ctx->arrays[decl->Array.ArrayID - 1] = decl->Range;
249 if (uses_temp_indirect_addressing(bld_base)) {
250 lp_emit_declaration_soa(bld_base, decl);
251 break;
252 }
253 first = decl->Range.First;
254 last = decl->Range.Last;
255 if (!ctx->temps_count) {
256 ctx->temps_count = bld_base->info->file_max[TGSI_FILE_TEMPORARY] + 1;
257 ctx->temps = MALLOC(TGSI_NUM_CHANNELS * ctx->temps_count * sizeof(LLVMValueRef));
258 }
259 for (idx = first; idx <= last; idx++) {
260 for (i = 0; i < TGSI_NUM_CHANNELS; i++) {
261 ctx->temps[idx * TGSI_NUM_CHANNELS + i] =
262 lp_build_alloca(bld_base->base.gallivm, bld_base->base.vec_type,
263 "temp");
264 }
265 }
266 break;
267
268 case TGSI_FILE_INPUT:
269 {
270 unsigned idx;
271 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
272 ctx->load_input(ctx, idx, decl);
273 }
274 }
275 break;
276
277 case TGSI_FILE_SYSTEM_VALUE:
278 {
279 unsigned idx;
280 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
281 ctx->load_system_value(ctx, idx, decl);
282 }
283 }
284 break;
285
286 case TGSI_FILE_OUTPUT:
287 {
288 unsigned idx;
289 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
290 unsigned chan;
291 assert(idx < RADEON_LLVM_MAX_OUTPUTS);
292 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
293 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm,
294 ctx->soa.bld_base.base.elem_type, "");
295 }
296 }
297
298 ctx->output_reg_count = MAX2(ctx->output_reg_count,
299 decl->Range.Last + 1);
300 break;
301 }
302
303 default:
304 break;
305 }
306 }
307
308 static void
309 emit_store(
310 struct lp_build_tgsi_context * bld_base,
311 const struct tgsi_full_instruction * inst,
312 const struct tgsi_opcode_info * info,
313 LLVMValueRef dst[4])
314 {
315 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
316 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
317 struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
318 struct lp_build_context base = bld->bld_base.base;
319 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
320 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
321 LLVMValueRef temp_ptr;
322 unsigned chan, chan_index;
323 boolean is_vec_store = FALSE;
324
325 if (dst[0]) {
326 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
327 is_vec_store = (k == LLVMVectorTypeKind);
328 }
329
330 if (is_vec_store) {
331 LLVMValueRef values[4] = {};
332 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
333 LLVMValueRef index = lp_build_const_int32(gallivm, chan);
334 values[chan] = LLVMBuildExtractElement(gallivm->builder,
335 dst[0], index, "");
336 }
337 bld_base->emit_store(bld_base, inst, info, values);
338 return;
339 }
340
341 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
342 LLVMValueRef value = dst[chan_index];
343
344 if (inst->Instruction.Saturate != TGSI_SAT_NONE) {
345 struct lp_build_emit_data clamp_emit_data;
346
347 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
348 clamp_emit_data.arg_count = 3;
349 clamp_emit_data.args[0] = value;
350 clamp_emit_data.args[2] = base.one;
351
352 switch(inst->Instruction.Saturate) {
353 case TGSI_SAT_ZERO_ONE:
354 clamp_emit_data.args[1] = base.zero;
355 break;
356 case TGSI_SAT_MINUS_PLUS_ONE:
357 clamp_emit_data.args[1] = LLVMConstReal(
358 base.elem_type, -1.0f);
359 break;
360 default:
361 assert(0);
362 }
363 value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
364 &clamp_emit_data);
365 }
366
367 if (reg->Register.File == TGSI_FILE_ADDRESS) {
368 temp_ptr = bld->addr[reg->Register.Index][chan_index];
369 LLVMBuildStore(builder, value, temp_ptr);
370 continue;
371 }
372
373 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
374
375 if (reg->Register.Indirect) {
376 struct tgsi_declaration_range range = get_array_range(bld_base,
377 reg->Register.File, &reg->Indirect);
378
379 unsigned i, size = range.Last - range.First + 1;
380 LLVMValueRef array = LLVMBuildInsertElement(builder,
381 emit_array_fetch(bld_base, reg->Register.File, TGSI_TYPE_FLOAT, range, chan_index),
382 value, emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First), "");
383
384 for (i = 0; i < size; ++i) {
385 switch(reg->Register.File) {
386 case TGSI_FILE_OUTPUT:
387 temp_ptr = bld->outputs[i + range.First][chan_index];
388 break;
389
390 case TGSI_FILE_TEMPORARY:
391 if (uses_temp_indirect_addressing(bld_base))
392 temp_ptr = lp_get_temp_ptr_soa(bld, i + range.First, chan_index);
393 else
394 temp_ptr = ctx->temps[(i + range.First) * TGSI_NUM_CHANNELS + chan_index];
395 break;
396
397 default:
398 return;
399 }
400 value = LLVMBuildExtractElement(builder, array,
401 lp_build_const_int32(gallivm, i), "");
402 LLVMBuildStore(builder, value, temp_ptr);
403 }
404
405 } else {
406 switch(reg->Register.File) {
407 case TGSI_FILE_OUTPUT:
408 temp_ptr = bld->outputs[reg->Register.Index][chan_index];
409 break;
410
411 case TGSI_FILE_TEMPORARY:
412 if (uses_temp_indirect_addressing(bld_base))
413 break;
414 temp_ptr = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index];
415 break;
416
417 default:
418 return;
419 }
420 LLVMBuildStore(builder, value, temp_ptr);
421 }
422 }
423 }
424
425 static void bgnloop_emit(
426 const struct lp_build_tgsi_action * action,
427 struct lp_build_tgsi_context * bld_base,
428 struct lp_build_emit_data * emit_data)
429 {
430 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
431 struct gallivm_state * gallivm = bld_base->base.gallivm;
432 LLVMBasicBlockRef loop_block;
433 LLVMBasicBlockRef endloop_block;
434 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
435 ctx->main_fn, "ENDLOOP");
436 loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
437 endloop_block, "LOOP");
438 LLVMBuildBr(gallivm->builder, loop_block);
439 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
440 ctx->loop_depth++;
441 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
442 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
443 }
444
445 static void brk_emit(
446 const struct lp_build_tgsi_action * action,
447 struct lp_build_tgsi_context * bld_base,
448 struct lp_build_emit_data * emit_data)
449 {
450 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
451 struct gallivm_state * gallivm = bld_base->base.gallivm;
452 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
453
454 LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
455 }
456
457 static void cont_emit(
458 const struct lp_build_tgsi_action * action,
459 struct lp_build_tgsi_context * bld_base,
460 struct lp_build_emit_data * emit_data)
461 {
462 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
463 struct gallivm_state * gallivm = bld_base->base.gallivm;
464 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
465
466 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
467 }
468
469 static void else_emit(
470 const struct lp_build_tgsi_action * action,
471 struct lp_build_tgsi_context * bld_base,
472 struct lp_build_emit_data * emit_data)
473 {
474 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
475 struct gallivm_state * gallivm = bld_base->base.gallivm;
476 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
477 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
478
479 /* We need to add a terminator to the current block if the previous
480 * instruction was an ENDIF.Example:
481 * IF
482 * [code]
483 * IF
484 * [code]
485 * ELSE
486 * [code]
487 * ENDIF <--
488 * ELSE<--
489 * [code]
490 * ENDIF
491 */
492
493 if (current_block != current_branch->if_block) {
494 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
495 }
496 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
497 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
498 }
499 current_branch->has_else = 1;
500 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
501 }
502
503 static void endif_emit(
504 const struct lp_build_tgsi_action * action,
505 struct lp_build_tgsi_context * bld_base,
506 struct lp_build_emit_data * emit_data)
507 {
508 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
509 struct gallivm_state * gallivm = bld_base->base.gallivm;
510 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
511 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
512
513 /* If we have consecutive ENDIF instructions, then the first ENDIF
514 * will not have a terminator, so we need to add one. */
515 if (current_block != current_branch->if_block
516 && current_block != current_branch->else_block
517 && !LLVMGetBasicBlockTerminator(current_block)) {
518
519 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
520 }
521 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
522 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
523 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
524 }
525
526 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
527 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
528 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
529 }
530
531 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
532 ctx->branch_depth--;
533 }
534
535 static void endloop_emit(
536 const struct lp_build_tgsi_action * action,
537 struct lp_build_tgsi_context * bld_base,
538 struct lp_build_emit_data * emit_data)
539 {
540 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
541 struct gallivm_state * gallivm = bld_base->base.gallivm;
542 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
543
544 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
545 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
546 }
547
548 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
549 ctx->loop_depth--;
550 }
551
552 static void if_cond_emit(
553 const struct lp_build_tgsi_action * action,
554 struct lp_build_tgsi_context * bld_base,
555 struct lp_build_emit_data * emit_data,
556 LLVMValueRef cond)
557 {
558 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
559 struct gallivm_state * gallivm = bld_base->base.gallivm;
560 LLVMBasicBlockRef if_block, else_block, endif_block;
561
562 endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
563 ctx->main_fn, "ENDIF");
564 if_block = LLVMInsertBasicBlockInContext(gallivm->context,
565 endif_block, "IF");
566 else_block = LLVMInsertBasicBlockInContext(gallivm->context,
567 endif_block, "ELSE");
568 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
569 LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
570
571 ctx->branch_depth++;
572 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
573 ctx->branch[ctx->branch_depth - 1].if_block = if_block;
574 ctx->branch[ctx->branch_depth - 1].else_block = else_block;
575 ctx->branch[ctx->branch_depth - 1].has_else = 0;
576 }
577
578 static void if_emit(
579 const struct lp_build_tgsi_action * action,
580 struct lp_build_tgsi_context * bld_base,
581 struct lp_build_emit_data * emit_data)
582 {
583 struct gallivm_state * gallivm = bld_base->base.gallivm;
584 LLVMValueRef cond;
585
586 cond = LLVMBuildFCmp(gallivm->builder, LLVMRealUNE,
587 emit_data->args[0],
588 bld_base->base.zero, "");
589
590 if_cond_emit(action, bld_base, emit_data, cond);
591 }
592
593 static void uif_emit(
594 const struct lp_build_tgsi_action * action,
595 struct lp_build_tgsi_context * bld_base,
596 struct lp_build_emit_data * emit_data)
597 {
598 struct gallivm_state * gallivm = bld_base->base.gallivm;
599 LLVMValueRef cond;
600
601 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
602 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
603 bld_base->int_bld.zero, "");
604
605 if_cond_emit(action, bld_base, emit_data, cond);
606 }
607
608 static void kil_emit(
609 const struct lp_build_tgsi_action * action,
610 struct lp_build_tgsi_context * bld_base,
611 struct lp_build_emit_data * emit_data)
612 {
613 unsigned i;
614 for (i = 0; i < emit_data->arg_count; i++) {
615 emit_data->output[i] = lp_build_intrinsic_unary(
616 bld_base->base.gallivm->builder,
617 action->intr_name,
618 emit_data->dst_type, emit_data->args[i]);
619 }
620 }
621
622 void radeon_llvm_emit_prepare_cube_coords(
623 struct lp_build_tgsi_context * bld_base,
624 struct lp_build_emit_data * emit_data,
625 LLVMValueRef *coords_arg)
626 {
627
628 unsigned target = emit_data->inst->Texture.Texture;
629 unsigned opcode = emit_data->inst->Instruction.Opcode;
630 struct gallivm_state * gallivm = bld_base->base.gallivm;
631 LLVMBuilderRef builder = gallivm->builder;
632 LLVMTypeRef type = bld_base->base.elem_type;
633 LLVMValueRef coords[4];
634 LLVMValueRef mad_args[3];
635 LLVMValueRef idx;
636 struct LLVMOpaqueValue *cube_vec;
637 LLVMValueRef v;
638 unsigned i;
639
640 cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
641 v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
642 &cube_vec, 1, LLVMReadNoneAttribute);
643
644 for (i = 0; i < 4; ++i) {
645 idx = lp_build_const_int32(gallivm, i);
646 coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
647 }
648
649 coords[2] = build_intrinsic(builder, "fabs",
650 type, &coords[2], 1, LLVMReadNoneAttribute);
651 coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]);
652
653 mad_args[1] = coords[2];
654 mad_args[2] = LLVMConstReal(type, 1.5);
655
656 mad_args[0] = coords[0];
657 coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
658 mad_args[0], mad_args[1], mad_args[2]);
659
660 mad_args[0] = coords[1];
661 coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
662 mad_args[0], mad_args[1], mad_args[2]);
663
664 /* apply xyz = yxw swizzle to cooords */
665 coords[2] = coords[3];
666 coords[3] = coords[1];
667 coords[1] = coords[0];
668 coords[0] = coords[3];
669
670 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
671 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
672 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
673 /* coords_arg.w component - array_index for cube arrays */
674 coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
675 coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
676 }
677
678 /* Preserve compare/lod/bias. Put it in coords.w. */
679 if (opcode == TGSI_OPCODE_TEX2 ||
680 opcode == TGSI_OPCODE_TXB2 ||
681 opcode == TGSI_OPCODE_TXL2) {
682 coords[3] = coords_arg[4];
683 } else if (opcode == TGSI_OPCODE_TXB ||
684 opcode == TGSI_OPCODE_TXL ||
685 target == TGSI_TEXTURE_SHADOWCUBE) {
686 coords[3] = coords_arg[3];
687 }
688
689 memcpy(coords_arg, coords, sizeof(coords));
690 }
691
692 static void txd_fetch_args(
693 struct lp_build_tgsi_context * bld_base,
694 struct lp_build_emit_data * emit_data)
695 {
696 const struct tgsi_full_instruction * inst = emit_data->inst;
697
698 LLVMValueRef coords[4];
699 unsigned chan, src;
700 for (src = 0; src < 3; src++) {
701 for (chan = 0; chan < 4; chan++)
702 coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan);
703
704 emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm,
705 coords, 4);
706 }
707 emit_data->arg_count = 3;
708 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
709 }
710
711
712 static void txp_fetch_args(
713 struct lp_build_tgsi_context * bld_base,
714 struct lp_build_emit_data * emit_data)
715 {
716 const struct tgsi_full_instruction * inst = emit_data->inst;
717 LLVMValueRef src_w;
718 unsigned chan;
719 LLVMValueRef coords[4];
720
721 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
722 src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
723
724 for (chan = 0; chan < 3; chan++ ) {
725 LLVMValueRef arg = lp_build_emit_fetch(bld_base,
726 emit_data->inst, 0, chan);
727 coords[chan] = lp_build_emit_llvm_binary(bld_base,
728 TGSI_OPCODE_DIV, arg, src_w);
729 }
730 coords[3] = bld_base->base.one;
731
732 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
733 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
734 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
735 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
736 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
737 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
738 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
739 }
740
741 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
742 coords, 4);
743 emit_data->arg_count = 1;
744 }
745
746 static void tex_fetch_args(
747 struct lp_build_tgsi_context * bld_base,
748 struct lp_build_emit_data * emit_data)
749 {
750 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
751 * when we used CHAN_ALL. We should be able to get this to work,
752 * but for now we will swizzle it ourselves
753 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
754 0, CHAN_ALL);
755
756 */
757
758 const struct tgsi_full_instruction * inst = emit_data->inst;
759
760 LLVMValueRef coords[5];
761 unsigned chan;
762 for (chan = 0; chan < 4; chan++) {
763 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
764 }
765
766 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
767 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
768 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
769 /* These instructions have additional operand that should be packed
770 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
771 * That operand should be passed as a float value in the args array
772 * right after the coord vector. After packing it's not used anymore,
773 * that's why arg_count is not increased */
774 coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
775 }
776
777 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
778 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
779 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
780 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
781 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
782 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
783 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
784 }
785
786 emit_data->arg_count = 1;
787 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
788 coords, 4);
789 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
790 }
791
792 static void txf_fetch_args(
793 struct lp_build_tgsi_context * bld_base,
794 struct lp_build_emit_data * emit_data)
795 {
796 const struct tgsi_full_instruction * inst = emit_data->inst;
797 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
798 const struct tgsi_texture_offset * off = inst->TexOffsets;
799 LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
800
801 /* fetch tex coords */
802 tex_fetch_args(bld_base, emit_data);
803
804 /* fetch tex offsets */
805 if (inst->Texture.NumOffsets) {
806 assert(inst->Texture.NumOffsets == 1);
807
808 emit_data->args[1] = LLVMConstBitCast(
809 bld->immediates[off->Index][off->SwizzleX],
810 offset_type);
811 emit_data->args[2] = LLVMConstBitCast(
812 bld->immediates[off->Index][off->SwizzleY],
813 offset_type);
814 emit_data->args[3] = LLVMConstBitCast(
815 bld->immediates[off->Index][off->SwizzleZ],
816 offset_type);
817 } else {
818 emit_data->args[1] = bld_base->int_bld.zero;
819 emit_data->args[2] = bld_base->int_bld.zero;
820 emit_data->args[3] = bld_base->int_bld.zero;
821 }
822
823 emit_data->arg_count = 4;
824 }
825
826 static void emit_icmp(
827 const struct lp_build_tgsi_action * action,
828 struct lp_build_tgsi_context * bld_base,
829 struct lp_build_emit_data * emit_data)
830 {
831 unsigned pred;
832 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
833 LLVMContextRef context = bld_base->base.gallivm->context;
834
835 switch (emit_data->inst->Instruction.Opcode) {
836 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
837 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
838 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
839 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
840 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
841 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
842 default:
843 assert(!"unknown instruction");
844 pred = 0;
845 break;
846 }
847
848 LLVMValueRef v = LLVMBuildICmp(builder, pred,
849 emit_data->args[0], emit_data->args[1],"");
850
851 v = LLVMBuildSExtOrBitCast(builder, v,
852 LLVMInt32TypeInContext(context), "");
853
854 emit_data->output[emit_data->chan] = v;
855 }
856
857 static void emit_ucmp(
858 const struct lp_build_tgsi_action * action,
859 struct lp_build_tgsi_context * bld_base,
860 struct lp_build_emit_data * emit_data)
861 {
862 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
863
864 LLVMValueRef arg0 = LLVMBuildBitCast(builder, emit_data->args[0],
865 bld_base->uint_bld.elem_type, "");
866
867 LLVMValueRef v = LLVMBuildICmp(builder, LLVMIntNE, arg0,
868 bld_base->uint_bld.zero, "");
869
870 emit_data->output[emit_data->chan] =
871 LLVMBuildSelect(builder, v, emit_data->args[1], emit_data->args[2], "");
872 }
873
874 static void emit_cmp(
875 const struct lp_build_tgsi_action *action,
876 struct lp_build_tgsi_context * bld_base,
877 struct lp_build_emit_data * emit_data)
878 {
879 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
880 LLVMRealPredicate pred;
881 LLVMValueRef cond;
882
883 /* Use ordered for everything but NE (which is usual for
884 * float comparisons)
885 */
886 switch (emit_data->inst->Instruction.Opcode) {
887 case TGSI_OPCODE_SGE: pred = LLVMRealOGE; break;
888 case TGSI_OPCODE_SEQ: pred = LLVMRealOEQ; break;
889 case TGSI_OPCODE_SLE: pred = LLVMRealOLE; break;
890 case TGSI_OPCODE_SLT: pred = LLVMRealOLT; break;
891 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
892 case TGSI_OPCODE_SGT: pred = LLVMRealOGT; break;
893 default: assert(!"unknown instruction"); pred = 0; break;
894 }
895
896 cond = LLVMBuildFCmp(builder,
897 pred, emit_data->args[0], emit_data->args[1], "");
898
899 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
900 cond, bld_base->base.one, bld_base->base.zero, "");
901 }
902
903 static void emit_fcmp(
904 const struct lp_build_tgsi_action *action,
905 struct lp_build_tgsi_context * bld_base,
906 struct lp_build_emit_data * emit_data)
907 {
908 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
909 LLVMContextRef context = bld_base->base.gallivm->context;
910 LLVMRealPredicate pred;
911
912 /* Use ordered for everything but NE (which is usual for
913 * float comparisons)
914 */
915 switch (emit_data->inst->Instruction.Opcode) {
916 case TGSI_OPCODE_FSEQ: pred = LLVMRealOEQ; break;
917 case TGSI_OPCODE_FSGE: pred = LLVMRealOGE; break;
918 case TGSI_OPCODE_FSLT: pred = LLVMRealOLT; break;
919 case TGSI_OPCODE_FSNE: pred = LLVMRealUNE; break;
920 default: assert(!"unknown instruction"); pred = 0; break;
921 }
922
923 LLVMValueRef v = LLVMBuildFCmp(builder, pred,
924 emit_data->args[0], emit_data->args[1],"");
925
926 v = LLVMBuildSExtOrBitCast(builder, v,
927 LLVMInt32TypeInContext(context), "");
928
929 emit_data->output[emit_data->chan] = v;
930 }
931
932 static void emit_not(
933 const struct lp_build_tgsi_action * action,
934 struct lp_build_tgsi_context * bld_base,
935 struct lp_build_emit_data * emit_data)
936 {
937 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
938 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
939 emit_data->args[0]);
940 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
941 }
942
943 static void emit_arl(
944 const struct lp_build_tgsi_action * action,
945 struct lp_build_tgsi_context * bld_base,
946 struct lp_build_emit_data * emit_data)
947 {
948 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
949 LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
950 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
951 floor_index, bld_base->base.int_elem_type , "");
952 }
953
954 static void emit_and(
955 const struct lp_build_tgsi_action * action,
956 struct lp_build_tgsi_context * bld_base,
957 struct lp_build_emit_data * emit_data)
958 {
959 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
960 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
961 emit_data->args[0], emit_data->args[1], "");
962 }
963
964 static void emit_or(
965 const struct lp_build_tgsi_action * action,
966 struct lp_build_tgsi_context * bld_base,
967 struct lp_build_emit_data * emit_data)
968 {
969 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
970 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
971 emit_data->args[0], emit_data->args[1], "");
972 }
973
974 static void emit_uadd(
975 const struct lp_build_tgsi_action * action,
976 struct lp_build_tgsi_context * bld_base,
977 struct lp_build_emit_data * emit_data)
978 {
979 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
980 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
981 emit_data->args[0], emit_data->args[1], "");
982 }
983
984 static void emit_udiv(
985 const struct lp_build_tgsi_action * action,
986 struct lp_build_tgsi_context * bld_base,
987 struct lp_build_emit_data * emit_data)
988 {
989 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
990 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
991 emit_data->args[0], emit_data->args[1], "");
992 }
993
994 static void emit_idiv(
995 const struct lp_build_tgsi_action * action,
996 struct lp_build_tgsi_context * bld_base,
997 struct lp_build_emit_data * emit_data)
998 {
999 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1000 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
1001 emit_data->args[0], emit_data->args[1], "");
1002 }
1003
1004 static void emit_mod(
1005 const struct lp_build_tgsi_action * action,
1006 struct lp_build_tgsi_context * bld_base,
1007 struct lp_build_emit_data * emit_data)
1008 {
1009 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1010 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
1011 emit_data->args[0], emit_data->args[1], "");
1012 }
1013
1014 static void emit_umod(
1015 const struct lp_build_tgsi_action * action,
1016 struct lp_build_tgsi_context * bld_base,
1017 struct lp_build_emit_data * emit_data)
1018 {
1019 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1020 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
1021 emit_data->args[0], emit_data->args[1], "");
1022 }
1023
1024 static void emit_shl(
1025 const struct lp_build_tgsi_action * action,
1026 struct lp_build_tgsi_context * bld_base,
1027 struct lp_build_emit_data * emit_data)
1028 {
1029 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1030 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
1031 emit_data->args[0], emit_data->args[1], "");
1032 }
1033
1034 static void emit_ushr(
1035 const struct lp_build_tgsi_action * action,
1036 struct lp_build_tgsi_context * bld_base,
1037 struct lp_build_emit_data * emit_data)
1038 {
1039 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1040 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
1041 emit_data->args[0], emit_data->args[1], "");
1042 }
1043 static void emit_ishr(
1044 const struct lp_build_tgsi_action * action,
1045 struct lp_build_tgsi_context * bld_base,
1046 struct lp_build_emit_data * emit_data)
1047 {
1048 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1049 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
1050 emit_data->args[0], emit_data->args[1], "");
1051 }
1052
1053 static void emit_xor(
1054 const struct lp_build_tgsi_action * action,
1055 struct lp_build_tgsi_context * bld_base,
1056 struct lp_build_emit_data * emit_data)
1057 {
1058 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1059 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
1060 emit_data->args[0], emit_data->args[1], "");
1061 }
1062
1063 static void emit_ssg(
1064 const struct lp_build_tgsi_action * action,
1065 struct lp_build_tgsi_context * bld_base,
1066 struct lp_build_emit_data * emit_data)
1067 {
1068 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1069
1070 LLVMValueRef cmp, val;
1071
1072 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
1073 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
1074 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
1075 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
1076 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
1077 } else { // float SSG
1078 cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->base.zero, "");
1079 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
1080 cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, "");
1081 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
1082 }
1083
1084 emit_data->output[emit_data->chan] = val;
1085 }
1086
1087 static void emit_ineg(
1088 const struct lp_build_tgsi_action * action,
1089 struct lp_build_tgsi_context * bld_base,
1090 struct lp_build_emit_data * emit_data)
1091 {
1092 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1093 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
1094 emit_data->args[0], "");
1095 }
1096
1097 static void emit_f2i(
1098 const struct lp_build_tgsi_action * action,
1099 struct lp_build_tgsi_context * bld_base,
1100 struct lp_build_emit_data * emit_data)
1101 {
1102 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1103 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
1104 emit_data->args[0], bld_base->int_bld.elem_type, "");
1105 }
1106
1107 static void emit_f2u(
1108 const struct lp_build_tgsi_action * action,
1109 struct lp_build_tgsi_context * bld_base,
1110 struct lp_build_emit_data * emit_data)
1111 {
1112 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1113 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
1114 emit_data->args[0], bld_base->uint_bld.elem_type, "");
1115 }
1116
1117 static void emit_i2f(
1118 const struct lp_build_tgsi_action * action,
1119 struct lp_build_tgsi_context * bld_base,
1120 struct lp_build_emit_data * emit_data)
1121 {
1122 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1123 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
1124 emit_data->args[0], bld_base->base.elem_type, "");
1125 }
1126
1127 static void emit_u2f(
1128 const struct lp_build_tgsi_action * action,
1129 struct lp_build_tgsi_context * bld_base,
1130 struct lp_build_emit_data * emit_data)
1131 {
1132 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1133 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
1134 emit_data->args[0], bld_base->base.elem_type, "");
1135 }
1136
1137 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
1138 const struct tgsi_full_immediate *imm)
1139 {
1140 unsigned i;
1141 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
1142
1143 for (i = 0; i < 4; ++i) {
1144 ctx->soa.immediates[ctx->soa.num_immediates][i] =
1145 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false );
1146 }
1147
1148 ctx->soa.num_immediates++;
1149 }
1150
1151 LLVMValueRef
1152 build_intrinsic(LLVMBuilderRef builder,
1153 const char *name,
1154 LLVMTypeRef ret_type,
1155 LLVMValueRef *args,
1156 unsigned num_args,
1157 LLVMAttribute attr)
1158 {
1159 LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
1160 LLVMValueRef function;
1161
1162 function = LLVMGetNamedFunction(module, name);
1163 if(!function) {
1164 LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
1165 unsigned i;
1166
1167 assert(num_args <= LP_MAX_FUNC_ARGS);
1168
1169 for(i = 0; i < num_args; ++i) {
1170 assert(args[i]);
1171 arg_types[i] = LLVMTypeOf(args[i]);
1172 }
1173
1174 function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
1175
1176 if (attr)
1177 LLVMAddFunctionAttr(function, attr);
1178 }
1179
1180 return LLVMBuildCall(builder, function, args, num_args, "");
1181 }
1182
1183 static void build_tgsi_intrinsic(
1184 const struct lp_build_tgsi_action * action,
1185 struct lp_build_tgsi_context * bld_base,
1186 struct lp_build_emit_data * emit_data,
1187 LLVMAttribute attr)
1188 {
1189 struct lp_build_context * base = &bld_base->base;
1190 emit_data->output[emit_data->chan] = build_intrinsic(
1191 base->gallivm->builder, action->intr_name,
1192 emit_data->dst_type, emit_data->args,
1193 emit_data->arg_count, attr);
1194 }
1195 void
1196 build_tgsi_intrinsic_nomem(
1197 const struct lp_build_tgsi_action * action,
1198 struct lp_build_tgsi_context * bld_base,
1199 struct lp_build_emit_data * emit_data)
1200 {
1201 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadNoneAttribute);
1202 }
1203
1204 static void build_tgsi_intrinsic_readonly(
1205 const struct lp_build_tgsi_action * action,
1206 struct lp_build_tgsi_context * bld_base,
1207 struct lp_build_emit_data * emit_data)
1208 {
1209 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadOnlyAttribute);
1210 }
1211
1212 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
1213 {
1214 struct lp_type type;
1215
1216 /* Initialize the gallivm object:
1217 * We are only using the module, context, and builder fields of this struct.
1218 * This should be enough for us to be able to pass our gallivm struct to the
1219 * helper functions in the gallivm module.
1220 */
1221 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
1222 memset(&ctx->soa, 0, sizeof(ctx->soa));
1223 ctx->gallivm.context = LLVMContextCreate();
1224 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
1225 ctx->gallivm.context);
1226 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
1227
1228 ctx->store_output_intr = "llvm.AMDGPU.store.output.";
1229 ctx->swizzle_intr = "llvm.AMDGPU.swizzle";
1230 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1231
1232 /* XXX: We need to revisit this.I think the correct way to do this is
1233 * to use length = 4 here and use the elem_bld for everything. */
1234 type.floating = TRUE;
1235 type.fixed = FALSE;
1236 type.sign = TRUE;
1237 type.norm = FALSE;
1238 type.width = 32;
1239 type.length = 1;
1240
1241 lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1242 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1243 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1244
1245 bld_base->soa = 1;
1246 bld_base->emit_store = emit_store;
1247 bld_base->emit_swizzle = emit_swizzle;
1248 bld_base->emit_declaration = emit_declaration;
1249 bld_base->emit_immediate = emit_immediate;
1250
1251 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch;
1252 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch;
1253 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch;
1254 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch;
1255 bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = fetch_system_value;
1256
1257 /* Allocate outputs */
1258 ctx->soa.outputs = ctx->outputs;
1259
1260 ctx->num_arrays = 0;
1261
1262 /* XXX: Is there a better way to initialize all this ? */
1263
1264 lp_set_default_actions(bld_base);
1265
1266 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
1267 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
1268 bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
1269 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1270 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1271 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1272 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
1273 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
1274 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1275 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
1276 bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
1277 bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
1278 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1279 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly;
1280 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
1281 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
1282 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
1283 bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
1284 bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
1285 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1286 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1287 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1288 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1289 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
1290 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_readonly;
1291 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
1292 bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
1293 bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
1294 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1295 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1296 bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
1297 bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp;
1298 bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp;
1299 bld_base->op_actions[TGSI_OPCODE_FSNE].emit = emit_fcmp;
1300 bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
1301 bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
1302 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1303 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1304 bld_base->op_actions[TGSI_OPCODE_UIF].emit = uif_emit;
1305 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1306 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
1307 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
1308 bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
1309 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1310 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1311 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1312 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1313 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1314 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1315 bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit;
1316 bld_base->op_actions[TGSI_OPCODE_KILL_IF].intr_name = "llvm.AMDGPU.kill";
1317 bld_base->op_actions[TGSI_OPCODE_KILL].emit = lp_build_tgsi_intrinsic;
1318 bld_base->op_actions[TGSI_OPCODE_KILL].intr_name = "llvm.AMDGPU.kilp";
1319 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_readonly;
1320 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
1321 bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
1322 bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
1323 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1324 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1325 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1326 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly;
1327 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
1328 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1329 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
1330 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
1331 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
1332 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1333 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
1334 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
1335 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
1336 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
1337 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly;
1338 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
1339 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1340 bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
1341 bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
1342 bld_base->op_actions[TGSI_OPCODE_TEX2].fetch_args = tex_fetch_args;
1343 bld_base->op_actions[TGSI_OPCODE_TEX2].intr_name = "llvm.AMDGPU.tex";
1344 bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
1345 bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
1346 bld_base->op_actions[TGSI_OPCODE_TXB2].fetch_args = tex_fetch_args;
1347 bld_base->op_actions[TGSI_OPCODE_TXB2].intr_name = "llvm.AMDGPU.txb";
1348 bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
1349 bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
1350 bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
1351 bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
1352 bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
1353 bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
1354 bld_base->op_actions[TGSI_OPCODE_TXL2].fetch_args = tex_fetch_args;
1355 bld_base->op_actions[TGSI_OPCODE_TXL2].intr_name = "llvm.AMDGPU.txl";
1356 bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
1357 bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
1358 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
1359 bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
1360 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1361 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
1362 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1363 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1364 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
1365 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
1366 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
1367 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
1368 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1369 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1370 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1371 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1372 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1373 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1374 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1375 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1376 bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
1377
1378 bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
1379 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
1380 }
1381
1382 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
1383 LLVMTypeRef *ParamTypes, unsigned ParamCount)
1384 {
1385 LLVMTypeRef main_fn_type;
1386 LLVMBasicBlockRef main_fn_body;
1387
1388 /* Setup the function */
1389 main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context),
1390 ParamTypes, ParamCount, 0);
1391 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1392 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1393 ctx->main_fn, "main_body");
1394 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1395 }
1396
1397 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1398 {
1399 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1400 /* End the main function with Return*/
1401 LLVMBuildRetVoid(gallivm->builder);
1402
1403 /* Create the pass manager */
1404 ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule(
1405 gallivm->module);
1406
1407 /* This pass should eliminate all the load and store instructions */
1408 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1409
1410 /* Add some optimization passes */
1411 LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1412 LLVMAddLICMPass(gallivm->passmgr);
1413 LLVMAddAggressiveDCEPass(gallivm->passmgr);
1414 LLVMAddCFGSimplificationPass(gallivm->passmgr);
1415
1416 /* Run the pass */
1417 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1418
1419 LLVMDisposeBuilder(gallivm->builder);
1420 LLVMDisposePassManager(gallivm->passmgr);
1421
1422 }
1423
1424 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1425 {
1426 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1427 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1428 FREE(ctx->temps);
1429 }