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radeon/vce: remove RVCE_NUM_CPB_EXTRA_FRAMES
[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26 #include "radeon_llvm.h"
27
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
42
43 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
44 {
45 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
46 }
47
48 static struct radeon_llvm_branch * get_current_branch(
49 struct radeon_llvm_context * ctx)
50 {
51 return ctx->branch_depth > 0 ?
52 ctx->branch + (ctx->branch_depth - 1) : NULL;
53 }
54
55 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
56 {
57 return (index * 4) + chan;
58 }
59
60 static LLVMValueRef emit_swizzle(
61 struct lp_build_tgsi_context * bld_base,
62 LLVMValueRef value,
63 unsigned swizzle_x,
64 unsigned swizzle_y,
65 unsigned swizzle_z,
66 unsigned swizzle_w)
67 {
68 LLVMValueRef swizzles[4];
69 LLVMTypeRef i32t =
70 LLVMInt32TypeInContext(bld_base->base.gallivm->context);
71
72 swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0);
73 swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0);
74 swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0);
75 swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0);
76
77 return LLVMBuildShuffleVector(bld_base->base.gallivm->builder,
78 value,
79 LLVMGetUndef(LLVMTypeOf(value)),
80 LLVMConstVector(swizzles, 4), "");
81 }
82
83 static struct tgsi_declaration_range
84 get_array_range(struct lp_build_tgsi_context *bld_base,
85 unsigned File, const struct tgsi_ind_register *reg)
86 {
87 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
88 if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 ||
89 reg->ArrayID > RADEON_LLVM_MAX_ARRAYS) {
90 struct tgsi_declaration_range range;
91 range.First = 0;
92 range.Last = bld_base->info->file_max[File];
93 return range;
94 }
95
96 return ctx->arrays[reg->ArrayID - 1];
97 }
98
99 static LLVMValueRef
100 emit_array_index(
101 struct lp_build_tgsi_soa_context *bld,
102 const struct tgsi_ind_register *reg,
103 unsigned offset)
104 {
105 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
106
107 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, bld->addr[reg->Index][reg->Swizzle], "");
108 return LLVMBuildAdd(gallivm->builder, addr, lp_build_const_int32(gallivm, offset), "");
109 }
110
111 static LLVMValueRef
112 emit_fetch(
113 struct lp_build_tgsi_context *bld_base,
114 const struct tgsi_full_src_register *reg,
115 enum tgsi_opcode_type type,
116 unsigned swizzle);
117
118 static LLVMValueRef
119 emit_array_fetch(
120 struct lp_build_tgsi_context *bld_base,
121 unsigned File, enum tgsi_opcode_type type,
122 struct tgsi_declaration_range range,
123 unsigned swizzle)
124 {
125 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
126 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
127 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
128
129 unsigned i, size = range.Last - range.First + 1;
130 LLVMTypeRef vec = LLVMVectorType(tgsi2llvmtype(bld_base, type), size);
131 LLVMValueRef result = LLVMGetUndef(vec);
132
133 struct tgsi_full_src_register tmp_reg = {};
134 tmp_reg.Register.File = File;
135
136 for (i = 0; i < size; ++i) {
137 tmp_reg.Register.Index = i + range.First;
138 LLVMValueRef temp = emit_fetch(bld_base, &tmp_reg, type, swizzle);
139 result = LLVMBuildInsertElement(builder, result, temp,
140 lp_build_const_int32(gallivm, i), "");
141 }
142 return result;
143 }
144
145 static bool uses_temp_indirect_addressing(
146 struct lp_build_tgsi_context *bld_base)
147 {
148 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
149 return (bld->indirect_files & (1 << TGSI_FILE_TEMPORARY));
150 }
151
152 static LLVMValueRef
153 emit_fetch(
154 struct lp_build_tgsi_context *bld_base,
155 const struct tgsi_full_src_register *reg,
156 enum tgsi_opcode_type type,
157 unsigned swizzle)
158 {
159 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
160 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
161 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
162 LLVMValueRef result = NULL, ptr;
163
164 if (swizzle == ~0) {
165 LLVMValueRef values[TGSI_NUM_CHANNELS];
166 unsigned chan;
167 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
168 values[chan] = emit_fetch(bld_base, reg, type, chan);
169 }
170 return lp_build_gather_values(bld_base->base.gallivm, values,
171 TGSI_NUM_CHANNELS);
172 }
173
174 if (reg->Register.Indirect) {
175 struct tgsi_declaration_range range = get_array_range(bld_base,
176 reg->Register.File, &reg->Indirect);
177 return LLVMBuildExtractElement(builder,
178 emit_array_fetch(bld_base, reg->Register.File, type, range, swizzle),
179 emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First),
180 "");
181 }
182
183 switch(reg->Register.File) {
184 case TGSI_FILE_IMMEDIATE: {
185 LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type);
186 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
187 }
188
189 case TGSI_FILE_INPUT:
190 result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)];
191 break;
192
193 case TGSI_FILE_TEMPORARY:
194 if (uses_temp_indirect_addressing(bld_base)) {
195 ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
196 break;
197 }
198 ptr = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle];
199 result = LLVMBuildLoad(builder, ptr, "");
200 break;
201
202 case TGSI_FILE_OUTPUT:
203 ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
204 result = LLVMBuildLoad(builder, ptr, "");
205 break;
206
207 default:
208 return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
209 }
210
211 return bitcast(bld_base, type, result);
212 }
213
214 static LLVMValueRef fetch_system_value(
215 struct lp_build_tgsi_context * bld_base,
216 const struct tgsi_full_src_register *reg,
217 enum tgsi_opcode_type type,
218 unsigned swizzle)
219 {
220 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
221 LLVMValueRef cval = ctx->system_values[reg->Register.Index];
222 return bitcast(bld_base, type, cval);
223 }
224
225 static void emit_declaration(
226 struct lp_build_tgsi_context * bld_base,
227 const struct tgsi_full_declaration *decl)
228 {
229 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
230 unsigned first, last, i, idx;
231 switch(decl->Declaration.File) {
232 case TGSI_FILE_ADDRESS:
233 {
234 unsigned idx;
235 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
236 unsigned chan;
237 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
238 ctx->soa.addr[idx][chan] = lp_build_alloca(
239 &ctx->gallivm,
240 ctx->soa.bld_base.uint_bld.elem_type, "");
241 }
242 }
243 break;
244 }
245
246 case TGSI_FILE_TEMPORARY:
247 if (decl->Declaration.Array && decl->Array.ArrayID <= RADEON_LLVM_MAX_ARRAYS)
248 ctx->arrays[decl->Array.ArrayID - 1] = decl->Range;
249 if (uses_temp_indirect_addressing(bld_base)) {
250 lp_emit_declaration_soa(bld_base, decl);
251 break;
252 }
253 first = decl->Range.First;
254 last = decl->Range.Last;
255 if (!ctx->temps_count) {
256 ctx->temps_count = bld_base->info->file_max[TGSI_FILE_TEMPORARY] + 1;
257 ctx->temps = MALLOC(TGSI_NUM_CHANNELS * ctx->temps_count * sizeof(LLVMValueRef));
258 }
259 for (idx = first; idx <= last; idx++) {
260 for (i = 0; i < TGSI_NUM_CHANNELS; i++) {
261 ctx->temps[idx * TGSI_NUM_CHANNELS + i] =
262 lp_build_alloca(bld_base->base.gallivm, bld_base->base.vec_type,
263 "temp");
264 }
265 }
266 break;
267
268 case TGSI_FILE_INPUT:
269 {
270 unsigned idx;
271 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
272 ctx->load_input(ctx, idx, decl);
273 }
274 }
275 break;
276
277 case TGSI_FILE_SYSTEM_VALUE:
278 {
279 unsigned idx;
280 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
281 ctx->load_system_value(ctx, idx, decl);
282 }
283 }
284 break;
285
286 case TGSI_FILE_OUTPUT:
287 {
288 unsigned idx;
289 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
290 unsigned chan;
291 assert(idx < RADEON_LLVM_MAX_OUTPUTS);
292 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
293 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm,
294 ctx->soa.bld_base.base.elem_type, "");
295 }
296 }
297
298 ctx->output_reg_count = MAX2(ctx->output_reg_count,
299 decl->Range.Last + 1);
300 break;
301 }
302
303 default:
304 break;
305 }
306 }
307
308 static void
309 emit_store(
310 struct lp_build_tgsi_context * bld_base,
311 const struct tgsi_full_instruction * inst,
312 const struct tgsi_opcode_info * info,
313 LLVMValueRef dst[4])
314 {
315 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
316 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
317 struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
318 struct lp_build_context base = bld->bld_base.base;
319 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
320 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
321 LLVMValueRef temp_ptr;
322 unsigned chan, chan_index;
323 boolean is_vec_store = FALSE;
324
325 if (dst[0]) {
326 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
327 is_vec_store = (k == LLVMVectorTypeKind);
328 }
329
330 if (is_vec_store) {
331 LLVMValueRef values[4] = {};
332 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
333 LLVMValueRef index = lp_build_const_int32(gallivm, chan);
334 values[chan] = LLVMBuildExtractElement(gallivm->builder,
335 dst[0], index, "");
336 }
337 bld_base->emit_store(bld_base, inst, info, values);
338 return;
339 }
340
341 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
342 LLVMValueRef value = dst[chan_index];
343
344 if (inst->Instruction.Saturate != TGSI_SAT_NONE) {
345 struct lp_build_emit_data clamp_emit_data;
346
347 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
348 clamp_emit_data.arg_count = 3;
349 clamp_emit_data.args[0] = value;
350 clamp_emit_data.args[2] = base.one;
351
352 switch(inst->Instruction.Saturate) {
353 case TGSI_SAT_ZERO_ONE:
354 clamp_emit_data.args[1] = base.zero;
355 break;
356 case TGSI_SAT_MINUS_PLUS_ONE:
357 clamp_emit_data.args[1] = LLVMConstReal(
358 base.elem_type, -1.0f);
359 break;
360 default:
361 assert(0);
362 }
363 value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
364 &clamp_emit_data);
365 }
366
367 if (reg->Register.File == TGSI_FILE_ADDRESS) {
368 temp_ptr = bld->addr[reg->Register.Index][chan_index];
369 LLVMBuildStore(builder, value, temp_ptr);
370 continue;
371 }
372
373 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
374
375 if (reg->Register.Indirect) {
376 struct tgsi_declaration_range range = get_array_range(bld_base,
377 reg->Register.File, &reg->Indirect);
378
379 unsigned i, size = range.Last - range.First + 1;
380 LLVMValueRef array = LLVMBuildInsertElement(builder,
381 emit_array_fetch(bld_base, reg->Register.File, TGSI_TYPE_FLOAT, range, chan_index),
382 value, emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First), "");
383
384 for (i = 0; i < size; ++i) {
385 switch(reg->Register.File) {
386 case TGSI_FILE_OUTPUT:
387 temp_ptr = bld->outputs[i + range.First][chan_index];
388 break;
389
390 case TGSI_FILE_TEMPORARY:
391 if (uses_temp_indirect_addressing(bld_base))
392 temp_ptr = lp_get_temp_ptr_soa(bld, i + range.First, chan_index);
393 else
394 temp_ptr = ctx->temps[(i + range.First) * TGSI_NUM_CHANNELS + chan_index];
395 break;
396
397 default:
398 return;
399 }
400 value = LLVMBuildExtractElement(builder, array,
401 lp_build_const_int32(gallivm, i), "");
402 LLVMBuildStore(builder, value, temp_ptr);
403 }
404
405 } else {
406 switch(reg->Register.File) {
407 case TGSI_FILE_OUTPUT:
408 temp_ptr = bld->outputs[reg->Register.Index][chan_index];
409 break;
410
411 case TGSI_FILE_TEMPORARY:
412 if (uses_temp_indirect_addressing(bld_base)) {
413 temp_ptr = NULL;
414 break;
415 }
416 temp_ptr = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index];
417 break;
418
419 default:
420 return;
421 }
422 LLVMBuildStore(builder, value, temp_ptr);
423 }
424 }
425 }
426
427 static void bgnloop_emit(
428 const struct lp_build_tgsi_action * action,
429 struct lp_build_tgsi_context * bld_base,
430 struct lp_build_emit_data * emit_data)
431 {
432 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
433 struct gallivm_state * gallivm = bld_base->base.gallivm;
434 LLVMBasicBlockRef loop_block;
435 LLVMBasicBlockRef endloop_block;
436 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
437 ctx->main_fn, "ENDLOOP");
438 loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
439 endloop_block, "LOOP");
440 LLVMBuildBr(gallivm->builder, loop_block);
441 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
442 ctx->loop_depth++;
443 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
444 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
445 }
446
447 static void brk_emit(
448 const struct lp_build_tgsi_action * action,
449 struct lp_build_tgsi_context * bld_base,
450 struct lp_build_emit_data * emit_data)
451 {
452 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
453 struct gallivm_state * gallivm = bld_base->base.gallivm;
454 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
455
456 LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
457 }
458
459 static void cont_emit(
460 const struct lp_build_tgsi_action * action,
461 struct lp_build_tgsi_context * bld_base,
462 struct lp_build_emit_data * emit_data)
463 {
464 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
465 struct gallivm_state * gallivm = bld_base->base.gallivm;
466 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
467
468 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
469 }
470
471 static void else_emit(
472 const struct lp_build_tgsi_action * action,
473 struct lp_build_tgsi_context * bld_base,
474 struct lp_build_emit_data * emit_data)
475 {
476 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
477 struct gallivm_state * gallivm = bld_base->base.gallivm;
478 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
479 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
480
481 /* We need to add a terminator to the current block if the previous
482 * instruction was an ENDIF.Example:
483 * IF
484 * [code]
485 * IF
486 * [code]
487 * ELSE
488 * [code]
489 * ENDIF <--
490 * ELSE<--
491 * [code]
492 * ENDIF
493 */
494
495 if (current_block != current_branch->if_block) {
496 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
497 }
498 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
499 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
500 }
501 current_branch->has_else = 1;
502 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
503 }
504
505 static void endif_emit(
506 const struct lp_build_tgsi_action * action,
507 struct lp_build_tgsi_context * bld_base,
508 struct lp_build_emit_data * emit_data)
509 {
510 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
511 struct gallivm_state * gallivm = bld_base->base.gallivm;
512 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
513 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
514
515 /* If we have consecutive ENDIF instructions, then the first ENDIF
516 * will not have a terminator, so we need to add one. */
517 if (current_block != current_branch->if_block
518 && current_block != current_branch->else_block
519 && !LLVMGetBasicBlockTerminator(current_block)) {
520
521 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
522 }
523 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
524 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
525 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
526 }
527
528 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
529 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
530 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
531 }
532
533 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
534 ctx->branch_depth--;
535 }
536
537 static void endloop_emit(
538 const struct lp_build_tgsi_action * action,
539 struct lp_build_tgsi_context * bld_base,
540 struct lp_build_emit_data * emit_data)
541 {
542 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
543 struct gallivm_state * gallivm = bld_base->base.gallivm;
544 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
545
546 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
547 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
548 }
549
550 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
551 ctx->loop_depth--;
552 }
553
554 static void if_cond_emit(
555 const struct lp_build_tgsi_action * action,
556 struct lp_build_tgsi_context * bld_base,
557 struct lp_build_emit_data * emit_data,
558 LLVMValueRef cond)
559 {
560 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
561 struct gallivm_state * gallivm = bld_base->base.gallivm;
562 LLVMBasicBlockRef if_block, else_block, endif_block;
563
564 endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
565 ctx->main_fn, "ENDIF");
566 if_block = LLVMInsertBasicBlockInContext(gallivm->context,
567 endif_block, "IF");
568 else_block = LLVMInsertBasicBlockInContext(gallivm->context,
569 endif_block, "ELSE");
570 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
571 LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
572
573 ctx->branch_depth++;
574 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
575 ctx->branch[ctx->branch_depth - 1].if_block = if_block;
576 ctx->branch[ctx->branch_depth - 1].else_block = else_block;
577 ctx->branch[ctx->branch_depth - 1].has_else = 0;
578 }
579
580 static void if_emit(
581 const struct lp_build_tgsi_action * action,
582 struct lp_build_tgsi_context * bld_base,
583 struct lp_build_emit_data * emit_data)
584 {
585 struct gallivm_state * gallivm = bld_base->base.gallivm;
586 LLVMValueRef cond;
587
588 cond = LLVMBuildFCmp(gallivm->builder, LLVMRealUNE,
589 emit_data->args[0],
590 bld_base->base.zero, "");
591
592 if_cond_emit(action, bld_base, emit_data, cond);
593 }
594
595 static void uif_emit(
596 const struct lp_build_tgsi_action * action,
597 struct lp_build_tgsi_context * bld_base,
598 struct lp_build_emit_data * emit_data)
599 {
600 struct gallivm_state * gallivm = bld_base->base.gallivm;
601 LLVMValueRef cond;
602
603 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
604 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
605 bld_base->int_bld.zero, "");
606
607 if_cond_emit(action, bld_base, emit_data, cond);
608 }
609
610 static void kil_emit(
611 const struct lp_build_tgsi_action * action,
612 struct lp_build_tgsi_context * bld_base,
613 struct lp_build_emit_data * emit_data)
614 {
615 unsigned i;
616 for (i = 0; i < emit_data->arg_count; i++) {
617 emit_data->output[i] = lp_build_intrinsic_unary(
618 bld_base->base.gallivm->builder,
619 action->intr_name,
620 emit_data->dst_type, emit_data->args[i]);
621 }
622 }
623
624 void radeon_llvm_emit_prepare_cube_coords(
625 struct lp_build_tgsi_context * bld_base,
626 struct lp_build_emit_data * emit_data,
627 LLVMValueRef *coords_arg)
628 {
629
630 unsigned target = emit_data->inst->Texture.Texture;
631 unsigned opcode = emit_data->inst->Instruction.Opcode;
632 struct gallivm_state * gallivm = bld_base->base.gallivm;
633 LLVMBuilderRef builder = gallivm->builder;
634 LLVMTypeRef type = bld_base->base.elem_type;
635 LLVMValueRef coords[4];
636 LLVMValueRef mad_args[3];
637 LLVMValueRef idx;
638 struct LLVMOpaqueValue *cube_vec;
639 LLVMValueRef v;
640 unsigned i;
641
642 cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
643 v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
644 &cube_vec, 1, LLVMReadNoneAttribute);
645
646 for (i = 0; i < 4; ++i) {
647 idx = lp_build_const_int32(gallivm, i);
648 coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
649 }
650
651 coords[2] = build_intrinsic(builder, "fabs",
652 type, &coords[2], 1, LLVMReadNoneAttribute);
653 coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]);
654
655 mad_args[1] = coords[2];
656 mad_args[2] = LLVMConstReal(type, 1.5);
657
658 mad_args[0] = coords[0];
659 coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
660 mad_args[0], mad_args[1], mad_args[2]);
661
662 mad_args[0] = coords[1];
663 coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
664 mad_args[0], mad_args[1], mad_args[2]);
665
666 /* apply xyz = yxw swizzle to cooords */
667 coords[2] = coords[3];
668 coords[3] = coords[1];
669 coords[1] = coords[0];
670 coords[0] = coords[3];
671
672 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
673 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
674 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
675 /* coords_arg.w component - array_index for cube arrays */
676 coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
677 coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
678 }
679
680 /* Preserve compare/lod/bias. Put it in coords.w. */
681 if (opcode == TGSI_OPCODE_TEX2 ||
682 opcode == TGSI_OPCODE_TXB2 ||
683 opcode == TGSI_OPCODE_TXL2) {
684 coords[3] = coords_arg[4];
685 } else if (opcode == TGSI_OPCODE_TXB ||
686 opcode == TGSI_OPCODE_TXL ||
687 target == TGSI_TEXTURE_SHADOWCUBE) {
688 coords[3] = coords_arg[3];
689 }
690
691 memcpy(coords_arg, coords, sizeof(coords));
692 }
693
694 static void txd_fetch_args(
695 struct lp_build_tgsi_context * bld_base,
696 struct lp_build_emit_data * emit_data)
697 {
698 const struct tgsi_full_instruction * inst = emit_data->inst;
699
700 LLVMValueRef coords[4];
701 unsigned chan, src;
702 for (src = 0; src < 3; src++) {
703 for (chan = 0; chan < 4; chan++)
704 coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan);
705
706 emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm,
707 coords, 4);
708 }
709 emit_data->arg_count = 3;
710 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
711 }
712
713
714 static void txp_fetch_args(
715 struct lp_build_tgsi_context * bld_base,
716 struct lp_build_emit_data * emit_data)
717 {
718 const struct tgsi_full_instruction * inst = emit_data->inst;
719 LLVMValueRef src_w;
720 unsigned chan;
721 LLVMValueRef coords[4];
722
723 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
724 src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
725
726 for (chan = 0; chan < 3; chan++ ) {
727 LLVMValueRef arg = lp_build_emit_fetch(bld_base,
728 emit_data->inst, 0, chan);
729 coords[chan] = lp_build_emit_llvm_binary(bld_base,
730 TGSI_OPCODE_DIV, arg, src_w);
731 }
732 coords[3] = bld_base->base.one;
733
734 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
735 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
736 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
737 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
738 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
739 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
740 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
741 }
742
743 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
744 coords, 4);
745 emit_data->arg_count = 1;
746 }
747
748 static void tex_fetch_args(
749 struct lp_build_tgsi_context * bld_base,
750 struct lp_build_emit_data * emit_data)
751 {
752 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
753 * when we used CHAN_ALL. We should be able to get this to work,
754 * but for now we will swizzle it ourselves
755 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
756 0, CHAN_ALL);
757
758 */
759
760 const struct tgsi_full_instruction * inst = emit_data->inst;
761
762 LLVMValueRef coords[5];
763 unsigned chan;
764 for (chan = 0; chan < 4; chan++) {
765 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
766 }
767
768 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
769 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
770 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
771 /* These instructions have additional operand that should be packed
772 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
773 * That operand should be passed as a float value in the args array
774 * right after the coord vector. After packing it's not used anymore,
775 * that's why arg_count is not increased */
776 coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
777 }
778
779 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
780 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
781 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
782 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
783 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
784 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
785 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
786 }
787
788 emit_data->arg_count = 1;
789 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
790 coords, 4);
791 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
792 }
793
794 static void txf_fetch_args(
795 struct lp_build_tgsi_context * bld_base,
796 struct lp_build_emit_data * emit_data)
797 {
798 const struct tgsi_full_instruction * inst = emit_data->inst;
799 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
800 const struct tgsi_texture_offset * off = inst->TexOffsets;
801 LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
802
803 /* fetch tex coords */
804 tex_fetch_args(bld_base, emit_data);
805
806 /* fetch tex offsets */
807 if (inst->Texture.NumOffsets) {
808 assert(inst->Texture.NumOffsets == 1);
809
810 emit_data->args[1] = LLVMConstBitCast(
811 bld->immediates[off->Index][off->SwizzleX],
812 offset_type);
813 emit_data->args[2] = LLVMConstBitCast(
814 bld->immediates[off->Index][off->SwizzleY],
815 offset_type);
816 emit_data->args[3] = LLVMConstBitCast(
817 bld->immediates[off->Index][off->SwizzleZ],
818 offset_type);
819 } else {
820 emit_data->args[1] = bld_base->int_bld.zero;
821 emit_data->args[2] = bld_base->int_bld.zero;
822 emit_data->args[3] = bld_base->int_bld.zero;
823 }
824
825 emit_data->arg_count = 4;
826 }
827
828 static void emit_icmp(
829 const struct lp_build_tgsi_action * action,
830 struct lp_build_tgsi_context * bld_base,
831 struct lp_build_emit_data * emit_data)
832 {
833 unsigned pred;
834 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
835 LLVMContextRef context = bld_base->base.gallivm->context;
836
837 switch (emit_data->inst->Instruction.Opcode) {
838 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
839 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
840 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
841 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
842 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
843 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
844 default:
845 assert(!"unknown instruction");
846 pred = 0;
847 break;
848 }
849
850 LLVMValueRef v = LLVMBuildICmp(builder, pred,
851 emit_data->args[0], emit_data->args[1],"");
852
853 v = LLVMBuildSExtOrBitCast(builder, v,
854 LLVMInt32TypeInContext(context), "");
855
856 emit_data->output[emit_data->chan] = v;
857 }
858
859 static void emit_ucmp(
860 const struct lp_build_tgsi_action * action,
861 struct lp_build_tgsi_context * bld_base,
862 struct lp_build_emit_data * emit_data)
863 {
864 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
865
866 LLVMValueRef arg0 = LLVMBuildBitCast(builder, emit_data->args[0],
867 bld_base->uint_bld.elem_type, "");
868
869 LLVMValueRef v = LLVMBuildICmp(builder, LLVMIntNE, arg0,
870 bld_base->uint_bld.zero, "");
871
872 emit_data->output[emit_data->chan] =
873 LLVMBuildSelect(builder, v, emit_data->args[1], emit_data->args[2], "");
874 }
875
876 static void emit_cmp(
877 const struct lp_build_tgsi_action *action,
878 struct lp_build_tgsi_context * bld_base,
879 struct lp_build_emit_data * emit_data)
880 {
881 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
882 LLVMRealPredicate pred;
883 LLVMValueRef cond;
884
885 /* Use ordered for everything but NE (which is usual for
886 * float comparisons)
887 */
888 switch (emit_data->inst->Instruction.Opcode) {
889 case TGSI_OPCODE_SGE: pred = LLVMRealOGE; break;
890 case TGSI_OPCODE_SEQ: pred = LLVMRealOEQ; break;
891 case TGSI_OPCODE_SLE: pred = LLVMRealOLE; break;
892 case TGSI_OPCODE_SLT: pred = LLVMRealOLT; break;
893 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
894 case TGSI_OPCODE_SGT: pred = LLVMRealOGT; break;
895 default: assert(!"unknown instruction"); pred = 0; break;
896 }
897
898 cond = LLVMBuildFCmp(builder,
899 pred, emit_data->args[0], emit_data->args[1], "");
900
901 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
902 cond, bld_base->base.one, bld_base->base.zero, "");
903 }
904
905 static void emit_fcmp(
906 const struct lp_build_tgsi_action *action,
907 struct lp_build_tgsi_context * bld_base,
908 struct lp_build_emit_data * emit_data)
909 {
910 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
911 LLVMContextRef context = bld_base->base.gallivm->context;
912 LLVMRealPredicate pred;
913
914 /* Use ordered for everything but NE (which is usual for
915 * float comparisons)
916 */
917 switch (emit_data->inst->Instruction.Opcode) {
918 case TGSI_OPCODE_FSEQ: pred = LLVMRealOEQ; break;
919 case TGSI_OPCODE_FSGE: pred = LLVMRealOGE; break;
920 case TGSI_OPCODE_FSLT: pred = LLVMRealOLT; break;
921 case TGSI_OPCODE_FSNE: pred = LLVMRealUNE; break;
922 default: assert(!"unknown instruction"); pred = 0; break;
923 }
924
925 LLVMValueRef v = LLVMBuildFCmp(builder, pred,
926 emit_data->args[0], emit_data->args[1],"");
927
928 v = LLVMBuildSExtOrBitCast(builder, v,
929 LLVMInt32TypeInContext(context), "");
930
931 emit_data->output[emit_data->chan] = v;
932 }
933
934 static void emit_not(
935 const struct lp_build_tgsi_action * action,
936 struct lp_build_tgsi_context * bld_base,
937 struct lp_build_emit_data * emit_data)
938 {
939 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
940 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
941 emit_data->args[0]);
942 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
943 }
944
945 static void emit_arl(
946 const struct lp_build_tgsi_action * action,
947 struct lp_build_tgsi_context * bld_base,
948 struct lp_build_emit_data * emit_data)
949 {
950 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
951 LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
952 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
953 floor_index, bld_base->base.int_elem_type , "");
954 }
955
956 static void emit_and(
957 const struct lp_build_tgsi_action * action,
958 struct lp_build_tgsi_context * bld_base,
959 struct lp_build_emit_data * emit_data)
960 {
961 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
962 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
963 emit_data->args[0], emit_data->args[1], "");
964 }
965
966 static void emit_or(
967 const struct lp_build_tgsi_action * action,
968 struct lp_build_tgsi_context * bld_base,
969 struct lp_build_emit_data * emit_data)
970 {
971 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
972 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
973 emit_data->args[0], emit_data->args[1], "");
974 }
975
976 static void emit_uadd(
977 const struct lp_build_tgsi_action * action,
978 struct lp_build_tgsi_context * bld_base,
979 struct lp_build_emit_data * emit_data)
980 {
981 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
982 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
983 emit_data->args[0], emit_data->args[1], "");
984 }
985
986 static void emit_udiv(
987 const struct lp_build_tgsi_action * action,
988 struct lp_build_tgsi_context * bld_base,
989 struct lp_build_emit_data * emit_data)
990 {
991 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
992 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
993 emit_data->args[0], emit_data->args[1], "");
994 }
995
996 static void emit_idiv(
997 const struct lp_build_tgsi_action * action,
998 struct lp_build_tgsi_context * bld_base,
999 struct lp_build_emit_data * emit_data)
1000 {
1001 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1002 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
1003 emit_data->args[0], emit_data->args[1], "");
1004 }
1005
1006 static void emit_mod(
1007 const struct lp_build_tgsi_action * action,
1008 struct lp_build_tgsi_context * bld_base,
1009 struct lp_build_emit_data * emit_data)
1010 {
1011 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1012 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
1013 emit_data->args[0], emit_data->args[1], "");
1014 }
1015
1016 static void emit_umod(
1017 const struct lp_build_tgsi_action * action,
1018 struct lp_build_tgsi_context * bld_base,
1019 struct lp_build_emit_data * emit_data)
1020 {
1021 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1022 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
1023 emit_data->args[0], emit_data->args[1], "");
1024 }
1025
1026 static void emit_shl(
1027 const struct lp_build_tgsi_action * action,
1028 struct lp_build_tgsi_context * bld_base,
1029 struct lp_build_emit_data * emit_data)
1030 {
1031 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1032 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
1033 emit_data->args[0], emit_data->args[1], "");
1034 }
1035
1036 static void emit_ushr(
1037 const struct lp_build_tgsi_action * action,
1038 struct lp_build_tgsi_context * bld_base,
1039 struct lp_build_emit_data * emit_data)
1040 {
1041 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1042 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
1043 emit_data->args[0], emit_data->args[1], "");
1044 }
1045 static void emit_ishr(
1046 const struct lp_build_tgsi_action * action,
1047 struct lp_build_tgsi_context * bld_base,
1048 struct lp_build_emit_data * emit_data)
1049 {
1050 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1051 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
1052 emit_data->args[0], emit_data->args[1], "");
1053 }
1054
1055 static void emit_xor(
1056 const struct lp_build_tgsi_action * action,
1057 struct lp_build_tgsi_context * bld_base,
1058 struct lp_build_emit_data * emit_data)
1059 {
1060 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1061 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
1062 emit_data->args[0], emit_data->args[1], "");
1063 }
1064
1065 static void emit_ssg(
1066 const struct lp_build_tgsi_action * action,
1067 struct lp_build_tgsi_context * bld_base,
1068 struct lp_build_emit_data * emit_data)
1069 {
1070 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1071
1072 LLVMValueRef cmp, val;
1073
1074 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
1075 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
1076 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
1077 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
1078 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
1079 } else { // float SSG
1080 cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->base.zero, "");
1081 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
1082 cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, "");
1083 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
1084 }
1085
1086 emit_data->output[emit_data->chan] = val;
1087 }
1088
1089 static void emit_ineg(
1090 const struct lp_build_tgsi_action * action,
1091 struct lp_build_tgsi_context * bld_base,
1092 struct lp_build_emit_data * emit_data)
1093 {
1094 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1095 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
1096 emit_data->args[0], "");
1097 }
1098
1099 static void emit_f2i(
1100 const struct lp_build_tgsi_action * action,
1101 struct lp_build_tgsi_context * bld_base,
1102 struct lp_build_emit_data * emit_data)
1103 {
1104 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1105 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
1106 emit_data->args[0], bld_base->int_bld.elem_type, "");
1107 }
1108
1109 static void emit_f2u(
1110 const struct lp_build_tgsi_action * action,
1111 struct lp_build_tgsi_context * bld_base,
1112 struct lp_build_emit_data * emit_data)
1113 {
1114 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1115 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
1116 emit_data->args[0], bld_base->uint_bld.elem_type, "");
1117 }
1118
1119 static void emit_i2f(
1120 const struct lp_build_tgsi_action * action,
1121 struct lp_build_tgsi_context * bld_base,
1122 struct lp_build_emit_data * emit_data)
1123 {
1124 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1125 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
1126 emit_data->args[0], bld_base->base.elem_type, "");
1127 }
1128
1129 static void emit_u2f(
1130 const struct lp_build_tgsi_action * action,
1131 struct lp_build_tgsi_context * bld_base,
1132 struct lp_build_emit_data * emit_data)
1133 {
1134 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1135 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
1136 emit_data->args[0], bld_base->base.elem_type, "");
1137 }
1138
1139 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
1140 const struct tgsi_full_immediate *imm)
1141 {
1142 unsigned i;
1143 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
1144
1145 for (i = 0; i < 4; ++i) {
1146 ctx->soa.immediates[ctx->soa.num_immediates][i] =
1147 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false );
1148 }
1149
1150 ctx->soa.num_immediates++;
1151 }
1152
1153 LLVMValueRef
1154 build_intrinsic(LLVMBuilderRef builder,
1155 const char *name,
1156 LLVMTypeRef ret_type,
1157 LLVMValueRef *args,
1158 unsigned num_args,
1159 LLVMAttribute attr)
1160 {
1161 LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
1162 LLVMValueRef function;
1163
1164 function = LLVMGetNamedFunction(module, name);
1165 if(!function) {
1166 LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
1167 unsigned i;
1168
1169 assert(num_args <= LP_MAX_FUNC_ARGS);
1170
1171 for(i = 0; i < num_args; ++i) {
1172 assert(args[i]);
1173 arg_types[i] = LLVMTypeOf(args[i]);
1174 }
1175
1176 function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
1177
1178 if (attr)
1179 LLVMAddFunctionAttr(function, attr);
1180 }
1181
1182 return LLVMBuildCall(builder, function, args, num_args, "");
1183 }
1184
1185 static void build_tgsi_intrinsic(
1186 const struct lp_build_tgsi_action * action,
1187 struct lp_build_tgsi_context * bld_base,
1188 struct lp_build_emit_data * emit_data,
1189 LLVMAttribute attr)
1190 {
1191 struct lp_build_context * base = &bld_base->base;
1192 emit_data->output[emit_data->chan] = build_intrinsic(
1193 base->gallivm->builder, action->intr_name,
1194 emit_data->dst_type, emit_data->args,
1195 emit_data->arg_count, attr);
1196 }
1197 void
1198 build_tgsi_intrinsic_nomem(
1199 const struct lp_build_tgsi_action * action,
1200 struct lp_build_tgsi_context * bld_base,
1201 struct lp_build_emit_data * emit_data)
1202 {
1203 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadNoneAttribute);
1204 }
1205
1206 static void build_tgsi_intrinsic_readonly(
1207 const struct lp_build_tgsi_action * action,
1208 struct lp_build_tgsi_context * bld_base,
1209 struct lp_build_emit_data * emit_data)
1210 {
1211 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadOnlyAttribute);
1212 }
1213
1214 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
1215 {
1216 struct lp_type type;
1217
1218 /* Initialize the gallivm object:
1219 * We are only using the module, context, and builder fields of this struct.
1220 * This should be enough for us to be able to pass our gallivm struct to the
1221 * helper functions in the gallivm module.
1222 */
1223 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
1224 memset(&ctx->soa, 0, sizeof(ctx->soa));
1225 ctx->gallivm.context = LLVMContextCreate();
1226 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
1227 ctx->gallivm.context);
1228 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
1229
1230 ctx->store_output_intr = "llvm.AMDGPU.store.output.";
1231 ctx->swizzle_intr = "llvm.AMDGPU.swizzle";
1232 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1233
1234 /* XXX: We need to revisit this.I think the correct way to do this is
1235 * to use length = 4 here and use the elem_bld for everything. */
1236 type.floating = TRUE;
1237 type.fixed = FALSE;
1238 type.sign = TRUE;
1239 type.norm = FALSE;
1240 type.width = 32;
1241 type.length = 1;
1242
1243 lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1244 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1245 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1246
1247 bld_base->soa = 1;
1248 bld_base->emit_store = emit_store;
1249 bld_base->emit_swizzle = emit_swizzle;
1250 bld_base->emit_declaration = emit_declaration;
1251 bld_base->emit_immediate = emit_immediate;
1252
1253 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch;
1254 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch;
1255 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch;
1256 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch;
1257 bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = fetch_system_value;
1258
1259 /* Allocate outputs */
1260 ctx->soa.outputs = ctx->outputs;
1261
1262 ctx->num_arrays = 0;
1263
1264 /* XXX: Is there a better way to initialize all this ? */
1265
1266 lp_set_default_actions(bld_base);
1267
1268 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
1269 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
1270 bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
1271 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1272 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1273 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1274 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
1275 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
1276 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1277 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
1278 bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
1279 bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
1280 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1281 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly;
1282 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
1283 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
1284 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
1285 bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
1286 bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
1287 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1288 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1289 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1290 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1291 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
1292 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_readonly;
1293 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
1294 bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
1295 bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
1296 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1297 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1298 bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
1299 bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp;
1300 bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp;
1301 bld_base->op_actions[TGSI_OPCODE_FSNE].emit = emit_fcmp;
1302 bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
1303 bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
1304 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1305 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1306 bld_base->op_actions[TGSI_OPCODE_UIF].emit = uif_emit;
1307 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1308 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
1309 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
1310 bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
1311 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1312 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1313 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1314 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1315 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1316 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1317 bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit;
1318 bld_base->op_actions[TGSI_OPCODE_KILL_IF].intr_name = "llvm.AMDGPU.kill";
1319 bld_base->op_actions[TGSI_OPCODE_KILL].emit = lp_build_tgsi_intrinsic;
1320 bld_base->op_actions[TGSI_OPCODE_KILL].intr_name = "llvm.AMDGPU.kilp";
1321 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_readonly;
1322 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
1323 bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
1324 bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
1325 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1326 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1327 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1328 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly;
1329 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
1330 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1331 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
1332 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
1333 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
1334 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1335 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
1336 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
1337 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
1338 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
1339 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly;
1340 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
1341 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1342 bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
1343 bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
1344 bld_base->op_actions[TGSI_OPCODE_TEX2].fetch_args = tex_fetch_args;
1345 bld_base->op_actions[TGSI_OPCODE_TEX2].intr_name = "llvm.AMDGPU.tex";
1346 bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
1347 bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
1348 bld_base->op_actions[TGSI_OPCODE_TXB2].fetch_args = tex_fetch_args;
1349 bld_base->op_actions[TGSI_OPCODE_TXB2].intr_name = "llvm.AMDGPU.txb";
1350 bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
1351 bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
1352 bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
1353 bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
1354 bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
1355 bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
1356 bld_base->op_actions[TGSI_OPCODE_TXL2].fetch_args = tex_fetch_args;
1357 bld_base->op_actions[TGSI_OPCODE_TXL2].intr_name = "llvm.AMDGPU.txl";
1358 bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
1359 bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
1360 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
1361 bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
1362 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1363 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
1364 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1365 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1366 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
1367 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
1368 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
1369 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
1370 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1371 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1372 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1373 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1374 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1375 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1376 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1377 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1378 bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
1379
1380 bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
1381 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
1382 }
1383
1384 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
1385 LLVMTypeRef *ParamTypes, unsigned ParamCount)
1386 {
1387 LLVMTypeRef main_fn_type;
1388 LLVMBasicBlockRef main_fn_body;
1389
1390 /* Setup the function */
1391 main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context),
1392 ParamTypes, ParamCount, 0);
1393 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1394 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1395 ctx->main_fn, "main_body");
1396 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1397 }
1398
1399 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1400 {
1401 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1402 /* End the main function with Return*/
1403 LLVMBuildRetVoid(gallivm->builder);
1404
1405 /* Create the pass manager */
1406 ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule(
1407 gallivm->module);
1408
1409 /* This pass should eliminate all the load and store instructions */
1410 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1411
1412 /* Add some optimization passes */
1413 LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1414 LLVMAddLICMPass(gallivm->passmgr);
1415 LLVMAddAggressiveDCEPass(gallivm->passmgr);
1416 LLVMAddCFGSimplificationPass(gallivm->passmgr);
1417
1418 /* Run the pass */
1419 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1420
1421 LLVMDisposeBuilder(gallivm->builder);
1422 LLVMDisposePassManager(gallivm->passmgr);
1423
1424 }
1425
1426 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1427 {
1428 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1429 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1430 FREE(ctx->temps);
1431 ctx->temps = NULL;
1432 }