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gallium/radeon: don't discard DCC if an external user can write to it
[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26 #include "radeon_llvm.h"
27
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "gallivm/lp_bld_swizzle.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "util/u_math.h"
38 #include "util/u_memory.h"
39 #include "util/u_debug.h"
40
41 #include <llvm-c/Core.h>
42 #include <llvm-c/Transforms/Scalar.h>
43
44 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
45 {
46 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
47 }
48
49 static struct radeon_llvm_branch * get_current_branch(
50 struct radeon_llvm_context * ctx)
51 {
52 return ctx->branch_depth > 0 ?
53 ctx->branch + (ctx->branch_depth - 1) : NULL;
54 }
55
56 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
57 {
58 return (index * 4) + chan;
59 }
60
61 static LLVMValueRef emit_swizzle(
62 struct lp_build_tgsi_context * bld_base,
63 LLVMValueRef value,
64 unsigned swizzle_x,
65 unsigned swizzle_y,
66 unsigned swizzle_z,
67 unsigned swizzle_w)
68 {
69 LLVMValueRef swizzles[4];
70 LLVMTypeRef i32t =
71 LLVMInt32TypeInContext(bld_base->base.gallivm->context);
72
73 swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0);
74 swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0);
75 swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0);
76 swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0);
77
78 return LLVMBuildShuffleVector(bld_base->base.gallivm->builder,
79 value,
80 LLVMGetUndef(LLVMTypeOf(value)),
81 LLVMConstVector(swizzles, 4), "");
82 }
83
84 static struct tgsi_declaration_range
85 get_array_range(struct lp_build_tgsi_context *bld_base,
86 unsigned File, const struct tgsi_ind_register *reg)
87 {
88 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
89
90 if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 ||
91 reg->ArrayID > bld_base->info->array_max[TGSI_FILE_TEMPORARY]) {
92 struct tgsi_declaration_range range;
93 range.First = 0;
94 range.Last = bld_base->info->file_max[File];
95 return range;
96 }
97
98 return ctx->arrays[reg->ArrayID - 1];
99 }
100
101 static LLVMValueRef
102 emit_array_index(
103 struct lp_build_tgsi_soa_context *bld,
104 const struct tgsi_ind_register *reg,
105 unsigned offset)
106 {
107 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
108
109 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, bld->addr[reg->Index][reg->Swizzle], "");
110 return LLVMBuildAdd(gallivm->builder, addr, lp_build_const_int32(gallivm, offset), "");
111 }
112
113 LLVMValueRef
114 radeon_llvm_emit_fetch_double(
115 struct lp_build_tgsi_context *bld_base,
116 LLVMValueRef ptr,
117 LLVMValueRef ptr2)
118 {
119 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
120 LLVMValueRef result;
121
122 result = LLVMGetUndef(LLVMVectorType(LLVMIntTypeInContext(bld_base->base.gallivm->context, 32), bld_base->base.type.length * 2));
123
124 result = LLVMBuildInsertElement(builder,
125 result,
126 bitcast(bld_base, TGSI_TYPE_UNSIGNED, ptr),
127 bld_base->int_bld.zero, "");
128 result = LLVMBuildInsertElement(builder,
129 result,
130 bitcast(bld_base, TGSI_TYPE_UNSIGNED, ptr2),
131 bld_base->int_bld.one, "");
132 return bitcast(bld_base, TGSI_TYPE_DOUBLE, result);
133 }
134
135 static LLVMValueRef
136 emit_array_fetch(
137 struct lp_build_tgsi_context *bld_base,
138 unsigned File, enum tgsi_opcode_type type,
139 struct tgsi_declaration_range range,
140 unsigned swizzle)
141 {
142 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
143 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
144 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
145
146 unsigned i, size = range.Last - range.First + 1;
147 LLVMTypeRef vec = LLVMVectorType(tgsi2llvmtype(bld_base, type), size);
148 LLVMValueRef result = LLVMGetUndef(vec);
149
150 struct tgsi_full_src_register tmp_reg = {};
151 tmp_reg.Register.File = File;
152
153 for (i = 0; i < size; ++i) {
154 tmp_reg.Register.Index = i + range.First;
155 LLVMValueRef temp = radeon_llvm_emit_fetch(bld_base, &tmp_reg, type, swizzle);
156 result = LLVMBuildInsertElement(builder, result, temp,
157 lp_build_const_int32(gallivm, i), "");
158 }
159 return result;
160 }
161
162 static bool uses_temp_indirect_addressing(
163 struct lp_build_tgsi_context *bld_base)
164 {
165 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
166 return (bld->indirect_files & (1 << TGSI_FILE_TEMPORARY));
167 }
168
169 LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
170 const struct tgsi_full_src_register *reg,
171 enum tgsi_opcode_type type,
172 unsigned swizzle)
173 {
174 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
175 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
176 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
177 LLVMValueRef result = NULL, ptr, ptr2;
178
179 if (swizzle == ~0) {
180 LLVMValueRef values[TGSI_NUM_CHANNELS];
181 unsigned chan;
182 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
183 values[chan] = radeon_llvm_emit_fetch(bld_base, reg, type, chan);
184 }
185 return lp_build_gather_values(bld_base->base.gallivm, values,
186 TGSI_NUM_CHANNELS);
187 }
188
189 if (reg->Register.Indirect) {
190 struct tgsi_declaration_range range = get_array_range(bld_base,
191 reg->Register.File, &reg->Indirect);
192 return LLVMBuildExtractElement(builder,
193 emit_array_fetch(bld_base, reg->Register.File, type, range, swizzle),
194 emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First),
195 "");
196 }
197
198 switch(reg->Register.File) {
199 case TGSI_FILE_IMMEDIATE: {
200 LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type);
201 if (type == TGSI_TYPE_DOUBLE) {
202 result = LLVMGetUndef(LLVMVectorType(LLVMIntTypeInContext(bld_base->base.gallivm->context, 32), bld_base->base.type.length * 2));
203 result = LLVMConstInsertElement(result,
204 bld->immediates[reg->Register.Index][swizzle],
205 bld_base->int_bld.zero);
206 result = LLVMConstInsertElement(result,
207 bld->immediates[reg->Register.Index][swizzle + 1],
208 bld_base->int_bld.one);
209 return LLVMConstBitCast(result, ctype);
210 } else {
211 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
212 }
213 }
214
215 case TGSI_FILE_INPUT:
216 result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)];
217 if (type == TGSI_TYPE_DOUBLE) {
218 ptr = result;
219 ptr2 = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle + 1)];
220 return radeon_llvm_emit_fetch_double(bld_base, ptr, ptr2);
221 }
222 break;
223
224 case TGSI_FILE_TEMPORARY:
225 if (reg->Register.Index >= ctx->temps_count)
226 return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
227 if (uses_temp_indirect_addressing(bld_base)) {
228 ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
229 break;
230 }
231 ptr = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle];
232 if (type == TGSI_TYPE_DOUBLE) {
233 ptr2 = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle + 1];
234 return radeon_llvm_emit_fetch_double(bld_base,
235 LLVMBuildLoad(builder, ptr, ""),
236 LLVMBuildLoad(builder, ptr2, ""));
237 }
238 result = LLVMBuildLoad(builder, ptr, "");
239 break;
240
241 case TGSI_FILE_OUTPUT:
242 ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
243 if (type == TGSI_TYPE_DOUBLE) {
244 ptr2 = lp_get_output_ptr(bld, reg->Register.Index, swizzle + 1);
245 return radeon_llvm_emit_fetch_double(bld_base,
246 LLVMBuildLoad(builder, ptr, ""),
247 LLVMBuildLoad(builder, ptr2, ""));
248 }
249 result = LLVMBuildLoad(builder, ptr, "");
250 break;
251
252 default:
253 return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
254 }
255
256 return bitcast(bld_base, type, result);
257 }
258
259 static LLVMValueRef fetch_system_value(
260 struct lp_build_tgsi_context * bld_base,
261 const struct tgsi_full_src_register *reg,
262 enum tgsi_opcode_type type,
263 unsigned swizzle)
264 {
265 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
266 struct gallivm_state *gallivm = bld_base->base.gallivm;
267
268 LLVMValueRef cval = ctx->system_values[reg->Register.Index];
269 if (LLVMGetTypeKind(LLVMTypeOf(cval)) == LLVMVectorTypeKind) {
270 cval = LLVMBuildExtractElement(gallivm->builder, cval,
271 lp_build_const_int32(gallivm, swizzle), "");
272 }
273 return bitcast(bld_base, type, cval);
274 }
275
276 static LLVMValueRef si_build_alloca_undef(struct gallivm_state *gallivm,
277 LLVMTypeRef type,
278 const char *name)
279 {
280 LLVMValueRef ptr = lp_build_alloca(gallivm, type, name);
281 LLVMBuildStore(gallivm->builder, LLVMGetUndef(type), ptr);
282 return ptr;
283 }
284
285 static void emit_declaration(
286 struct lp_build_tgsi_context * bld_base,
287 const struct tgsi_full_declaration *decl)
288 {
289 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
290 unsigned first, last, i, idx;
291 switch(decl->Declaration.File) {
292 case TGSI_FILE_ADDRESS:
293 {
294 unsigned idx;
295 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
296 unsigned chan;
297 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
298 ctx->soa.addr[idx][chan] = si_build_alloca_undef(
299 &ctx->gallivm,
300 ctx->soa.bld_base.uint_bld.elem_type, "");
301 }
302 }
303 break;
304 }
305
306 case TGSI_FILE_TEMPORARY:
307 if (decl->Declaration.Array) {
308 if (!ctx->arrays) {
309 int size = bld_base->info->array_max[TGSI_FILE_TEMPORARY];
310 ctx->arrays = MALLOC(sizeof(ctx->arrays[0]) * size);
311 }
312
313 ctx->arrays[decl->Array.ArrayID - 1] = decl->Range;
314 }
315 if (uses_temp_indirect_addressing(bld_base)) {
316 lp_emit_declaration_soa(bld_base, decl);
317 break;
318 }
319 first = decl->Range.First;
320 last = decl->Range.Last;
321 if (!ctx->temps_count) {
322 ctx->temps_count = bld_base->info->file_max[TGSI_FILE_TEMPORARY] + 1;
323 ctx->temps = MALLOC(TGSI_NUM_CHANNELS * ctx->temps_count * sizeof(LLVMValueRef));
324 }
325 for (idx = first; idx <= last; idx++) {
326 for (i = 0; i < TGSI_NUM_CHANNELS; i++) {
327 ctx->temps[idx * TGSI_NUM_CHANNELS + i] =
328 si_build_alloca_undef(bld_base->base.gallivm,
329 bld_base->base.vec_type,
330 "temp");
331 }
332 }
333 break;
334
335 case TGSI_FILE_INPUT:
336 {
337 unsigned idx;
338 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
339 if (ctx->load_input)
340 ctx->load_input(ctx, idx, decl);
341 }
342 }
343 break;
344
345 case TGSI_FILE_SYSTEM_VALUE:
346 {
347 unsigned idx;
348 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
349 ctx->load_system_value(ctx, idx, decl);
350 }
351 }
352 break;
353
354 case TGSI_FILE_OUTPUT:
355 {
356 unsigned idx;
357 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
358 unsigned chan;
359 assert(idx < RADEON_LLVM_MAX_OUTPUTS);
360 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
361 ctx->soa.outputs[idx][chan] = si_build_alloca_undef(
362 &ctx->gallivm,
363 ctx->soa.bld_base.base.elem_type, "");
364 }
365 }
366 break;
367 }
368
369 case TGSI_FILE_MEMORY:
370 ctx->declare_memory_region(ctx, decl);
371 break;
372
373 default:
374 break;
375 }
376 }
377
378 LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base,
379 LLVMValueRef value)
380 {
381 struct lp_build_emit_data clamp_emit_data;
382
383 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
384 clamp_emit_data.arg_count = 3;
385 clamp_emit_data.args[0] = value;
386 clamp_emit_data.args[2] = bld_base->base.one;
387 clamp_emit_data.args[1] = bld_base->base.zero;
388
389 return lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
390 &clamp_emit_data);
391 }
392
393 void radeon_llvm_emit_store(
394 struct lp_build_tgsi_context * bld_base,
395 const struct tgsi_full_instruction * inst,
396 const struct tgsi_opcode_info * info,
397 LLVMValueRef dst[4])
398 {
399 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
400 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
401 struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
402 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
403 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
404 LLVMValueRef temp_ptr, temp_ptr2 = NULL;
405 unsigned chan, chan_index;
406 boolean is_vec_store = FALSE;
407 enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
408
409 if (dst[0]) {
410 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
411 is_vec_store = (k == LLVMVectorTypeKind);
412 }
413
414 if (is_vec_store) {
415 LLVMValueRef values[4] = {};
416 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
417 LLVMValueRef index = lp_build_const_int32(gallivm, chan);
418 values[chan] = LLVMBuildExtractElement(gallivm->builder,
419 dst[0], index, "");
420 }
421 bld_base->emit_store(bld_base, inst, info, values);
422 return;
423 }
424
425 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
426 LLVMValueRef value = dst[chan_index];
427
428 if (dtype == TGSI_TYPE_DOUBLE && (chan_index == 1 || chan_index == 3))
429 continue;
430 if (inst->Instruction.Saturate)
431 value = radeon_llvm_saturate(bld_base, value);
432
433 if (reg->Register.File == TGSI_FILE_ADDRESS) {
434 temp_ptr = bld->addr[reg->Register.Index][chan_index];
435 LLVMBuildStore(builder, value, temp_ptr);
436 continue;
437 }
438
439 if (dtype != TGSI_TYPE_DOUBLE)
440 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
441
442 if (reg->Register.Indirect) {
443 struct tgsi_declaration_range range = get_array_range(bld_base,
444 reg->Register.File, &reg->Indirect);
445
446 unsigned i, size = range.Last - range.First + 1;
447 LLVMValueRef array = LLVMBuildInsertElement(builder,
448 emit_array_fetch(bld_base, reg->Register.File, TGSI_TYPE_FLOAT, range, chan_index),
449 value, emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First), "");
450
451 for (i = 0; i < size; ++i) {
452 switch(reg->Register.File) {
453 case TGSI_FILE_OUTPUT:
454 temp_ptr = bld->outputs[i + range.First][chan_index];
455 break;
456
457 case TGSI_FILE_TEMPORARY:
458 if (range.First + i >= ctx->temps_count)
459 continue;
460 if (uses_temp_indirect_addressing(bld_base))
461 temp_ptr = lp_get_temp_ptr_soa(bld, i + range.First, chan_index);
462 else
463 temp_ptr = ctx->temps[(i + range.First) * TGSI_NUM_CHANNELS + chan_index];
464 break;
465
466 default:
467 return;
468 }
469 value = LLVMBuildExtractElement(builder, array,
470 lp_build_const_int32(gallivm, i), "");
471 LLVMBuildStore(builder, value, temp_ptr);
472 }
473
474 } else {
475 switch(reg->Register.File) {
476 case TGSI_FILE_OUTPUT:
477 temp_ptr = bld->outputs[reg->Register.Index][chan_index];
478 if (dtype == TGSI_TYPE_DOUBLE)
479 temp_ptr2 = bld->outputs[reg->Register.Index][chan_index + 1];
480 break;
481
482 case TGSI_FILE_TEMPORARY:
483 if (reg->Register.Index >= ctx->temps_count)
484 continue;
485 if (uses_temp_indirect_addressing(bld_base)) {
486 temp_ptr = NULL;
487 break;
488 }
489 temp_ptr = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index];
490 if (dtype == TGSI_TYPE_DOUBLE)
491 temp_ptr2 = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index + 1];
492
493 break;
494
495 default:
496 return;
497 }
498 if (dtype != TGSI_TYPE_DOUBLE)
499 LLVMBuildStore(builder, value, temp_ptr);
500 else {
501 LLVMValueRef ptr = LLVMBuildBitCast(builder, value,
502 LLVMVectorType(LLVMIntTypeInContext(bld_base->base.gallivm->context, 32), 2), "");
503 LLVMValueRef val2;
504 value = LLVMBuildExtractElement(builder, ptr,
505 bld_base->uint_bld.zero, "");
506 val2 = LLVMBuildExtractElement(builder, ptr,
507 bld_base->uint_bld.one, "");
508
509 LLVMBuildStore(builder, bitcast(bld_base, TGSI_TYPE_FLOAT, value), temp_ptr);
510 LLVMBuildStore(builder, bitcast(bld_base, TGSI_TYPE_FLOAT, val2), temp_ptr2);
511 }
512 }
513 }
514 }
515
516 static void bgnloop_emit(
517 const struct lp_build_tgsi_action * action,
518 struct lp_build_tgsi_context * bld_base,
519 struct lp_build_emit_data * emit_data)
520 {
521 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
522 struct gallivm_state * gallivm = bld_base->base.gallivm;
523 LLVMBasicBlockRef loop_block;
524 LLVMBasicBlockRef endloop_block;
525 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
526 ctx->main_fn, "ENDLOOP");
527 loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
528 endloop_block, "LOOP");
529 LLVMBuildBr(gallivm->builder, loop_block);
530 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
531
532 if (++ctx->loop_depth > ctx->loop_depth_max) {
533 unsigned new_max = ctx->loop_depth_max << 1;
534
535 if (!new_max)
536 new_max = RADEON_LLVM_INITIAL_CF_DEPTH;
537
538 ctx->loop = REALLOC(ctx->loop, ctx->loop_depth_max *
539 sizeof(ctx->loop[0]),
540 new_max * sizeof(ctx->loop[0]));
541 ctx->loop_depth_max = new_max;
542 }
543
544 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
545 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
546 }
547
548 static void brk_emit(
549 const struct lp_build_tgsi_action * action,
550 struct lp_build_tgsi_context * bld_base,
551 struct lp_build_emit_data * emit_data)
552 {
553 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
554 struct gallivm_state * gallivm = bld_base->base.gallivm;
555 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
556
557 LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
558 }
559
560 static void cont_emit(
561 const struct lp_build_tgsi_action * action,
562 struct lp_build_tgsi_context * bld_base,
563 struct lp_build_emit_data * emit_data)
564 {
565 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
566 struct gallivm_state * gallivm = bld_base->base.gallivm;
567 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
568
569 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
570 }
571
572 static void else_emit(
573 const struct lp_build_tgsi_action * action,
574 struct lp_build_tgsi_context * bld_base,
575 struct lp_build_emit_data * emit_data)
576 {
577 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
578 struct gallivm_state * gallivm = bld_base->base.gallivm;
579 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
580 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
581
582 /* We need to add a terminator to the current block if the previous
583 * instruction was an ENDIF.Example:
584 * IF
585 * [code]
586 * IF
587 * [code]
588 * ELSE
589 * [code]
590 * ENDIF <--
591 * ELSE<--
592 * [code]
593 * ENDIF
594 */
595
596 if (current_block != current_branch->if_block) {
597 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
598 }
599 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
600 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
601 }
602 current_branch->has_else = 1;
603 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
604 }
605
606 static void endif_emit(
607 const struct lp_build_tgsi_action * action,
608 struct lp_build_tgsi_context * bld_base,
609 struct lp_build_emit_data * emit_data)
610 {
611 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
612 struct gallivm_state * gallivm = bld_base->base.gallivm;
613 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
614 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
615
616 /* If we have consecutive ENDIF instructions, then the first ENDIF
617 * will not have a terminator, so we need to add one. */
618 if (current_block != current_branch->if_block
619 && current_block != current_branch->else_block
620 && !LLVMGetBasicBlockTerminator(current_block)) {
621
622 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
623 }
624 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
625 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
626 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
627 }
628
629 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
630 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
631 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
632 }
633
634 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
635 ctx->branch_depth--;
636 }
637
638 static void endloop_emit(
639 const struct lp_build_tgsi_action * action,
640 struct lp_build_tgsi_context * bld_base,
641 struct lp_build_emit_data * emit_data)
642 {
643 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
644 struct gallivm_state * gallivm = bld_base->base.gallivm;
645 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
646
647 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
648 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
649 }
650
651 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
652 ctx->loop_depth--;
653 }
654
655 static void if_cond_emit(
656 const struct lp_build_tgsi_action * action,
657 struct lp_build_tgsi_context * bld_base,
658 struct lp_build_emit_data * emit_data,
659 LLVMValueRef cond)
660 {
661 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
662 struct gallivm_state * gallivm = bld_base->base.gallivm;
663 LLVMBasicBlockRef if_block, else_block, endif_block;
664
665 endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
666 ctx->main_fn, "ENDIF");
667 if_block = LLVMInsertBasicBlockInContext(gallivm->context,
668 endif_block, "IF");
669 else_block = LLVMInsertBasicBlockInContext(gallivm->context,
670 endif_block, "ELSE");
671 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
672 LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
673
674 if (++ctx->branch_depth > ctx->branch_depth_max) {
675 unsigned new_max = ctx->branch_depth_max << 1;
676
677 if (!new_max)
678 new_max = RADEON_LLVM_INITIAL_CF_DEPTH;
679
680 ctx->branch = REALLOC(ctx->branch, ctx->branch_depth_max *
681 sizeof(ctx->branch[0]),
682 new_max * sizeof(ctx->branch[0]));
683 ctx->branch_depth_max = new_max;
684 }
685
686 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
687 ctx->branch[ctx->branch_depth - 1].if_block = if_block;
688 ctx->branch[ctx->branch_depth - 1].else_block = else_block;
689 ctx->branch[ctx->branch_depth - 1].has_else = 0;
690 }
691
692 static void if_emit(
693 const struct lp_build_tgsi_action * action,
694 struct lp_build_tgsi_context * bld_base,
695 struct lp_build_emit_data * emit_data)
696 {
697 struct gallivm_state * gallivm = bld_base->base.gallivm;
698 LLVMValueRef cond;
699
700 cond = LLVMBuildFCmp(gallivm->builder, LLVMRealUNE,
701 emit_data->args[0],
702 bld_base->base.zero, "");
703
704 if_cond_emit(action, bld_base, emit_data, cond);
705 }
706
707 static void uif_emit(
708 const struct lp_build_tgsi_action * action,
709 struct lp_build_tgsi_context * bld_base,
710 struct lp_build_emit_data * emit_data)
711 {
712 struct gallivm_state * gallivm = bld_base->base.gallivm;
713 LLVMValueRef cond;
714
715 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
716 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
717 bld_base->int_bld.zero, "");
718
719 if_cond_emit(action, bld_base, emit_data, cond);
720 }
721
722 static void kill_if_fetch_args(
723 struct lp_build_tgsi_context * bld_base,
724 struct lp_build_emit_data * emit_data)
725 {
726 const struct tgsi_full_instruction * inst = emit_data->inst;
727 struct gallivm_state *gallivm = bld_base->base.gallivm;
728 LLVMBuilderRef builder = gallivm->builder;
729 unsigned i;
730 LLVMValueRef conds[TGSI_NUM_CHANNELS];
731
732 for (i = 0; i < TGSI_NUM_CHANNELS; i++) {
733 LLVMValueRef value = lp_build_emit_fetch(bld_base, inst, 0, i);
734 conds[i] = LLVMBuildFCmp(builder, LLVMRealOLT, value,
735 bld_base->base.zero, "");
736 }
737
738 /* Or the conditions together */
739 for (i = TGSI_NUM_CHANNELS - 1; i > 0; i--) {
740 conds[i - 1] = LLVMBuildOr(builder, conds[i], conds[i - 1], "");
741 }
742
743 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
744 emit_data->arg_count = 1;
745 emit_data->args[0] = LLVMBuildSelect(builder, conds[0],
746 lp_build_const_float(gallivm, -1.0f),
747 bld_base->base.zero, "");
748 }
749
750 static void kil_emit(
751 const struct lp_build_tgsi_action * action,
752 struct lp_build_tgsi_context * bld_base,
753 struct lp_build_emit_data * emit_data)
754 {
755 unsigned i;
756 for (i = 0; i < emit_data->arg_count; i++) {
757 emit_data->output[i] = lp_build_intrinsic_unary(
758 bld_base->base.gallivm->builder,
759 action->intr_name,
760 emit_data->dst_type, emit_data->args[i]);
761 }
762 }
763
764 static void radeon_llvm_cube_to_2d_coords(struct lp_build_tgsi_context *bld_base,
765 LLVMValueRef *in, LLVMValueRef *out)
766 {
767 struct gallivm_state * gallivm = bld_base->base.gallivm;
768 LLVMBuilderRef builder = gallivm->builder;
769 LLVMTypeRef type = bld_base->base.elem_type;
770 LLVMValueRef coords[4];
771 LLVMValueRef mad_args[3];
772 LLVMValueRef v, cube_vec;
773 unsigned i;
774
775 cube_vec = lp_build_gather_values(bld_base->base.gallivm, in, 4);
776 v = lp_build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
777 &cube_vec, 1, LLVMReadNoneAttribute);
778
779 for (i = 0; i < 4; ++i)
780 coords[i] = LLVMBuildExtractElement(builder, v,
781 lp_build_const_int32(gallivm, i), "");
782
783 coords[2] = lp_build_intrinsic(builder, "llvm.fabs.f32",
784 type, &coords[2], 1, LLVMReadNoneAttribute);
785 coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]);
786
787 mad_args[1] = coords[2];
788 mad_args[2] = LLVMConstReal(type, 1.5);
789
790 mad_args[0] = coords[0];
791 coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
792 mad_args[0], mad_args[1], mad_args[2]);
793
794 mad_args[0] = coords[1];
795 coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
796 mad_args[0], mad_args[1], mad_args[2]);
797
798 /* apply xyz = yxw swizzle to cooords */
799 out[0] = coords[1];
800 out[1] = coords[0];
801 out[2] = coords[3];
802 }
803
804 void radeon_llvm_emit_prepare_cube_coords(
805 struct lp_build_tgsi_context * bld_base,
806 struct lp_build_emit_data * emit_data,
807 LLVMValueRef *coords_arg,
808 LLVMValueRef *derivs_arg)
809 {
810
811 unsigned target = emit_data->inst->Texture.Texture;
812 unsigned opcode = emit_data->inst->Instruction.Opcode;
813 struct gallivm_state * gallivm = bld_base->base.gallivm;
814 LLVMBuilderRef builder = gallivm->builder;
815 LLVMValueRef coords[4];
816 unsigned i;
817
818 radeon_llvm_cube_to_2d_coords(bld_base, coords_arg, coords);
819
820 if (opcode == TGSI_OPCODE_TXD && derivs_arg) {
821 LLVMValueRef derivs[4];
822 int axis;
823
824 /* Convert cube derivatives to 2D derivatives. */
825 for (axis = 0; axis < 2; axis++) {
826 LLVMValueRef shifted_cube_coords[4], shifted_coords[4];
827
828 /* Shift the cube coordinates by the derivatives to get
829 * the cube coordinates of the "neighboring pixel".
830 */
831 for (i = 0; i < 3; i++)
832 shifted_cube_coords[i] =
833 LLVMBuildFAdd(builder, coords_arg[i],
834 derivs_arg[axis*3+i], "");
835 shifted_cube_coords[3] = LLVMGetUndef(bld_base->base.elem_type);
836
837 /* Project the shifted cube coordinates onto the face. */
838 radeon_llvm_cube_to_2d_coords(bld_base, shifted_cube_coords,
839 shifted_coords);
840
841 /* Subtract both sets of 2D coordinates to get 2D derivatives.
842 * This won't work if the shifted coordinates ended up
843 * in a different face.
844 */
845 for (i = 0; i < 2; i++)
846 derivs[axis * 2 + i] =
847 LLVMBuildFSub(builder, shifted_coords[i],
848 coords[i], "");
849 }
850
851 memcpy(derivs_arg, derivs, sizeof(derivs));
852 }
853
854 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
855 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
856 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
857 /* coords_arg.w component - array_index for cube arrays */
858 coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
859 coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
860 }
861
862 /* Preserve compare/lod/bias. Put it in coords.w. */
863 if (opcode == TGSI_OPCODE_TEX2 ||
864 opcode == TGSI_OPCODE_TXB2 ||
865 opcode == TGSI_OPCODE_TXL2) {
866 coords[3] = coords_arg[4];
867 } else if (opcode == TGSI_OPCODE_TXB ||
868 opcode == TGSI_OPCODE_TXL ||
869 target == TGSI_TEXTURE_SHADOWCUBE) {
870 coords[3] = coords_arg[3];
871 }
872
873 memcpy(coords_arg, coords, sizeof(coords));
874 }
875
876 static void emit_icmp(
877 const struct lp_build_tgsi_action * action,
878 struct lp_build_tgsi_context * bld_base,
879 struct lp_build_emit_data * emit_data)
880 {
881 unsigned pred;
882 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
883 LLVMContextRef context = bld_base->base.gallivm->context;
884
885 switch (emit_data->inst->Instruction.Opcode) {
886 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
887 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
888 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
889 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
890 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
891 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
892 default:
893 assert(!"unknown instruction");
894 pred = 0;
895 break;
896 }
897
898 LLVMValueRef v = LLVMBuildICmp(builder, pred,
899 emit_data->args[0], emit_data->args[1],"");
900
901 v = LLVMBuildSExtOrBitCast(builder, v,
902 LLVMInt32TypeInContext(context), "");
903
904 emit_data->output[emit_data->chan] = v;
905 }
906
907 static void emit_ucmp(
908 const struct lp_build_tgsi_action * action,
909 struct lp_build_tgsi_context * bld_base,
910 struct lp_build_emit_data * emit_data)
911 {
912 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
913
914 LLVMValueRef arg0 = LLVMBuildBitCast(builder, emit_data->args[0],
915 bld_base->uint_bld.elem_type, "");
916
917 LLVMValueRef v = LLVMBuildICmp(builder, LLVMIntNE, arg0,
918 bld_base->uint_bld.zero, "");
919
920 emit_data->output[emit_data->chan] =
921 LLVMBuildSelect(builder, v, emit_data->args[1], emit_data->args[2], "");
922 }
923
924 static void emit_cmp(const struct lp_build_tgsi_action *action,
925 struct lp_build_tgsi_context *bld_base,
926 struct lp_build_emit_data *emit_data)
927 {
928 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
929 LLVMValueRef cond, *args = emit_data->args;
930
931 cond = LLVMBuildFCmp(builder, LLVMRealOLT, args[0],
932 bld_base->base.zero, "");
933
934 emit_data->output[emit_data->chan] =
935 LLVMBuildSelect(builder, cond, args[1], args[2], "");
936 }
937
938 static void emit_set_cond(
939 const struct lp_build_tgsi_action *action,
940 struct lp_build_tgsi_context * bld_base,
941 struct lp_build_emit_data * emit_data)
942 {
943 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
944 LLVMRealPredicate pred;
945 LLVMValueRef cond;
946
947 /* Use ordered for everything but NE (which is usual for
948 * float comparisons)
949 */
950 switch (emit_data->inst->Instruction.Opcode) {
951 case TGSI_OPCODE_SGE: pred = LLVMRealOGE; break;
952 case TGSI_OPCODE_SEQ: pred = LLVMRealOEQ; break;
953 case TGSI_OPCODE_SLE: pred = LLVMRealOLE; break;
954 case TGSI_OPCODE_SLT: pred = LLVMRealOLT; break;
955 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
956 case TGSI_OPCODE_SGT: pred = LLVMRealOGT; break;
957 default: assert(!"unknown instruction"); pred = 0; break;
958 }
959
960 cond = LLVMBuildFCmp(builder,
961 pred, emit_data->args[0], emit_data->args[1], "");
962
963 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
964 cond, bld_base->base.one, bld_base->base.zero, "");
965 }
966
967 static void emit_fcmp(
968 const struct lp_build_tgsi_action *action,
969 struct lp_build_tgsi_context * bld_base,
970 struct lp_build_emit_data * emit_data)
971 {
972 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
973 LLVMContextRef context = bld_base->base.gallivm->context;
974 LLVMRealPredicate pred;
975
976 /* Use ordered for everything but NE (which is usual for
977 * float comparisons)
978 */
979 switch (emit_data->inst->Instruction.Opcode) {
980 case TGSI_OPCODE_FSEQ: pred = LLVMRealOEQ; break;
981 case TGSI_OPCODE_FSGE: pred = LLVMRealOGE; break;
982 case TGSI_OPCODE_FSLT: pred = LLVMRealOLT; break;
983 case TGSI_OPCODE_FSNE: pred = LLVMRealUNE; break;
984 default: assert(!"unknown instruction"); pred = 0; break;
985 }
986
987 LLVMValueRef v = LLVMBuildFCmp(builder, pred,
988 emit_data->args[0], emit_data->args[1],"");
989
990 v = LLVMBuildSExtOrBitCast(builder, v,
991 LLVMInt32TypeInContext(context), "");
992
993 emit_data->output[emit_data->chan] = v;
994 }
995
996 static void emit_dcmp(
997 const struct lp_build_tgsi_action *action,
998 struct lp_build_tgsi_context * bld_base,
999 struct lp_build_emit_data * emit_data)
1000 {
1001 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1002 LLVMContextRef context = bld_base->base.gallivm->context;
1003 LLVMRealPredicate pred;
1004
1005 /* Use ordered for everything but NE (which is usual for
1006 * float comparisons)
1007 */
1008 switch (emit_data->inst->Instruction.Opcode) {
1009 case TGSI_OPCODE_DSEQ: pred = LLVMRealOEQ; break;
1010 case TGSI_OPCODE_DSGE: pred = LLVMRealOGE; break;
1011 case TGSI_OPCODE_DSLT: pred = LLVMRealOLT; break;
1012 case TGSI_OPCODE_DSNE: pred = LLVMRealUNE; break;
1013 default: assert(!"unknown instruction"); pred = 0; break;
1014 }
1015
1016 LLVMValueRef v = LLVMBuildFCmp(builder, pred,
1017 emit_data->args[0], emit_data->args[1],"");
1018
1019 v = LLVMBuildSExtOrBitCast(builder, v,
1020 LLVMInt32TypeInContext(context), "");
1021
1022 emit_data->output[emit_data->chan] = v;
1023 }
1024
1025 static void emit_not(
1026 const struct lp_build_tgsi_action * action,
1027 struct lp_build_tgsi_context * bld_base,
1028 struct lp_build_emit_data * emit_data)
1029 {
1030 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1031 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
1032 emit_data->args[0]);
1033 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
1034 }
1035
1036 static void emit_arl(
1037 const struct lp_build_tgsi_action * action,
1038 struct lp_build_tgsi_context * bld_base,
1039 struct lp_build_emit_data * emit_data)
1040 {
1041 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1042 LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
1043 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
1044 floor_index, bld_base->base.int_elem_type , "");
1045 }
1046
1047 static void emit_and(
1048 const struct lp_build_tgsi_action * action,
1049 struct lp_build_tgsi_context * bld_base,
1050 struct lp_build_emit_data * emit_data)
1051 {
1052 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1053 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
1054 emit_data->args[0], emit_data->args[1], "");
1055 }
1056
1057 static void emit_or(
1058 const struct lp_build_tgsi_action * action,
1059 struct lp_build_tgsi_context * bld_base,
1060 struct lp_build_emit_data * emit_data)
1061 {
1062 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1063 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
1064 emit_data->args[0], emit_data->args[1], "");
1065 }
1066
1067 static void emit_uadd(
1068 const struct lp_build_tgsi_action * action,
1069 struct lp_build_tgsi_context * bld_base,
1070 struct lp_build_emit_data * emit_data)
1071 {
1072 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1073 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
1074 emit_data->args[0], emit_data->args[1], "");
1075 }
1076
1077 static void emit_udiv(
1078 const struct lp_build_tgsi_action * action,
1079 struct lp_build_tgsi_context * bld_base,
1080 struct lp_build_emit_data * emit_data)
1081 {
1082 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1083 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
1084 emit_data->args[0], emit_data->args[1], "");
1085 }
1086
1087 static void emit_idiv(
1088 const struct lp_build_tgsi_action * action,
1089 struct lp_build_tgsi_context * bld_base,
1090 struct lp_build_emit_data * emit_data)
1091 {
1092 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1093 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
1094 emit_data->args[0], emit_data->args[1], "");
1095 }
1096
1097 static void emit_mod(
1098 const struct lp_build_tgsi_action * action,
1099 struct lp_build_tgsi_context * bld_base,
1100 struct lp_build_emit_data * emit_data)
1101 {
1102 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1103 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
1104 emit_data->args[0], emit_data->args[1], "");
1105 }
1106
1107 static void emit_umod(
1108 const struct lp_build_tgsi_action * action,
1109 struct lp_build_tgsi_context * bld_base,
1110 struct lp_build_emit_data * emit_data)
1111 {
1112 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1113 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
1114 emit_data->args[0], emit_data->args[1], "");
1115 }
1116
1117 static void emit_shl(
1118 const struct lp_build_tgsi_action * action,
1119 struct lp_build_tgsi_context * bld_base,
1120 struct lp_build_emit_data * emit_data)
1121 {
1122 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1123 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
1124 emit_data->args[0], emit_data->args[1], "");
1125 }
1126
1127 static void emit_ushr(
1128 const struct lp_build_tgsi_action * action,
1129 struct lp_build_tgsi_context * bld_base,
1130 struct lp_build_emit_data * emit_data)
1131 {
1132 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1133 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
1134 emit_data->args[0], emit_data->args[1], "");
1135 }
1136 static void emit_ishr(
1137 const struct lp_build_tgsi_action * action,
1138 struct lp_build_tgsi_context * bld_base,
1139 struct lp_build_emit_data * emit_data)
1140 {
1141 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1142 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
1143 emit_data->args[0], emit_data->args[1], "");
1144 }
1145
1146 static void emit_xor(
1147 const struct lp_build_tgsi_action * action,
1148 struct lp_build_tgsi_context * bld_base,
1149 struct lp_build_emit_data * emit_data)
1150 {
1151 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1152 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
1153 emit_data->args[0], emit_data->args[1], "");
1154 }
1155
1156 static void emit_ssg(
1157 const struct lp_build_tgsi_action * action,
1158 struct lp_build_tgsi_context * bld_base,
1159 struct lp_build_emit_data * emit_data)
1160 {
1161 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1162
1163 LLVMValueRef cmp, val;
1164
1165 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
1166 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
1167 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
1168 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
1169 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
1170 } else { // float SSG
1171 cmp = LLVMBuildFCmp(builder, LLVMRealOGT, emit_data->args[0], bld_base->base.zero, "");
1172 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
1173 cmp = LLVMBuildFCmp(builder, LLVMRealOGE, val, bld_base->base.zero, "");
1174 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
1175 }
1176
1177 emit_data->output[emit_data->chan] = val;
1178 }
1179
1180 static void emit_ineg(
1181 const struct lp_build_tgsi_action * action,
1182 struct lp_build_tgsi_context * bld_base,
1183 struct lp_build_emit_data * emit_data)
1184 {
1185 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1186 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
1187 emit_data->args[0], "");
1188 }
1189
1190 static void emit_dneg(
1191 const struct lp_build_tgsi_action * action,
1192 struct lp_build_tgsi_context * bld_base,
1193 struct lp_build_emit_data * emit_data)
1194 {
1195 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1196 emit_data->output[emit_data->chan] = LLVMBuildFNeg(builder,
1197 emit_data->args[0], "");
1198 }
1199
1200 static void emit_frac(
1201 const struct lp_build_tgsi_action * action,
1202 struct lp_build_tgsi_context * bld_base,
1203 struct lp_build_emit_data * emit_data)
1204 {
1205 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1206 char *intr;
1207
1208 if (emit_data->info->opcode == TGSI_OPCODE_FRC)
1209 intr = "llvm.floor.f32";
1210 else if (emit_data->info->opcode == TGSI_OPCODE_DFRAC)
1211 intr = "llvm.floor.f64";
1212 else {
1213 assert(0);
1214 return;
1215 }
1216
1217 LLVMValueRef floor = lp_build_intrinsic(builder, intr, emit_data->dst_type,
1218 &emit_data->args[0], 1,
1219 LLVMReadNoneAttribute);
1220 emit_data->output[emit_data->chan] = LLVMBuildFSub(builder,
1221 emit_data->args[0], floor, "");
1222 }
1223
1224 static void emit_f2i(
1225 const struct lp_build_tgsi_action * action,
1226 struct lp_build_tgsi_context * bld_base,
1227 struct lp_build_emit_data * emit_data)
1228 {
1229 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1230 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
1231 emit_data->args[0], bld_base->int_bld.elem_type, "");
1232 }
1233
1234 static void emit_f2u(
1235 const struct lp_build_tgsi_action * action,
1236 struct lp_build_tgsi_context * bld_base,
1237 struct lp_build_emit_data * emit_data)
1238 {
1239 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1240 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
1241 emit_data->args[0], bld_base->uint_bld.elem_type, "");
1242 }
1243
1244 static void emit_i2f(
1245 const struct lp_build_tgsi_action * action,
1246 struct lp_build_tgsi_context * bld_base,
1247 struct lp_build_emit_data * emit_data)
1248 {
1249 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1250 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
1251 emit_data->args[0], bld_base->base.elem_type, "");
1252 }
1253
1254 static void emit_u2f(
1255 const struct lp_build_tgsi_action * action,
1256 struct lp_build_tgsi_context * bld_base,
1257 struct lp_build_emit_data * emit_data)
1258 {
1259 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1260 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
1261 emit_data->args[0], bld_base->base.elem_type, "");
1262 }
1263
1264 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
1265 const struct tgsi_full_immediate *imm)
1266 {
1267 unsigned i;
1268 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
1269
1270 for (i = 0; i < 4; ++i) {
1271 ctx->soa.immediates[ctx->soa.num_immediates][i] =
1272 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false );
1273 }
1274
1275 ctx->soa.num_immediates++;
1276 }
1277
1278 void
1279 build_tgsi_intrinsic_nomem(const struct lp_build_tgsi_action *action,
1280 struct lp_build_tgsi_context *bld_base,
1281 struct lp_build_emit_data *emit_data)
1282 {
1283 struct lp_build_context * base = &bld_base->base;
1284 emit_data->output[emit_data->chan] =
1285 lp_build_intrinsic(base->gallivm->builder, action->intr_name,
1286 emit_data->dst_type, emit_data->args,
1287 emit_data->arg_count, LLVMReadNoneAttribute);
1288 }
1289
1290 static void emit_bfi(const struct lp_build_tgsi_action * action,
1291 struct lp_build_tgsi_context * bld_base,
1292 struct lp_build_emit_data * emit_data)
1293 {
1294 struct gallivm_state *gallivm = bld_base->base.gallivm;
1295 LLVMBuilderRef builder = gallivm->builder;
1296 LLVMValueRef bfi_args[3];
1297
1298 // Calculate the bitmask: (((1 << src3) - 1) << src2
1299 bfi_args[0] = LLVMBuildShl(builder,
1300 LLVMBuildSub(builder,
1301 LLVMBuildShl(builder,
1302 bld_base->int_bld.one,
1303 emit_data->args[3], ""),
1304 bld_base->int_bld.one, ""),
1305 emit_data->args[2], "");
1306
1307 bfi_args[1] = LLVMBuildShl(builder, emit_data->args[1],
1308 emit_data->args[2], "");
1309
1310 bfi_args[2] = emit_data->args[0];
1311
1312 /* Calculate:
1313 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1314 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1315 */
1316 emit_data->output[emit_data->chan] =
1317 LLVMBuildXor(builder, bfi_args[2],
1318 LLVMBuildAnd(builder, bfi_args[0],
1319 LLVMBuildXor(builder, bfi_args[1], bfi_args[2],
1320 ""), ""), "");
1321 }
1322
1323 /* this is ffs in C */
1324 static void emit_lsb(const struct lp_build_tgsi_action * action,
1325 struct lp_build_tgsi_context * bld_base,
1326 struct lp_build_emit_data * emit_data)
1327 {
1328 struct gallivm_state *gallivm = bld_base->base.gallivm;
1329 LLVMValueRef args[2] = {
1330 emit_data->args[0],
1331
1332 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1333 * add special code to check for x=0. The reason is that
1334 * the LLVM behavior for x=0 is different from what we
1335 * need here.
1336 *
1337 * The hardware already implements the correct behavior.
1338 */
1339 lp_build_const_int32(gallivm, 1)
1340 };
1341
1342 emit_data->output[emit_data->chan] =
1343 lp_build_intrinsic(gallivm->builder, "llvm.cttz.i32",
1344 emit_data->dst_type, args, ARRAY_SIZE(args),
1345 LLVMReadNoneAttribute);
1346 }
1347
1348 /* Find the last bit set. */
1349 static void emit_umsb(const struct lp_build_tgsi_action * action,
1350 struct lp_build_tgsi_context * bld_base,
1351 struct lp_build_emit_data * emit_data)
1352 {
1353 struct gallivm_state *gallivm = bld_base->base.gallivm;
1354 LLVMBuilderRef builder = gallivm->builder;
1355 LLVMValueRef args[2] = {
1356 emit_data->args[0],
1357 /* Don't generate code for handling zero: */
1358 lp_build_const_int32(gallivm, 1)
1359 };
1360
1361 LLVMValueRef msb =
1362 lp_build_intrinsic(builder, "llvm.ctlz.i32",
1363 emit_data->dst_type, args, ARRAY_SIZE(args),
1364 LLVMReadNoneAttribute);
1365
1366 /* The HW returns the last bit index from MSB, but TGSI wants
1367 * the index from LSB. Invert it by doing "31 - msb". */
1368 msb = LLVMBuildSub(builder, lp_build_const_int32(gallivm, 31),
1369 msb, "");
1370
1371 /* Check for zero: */
1372 emit_data->output[emit_data->chan] =
1373 LLVMBuildSelect(builder,
1374 LLVMBuildICmp(builder, LLVMIntEQ, args[0],
1375 bld_base->uint_bld.zero, ""),
1376 lp_build_const_int32(gallivm, -1), msb, "");
1377 }
1378
1379 /* Find the last bit opposite of the sign bit. */
1380 static void emit_imsb(const struct lp_build_tgsi_action * action,
1381 struct lp_build_tgsi_context * bld_base,
1382 struct lp_build_emit_data * emit_data)
1383 {
1384 struct gallivm_state *gallivm = bld_base->base.gallivm;
1385 LLVMBuilderRef builder = gallivm->builder;
1386 LLVMValueRef arg = emit_data->args[0];
1387
1388 LLVMValueRef msb =
1389 lp_build_intrinsic(builder, "llvm.AMDGPU.flbit.i32",
1390 emit_data->dst_type, &arg, 1,
1391 LLVMReadNoneAttribute);
1392
1393 /* The HW returns the last bit index from MSB, but TGSI wants
1394 * the index from LSB. Invert it by doing "31 - msb". */
1395 msb = LLVMBuildSub(builder, lp_build_const_int32(gallivm, 31),
1396 msb, "");
1397
1398 /* If arg == 0 || arg == -1 (0xffffffff), return -1. */
1399 LLVMValueRef all_ones = lp_build_const_int32(gallivm, -1);
1400
1401 LLVMValueRef cond =
1402 LLVMBuildOr(builder,
1403 LLVMBuildICmp(builder, LLVMIntEQ, arg,
1404 bld_base->uint_bld.zero, ""),
1405 LLVMBuildICmp(builder, LLVMIntEQ, arg,
1406 all_ones, ""), "");
1407
1408 emit_data->output[emit_data->chan] =
1409 LLVMBuildSelect(builder, cond, all_ones, msb, "");
1410 }
1411
1412 static void emit_iabs(const struct lp_build_tgsi_action *action,
1413 struct lp_build_tgsi_context *bld_base,
1414 struct lp_build_emit_data *emit_data)
1415 {
1416 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1417
1418 emit_data->output[emit_data->chan] =
1419 lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_IMAX,
1420 emit_data->args[0],
1421 LLVMBuildNeg(builder,
1422 emit_data->args[0], ""));
1423 }
1424
1425 static void emit_minmax_int(const struct lp_build_tgsi_action *action,
1426 struct lp_build_tgsi_context *bld_base,
1427 struct lp_build_emit_data *emit_data)
1428 {
1429 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1430 LLVMIntPredicate op;
1431
1432 switch (emit_data->info->opcode) {
1433 default:
1434 assert(0);
1435 case TGSI_OPCODE_IMAX:
1436 op = LLVMIntSGT;
1437 break;
1438 case TGSI_OPCODE_IMIN:
1439 op = LLVMIntSLT;
1440 break;
1441 case TGSI_OPCODE_UMAX:
1442 op = LLVMIntUGT;
1443 break;
1444 case TGSI_OPCODE_UMIN:
1445 op = LLVMIntULT;
1446 break;
1447 }
1448
1449 emit_data->output[emit_data->chan] =
1450 LLVMBuildSelect(builder,
1451 LLVMBuildICmp(builder, op, emit_data->args[0],
1452 emit_data->args[1], ""),
1453 emit_data->args[0],
1454 emit_data->args[1], "");
1455 }
1456
1457 static void pk2h_fetch_args(struct lp_build_tgsi_context * bld_base,
1458 struct lp_build_emit_data * emit_data)
1459 {
1460 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
1461 0, TGSI_CHAN_X);
1462 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
1463 0, TGSI_CHAN_Y);
1464 }
1465
1466 static void emit_pk2h(const struct lp_build_tgsi_action *action,
1467 struct lp_build_tgsi_context *bld_base,
1468 struct lp_build_emit_data *emit_data)
1469 {
1470 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1471 LLVMContextRef context = bld_base->base.gallivm->context;
1472 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1473 LLVMTypeRef fp16, i16;
1474 LLVMValueRef const16, comp[2];
1475 unsigned i;
1476
1477 fp16 = LLVMHalfTypeInContext(context);
1478 i16 = LLVMInt16TypeInContext(context);
1479 const16 = lp_build_const_int32(uint_bld->gallivm, 16);
1480
1481 for (i = 0; i < 2; i++) {
1482 comp[i] = LLVMBuildFPTrunc(builder, emit_data->args[i], fp16, "");
1483 comp[i] = LLVMBuildBitCast(builder, comp[i], i16, "");
1484 comp[i] = LLVMBuildZExt(builder, comp[i], uint_bld->elem_type, "");
1485 }
1486
1487 comp[1] = LLVMBuildShl(builder, comp[1], const16, "");
1488 comp[0] = LLVMBuildOr(builder, comp[0], comp[1], "");
1489
1490 emit_data->output[emit_data->chan] = comp[0];
1491 }
1492
1493 static void up2h_fetch_args(struct lp_build_tgsi_context * bld_base,
1494 struct lp_build_emit_data * emit_data)
1495 {
1496 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
1497 0, TGSI_CHAN_X);
1498 }
1499
1500 static void emit_up2h(const struct lp_build_tgsi_action *action,
1501 struct lp_build_tgsi_context *bld_base,
1502 struct lp_build_emit_data *emit_data)
1503 {
1504 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1505 LLVMContextRef context = bld_base->base.gallivm->context;
1506 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1507 LLVMTypeRef fp16, i16;
1508 LLVMValueRef const16, input, val;
1509 unsigned i;
1510
1511 fp16 = LLVMHalfTypeInContext(context);
1512 i16 = LLVMInt16TypeInContext(context);
1513 const16 = lp_build_const_int32(uint_bld->gallivm, 16);
1514 input = emit_data->args[0];
1515
1516 for (i = 0; i < 2; i++) {
1517 val = i == 1 ? LLVMBuildLShr(builder, input, const16, "") : input;
1518 val = LLVMBuildTrunc(builder, val, i16, "");
1519 val = LLVMBuildBitCast(builder, val, fp16, "");
1520 emit_data->output[i] =
1521 LLVMBuildFPExt(builder, val, bld_base->base.elem_type, "");
1522 }
1523 }
1524
1525 void radeon_llvm_context_init(struct radeon_llvm_context * ctx, const char *triple)
1526 {
1527 struct lp_type type;
1528
1529 /* Initialize the gallivm object:
1530 * We are only using the module, context, and builder fields of this struct.
1531 * This should be enough for us to be able to pass our gallivm struct to the
1532 * helper functions in the gallivm module.
1533 */
1534 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
1535 memset(&ctx->soa, 0, sizeof(ctx->soa));
1536 ctx->gallivm.context = LLVMContextCreate();
1537 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
1538 ctx->gallivm.context);
1539 LLVMSetTarget(ctx->gallivm.module, triple);
1540 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
1541
1542 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1543
1544 type.floating = TRUE;
1545 type.fixed = FALSE;
1546 type.sign = TRUE;
1547 type.norm = FALSE;
1548 type.width = 32;
1549 type.length = 1;
1550
1551 lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1552 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1553 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1554 {
1555 struct lp_type dbl_type;
1556 dbl_type = type;
1557 dbl_type.width *= 2;
1558 lp_build_context_init(&ctx->soa.bld_base.dbl_bld, &ctx->gallivm, dbl_type);
1559 }
1560
1561 bld_base->soa = 1;
1562 bld_base->emit_store = radeon_llvm_emit_store;
1563 bld_base->emit_swizzle = emit_swizzle;
1564 bld_base->emit_declaration = emit_declaration;
1565 bld_base->emit_immediate = emit_immediate;
1566
1567 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = radeon_llvm_emit_fetch;
1568 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = radeon_llvm_emit_fetch;
1569 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = radeon_llvm_emit_fetch;
1570 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = radeon_llvm_emit_fetch;
1571 bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = fetch_system_value;
1572
1573 /* Allocate outputs */
1574 ctx->soa.outputs = ctx->outputs;
1575
1576 lp_set_default_actions(bld_base);
1577
1578 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_nomem;
1579 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "llvm.fabs.f32";
1580 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1581 bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
1582 bld_base->op_actions[TGSI_OPCODE_BFI].emit = emit_bfi;
1583 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1584 bld_base->op_actions[TGSI_OPCODE_BREV].emit = build_tgsi_intrinsic_nomem;
1585 bld_base->op_actions[TGSI_OPCODE_BREV].intr_name =
1586 HAVE_LLVM >= 0x0308 ? "llvm.bitreverse.i32" : "llvm.AMDGPU.brev";
1587 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1588 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
1589 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.ceil.f32";
1590 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1591 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name =
1592 HAVE_LLVM >= 0x0308 ? "llvm.AMDGPU.clamp." : "llvm.AMDIL.clamp.";
1593 bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cmp;
1594 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1595 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
1596 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
1597 bld_base->op_actions[TGSI_OPCODE_DABS].emit = build_tgsi_intrinsic_nomem;
1598 bld_base->op_actions[TGSI_OPCODE_DABS].intr_name = "llvm.fabs.f64";
1599 bld_base->op_actions[TGSI_OPCODE_DFMA].emit = build_tgsi_intrinsic_nomem;
1600 bld_base->op_actions[TGSI_OPCODE_DFMA].intr_name = "llvm.fma.f64";
1601 bld_base->op_actions[TGSI_OPCODE_DFRAC].emit = emit_frac;
1602 bld_base->op_actions[TGSI_OPCODE_DNEG].emit = emit_dneg;
1603 bld_base->op_actions[TGSI_OPCODE_DSEQ].emit = emit_dcmp;
1604 bld_base->op_actions[TGSI_OPCODE_DSGE].emit = emit_dcmp;
1605 bld_base->op_actions[TGSI_OPCODE_DSLT].emit = emit_dcmp;
1606 bld_base->op_actions[TGSI_OPCODE_DSNE].emit = emit_dcmp;
1607 bld_base->op_actions[TGSI_OPCODE_DRSQ].emit = build_tgsi_intrinsic_nomem;
1608 bld_base->op_actions[TGSI_OPCODE_DRSQ].intr_name = "llvm.AMDGPU.rsq.f64";
1609 bld_base->op_actions[TGSI_OPCODE_DSQRT].emit = build_tgsi_intrinsic_nomem;
1610 bld_base->op_actions[TGSI_OPCODE_DSQRT].intr_name = "llvm.sqrt.f64";
1611 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1612 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1613 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1614 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1615 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name =
1616 HAVE_LLVM >= 0x0308 ? "llvm.exp2.f32" : "llvm.AMDIL.exp.";
1617 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
1618 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.floor.f32";
1619 bld_base->op_actions[TGSI_OPCODE_FMA].emit = build_tgsi_intrinsic_nomem;
1620 bld_base->op_actions[TGSI_OPCODE_FMA].intr_name = "llvm.fma.f32";
1621 bld_base->op_actions[TGSI_OPCODE_FRC].emit = emit_frac;
1622 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1623 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1624 bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
1625 bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp;
1626 bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp;
1627 bld_base->op_actions[TGSI_OPCODE_FSNE].emit = emit_fcmp;
1628 bld_base->op_actions[TGSI_OPCODE_IABS].emit = emit_iabs;
1629 bld_base->op_actions[TGSI_OPCODE_IBFE].emit = build_tgsi_intrinsic_nomem;
1630 bld_base->op_actions[TGSI_OPCODE_IBFE].intr_name = "llvm.AMDGPU.bfe.i32";
1631 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1632 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1633 bld_base->op_actions[TGSI_OPCODE_UIF].emit = uif_emit;
1634 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = emit_minmax_int;
1635 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = emit_minmax_int;
1636 bld_base->op_actions[TGSI_OPCODE_IMSB].emit = emit_imsb;
1637 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1638 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1639 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1640 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1641 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1642 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1643 bld_base->op_actions[TGSI_OPCODE_KILL_IF].fetch_args = kill_if_fetch_args;
1644 bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit;
1645 bld_base->op_actions[TGSI_OPCODE_KILL_IF].intr_name = "llvm.AMDGPU.kill";
1646 bld_base->op_actions[TGSI_OPCODE_KILL].emit = lp_build_tgsi_intrinsic;
1647 bld_base->op_actions[TGSI_OPCODE_KILL].intr_name = "llvm.AMDGPU.kilp";
1648 bld_base->op_actions[TGSI_OPCODE_LSB].emit = emit_lsb;
1649 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem;
1650 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
1651 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1652 bld_base->op_actions[TGSI_OPCODE_UMSB].emit = emit_umsb;
1653 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1654 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1655 bld_base->op_actions[TGSI_OPCODE_PK2H].fetch_args = pk2h_fetch_args;
1656 bld_base->op_actions[TGSI_OPCODE_PK2H].emit = emit_pk2h;
1657 bld_base->op_actions[TGSI_OPCODE_POPC].emit = build_tgsi_intrinsic_nomem;
1658 bld_base->op_actions[TGSI_OPCODE_POPC].intr_name = "llvm.ctpop.i32";
1659 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_nomem;
1660 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
1661 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1662 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.rint.f32";
1663 bld_base->op_actions[TGSI_OPCODE_RSQ].intr_name = "llvm.AMDGPU.rsq.clamped.f32";
1664 bld_base->op_actions[TGSI_OPCODE_RSQ].emit = build_tgsi_intrinsic_nomem;
1665 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_set_cond;
1666 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_set_cond;
1667 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1668 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_set_cond;
1669 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_set_cond;
1670 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_set_cond;
1671 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_set_cond;
1672 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
1673 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
1674 bld_base->op_actions[TGSI_OPCODE_SQRT].emit = build_tgsi_intrinsic_nomem;
1675 bld_base->op_actions[TGSI_OPCODE_SQRT].intr_name = "llvm.sqrt.f32";
1676 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1677 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1678 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.trunc.f32";
1679 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1680 bld_base->op_actions[TGSI_OPCODE_UBFE].emit = build_tgsi_intrinsic_nomem;
1681 bld_base->op_actions[TGSI_OPCODE_UBFE].intr_name = "llvm.AMDGPU.bfe.u32";
1682 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1683 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = emit_minmax_int;
1684 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = emit_minmax_int;
1685 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1686 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1687 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1688 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1689 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1690 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1691 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1692 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1693 bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
1694 bld_base->op_actions[TGSI_OPCODE_UP2H].fetch_args = up2h_fetch_args;
1695 bld_base->op_actions[TGSI_OPCODE_UP2H].emit = emit_up2h;
1696 }
1697
1698 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
1699 LLVMTypeRef *return_types, unsigned num_return_elems,
1700 LLVMTypeRef *ParamTypes, unsigned ParamCount)
1701 {
1702 LLVMTypeRef main_fn_type, ret_type;
1703 LLVMBasicBlockRef main_fn_body;
1704
1705 if (num_return_elems)
1706 ret_type = LLVMStructTypeInContext(ctx->gallivm.context,
1707 return_types,
1708 num_return_elems, true);
1709 else
1710 ret_type = LLVMVoidTypeInContext(ctx->gallivm.context);
1711
1712 /* Setup the function */
1713 ctx->return_type = ret_type;
1714 main_fn_type = LLVMFunctionType(ret_type, ParamTypes, ParamCount, 0);
1715 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1716 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1717 ctx->main_fn, "main_body");
1718 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1719 }
1720
1721 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1722 {
1723 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1724 const char *triple = LLVMGetTarget(gallivm->module);
1725 LLVMTargetLibraryInfoRef target_library_info;
1726
1727 /* Create the pass manager */
1728 gallivm->passmgr = LLVMCreateFunctionPassManagerForModule(
1729 gallivm->module);
1730
1731 target_library_info = gallivm_create_target_library_info(triple);
1732 LLVMAddTargetLibraryInfo(target_library_info, gallivm->passmgr);
1733
1734 /* This pass should eliminate all the load and store instructions */
1735 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1736
1737 /* Add some optimization passes */
1738 LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1739 LLVMAddLICMPass(gallivm->passmgr);
1740 LLVMAddAggressiveDCEPass(gallivm->passmgr);
1741 LLVMAddCFGSimplificationPass(gallivm->passmgr);
1742 LLVMAddInstructionCombiningPass(gallivm->passmgr);
1743
1744 /* Run the pass */
1745 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1746
1747 LLVMDisposeBuilder(gallivm->builder);
1748 LLVMDisposePassManager(gallivm->passmgr);
1749 gallivm_dispose_target_library_info(target_library_info);
1750 }
1751
1752 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1753 {
1754 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1755 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1756 FREE(ctx->arrays);
1757 ctx->arrays = NULL;
1758 FREE(ctx->temps);
1759 ctx->temps = NULL;
1760 ctx->temps_count = 0;
1761 FREE(ctx->loop);
1762 ctx->loop = NULL;
1763 ctx->loop_depth_max = 0;
1764 FREE(ctx->branch);
1765 ctx->branch = NULL;
1766 ctx->branch_depth_max = 0;
1767 }