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[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26 #include "radeon_llvm.h"
27
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
42
43 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
44 {
45 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
46 }
47
48 static struct radeon_llvm_branch * get_current_branch(
49 struct radeon_llvm_context * ctx)
50 {
51 return ctx->branch_depth > 0 ?
52 ctx->branch + (ctx->branch_depth - 1) : NULL;
53 }
54
55 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
56 {
57 return (index * 4) + chan;
58 }
59
60 static LLVMValueRef emit_swizzle(
61 struct lp_build_tgsi_context * bld_base,
62 LLVMValueRef value,
63 unsigned swizzle_x,
64 unsigned swizzle_y,
65 unsigned swizzle_z,
66 unsigned swizzle_w)
67 {
68 unsigned char swizzles[4];
69 swizzles[0] = swizzle_x;
70 swizzles[1] = swizzle_y;
71 swizzles[2] = swizzle_z;
72 swizzles[3] = swizzle_w;
73
74
75 return lp_build_swizzle_aos(&bld_base->base, value, swizzles);
76 }
77
78 static LLVMValueRef
79 emit_array_index(
80 struct lp_build_tgsi_soa_context *bld,
81 const struct tgsi_full_src_register *reg,
82 unsigned swizzle)
83 {
84 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
85
86 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder,
87 bld->addr[reg->Indirect.Index][swizzle], "");
88 LLVMValueRef offset = lp_build_const_int32(gallivm, reg->Register.Index);
89 LLVMValueRef hw_index = LLVMBuildAdd(gallivm->builder, addr, offset, "");
90 LLVMValueRef soa_index = LLVMBuildMul(gallivm->builder, hw_index,
91 lp_build_const_int32(gallivm, 4), "");
92 LLVMValueRef array_index = LLVMBuildAdd(gallivm->builder, soa_index,
93 lp_build_const_int32(gallivm, swizzle), "");
94
95 return array_index;
96 }
97
98 static LLVMValueRef
99 emit_fetch_immediate(
100 struct lp_build_tgsi_context *bld_base,
101 const struct tgsi_full_src_register *reg,
102 enum tgsi_opcode_type type,
103 unsigned swizzle)
104 {
105 LLVMTypeRef ctype;
106 LLVMContextRef ctx = bld_base->base.gallivm->context;
107
108 switch (type) {
109 case TGSI_TYPE_UNSIGNED:
110 case TGSI_TYPE_SIGNED:
111 ctype = LLVMInt32TypeInContext(ctx);
112 break;
113 case TGSI_TYPE_UNTYPED:
114 case TGSI_TYPE_FLOAT:
115 ctype = LLVMFloatTypeInContext(ctx);
116 break;
117 default:
118 ctype = 0;
119 break;
120 }
121
122 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
123 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
124 }
125
126 static LLVMValueRef
127 emit_fetch_input(
128 struct lp_build_tgsi_context *bld_base,
129 const struct tgsi_full_src_register *reg,
130 enum tgsi_opcode_type type,
131 unsigned swizzle)
132 {
133 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
134 if (swizzle == ~0) {
135 LLVMValueRef values[TGSI_NUM_CHANNELS] = {};
136 unsigned chan;
137 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
138 values[chan] = ctx->inputs[radeon_llvm_reg_index_soa(
139 reg->Register.Index, chan)];
140 }
141 return lp_build_gather_values(bld_base->base.gallivm, values,
142 TGSI_NUM_CHANNELS);
143 } else {
144 return bitcast(bld_base, type, ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)]);
145 }
146 }
147
148 static LLVMValueRef
149 emit_fetch_temporary(
150 struct lp_build_tgsi_context *bld_base,
151 const struct tgsi_full_src_register *reg,
152 enum tgsi_opcode_type type,
153 unsigned swizzle)
154 {
155 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
156 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
157 if (reg->Register.Indirect) {
158 LLVMValueRef array_index = emit_array_index(bld, reg, swizzle);
159 LLVMValueRef ptr = LLVMBuildGEP(builder, bld->temps_array, &array_index,
160 1, "");
161 return LLVMBuildLoad(builder, ptr, "");
162 } else {
163 LLVMValueRef temp_ptr;
164 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
165 return bitcast(bld_base,type,LLVMBuildLoad(builder, temp_ptr, ""));
166 }
167 }
168
169 static LLVMValueRef
170 emit_fetch_output(
171 struct lp_build_tgsi_context *bld_base,
172 const struct tgsi_full_src_register *reg,
173 enum tgsi_opcode_type type,
174 unsigned swizzle)
175 {
176 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
177 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
178 if (reg->Register.Indirect) {
179 LLVMValueRef array_index = emit_array_index(bld, reg, swizzle);
180 LLVMValueRef ptr = LLVMBuildGEP(builder, bld->outputs_array, &array_index,
181 1, "");
182 return LLVMBuildLoad(builder, ptr, "");
183 } else {
184 LLVMValueRef temp_ptr;
185 temp_ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
186 return LLVMBuildLoad(builder, temp_ptr, "");
187 }
188 }
189
190 static void emit_declaration(
191 struct lp_build_tgsi_context * bld_base,
192 const struct tgsi_full_declaration *decl)
193 {
194 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
195 switch(decl->Declaration.File) {
196 case TGSI_FILE_ADDRESS:
197 {
198 unsigned idx;
199 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
200 unsigned chan;
201 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
202 ctx->soa.addr[idx][chan] = lp_build_alloca(
203 &ctx->gallivm,
204 ctx->soa.bld_base.uint_bld.elem_type, "");
205 }
206 }
207 break;
208 }
209
210 case TGSI_FILE_TEMPORARY:
211 lp_emit_declaration_soa(bld_base, decl);
212 break;
213
214 case TGSI_FILE_INPUT:
215 {
216 unsigned idx;
217 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
218 ctx->load_input(ctx, idx, decl);
219 }
220 }
221 break;
222
223 case TGSI_FILE_SYSTEM_VALUE:
224 {
225 unsigned idx;
226 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
227 ctx->load_system_value(ctx, idx, decl);
228 }
229 }
230 break;
231
232 case TGSI_FILE_OUTPUT:
233 {
234 unsigned idx;
235 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
236 unsigned chan;
237 assert(idx < RADEON_LLVM_MAX_OUTPUTS);
238 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
239 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm,
240 ctx->soa.bld_base.base.elem_type, "");
241 }
242 }
243
244 ctx->output_reg_count = MAX2(ctx->output_reg_count,
245 decl->Range.Last + 1);
246 break;
247 }
248
249 default:
250 break;
251 }
252 }
253
254 static void
255 emit_store(
256 struct lp_build_tgsi_context * bld_base,
257 const struct tgsi_full_instruction * inst,
258 const struct tgsi_opcode_info * info,
259 LLVMValueRef dst[4])
260 {
261 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
262 struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
263 struct lp_build_context base = bld->bld_base.base;
264 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
265 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
266 LLVMValueRef temp_ptr;
267 unsigned chan, chan_index;
268 boolean is_vec_store = FALSE;
269 if (dst[0]) {
270 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
271 is_vec_store = (k == LLVMVectorTypeKind);
272 }
273
274 if (is_vec_store) {
275 LLVMValueRef values[4] = {};
276 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
277 LLVMValueRef index = lp_build_const_int32(gallivm, chan);
278 values[chan] = LLVMBuildExtractElement(gallivm->builder,
279 dst[0], index, "");
280 }
281 bld_base->emit_store(bld_base, inst, info, values);
282 return;
283 }
284
285 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
286 LLVMValueRef value = dst[chan_index];
287
288 if (inst->Instruction.Saturate != TGSI_SAT_NONE) {
289 struct lp_build_emit_data clamp_emit_data;
290
291 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
292 clamp_emit_data.arg_count = 3;
293 clamp_emit_data.args[0] = value;
294 clamp_emit_data.args[2] = base.one;
295
296 switch(inst->Instruction.Saturate) {
297 case TGSI_SAT_ZERO_ONE:
298 clamp_emit_data.args[1] = base.zero;
299 break;
300 case TGSI_SAT_MINUS_PLUS_ONE:
301 clamp_emit_data.args[1] = LLVMConstReal(
302 base.elem_type, -1.0f);
303 break;
304 default:
305 assert(0);
306 }
307 value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
308 &clamp_emit_data);
309 }
310
311 switch(reg->Register.File) {
312 case TGSI_FILE_OUTPUT:
313 temp_ptr = bld->outputs[reg->Register.Index][chan_index];
314 break;
315
316 case TGSI_FILE_TEMPORARY:
317 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, chan_index);
318 break;
319
320 default:
321 return;
322 }
323
324 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
325
326 LLVMBuildStore(builder, value, temp_ptr);
327 }
328 }
329
330 static void bgnloop_emit(
331 const struct lp_build_tgsi_action * action,
332 struct lp_build_tgsi_context * bld_base,
333 struct lp_build_emit_data * emit_data)
334 {
335 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
336 struct gallivm_state * gallivm = bld_base->base.gallivm;
337 LLVMBasicBlockRef loop_block;
338 LLVMBasicBlockRef endloop_block;
339 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
340 ctx->main_fn, "ENDLOOP");
341 loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
342 endloop_block, "LOOP");
343 LLVMBuildBr(gallivm->builder, loop_block);
344 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
345 ctx->loop_depth++;
346 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
347 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
348 }
349
350 static void brk_emit(
351 const struct lp_build_tgsi_action * action,
352 struct lp_build_tgsi_context * bld_base,
353 struct lp_build_emit_data * emit_data)
354 {
355 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
356 struct gallivm_state * gallivm = bld_base->base.gallivm;
357 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
358
359 LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
360 }
361
362 static void cont_emit(
363 const struct lp_build_tgsi_action * action,
364 struct lp_build_tgsi_context * bld_base,
365 struct lp_build_emit_data * emit_data)
366 {
367 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
368 struct gallivm_state * gallivm = bld_base->base.gallivm;
369 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
370
371 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
372 }
373
374 static void else_emit(
375 const struct lp_build_tgsi_action * action,
376 struct lp_build_tgsi_context * bld_base,
377 struct lp_build_emit_data * emit_data)
378 {
379 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
380 struct gallivm_state * gallivm = bld_base->base.gallivm;
381 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
382 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
383
384 /* We need to add a terminator to the current block if the previous
385 * instruction was an ENDIF.Example:
386 * IF
387 * [code]
388 * IF
389 * [code]
390 * ELSE
391 * [code]
392 * ENDIF <--
393 * ELSE<--
394 * [code]
395 * ENDIF
396 */
397
398 if (current_block != current_branch->if_block) {
399 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
400 }
401 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
402 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
403 }
404 current_branch->has_else = 1;
405 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
406 }
407
408 static void endif_emit(
409 const struct lp_build_tgsi_action * action,
410 struct lp_build_tgsi_context * bld_base,
411 struct lp_build_emit_data * emit_data)
412 {
413 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
414 struct gallivm_state * gallivm = bld_base->base.gallivm;
415 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
416 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
417
418 /* If we have consecutive ENDIF instructions, then the first ENDIF
419 * will not have a terminator, so we need to add one. */
420 if (current_block != current_branch->if_block
421 && current_block != current_branch->else_block
422 && !LLVMGetBasicBlockTerminator(current_block)) {
423
424 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
425 }
426 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
427 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
428 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
429 }
430
431 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
432 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
433 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
434 }
435
436 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
437 ctx->branch_depth--;
438 }
439
440 static void endloop_emit(
441 const struct lp_build_tgsi_action * action,
442 struct lp_build_tgsi_context * bld_base,
443 struct lp_build_emit_data * emit_data)
444 {
445 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
446 struct gallivm_state * gallivm = bld_base->base.gallivm;
447 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
448
449 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
450 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
451 }
452
453 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
454 ctx->loop_depth--;
455 }
456
457 static void if_emit(
458 const struct lp_build_tgsi_action * action,
459 struct lp_build_tgsi_context * bld_base,
460 struct lp_build_emit_data * emit_data)
461 {
462 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
463 struct gallivm_state * gallivm = bld_base->base.gallivm;
464 LLVMValueRef cond;
465 LLVMBasicBlockRef if_block, else_block, endif_block;
466
467 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
468 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
469 bld_base->int_bld.zero, "");
470
471 endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
472 ctx->main_fn, "ENDIF");
473 if_block = LLVMInsertBasicBlockInContext(gallivm->context,
474 endif_block, "IF");
475 else_block = LLVMInsertBasicBlockInContext(gallivm->context,
476 endif_block, "ELSE");
477 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
478 LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
479
480 ctx->branch_depth++;
481 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
482 ctx->branch[ctx->branch_depth - 1].if_block = if_block;
483 ctx->branch[ctx->branch_depth - 1].else_block = else_block;
484 ctx->branch[ctx->branch_depth - 1].has_else = 0;
485 }
486
487 static void kil_emit(
488 const struct lp_build_tgsi_action * action,
489 struct lp_build_tgsi_context * bld_base,
490 struct lp_build_emit_data * emit_data)
491 {
492 unsigned i;
493 for (i = 0; i < emit_data->arg_count; i++) {
494 emit_data->output[i] = lp_build_intrinsic_unary(
495 bld_base->base.gallivm->builder,
496 action->intr_name,
497 emit_data->dst_type, emit_data->args[i]);
498 }
499 }
500
501
502 static void emit_prepare_cube_coords(
503 struct lp_build_tgsi_context * bld_base,
504 struct lp_build_emit_data * emit_data)
505 {
506 boolean shadowcube = (emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE);
507 struct gallivm_state * gallivm = bld_base->base.gallivm;
508 LLVMBuilderRef builder = gallivm->builder;
509 LLVMTypeRef type = bld_base->base.elem_type;
510 LLVMValueRef coords[4];
511 LLVMValueRef mad_args[3];
512 unsigned i, cnt;
513
514 LLVMValueRef v = build_intrinsic(builder, "llvm.AMDGPU.cube",
515 LLVMVectorType(type, 4),
516 &emit_data->args[0],1, LLVMReadNoneAttribute);
517
518 /* save src.w for shadow cube */
519 cnt = shadowcube ? 3 : 4;
520
521 for (i = 0; i < cnt; ++i) {
522 LLVMValueRef idx = lp_build_const_int32(gallivm, i);
523 coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
524 }
525
526 coords[2] = build_intrinsic(builder, "llvm.AMDIL.fabs.",
527 type, &coords[2], 1, LLVMReadNoneAttribute);
528 coords[2] = build_intrinsic(builder, "llvm.AMDGPU.rcp",
529 type, &coords[2], 1, LLVMReadNoneAttribute);
530
531 mad_args[1] = coords[2];
532 mad_args[2] = LLVMConstReal(type, 1.5);
533
534 mad_args[0] = coords[0];
535 coords[0] = build_intrinsic(builder, "llvm.AMDIL.mad.",
536 type, mad_args, 3, LLVMReadNoneAttribute);
537
538 mad_args[0] = coords[1];
539 coords[1] = build_intrinsic(builder, "llvm.AMDIL.mad.",
540 type, mad_args, 3, LLVMReadNoneAttribute);
541
542 /* apply yxwy swizzle to cooords */
543 coords[2] = coords[3];
544 coords[3] = coords[1];
545 coords[1] = coords[0];
546 coords[0] = coords[3];
547
548 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
549 coords, 4);
550 }
551
552 static void txd_fetch_args(
553 struct lp_build_tgsi_context * bld_base,
554 struct lp_build_emit_data * emit_data)
555 {
556 const struct tgsi_full_instruction * inst = emit_data->inst;
557
558 LLVMValueRef coords[4];
559 unsigned chan, src;
560 for (src = 0; src < 3; src++) {
561 for (chan = 0; chan < 4; chan++)
562 coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan);
563
564 emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm,
565 coords, 4);
566 }
567 emit_data->arg_count = 3;
568 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
569 }
570
571
572 static void txp_fetch_args(
573 struct lp_build_tgsi_context * bld_base,
574 struct lp_build_emit_data * emit_data)
575 {
576 const struct tgsi_full_instruction * inst = emit_data->inst;
577 LLVMValueRef src_w;
578 unsigned chan;
579 LLVMValueRef coords[4];
580
581 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
582 src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
583
584 for (chan = 0; chan < 3; chan++ ) {
585 LLVMValueRef arg = lp_build_emit_fetch(bld_base,
586 emit_data->inst, 0, chan);
587 coords[chan] = lp_build_emit_llvm_binary(bld_base,
588 TGSI_OPCODE_DIV, arg, src_w);
589 }
590 coords[3] = bld_base->base.one;
591 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
592 coords, 4);
593 emit_data->arg_count = 1;
594
595 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
596 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) &&
597 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
598 emit_prepare_cube_coords(bld_base, emit_data);
599 }
600 }
601
602 static void tex_fetch_args(
603 struct lp_build_tgsi_context * bld_base,
604 struct lp_build_emit_data * emit_data)
605 {
606 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
607 * when we used CHAN_ALL. We should be able to get this to work,
608 * but for now we will swizzle it ourselves
609 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
610 0, CHAN_ALL);
611
612 */
613
614 const struct tgsi_full_instruction * inst = emit_data->inst;
615
616 LLVMValueRef coords[4];
617 unsigned chan;
618 for (chan = 0; chan < 4; chan++) {
619 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
620 }
621
622 emit_data->arg_count = 1;
623 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
624 coords, 4);
625 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
626
627 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
628 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) &&
629 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
630 emit_prepare_cube_coords(bld_base, emit_data);
631 }
632 }
633
634 static void txf_fetch_args(
635 struct lp_build_tgsi_context * bld_base,
636 struct lp_build_emit_data * emit_data)
637 {
638 const struct tgsi_full_instruction * inst = emit_data->inst;
639 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
640 const struct tgsi_texture_offset * off = inst->TexOffsets;
641 LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
642
643 /* fetch tex coords */
644 tex_fetch_args(bld_base, emit_data);
645
646 /* fetch tex offsets */
647 if (inst->Texture.NumOffsets) {
648 assert(inst->Texture.NumOffsets == 1);
649
650 emit_data->args[1] = LLVMConstBitCast(
651 bld->immediates[off->Index][off->SwizzleX],
652 offset_type);
653 emit_data->args[2] = LLVMConstBitCast(
654 bld->immediates[off->Index][off->SwizzleY],
655 offset_type);
656 emit_data->args[3] = LLVMConstBitCast(
657 bld->immediates[off->Index][off->SwizzleZ],
658 offset_type);
659 } else {
660 emit_data->args[1] = bld_base->int_bld.zero;
661 emit_data->args[2] = bld_base->int_bld.zero;
662 emit_data->args[3] = bld_base->int_bld.zero;
663 }
664
665 emit_data->arg_count = 4;
666 }
667
668 static void emit_icmp(
669 const struct lp_build_tgsi_action * action,
670 struct lp_build_tgsi_context * bld_base,
671 struct lp_build_emit_data * emit_data)
672 {
673 unsigned pred;
674 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
675 LLVMContextRef context = bld_base->base.gallivm->context;
676
677 switch (emit_data->inst->Instruction.Opcode) {
678 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
679 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
680 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
681 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
682 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
683 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
684 default:
685 assert(!"unknown instruction");
686 }
687
688 LLVMValueRef v = LLVMBuildICmp(builder, pred,
689 emit_data->args[0], emit_data->args[1],"");
690
691 v = LLVMBuildSExtOrBitCast(builder, v,
692 LLVMInt32TypeInContext(context), "");
693
694 emit_data->output[emit_data->chan] = v;
695 }
696
697 static void emit_cmp(
698 const struct lp_build_tgsi_action *action,
699 struct lp_build_tgsi_context * bld_base,
700 struct lp_build_emit_data * emit_data)
701 {
702 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
703 LLVMRealPredicate pred;
704 LLVMValueRef cond;
705
706 /* XXX I'm not sure whether to do unordered or ordered comparisons,
707 * but llvmpipe uses unordered comparisons, so for consistency we use
708 * unordered. (The authors of llvmpipe aren't sure about using
709 * unordered vs ordered comparisons either.
710 */
711 switch (emit_data->inst->Instruction.Opcode) {
712 case TGSI_OPCODE_SGE: pred = LLVMRealUGE; break;
713 case TGSI_OPCODE_SEQ: pred = LLVMRealUEQ; break;
714 case TGSI_OPCODE_SLE: pred = LLVMRealULE; break;
715 case TGSI_OPCODE_SLT: pred = LLVMRealULT; break;
716 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
717 case TGSI_OPCODE_SGT: pred = LLVMRealUGT; break;
718 default: assert(!"unknown instruction");
719 }
720
721 cond = LLVMBuildFCmp(builder,
722 pred, emit_data->args[0], emit_data->args[1], "");
723
724 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
725 cond, bld_base->base.one, bld_base->base.zero, "");
726 }
727
728 static void emit_not(
729 const struct lp_build_tgsi_action * action,
730 struct lp_build_tgsi_context * bld_base,
731 struct lp_build_emit_data * emit_data)
732 {
733 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
734 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
735 emit_data->args[0]);
736 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
737 }
738
739 static void emit_and(
740 const struct lp_build_tgsi_action * action,
741 struct lp_build_tgsi_context * bld_base,
742 struct lp_build_emit_data * emit_data)
743 {
744 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
745 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
746 emit_data->args[0], emit_data->args[1], "");
747 }
748
749 static void emit_or(
750 const struct lp_build_tgsi_action * action,
751 struct lp_build_tgsi_context * bld_base,
752 struct lp_build_emit_data * emit_data)
753 {
754 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
755 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
756 emit_data->args[0], emit_data->args[1], "");
757 }
758
759 static void emit_uadd(
760 const struct lp_build_tgsi_action * action,
761 struct lp_build_tgsi_context * bld_base,
762 struct lp_build_emit_data * emit_data)
763 {
764 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
765 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
766 emit_data->args[0], emit_data->args[1], "");
767 }
768
769 static void emit_udiv(
770 const struct lp_build_tgsi_action * action,
771 struct lp_build_tgsi_context * bld_base,
772 struct lp_build_emit_data * emit_data)
773 {
774 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
775 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
776 emit_data->args[0], emit_data->args[1], "");
777 }
778
779 static void emit_idiv(
780 const struct lp_build_tgsi_action * action,
781 struct lp_build_tgsi_context * bld_base,
782 struct lp_build_emit_data * emit_data)
783 {
784 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
785 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
786 emit_data->args[0], emit_data->args[1], "");
787 }
788
789 static void emit_mod(
790 const struct lp_build_tgsi_action * action,
791 struct lp_build_tgsi_context * bld_base,
792 struct lp_build_emit_data * emit_data)
793 {
794 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
795 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
796 emit_data->args[0], emit_data->args[1], "");
797 }
798
799 static void emit_umod(
800 const struct lp_build_tgsi_action * action,
801 struct lp_build_tgsi_context * bld_base,
802 struct lp_build_emit_data * emit_data)
803 {
804 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
805 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
806 emit_data->args[0], emit_data->args[1], "");
807 }
808
809 static void emit_shl(
810 const struct lp_build_tgsi_action * action,
811 struct lp_build_tgsi_context * bld_base,
812 struct lp_build_emit_data * emit_data)
813 {
814 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
815 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
816 emit_data->args[0], emit_data->args[1], "");
817 }
818
819 static void emit_ushr(
820 const struct lp_build_tgsi_action * action,
821 struct lp_build_tgsi_context * bld_base,
822 struct lp_build_emit_data * emit_data)
823 {
824 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
825 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
826 emit_data->args[0], emit_data->args[1], "");
827 }
828 static void emit_ishr(
829 const struct lp_build_tgsi_action * action,
830 struct lp_build_tgsi_context * bld_base,
831 struct lp_build_emit_data * emit_data)
832 {
833 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
834 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
835 emit_data->args[0], emit_data->args[1], "");
836 }
837
838 static void emit_xor(
839 const struct lp_build_tgsi_action * action,
840 struct lp_build_tgsi_context * bld_base,
841 struct lp_build_emit_data * emit_data)
842 {
843 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
844 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
845 emit_data->args[0], emit_data->args[1], "");
846 }
847
848 static void emit_ssg(
849 const struct lp_build_tgsi_action * action,
850 struct lp_build_tgsi_context * bld_base,
851 struct lp_build_emit_data * emit_data)
852 {
853 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
854
855 LLVMValueRef cmp, val;
856
857 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
858 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
859 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
860 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
861 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
862 } else { // float SSG
863 cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->int_bld.zero, "");
864 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
865 cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, "");
866 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
867 }
868
869 emit_data->output[emit_data->chan] = val;
870 }
871
872 static void emit_ineg(
873 const struct lp_build_tgsi_action * action,
874 struct lp_build_tgsi_context * bld_base,
875 struct lp_build_emit_data * emit_data)
876 {
877 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
878 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
879 emit_data->args[0], "");
880 }
881
882 static void emit_f2i(
883 const struct lp_build_tgsi_action * action,
884 struct lp_build_tgsi_context * bld_base,
885 struct lp_build_emit_data * emit_data)
886 {
887 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
888 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
889 emit_data->args[0], bld_base->int_bld.elem_type, "");
890 }
891
892 static void emit_f2u(
893 const struct lp_build_tgsi_action * action,
894 struct lp_build_tgsi_context * bld_base,
895 struct lp_build_emit_data * emit_data)
896 {
897 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
898 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
899 emit_data->args[0], bld_base->uint_bld.elem_type, "");
900 }
901
902 static void emit_i2f(
903 const struct lp_build_tgsi_action * action,
904 struct lp_build_tgsi_context * bld_base,
905 struct lp_build_emit_data * emit_data)
906 {
907 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
908 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
909 emit_data->args[0], bld_base->base.elem_type, "");
910 }
911
912 static void emit_u2f(
913 const struct lp_build_tgsi_action * action,
914 struct lp_build_tgsi_context * bld_base,
915 struct lp_build_emit_data * emit_data)
916 {
917 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
918 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
919 emit_data->args[0], bld_base->base.elem_type, "");
920 }
921
922 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
923 const struct tgsi_full_immediate *imm)
924 {
925 unsigned i;
926 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
927
928 for (i = 0; i < 4; ++i) {
929 ctx->soa.immediates[ctx->soa.num_immediates][i] =
930 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false );
931 }
932
933 ctx->soa.num_immediates++;
934 }
935
936 LLVMValueRef
937 build_intrinsic(LLVMBuilderRef builder,
938 const char *name,
939 LLVMTypeRef ret_type,
940 LLVMValueRef *args,
941 unsigned num_args,
942 LLVMAttribute attr)
943 {
944 LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
945 LLVMValueRef function;
946
947 function = LLVMGetNamedFunction(module, name);
948 if(!function) {
949 LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
950 unsigned i;
951
952 assert(num_args <= LP_MAX_FUNC_ARGS);
953
954 for(i = 0; i < num_args; ++i) {
955 assert(args[i]);
956 arg_types[i] = LLVMTypeOf(args[i]);
957 }
958
959 function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
960
961 if (attr)
962 LLVMAddFunctionAttr(function, attr);
963 }
964
965 return LLVMBuildCall(builder, function, args, num_args, "");
966 }
967
968 void
969 build_tgsi_intrinsic_nomem(
970 const struct lp_build_tgsi_action * action,
971 struct lp_build_tgsi_context * bld_base,
972 struct lp_build_emit_data * emit_data)
973 {
974 struct lp_build_context * base = &bld_base->base;
975 emit_data->output[emit_data->chan] = build_intrinsic(
976 base->gallivm->builder, action->intr_name,
977 emit_data->dst_type, emit_data->args,
978 emit_data->arg_count, LLVMReadNoneAttribute);
979 }
980
981 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
982 {
983 struct lp_type type;
984 LLVMTypeRef main_fn_type;
985 LLVMBasicBlockRef main_fn_body;
986
987 /* Initialize the gallivm object:
988 * We are only using the module, context, and builder fields of this struct.
989 * This should be enough for us to be able to pass our gallivm struct to the
990 * helper functions in the gallivm module.
991 */
992 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
993 memset(&ctx->soa, 0, sizeof(ctx->soa));
994 ctx->gallivm.context = LLVMContextCreate();
995 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
996 ctx->gallivm.context);
997 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
998
999 /* Setup the module */
1000 main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context),
1001 NULL, 0, 0);
1002 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1003 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1004 ctx->main_fn, "main_body");
1005 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1006
1007 ctx->store_output_intr = "llvm.AMDGPU.store.output.";
1008 ctx->swizzle_intr = "llvm.AMDGPU.swizzle";
1009 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1010
1011 /* XXX: We need to revisit this.I think the correct way to do this is
1012 * to use length = 4 here and use the elem_bld for everything. */
1013 type.floating = TRUE;
1014 type.sign = TRUE;
1015 type.width = 32;
1016 type.length = 1;
1017
1018 lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1019 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1020 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1021
1022 bld_base->soa = 1;
1023 bld_base->emit_store = emit_store;
1024 bld_base->emit_swizzle = emit_swizzle;
1025 bld_base->emit_declaration = emit_declaration;
1026 bld_base->emit_immediate = emit_immediate;
1027
1028 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch_immediate;
1029 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch_input;
1030 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch_temporary;
1031 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch_output;
1032
1033 /* Allocate outputs */
1034 ctx->soa.outputs = ctx->outputs;
1035
1036 /* XXX: Is there a better way to initialize all this ? */
1037
1038 lp_set_default_actions(bld_base);
1039
1040 bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
1041 bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
1042 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1043 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1044 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1045 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1046 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1047 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1048 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1049 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1050 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1051 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1052 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1053 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1054 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1055 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1056 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1057 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1058 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1059 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1060 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1061 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
1062 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
1063 bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
1064 bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
1065 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1066 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1067 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1068 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1069 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1070 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1071 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1072 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
1073 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
1074 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
1075 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
1076 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
1077 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
1078 bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
1079 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1080 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
1081 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
1082 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
1083 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
1084 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
1085 bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
1086 bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
1087 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
1088 bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
1089 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
1090 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.AMDIL.round.posinf.";
1091
1092
1093
1094 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_nomem;
1095 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "llvm.AMDIL.fabs.";
1096 bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem;
1097 bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl";
1098 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1099 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1100 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1101 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1102 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
1103 bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
1104 bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
1105 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
1106 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.AMDGPU.cos";
1107 bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem;
1108 bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div";
1109 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1110 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1111 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1112 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1113 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
1114 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
1115 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.AMDGPU.floor";
1116 bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
1117 bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
1118 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1119 bld_base->op_actions[TGSI_OPCODE_KIL].emit = kil_emit;
1120 bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill";
1121 bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic;
1122 bld_base->op_actions[TGSI_OPCODE_KILP].intr_name = "llvm.AMDGPU.kilp";
1123 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem;
1124 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.AMDIL.log.";
1125 bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
1126 bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
1127 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
1128 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
1129 bld_base->op_actions[TGSI_OPCODE_MAD].emit = build_tgsi_intrinsic_nomem;
1130 bld_base->op_actions[TGSI_OPCODE_MAD].intr_name = "llvm.AMDIL.mad.";
1131 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
1132 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
1133 bld_base->op_actions[TGSI_OPCODE_MUL].emit = build_tgsi_intrinsic_nomem;
1134 bld_base->op_actions[TGSI_OPCODE_MUL].intr_name = "llvm.AMDGPU.mul";
1135 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_nomem;
1136 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.AMDGPU.pow";
1137 bld_base->op_actions[TGSI_OPCODE_RCP].emit = build_tgsi_intrinsic_nomem;
1138 bld_base->op_actions[TGSI_OPCODE_RCP].intr_name = "llvm.AMDGPU.rcp";
1139 bld_base->op_actions[TGSI_OPCODE_SSG].emit = build_tgsi_intrinsic_nomem;
1140 bld_base->op_actions[TGSI_OPCODE_SSG].intr_name = "llvm.AMDGPU.ssg";
1141 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
1142 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
1143 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
1144 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
1145 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
1146 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
1147 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
1148 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.AMDGPU.sin";
1149 bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
1150 bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
1151 bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
1152 bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
1153 bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
1154 bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
1155 bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
1156 bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
1157 bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
1158 bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
1159 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1160 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
1161
1162 bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
1163 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
1164 }
1165
1166 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1167 {
1168 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1169 /* End the main function with Return*/
1170 LLVMBuildRetVoid(gallivm->builder);
1171
1172 /* Create the pass manager */
1173 ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule(
1174 gallivm->module);
1175
1176 /* This pass should eliminate all the load and store instructions */
1177 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1178
1179 /* Add some optimization passes */
1180 LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1181 LLVMAddCFGSimplificationPass(gallivm->passmgr);
1182
1183 /* Run the passs */
1184 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1185
1186 LLVMDisposeBuilder(gallivm->builder);
1187 LLVMDisposePassManager(gallivm->passmgr);
1188
1189 }
1190
1191 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1192 {
1193 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1194 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1195 }