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radeon/llvm: reset temps_count on deallocation
[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26 #include "radeon_llvm.h"
27
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
42
43 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
44 {
45 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
46 }
47
48 static struct radeon_llvm_branch * get_current_branch(
49 struct radeon_llvm_context * ctx)
50 {
51 return ctx->branch_depth > 0 ?
52 ctx->branch + (ctx->branch_depth - 1) : NULL;
53 }
54
55 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
56 {
57 return (index * 4) + chan;
58 }
59
60 static LLVMValueRef emit_swizzle(
61 struct lp_build_tgsi_context * bld_base,
62 LLVMValueRef value,
63 unsigned swizzle_x,
64 unsigned swizzle_y,
65 unsigned swizzle_z,
66 unsigned swizzle_w)
67 {
68 LLVMValueRef swizzles[4];
69 LLVMTypeRef i32t =
70 LLVMInt32TypeInContext(bld_base->base.gallivm->context);
71
72 swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0);
73 swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0);
74 swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0);
75 swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0);
76
77 return LLVMBuildShuffleVector(bld_base->base.gallivm->builder,
78 value,
79 LLVMGetUndef(LLVMTypeOf(value)),
80 LLVMConstVector(swizzles, 4), "");
81 }
82
83 static struct tgsi_declaration_range
84 get_array_range(struct lp_build_tgsi_context *bld_base,
85 unsigned File, const struct tgsi_ind_register *reg)
86 {
87 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
88
89 if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 ||
90 reg->ArrayID > bld_base->info->array_max[TGSI_FILE_TEMPORARY]) {
91 struct tgsi_declaration_range range;
92 range.First = 0;
93 range.Last = bld_base->info->file_max[File];
94 return range;
95 }
96
97 return ctx->arrays[reg->ArrayID - 1];
98 }
99
100 static LLVMValueRef
101 emit_array_index(
102 struct lp_build_tgsi_soa_context *bld,
103 const struct tgsi_ind_register *reg,
104 unsigned offset)
105 {
106 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
107
108 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, bld->addr[reg->Index][reg->Swizzle], "");
109 return LLVMBuildAdd(gallivm->builder, addr, lp_build_const_int32(gallivm, offset), "");
110 }
111
112 static LLVMValueRef
113 emit_fetch(
114 struct lp_build_tgsi_context *bld_base,
115 const struct tgsi_full_src_register *reg,
116 enum tgsi_opcode_type type,
117 unsigned swizzle);
118
119 static LLVMValueRef
120 emit_array_fetch(
121 struct lp_build_tgsi_context *bld_base,
122 unsigned File, enum tgsi_opcode_type type,
123 struct tgsi_declaration_range range,
124 unsigned swizzle)
125 {
126 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
127 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
128 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
129
130 unsigned i, size = range.Last - range.First + 1;
131 LLVMTypeRef vec = LLVMVectorType(tgsi2llvmtype(bld_base, type), size);
132 LLVMValueRef result = LLVMGetUndef(vec);
133
134 struct tgsi_full_src_register tmp_reg = {};
135 tmp_reg.Register.File = File;
136
137 for (i = 0; i < size; ++i) {
138 tmp_reg.Register.Index = i + range.First;
139 LLVMValueRef temp = emit_fetch(bld_base, &tmp_reg, type, swizzle);
140 result = LLVMBuildInsertElement(builder, result, temp,
141 lp_build_const_int32(gallivm, i), "");
142 }
143 return result;
144 }
145
146 static bool uses_temp_indirect_addressing(
147 struct lp_build_tgsi_context *bld_base)
148 {
149 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
150 return (bld->indirect_files & (1 << TGSI_FILE_TEMPORARY));
151 }
152
153 static LLVMValueRef
154 emit_fetch(
155 struct lp_build_tgsi_context *bld_base,
156 const struct tgsi_full_src_register *reg,
157 enum tgsi_opcode_type type,
158 unsigned swizzle)
159 {
160 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
161 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
162 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
163 LLVMValueRef result = NULL, ptr;
164
165 if (swizzle == ~0) {
166 LLVMValueRef values[TGSI_NUM_CHANNELS];
167 unsigned chan;
168 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
169 values[chan] = emit_fetch(bld_base, reg, type, chan);
170 }
171 return lp_build_gather_values(bld_base->base.gallivm, values,
172 TGSI_NUM_CHANNELS);
173 }
174
175 if (reg->Register.Indirect) {
176 struct tgsi_declaration_range range = get_array_range(bld_base,
177 reg->Register.File, &reg->Indirect);
178 return LLVMBuildExtractElement(builder,
179 emit_array_fetch(bld_base, reg->Register.File, type, range, swizzle),
180 emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First),
181 "");
182 }
183
184 switch(reg->Register.File) {
185 case TGSI_FILE_IMMEDIATE: {
186 LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type);
187 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
188 }
189
190 case TGSI_FILE_INPUT:
191 result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)];
192 break;
193
194 case TGSI_FILE_TEMPORARY:
195 if (reg->Register.Index >= ctx->temps_count)
196 return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
197 if (uses_temp_indirect_addressing(bld_base)) {
198 ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
199 break;
200 }
201 ptr = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle];
202 result = LLVMBuildLoad(builder, ptr, "");
203 break;
204
205 case TGSI_FILE_OUTPUT:
206 ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
207 result = LLVMBuildLoad(builder, ptr, "");
208 break;
209
210 default:
211 return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
212 }
213
214 return bitcast(bld_base, type, result);
215 }
216
217 static LLVMValueRef fetch_system_value(
218 struct lp_build_tgsi_context * bld_base,
219 const struct tgsi_full_src_register *reg,
220 enum tgsi_opcode_type type,
221 unsigned swizzle)
222 {
223 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
224 struct gallivm_state *gallivm = bld_base->base.gallivm;
225
226 LLVMValueRef cval = ctx->system_values[reg->Register.Index];
227 if (LLVMGetTypeKind(LLVMTypeOf(cval)) == LLVMVectorTypeKind) {
228 cval = LLVMBuildExtractElement(gallivm->builder, cval,
229 lp_build_const_int32(gallivm, swizzle), "");
230 }
231 return bitcast(bld_base, type, cval);
232 }
233
234 static void emit_declaration(
235 struct lp_build_tgsi_context * bld_base,
236 const struct tgsi_full_declaration *decl)
237 {
238 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
239 unsigned first, last, i, idx;
240 switch(decl->Declaration.File) {
241 case TGSI_FILE_ADDRESS:
242 {
243 unsigned idx;
244 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
245 unsigned chan;
246 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
247 ctx->soa.addr[idx][chan] = lp_build_alloca(
248 &ctx->gallivm,
249 ctx->soa.bld_base.uint_bld.elem_type, "");
250 }
251 }
252 break;
253 }
254
255 case TGSI_FILE_TEMPORARY:
256 if (decl->Declaration.Array) {
257 if (!ctx->arrays) {
258 int size = bld_base->info->array_max[TGSI_FILE_TEMPORARY];
259 ctx->arrays = MALLOC(sizeof(ctx->arrays[0]) * size);
260 }
261
262 ctx->arrays[decl->Array.ArrayID - 1] = decl->Range;
263 }
264 if (uses_temp_indirect_addressing(bld_base)) {
265 lp_emit_declaration_soa(bld_base, decl);
266 break;
267 }
268 first = decl->Range.First;
269 last = decl->Range.Last;
270 if (!ctx->temps_count) {
271 ctx->temps_count = bld_base->info->file_max[TGSI_FILE_TEMPORARY] + 1;
272 ctx->temps = MALLOC(TGSI_NUM_CHANNELS * ctx->temps_count * sizeof(LLVMValueRef));
273 }
274 for (idx = first; idx <= last; idx++) {
275 for (i = 0; i < TGSI_NUM_CHANNELS; i++) {
276 ctx->temps[idx * TGSI_NUM_CHANNELS + i] =
277 lp_build_alloca(bld_base->base.gallivm, bld_base->base.vec_type,
278 "temp");
279 }
280 }
281 break;
282
283 case TGSI_FILE_INPUT:
284 {
285 unsigned idx;
286 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
287 if (ctx->load_input)
288 ctx->load_input(ctx, idx, decl);
289 }
290 }
291 break;
292
293 case TGSI_FILE_SYSTEM_VALUE:
294 {
295 unsigned idx;
296 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
297 ctx->load_system_value(ctx, idx, decl);
298 }
299 }
300 break;
301
302 case TGSI_FILE_OUTPUT:
303 {
304 unsigned idx;
305 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
306 unsigned chan;
307 assert(idx < RADEON_LLVM_MAX_OUTPUTS);
308 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
309 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm,
310 ctx->soa.bld_base.base.elem_type, "");
311 }
312 }
313
314 ctx->output_reg_count = MAX2(ctx->output_reg_count,
315 decl->Range.Last + 1);
316 break;
317 }
318
319 default:
320 break;
321 }
322 }
323
324 static LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base,
325 LLVMValueRef value)
326 {
327 struct lp_build_emit_data clamp_emit_data;
328
329 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
330 clamp_emit_data.arg_count = 3;
331 clamp_emit_data.args[0] = value;
332 clamp_emit_data.args[2] = bld_base->base.one;
333 clamp_emit_data.args[1] = bld_base->base.zero;
334
335 return lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
336 &clamp_emit_data);
337 }
338
339 static void
340 emit_store(
341 struct lp_build_tgsi_context * bld_base,
342 const struct tgsi_full_instruction * inst,
343 const struct tgsi_opcode_info * info,
344 LLVMValueRef dst[4])
345 {
346 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
347 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
348 struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
349 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
350 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
351 LLVMValueRef temp_ptr;
352 unsigned chan, chan_index;
353 boolean is_vec_store = FALSE;
354
355 if (dst[0]) {
356 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
357 is_vec_store = (k == LLVMVectorTypeKind);
358 }
359
360 if (is_vec_store) {
361 LLVMValueRef values[4] = {};
362 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
363 LLVMValueRef index = lp_build_const_int32(gallivm, chan);
364 values[chan] = LLVMBuildExtractElement(gallivm->builder,
365 dst[0], index, "");
366 }
367 bld_base->emit_store(bld_base, inst, info, values);
368 return;
369 }
370
371 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
372 LLVMValueRef value = dst[chan_index];
373
374 if (inst->Instruction.Saturate)
375 value = radeon_llvm_saturate(bld_base, value);
376
377 if (reg->Register.File == TGSI_FILE_ADDRESS) {
378 temp_ptr = bld->addr[reg->Register.Index][chan_index];
379 LLVMBuildStore(builder, value, temp_ptr);
380 continue;
381 }
382
383 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
384
385 if (reg->Register.Indirect) {
386 struct tgsi_declaration_range range = get_array_range(bld_base,
387 reg->Register.File, &reg->Indirect);
388
389 unsigned i, size = range.Last - range.First + 1;
390 LLVMValueRef array = LLVMBuildInsertElement(builder,
391 emit_array_fetch(bld_base, reg->Register.File, TGSI_TYPE_FLOAT, range, chan_index),
392 value, emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First), "");
393
394 for (i = 0; i < size; ++i) {
395 switch(reg->Register.File) {
396 case TGSI_FILE_OUTPUT:
397 temp_ptr = bld->outputs[i + range.First][chan_index];
398 break;
399
400 case TGSI_FILE_TEMPORARY:
401 if (range.First + i >= ctx->temps_count)
402 continue;
403 if (uses_temp_indirect_addressing(bld_base))
404 temp_ptr = lp_get_temp_ptr_soa(bld, i + range.First, chan_index);
405 else
406 temp_ptr = ctx->temps[(i + range.First) * TGSI_NUM_CHANNELS + chan_index];
407 break;
408
409 default:
410 return;
411 }
412 value = LLVMBuildExtractElement(builder, array,
413 lp_build_const_int32(gallivm, i), "");
414 LLVMBuildStore(builder, value, temp_ptr);
415 }
416
417 } else {
418 switch(reg->Register.File) {
419 case TGSI_FILE_OUTPUT:
420 temp_ptr = bld->outputs[reg->Register.Index][chan_index];
421 break;
422
423 case TGSI_FILE_TEMPORARY:
424 if (reg->Register.Index >= ctx->temps_count)
425 continue;
426 if (uses_temp_indirect_addressing(bld_base)) {
427 temp_ptr = NULL;
428 break;
429 }
430 temp_ptr = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index];
431 break;
432
433 default:
434 return;
435 }
436 LLVMBuildStore(builder, value, temp_ptr);
437 }
438 }
439 }
440
441 static void bgnloop_emit(
442 const struct lp_build_tgsi_action * action,
443 struct lp_build_tgsi_context * bld_base,
444 struct lp_build_emit_data * emit_data)
445 {
446 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
447 struct gallivm_state * gallivm = bld_base->base.gallivm;
448 LLVMBasicBlockRef loop_block;
449 LLVMBasicBlockRef endloop_block;
450 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
451 ctx->main_fn, "ENDLOOP");
452 loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
453 endloop_block, "LOOP");
454 LLVMBuildBr(gallivm->builder, loop_block);
455 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
456
457 if (++ctx->loop_depth > ctx->loop_depth_max) {
458 unsigned new_max = ctx->loop_depth_max << 1;
459
460 if (!new_max)
461 new_max = RADEON_LLVM_INITIAL_CF_DEPTH;
462
463 ctx->loop = REALLOC(ctx->loop, ctx->loop_depth_max *
464 sizeof(ctx->loop[0]),
465 new_max * sizeof(ctx->loop[0]));
466 ctx->loop_depth_max = new_max;
467 }
468
469 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
470 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
471 }
472
473 static void brk_emit(
474 const struct lp_build_tgsi_action * action,
475 struct lp_build_tgsi_context * bld_base,
476 struct lp_build_emit_data * emit_data)
477 {
478 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
479 struct gallivm_state * gallivm = bld_base->base.gallivm;
480 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
481
482 LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
483 }
484
485 static void cont_emit(
486 const struct lp_build_tgsi_action * action,
487 struct lp_build_tgsi_context * bld_base,
488 struct lp_build_emit_data * emit_data)
489 {
490 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
491 struct gallivm_state * gallivm = bld_base->base.gallivm;
492 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
493
494 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
495 }
496
497 static void else_emit(
498 const struct lp_build_tgsi_action * action,
499 struct lp_build_tgsi_context * bld_base,
500 struct lp_build_emit_data * emit_data)
501 {
502 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
503 struct gallivm_state * gallivm = bld_base->base.gallivm;
504 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
505 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
506
507 /* We need to add a terminator to the current block if the previous
508 * instruction was an ENDIF.Example:
509 * IF
510 * [code]
511 * IF
512 * [code]
513 * ELSE
514 * [code]
515 * ENDIF <--
516 * ELSE<--
517 * [code]
518 * ENDIF
519 */
520
521 if (current_block != current_branch->if_block) {
522 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
523 }
524 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
525 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
526 }
527 current_branch->has_else = 1;
528 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
529 }
530
531 static void endif_emit(
532 const struct lp_build_tgsi_action * action,
533 struct lp_build_tgsi_context * bld_base,
534 struct lp_build_emit_data * emit_data)
535 {
536 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
537 struct gallivm_state * gallivm = bld_base->base.gallivm;
538 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
539 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
540
541 /* If we have consecutive ENDIF instructions, then the first ENDIF
542 * will not have a terminator, so we need to add one. */
543 if (current_block != current_branch->if_block
544 && current_block != current_branch->else_block
545 && !LLVMGetBasicBlockTerminator(current_block)) {
546
547 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
548 }
549 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
550 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
551 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
552 }
553
554 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
555 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
556 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
557 }
558
559 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
560 ctx->branch_depth--;
561 }
562
563 static void endloop_emit(
564 const struct lp_build_tgsi_action * action,
565 struct lp_build_tgsi_context * bld_base,
566 struct lp_build_emit_data * emit_data)
567 {
568 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
569 struct gallivm_state * gallivm = bld_base->base.gallivm;
570 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
571
572 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
573 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
574 }
575
576 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
577 ctx->loop_depth--;
578 }
579
580 static void if_cond_emit(
581 const struct lp_build_tgsi_action * action,
582 struct lp_build_tgsi_context * bld_base,
583 struct lp_build_emit_data * emit_data,
584 LLVMValueRef cond)
585 {
586 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
587 struct gallivm_state * gallivm = bld_base->base.gallivm;
588 LLVMBasicBlockRef if_block, else_block, endif_block;
589
590 endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
591 ctx->main_fn, "ENDIF");
592 if_block = LLVMInsertBasicBlockInContext(gallivm->context,
593 endif_block, "IF");
594 else_block = LLVMInsertBasicBlockInContext(gallivm->context,
595 endif_block, "ELSE");
596 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
597 LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
598
599 if (++ctx->branch_depth > ctx->branch_depth_max) {
600 unsigned new_max = ctx->branch_depth_max << 1;
601
602 if (!new_max)
603 new_max = RADEON_LLVM_INITIAL_CF_DEPTH;
604
605 ctx->branch = REALLOC(ctx->branch, ctx->branch_depth_max *
606 sizeof(ctx->branch[0]),
607 new_max * sizeof(ctx->branch[0]));
608 ctx->branch_depth_max = new_max;
609 }
610
611 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
612 ctx->branch[ctx->branch_depth - 1].if_block = if_block;
613 ctx->branch[ctx->branch_depth - 1].else_block = else_block;
614 ctx->branch[ctx->branch_depth - 1].has_else = 0;
615 }
616
617 static void if_emit(
618 const struct lp_build_tgsi_action * action,
619 struct lp_build_tgsi_context * bld_base,
620 struct lp_build_emit_data * emit_data)
621 {
622 struct gallivm_state * gallivm = bld_base->base.gallivm;
623 LLVMValueRef cond;
624
625 cond = LLVMBuildFCmp(gallivm->builder, LLVMRealUNE,
626 emit_data->args[0],
627 bld_base->base.zero, "");
628
629 if_cond_emit(action, bld_base, emit_data, cond);
630 }
631
632 static void uif_emit(
633 const struct lp_build_tgsi_action * action,
634 struct lp_build_tgsi_context * bld_base,
635 struct lp_build_emit_data * emit_data)
636 {
637 struct gallivm_state * gallivm = bld_base->base.gallivm;
638 LLVMValueRef cond;
639
640 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
641 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
642 bld_base->int_bld.zero, "");
643
644 if_cond_emit(action, bld_base, emit_data, cond);
645 }
646
647 static void kill_if_fetch_args(
648 struct lp_build_tgsi_context * bld_base,
649 struct lp_build_emit_data * emit_data)
650 {
651 const struct tgsi_full_instruction * inst = emit_data->inst;
652 struct gallivm_state *gallivm = bld_base->base.gallivm;
653 LLVMBuilderRef builder = gallivm->builder;
654 unsigned i;
655 LLVMValueRef conds[TGSI_NUM_CHANNELS];
656
657 for (i = 0; i < TGSI_NUM_CHANNELS; i++) {
658 LLVMValueRef value = lp_build_emit_fetch(bld_base, inst, 0, i);
659 conds[i] = LLVMBuildFCmp(builder, LLVMRealOLT, value,
660 bld_base->base.zero, "");
661 }
662
663 /* Or the conditions together */
664 for (i = TGSI_NUM_CHANNELS - 1; i > 0; i--) {
665 conds[i - 1] = LLVMBuildOr(builder, conds[i], conds[i - 1], "");
666 }
667
668 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
669 emit_data->arg_count = 1;
670 emit_data->args[0] = LLVMBuildSelect(builder, conds[0],
671 lp_build_const_float(gallivm, -1.0f),
672 bld_base->base.zero, "");
673 }
674
675 static void kil_emit(
676 const struct lp_build_tgsi_action * action,
677 struct lp_build_tgsi_context * bld_base,
678 struct lp_build_emit_data * emit_data)
679 {
680 unsigned i;
681 for (i = 0; i < emit_data->arg_count; i++) {
682 emit_data->output[i] = lp_build_intrinsic_unary(
683 bld_base->base.gallivm->builder,
684 action->intr_name,
685 emit_data->dst_type, emit_data->args[i]);
686 }
687 }
688
689 void radeon_llvm_emit_prepare_cube_coords(
690 struct lp_build_tgsi_context * bld_base,
691 struct lp_build_emit_data * emit_data,
692 LLVMValueRef *coords_arg)
693 {
694
695 unsigned target = emit_data->inst->Texture.Texture;
696 unsigned opcode = emit_data->inst->Instruction.Opcode;
697 struct gallivm_state * gallivm = bld_base->base.gallivm;
698 LLVMBuilderRef builder = gallivm->builder;
699 LLVMTypeRef type = bld_base->base.elem_type;
700 LLVMValueRef coords[4];
701 LLVMValueRef mad_args[3];
702 LLVMValueRef idx;
703 struct LLVMOpaqueValue *cube_vec;
704 LLVMValueRef v;
705 unsigned i;
706
707 cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
708 v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
709 &cube_vec, 1, LLVMReadNoneAttribute);
710
711 for (i = 0; i < 4; ++i) {
712 idx = lp_build_const_int32(gallivm, i);
713 coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
714 }
715
716 coords[2] = build_intrinsic(builder, "fabs",
717 type, &coords[2], 1, LLVMReadNoneAttribute);
718 coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]);
719
720 mad_args[1] = coords[2];
721 mad_args[2] = LLVMConstReal(type, 1.5);
722
723 mad_args[0] = coords[0];
724 coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
725 mad_args[0], mad_args[1], mad_args[2]);
726
727 mad_args[0] = coords[1];
728 coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
729 mad_args[0], mad_args[1], mad_args[2]);
730
731 /* apply xyz = yxw swizzle to cooords */
732 coords[2] = coords[3];
733 coords[3] = coords[1];
734 coords[1] = coords[0];
735 coords[0] = coords[3];
736
737 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
738 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
739 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
740 /* coords_arg.w component - array_index for cube arrays */
741 coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
742 coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
743 }
744
745 /* Preserve compare/lod/bias. Put it in coords.w. */
746 if (opcode == TGSI_OPCODE_TEX2 ||
747 opcode == TGSI_OPCODE_TXB2 ||
748 opcode == TGSI_OPCODE_TXL2) {
749 coords[3] = coords_arg[4];
750 } else if (opcode == TGSI_OPCODE_TXB ||
751 opcode == TGSI_OPCODE_TXL ||
752 target == TGSI_TEXTURE_SHADOWCUBE) {
753 coords[3] = coords_arg[3];
754 }
755
756 memcpy(coords_arg, coords, sizeof(coords));
757 }
758
759 static void txd_fetch_args(
760 struct lp_build_tgsi_context * bld_base,
761 struct lp_build_emit_data * emit_data)
762 {
763 const struct tgsi_full_instruction * inst = emit_data->inst;
764
765 LLVMValueRef coords[4];
766 unsigned chan, src;
767 for (src = 0; src < 3; src++) {
768 for (chan = 0; chan < 4; chan++)
769 coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan);
770
771 emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm,
772 coords, 4);
773 }
774 emit_data->arg_count = 3;
775 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
776 }
777
778
779 static void txp_fetch_args(
780 struct lp_build_tgsi_context * bld_base,
781 struct lp_build_emit_data * emit_data)
782 {
783 const struct tgsi_full_instruction * inst = emit_data->inst;
784 LLVMValueRef src_w;
785 unsigned chan;
786 LLVMValueRef coords[5];
787
788 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
789 src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
790
791 for (chan = 0; chan < 3; chan++ ) {
792 LLVMValueRef arg = lp_build_emit_fetch(bld_base,
793 emit_data->inst, 0, chan);
794 coords[chan] = lp_build_emit_llvm_binary(bld_base,
795 TGSI_OPCODE_DIV, arg, src_w);
796 }
797 coords[3] = bld_base->base.one;
798
799 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
800 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
801 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
802 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
803 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
804 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
805 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
806 }
807
808 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
809 coords, 4);
810 emit_data->arg_count = 1;
811 }
812
813 static void tex_fetch_args(
814 struct lp_build_tgsi_context * bld_base,
815 struct lp_build_emit_data * emit_data)
816 {
817 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
818 * when we used CHAN_ALL. We should be able to get this to work,
819 * but for now we will swizzle it ourselves
820 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
821 0, CHAN_ALL);
822
823 */
824
825 const struct tgsi_full_instruction * inst = emit_data->inst;
826
827 LLVMValueRef coords[5];
828 unsigned chan;
829 for (chan = 0; chan < 4; chan++) {
830 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
831 }
832
833 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
834 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
835 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
836 /* These instructions have additional operand that should be packed
837 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
838 * That operand should be passed as a float value in the args array
839 * right after the coord vector. After packing it's not used anymore,
840 * that's why arg_count is not increased */
841 coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
842 }
843
844 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
845 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
846 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
847 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
848 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
849 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
850 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
851 }
852
853 emit_data->arg_count = 1;
854 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
855 coords, 4);
856 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
857 }
858
859 static void txf_fetch_args(
860 struct lp_build_tgsi_context * bld_base,
861 struct lp_build_emit_data * emit_data)
862 {
863 const struct tgsi_full_instruction * inst = emit_data->inst;
864 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
865 const struct tgsi_texture_offset * off = inst->TexOffsets;
866 LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
867
868 /* fetch tex coords */
869 tex_fetch_args(bld_base, emit_data);
870
871 /* fetch tex offsets */
872 if (inst->Texture.NumOffsets) {
873 assert(inst->Texture.NumOffsets == 1);
874
875 emit_data->args[1] = LLVMConstBitCast(
876 bld->immediates[off->Index][off->SwizzleX],
877 offset_type);
878 emit_data->args[2] = LLVMConstBitCast(
879 bld->immediates[off->Index][off->SwizzleY],
880 offset_type);
881 emit_data->args[3] = LLVMConstBitCast(
882 bld->immediates[off->Index][off->SwizzleZ],
883 offset_type);
884 } else {
885 emit_data->args[1] = bld_base->int_bld.zero;
886 emit_data->args[2] = bld_base->int_bld.zero;
887 emit_data->args[3] = bld_base->int_bld.zero;
888 }
889
890 emit_data->arg_count = 4;
891 }
892
893 static void emit_icmp(
894 const struct lp_build_tgsi_action * action,
895 struct lp_build_tgsi_context * bld_base,
896 struct lp_build_emit_data * emit_data)
897 {
898 unsigned pred;
899 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
900 LLVMContextRef context = bld_base->base.gallivm->context;
901
902 switch (emit_data->inst->Instruction.Opcode) {
903 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
904 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
905 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
906 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
907 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
908 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
909 default:
910 assert(!"unknown instruction");
911 pred = 0;
912 break;
913 }
914
915 LLVMValueRef v = LLVMBuildICmp(builder, pred,
916 emit_data->args[0], emit_data->args[1],"");
917
918 v = LLVMBuildSExtOrBitCast(builder, v,
919 LLVMInt32TypeInContext(context), "");
920
921 emit_data->output[emit_data->chan] = v;
922 }
923
924 static void emit_ucmp(
925 const struct lp_build_tgsi_action * action,
926 struct lp_build_tgsi_context * bld_base,
927 struct lp_build_emit_data * emit_data)
928 {
929 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
930
931 LLVMValueRef arg0 = LLVMBuildBitCast(builder, emit_data->args[0],
932 bld_base->uint_bld.elem_type, "");
933
934 LLVMValueRef v = LLVMBuildICmp(builder, LLVMIntNE, arg0,
935 bld_base->uint_bld.zero, "");
936
937 emit_data->output[emit_data->chan] =
938 LLVMBuildSelect(builder, v, emit_data->args[1], emit_data->args[2], "");
939 }
940
941 static void emit_cmp(
942 const struct lp_build_tgsi_action *action,
943 struct lp_build_tgsi_context * bld_base,
944 struct lp_build_emit_data * emit_data)
945 {
946 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
947 LLVMRealPredicate pred;
948 LLVMValueRef cond;
949
950 /* Use ordered for everything but NE (which is usual for
951 * float comparisons)
952 */
953 switch (emit_data->inst->Instruction.Opcode) {
954 case TGSI_OPCODE_SGE: pred = LLVMRealOGE; break;
955 case TGSI_OPCODE_SEQ: pred = LLVMRealOEQ; break;
956 case TGSI_OPCODE_SLE: pred = LLVMRealOLE; break;
957 case TGSI_OPCODE_SLT: pred = LLVMRealOLT; break;
958 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
959 case TGSI_OPCODE_SGT: pred = LLVMRealOGT; break;
960 default: assert(!"unknown instruction"); pred = 0; break;
961 }
962
963 cond = LLVMBuildFCmp(builder,
964 pred, emit_data->args[0], emit_data->args[1], "");
965
966 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
967 cond, bld_base->base.one, bld_base->base.zero, "");
968 }
969
970 static void emit_fcmp(
971 const struct lp_build_tgsi_action *action,
972 struct lp_build_tgsi_context * bld_base,
973 struct lp_build_emit_data * emit_data)
974 {
975 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
976 LLVMContextRef context = bld_base->base.gallivm->context;
977 LLVMRealPredicate pred;
978
979 /* Use ordered for everything but NE (which is usual for
980 * float comparisons)
981 */
982 switch (emit_data->inst->Instruction.Opcode) {
983 case TGSI_OPCODE_FSEQ: pred = LLVMRealOEQ; break;
984 case TGSI_OPCODE_FSGE: pred = LLVMRealOGE; break;
985 case TGSI_OPCODE_FSLT: pred = LLVMRealOLT; break;
986 case TGSI_OPCODE_FSNE: pred = LLVMRealUNE; break;
987 default: assert(!"unknown instruction"); pred = 0; break;
988 }
989
990 LLVMValueRef v = LLVMBuildFCmp(builder, pred,
991 emit_data->args[0], emit_data->args[1],"");
992
993 v = LLVMBuildSExtOrBitCast(builder, v,
994 LLVMInt32TypeInContext(context), "");
995
996 emit_data->output[emit_data->chan] = v;
997 }
998
999 static void emit_not(
1000 const struct lp_build_tgsi_action * action,
1001 struct lp_build_tgsi_context * bld_base,
1002 struct lp_build_emit_data * emit_data)
1003 {
1004 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1005 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
1006 emit_data->args[0]);
1007 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
1008 }
1009
1010 static void emit_arl(
1011 const struct lp_build_tgsi_action * action,
1012 struct lp_build_tgsi_context * bld_base,
1013 struct lp_build_emit_data * emit_data)
1014 {
1015 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1016 LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
1017 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
1018 floor_index, bld_base->base.int_elem_type , "");
1019 }
1020
1021 static void emit_and(
1022 const struct lp_build_tgsi_action * action,
1023 struct lp_build_tgsi_context * bld_base,
1024 struct lp_build_emit_data * emit_data)
1025 {
1026 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1027 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
1028 emit_data->args[0], emit_data->args[1], "");
1029 }
1030
1031 static void emit_or(
1032 const struct lp_build_tgsi_action * action,
1033 struct lp_build_tgsi_context * bld_base,
1034 struct lp_build_emit_data * emit_data)
1035 {
1036 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1037 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
1038 emit_data->args[0], emit_data->args[1], "");
1039 }
1040
1041 static void emit_uadd(
1042 const struct lp_build_tgsi_action * action,
1043 struct lp_build_tgsi_context * bld_base,
1044 struct lp_build_emit_data * emit_data)
1045 {
1046 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1047 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
1048 emit_data->args[0], emit_data->args[1], "");
1049 }
1050
1051 static void emit_udiv(
1052 const struct lp_build_tgsi_action * action,
1053 struct lp_build_tgsi_context * bld_base,
1054 struct lp_build_emit_data * emit_data)
1055 {
1056 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1057 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
1058 emit_data->args[0], emit_data->args[1], "");
1059 }
1060
1061 static void emit_idiv(
1062 const struct lp_build_tgsi_action * action,
1063 struct lp_build_tgsi_context * bld_base,
1064 struct lp_build_emit_data * emit_data)
1065 {
1066 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1067 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
1068 emit_data->args[0], emit_data->args[1], "");
1069 }
1070
1071 static void emit_mod(
1072 const struct lp_build_tgsi_action * action,
1073 struct lp_build_tgsi_context * bld_base,
1074 struct lp_build_emit_data * emit_data)
1075 {
1076 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1077 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
1078 emit_data->args[0], emit_data->args[1], "");
1079 }
1080
1081 static void emit_umod(
1082 const struct lp_build_tgsi_action * action,
1083 struct lp_build_tgsi_context * bld_base,
1084 struct lp_build_emit_data * emit_data)
1085 {
1086 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1087 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
1088 emit_data->args[0], emit_data->args[1], "");
1089 }
1090
1091 static void emit_shl(
1092 const struct lp_build_tgsi_action * action,
1093 struct lp_build_tgsi_context * bld_base,
1094 struct lp_build_emit_data * emit_data)
1095 {
1096 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1097 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
1098 emit_data->args[0], emit_data->args[1], "");
1099 }
1100
1101 static void emit_ushr(
1102 const struct lp_build_tgsi_action * action,
1103 struct lp_build_tgsi_context * bld_base,
1104 struct lp_build_emit_data * emit_data)
1105 {
1106 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1107 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
1108 emit_data->args[0], emit_data->args[1], "");
1109 }
1110 static void emit_ishr(
1111 const struct lp_build_tgsi_action * action,
1112 struct lp_build_tgsi_context * bld_base,
1113 struct lp_build_emit_data * emit_data)
1114 {
1115 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1116 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
1117 emit_data->args[0], emit_data->args[1], "");
1118 }
1119
1120 static void emit_xor(
1121 const struct lp_build_tgsi_action * action,
1122 struct lp_build_tgsi_context * bld_base,
1123 struct lp_build_emit_data * emit_data)
1124 {
1125 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1126 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
1127 emit_data->args[0], emit_data->args[1], "");
1128 }
1129
1130 static void emit_ssg(
1131 const struct lp_build_tgsi_action * action,
1132 struct lp_build_tgsi_context * bld_base,
1133 struct lp_build_emit_data * emit_data)
1134 {
1135 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1136
1137 LLVMValueRef cmp, val;
1138
1139 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
1140 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
1141 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
1142 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
1143 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
1144 } else { // float SSG
1145 cmp = LLVMBuildFCmp(builder, LLVMRealOGT, emit_data->args[0], bld_base->base.zero, "");
1146 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
1147 cmp = LLVMBuildFCmp(builder, LLVMRealOGE, val, bld_base->base.zero, "");
1148 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
1149 }
1150
1151 emit_data->output[emit_data->chan] = val;
1152 }
1153
1154 static void emit_ineg(
1155 const struct lp_build_tgsi_action * action,
1156 struct lp_build_tgsi_context * bld_base,
1157 struct lp_build_emit_data * emit_data)
1158 {
1159 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1160 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
1161 emit_data->args[0], "");
1162 }
1163
1164 static void emit_f2i(
1165 const struct lp_build_tgsi_action * action,
1166 struct lp_build_tgsi_context * bld_base,
1167 struct lp_build_emit_data * emit_data)
1168 {
1169 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1170 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
1171 emit_data->args[0], bld_base->int_bld.elem_type, "");
1172 }
1173
1174 static void emit_f2u(
1175 const struct lp_build_tgsi_action * action,
1176 struct lp_build_tgsi_context * bld_base,
1177 struct lp_build_emit_data * emit_data)
1178 {
1179 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1180 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
1181 emit_data->args[0], bld_base->uint_bld.elem_type, "");
1182 }
1183
1184 static void emit_i2f(
1185 const struct lp_build_tgsi_action * action,
1186 struct lp_build_tgsi_context * bld_base,
1187 struct lp_build_emit_data * emit_data)
1188 {
1189 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1190 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
1191 emit_data->args[0], bld_base->base.elem_type, "");
1192 }
1193
1194 static void emit_u2f(
1195 const struct lp_build_tgsi_action * action,
1196 struct lp_build_tgsi_context * bld_base,
1197 struct lp_build_emit_data * emit_data)
1198 {
1199 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1200 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
1201 emit_data->args[0], bld_base->base.elem_type, "");
1202 }
1203
1204 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
1205 const struct tgsi_full_immediate *imm)
1206 {
1207 unsigned i;
1208 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
1209
1210 for (i = 0; i < 4; ++i) {
1211 ctx->soa.immediates[ctx->soa.num_immediates][i] =
1212 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false );
1213 }
1214
1215 ctx->soa.num_immediates++;
1216 }
1217
1218 LLVMValueRef
1219 build_intrinsic(LLVMBuilderRef builder,
1220 const char *name,
1221 LLVMTypeRef ret_type,
1222 LLVMValueRef *args,
1223 unsigned num_args,
1224 LLVMAttribute attr)
1225 {
1226 LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
1227 LLVMValueRef function;
1228
1229 function = LLVMGetNamedFunction(module, name);
1230 if(!function) {
1231 LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
1232 unsigned i;
1233
1234 assert(num_args <= LP_MAX_FUNC_ARGS);
1235
1236 for(i = 0; i < num_args; ++i) {
1237 assert(args[i]);
1238 arg_types[i] = LLVMTypeOf(args[i]);
1239 }
1240
1241 function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
1242
1243 if (attr)
1244 LLVMAddFunctionAttr(function, attr);
1245 }
1246
1247 return LLVMBuildCall(builder, function, args, num_args, "");
1248 }
1249
1250 static void build_tgsi_intrinsic(
1251 const struct lp_build_tgsi_action * action,
1252 struct lp_build_tgsi_context * bld_base,
1253 struct lp_build_emit_data * emit_data,
1254 LLVMAttribute attr)
1255 {
1256 struct lp_build_context * base = &bld_base->base;
1257 emit_data->output[emit_data->chan] = build_intrinsic(
1258 base->gallivm->builder, action->intr_name,
1259 emit_data->dst_type, emit_data->args,
1260 emit_data->arg_count, attr);
1261 }
1262
1263 void
1264 build_tgsi_intrinsic_nomem(
1265 const struct lp_build_tgsi_action * action,
1266 struct lp_build_tgsi_context * bld_base,
1267 struct lp_build_emit_data * emit_data)
1268 {
1269 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadNoneAttribute);
1270 }
1271
1272 static void emit_bfi(const struct lp_build_tgsi_action * action,
1273 struct lp_build_tgsi_context * bld_base,
1274 struct lp_build_emit_data * emit_data)
1275 {
1276 struct gallivm_state *gallivm = bld_base->base.gallivm;
1277 LLVMBuilderRef builder = gallivm->builder;
1278 LLVMValueRef bfi_args[3];
1279
1280 // Calculate the bitmask: (((1 << src3) - 1) << src2
1281 bfi_args[0] = LLVMBuildShl(builder,
1282 LLVMBuildSub(builder,
1283 LLVMBuildShl(builder,
1284 bld_base->int_bld.one,
1285 emit_data->args[3], ""),
1286 bld_base->int_bld.one, ""),
1287 emit_data->args[2], "");
1288
1289 bfi_args[1] = LLVMBuildShl(builder, emit_data->args[1],
1290 emit_data->args[2], "");
1291
1292 bfi_args[2] = emit_data->args[0];
1293
1294 /* Calculate:
1295 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1296 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1297 */
1298 emit_data->output[emit_data->chan] =
1299 LLVMBuildXor(builder, bfi_args[2],
1300 LLVMBuildAnd(builder, bfi_args[0],
1301 LLVMBuildXor(builder, bfi_args[1], bfi_args[2],
1302 ""), ""), "");
1303 }
1304
1305 /* this is ffs in C */
1306 static void emit_lsb(const struct lp_build_tgsi_action * action,
1307 struct lp_build_tgsi_context * bld_base,
1308 struct lp_build_emit_data * emit_data)
1309 {
1310 struct gallivm_state *gallivm = bld_base->base.gallivm;
1311 LLVMValueRef args[2] = {
1312 emit_data->args[0],
1313
1314 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1315 * add special code to check for x=0. The reason is that
1316 * the LLVM behavior for x=0 is different from what we
1317 * need here.
1318 *
1319 * The hardware already implements the correct behavior.
1320 */
1321 lp_build_const_int32(gallivm, 1)
1322 };
1323
1324 emit_data->output[emit_data->chan] =
1325 build_intrinsic(gallivm->builder, "llvm.cttz.i32",
1326 emit_data->dst_type, args, Elements(args),
1327 LLVMReadNoneAttribute);
1328 }
1329
1330 /* Find the last bit set. */
1331 static void emit_umsb(const struct lp_build_tgsi_action * action,
1332 struct lp_build_tgsi_context * bld_base,
1333 struct lp_build_emit_data * emit_data)
1334 {
1335 struct gallivm_state *gallivm = bld_base->base.gallivm;
1336 LLVMBuilderRef builder = gallivm->builder;
1337 LLVMValueRef args[2] = {
1338 emit_data->args[0],
1339 /* Don't generate code for handling zero: */
1340 lp_build_const_int32(gallivm, 1)
1341 };
1342
1343 LLVMValueRef msb =
1344 build_intrinsic(builder, "llvm.ctlz.i32",
1345 emit_data->dst_type, args, Elements(args),
1346 LLVMReadNoneAttribute);
1347
1348 /* The HW returns the last bit index from MSB, but TGSI wants
1349 * the index from LSB. Invert it by doing "31 - msb". */
1350 msb = LLVMBuildSub(builder, lp_build_const_int32(gallivm, 31),
1351 msb, "");
1352
1353 /* Check for zero: */
1354 emit_data->output[emit_data->chan] =
1355 LLVMBuildSelect(builder,
1356 LLVMBuildICmp(builder, LLVMIntEQ, args[0],
1357 bld_base->uint_bld.zero, ""),
1358 lp_build_const_int32(gallivm, -1), msb, "");
1359 }
1360
1361 /* Find the last bit opposite of the sign bit. */
1362 static void emit_imsb(const struct lp_build_tgsi_action * action,
1363 struct lp_build_tgsi_context * bld_base,
1364 struct lp_build_emit_data * emit_data)
1365 {
1366 struct gallivm_state *gallivm = bld_base->base.gallivm;
1367 LLVMBuilderRef builder = gallivm->builder;
1368 LLVMValueRef arg = emit_data->args[0];
1369
1370 LLVMValueRef msb =
1371 build_intrinsic(builder, "llvm.AMDGPU.flbit.i32",
1372 emit_data->dst_type, &arg, 1,
1373 LLVMReadNoneAttribute);
1374
1375 /* The HW returns the last bit index from MSB, but TGSI wants
1376 * the index from LSB. Invert it by doing "31 - msb". */
1377 msb = LLVMBuildSub(builder, lp_build_const_int32(gallivm, 31),
1378 msb, "");
1379
1380 /* If arg == 0 || arg == -1 (0xffffffff), return -1. */
1381 LLVMValueRef all_ones = lp_build_const_int32(gallivm, -1);
1382
1383 LLVMValueRef cond =
1384 LLVMBuildOr(builder,
1385 LLVMBuildICmp(builder, LLVMIntEQ, arg,
1386 bld_base->uint_bld.zero, ""),
1387 LLVMBuildICmp(builder, LLVMIntEQ, arg,
1388 all_ones, ""), "");
1389
1390 emit_data->output[emit_data->chan] =
1391 LLVMBuildSelect(builder, cond, all_ones, msb, "");
1392 }
1393
1394 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
1395 {
1396 struct lp_type type;
1397
1398 /* Initialize the gallivm object:
1399 * We are only using the module, context, and builder fields of this struct.
1400 * This should be enough for us to be able to pass our gallivm struct to the
1401 * helper functions in the gallivm module.
1402 */
1403 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
1404 memset(&ctx->soa, 0, sizeof(ctx->soa));
1405 ctx->gallivm.context = LLVMContextCreate();
1406 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
1407 ctx->gallivm.context);
1408 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
1409
1410 ctx->store_output_intr = "llvm.AMDGPU.store.output.";
1411 ctx->swizzle_intr = "llvm.AMDGPU.swizzle";
1412 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1413
1414 /* XXX: We need to revisit this.I think the correct way to do this is
1415 * to use length = 4 here and use the elem_bld for everything. */
1416 type.floating = TRUE;
1417 type.fixed = FALSE;
1418 type.sign = TRUE;
1419 type.norm = FALSE;
1420 type.width = 32;
1421 type.length = 1;
1422
1423 lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1424 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1425 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1426
1427 bld_base->soa = 1;
1428 bld_base->emit_store = emit_store;
1429 bld_base->emit_swizzle = emit_swizzle;
1430 bld_base->emit_declaration = emit_declaration;
1431 bld_base->emit_immediate = emit_immediate;
1432
1433 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch;
1434 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch;
1435 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch;
1436 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch;
1437 bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = fetch_system_value;
1438
1439 /* Allocate outputs */
1440 ctx->soa.outputs = ctx->outputs;
1441
1442 /* XXX: Is there a better way to initialize all this ? */
1443
1444 lp_set_default_actions(bld_base);
1445
1446 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_nomem;
1447 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
1448 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1449 bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
1450 bld_base->op_actions[TGSI_OPCODE_BFI].emit = emit_bfi;
1451 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1452 bld_base->op_actions[TGSI_OPCODE_BREV].emit = build_tgsi_intrinsic_nomem;
1453 bld_base->op_actions[TGSI_OPCODE_BREV].intr_name = "llvm.AMDGPU.brev";
1454 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1455 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
1456 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
1457 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1458 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
1459 bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
1460 bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
1461 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1462 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
1463 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
1464 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
1465 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
1466 bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
1467 bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
1468 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1469 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1470 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1471 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1472 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
1473 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
1474 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
1475 bld_base->op_actions[TGSI_OPCODE_FMA].emit = build_tgsi_intrinsic_nomem;
1476 bld_base->op_actions[TGSI_OPCODE_FMA].intr_name = "llvm.fma.f32";
1477 bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
1478 bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
1479 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1480 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1481 bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
1482 bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp;
1483 bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp;
1484 bld_base->op_actions[TGSI_OPCODE_FSNE].emit = emit_fcmp;
1485 bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
1486 bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
1487 bld_base->op_actions[TGSI_OPCODE_IBFE].emit = build_tgsi_intrinsic_nomem;
1488 bld_base->op_actions[TGSI_OPCODE_IBFE].intr_name = "llvm.AMDGPU.bfe.i32";
1489 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1490 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1491 bld_base->op_actions[TGSI_OPCODE_UIF].emit = uif_emit;
1492 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1493 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
1494 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
1495 bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
1496 bld_base->op_actions[TGSI_OPCODE_IMSB].emit = emit_imsb;
1497 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1498 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1499 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1500 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1501 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1502 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1503 bld_base->op_actions[TGSI_OPCODE_KILL_IF].fetch_args = kill_if_fetch_args;
1504 bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit;
1505 bld_base->op_actions[TGSI_OPCODE_KILL_IF].intr_name = "llvm.AMDGPU.kill";
1506 bld_base->op_actions[TGSI_OPCODE_KILL].emit = lp_build_tgsi_intrinsic;
1507 bld_base->op_actions[TGSI_OPCODE_KILL].intr_name = "llvm.AMDGPU.kilp";
1508 bld_base->op_actions[TGSI_OPCODE_LSB].emit = emit_lsb;
1509 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem;
1510 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
1511 bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
1512 bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
1513 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1514 bld_base->op_actions[TGSI_OPCODE_UMSB].emit = emit_umsb;
1515 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1516 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1517 bld_base->op_actions[TGSI_OPCODE_POPC].emit = build_tgsi_intrinsic_nomem;
1518 bld_base->op_actions[TGSI_OPCODE_POPC].intr_name = "llvm.ctpop.i32";
1519 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_nomem;
1520 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
1521 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1522 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
1523 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
1524 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
1525 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1526 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
1527 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
1528 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
1529 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
1530 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
1531 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
1532 bld_base->op_actions[TGSI_OPCODE_SQRT].emit = build_tgsi_intrinsic_nomem;
1533 bld_base->op_actions[TGSI_OPCODE_SQRT].intr_name = "llvm.sqrt.f32";
1534 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1535 bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
1536 bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
1537 bld_base->op_actions[TGSI_OPCODE_TEX2].fetch_args = tex_fetch_args;
1538 bld_base->op_actions[TGSI_OPCODE_TEX2].intr_name = "llvm.AMDGPU.tex";
1539 bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
1540 bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
1541 bld_base->op_actions[TGSI_OPCODE_TXB2].fetch_args = tex_fetch_args;
1542 bld_base->op_actions[TGSI_OPCODE_TXB2].intr_name = "llvm.AMDGPU.txb";
1543 bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
1544 bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
1545 bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
1546 bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
1547 bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
1548 bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
1549 bld_base->op_actions[TGSI_OPCODE_TXL2].fetch_args = tex_fetch_args;
1550 bld_base->op_actions[TGSI_OPCODE_TXL2].intr_name = "llvm.AMDGPU.txl";
1551 bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
1552 bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
1553 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
1554 bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
1555 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1556 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
1557 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1558 bld_base->op_actions[TGSI_OPCODE_UBFE].emit = build_tgsi_intrinsic_nomem;
1559 bld_base->op_actions[TGSI_OPCODE_UBFE].intr_name = "llvm.AMDGPU.bfe.u32";
1560 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1561 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
1562 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
1563 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
1564 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
1565 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1566 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1567 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1568 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1569 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1570 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1571 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1572 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1573 bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
1574
1575 bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
1576 #if HAVE_LLVM >= 0x0305
1577 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq.clamped.f32";
1578 #else
1579 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
1580 #endif
1581 }
1582
1583 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
1584 LLVMTypeRef *ParamTypes, unsigned ParamCount)
1585 {
1586 LLVMTypeRef main_fn_type;
1587 LLVMBasicBlockRef main_fn_body;
1588
1589 /* Setup the function */
1590 main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context),
1591 ParamTypes, ParamCount, 0);
1592 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1593 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1594 ctx->main_fn, "main_body");
1595 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1596 }
1597
1598 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1599 {
1600 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1601 /* End the main function with Return*/
1602 LLVMBuildRetVoid(gallivm->builder);
1603
1604 /* Create the pass manager */
1605 ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule(
1606 gallivm->module);
1607
1608 /* This pass should eliminate all the load and store instructions */
1609 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1610
1611 /* Add some optimization passes */
1612 LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1613 LLVMAddLICMPass(gallivm->passmgr);
1614 LLVMAddAggressiveDCEPass(gallivm->passmgr);
1615 LLVMAddCFGSimplificationPass(gallivm->passmgr);
1616 LLVMAddInstructionCombiningPass(gallivm->passmgr);
1617
1618 /* Run the pass */
1619 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1620
1621 LLVMDisposeBuilder(gallivm->builder);
1622 LLVMDisposePassManager(gallivm->passmgr);
1623
1624 }
1625
1626 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1627 {
1628 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1629 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1630 FREE(ctx->arrays);
1631 ctx->arrays = NULL;
1632 FREE(ctx->temps);
1633 ctx->temps = NULL;
1634 ctx->temps_count = 0;
1635 FREE(ctx->loop);
1636 ctx->loop = NULL;
1637 ctx->loop_depth_max = 0;
1638 FREE(ctx->branch);
1639 ctx->branch = NULL;
1640 ctx->branch_depth_max = 0;
1641 }