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[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26 #include "radeon_llvm.h"
27
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
42
43 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
44 {
45 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
46 }
47
48 static struct radeon_llvm_branch * get_current_branch(
49 struct radeon_llvm_context * ctx)
50 {
51 return ctx->branch_depth > 0 ?
52 ctx->branch + (ctx->branch_depth - 1) : NULL;
53 }
54
55 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
56 {
57 return (index * 4) + chan;
58 }
59
60 static LLVMValueRef emit_swizzle(
61 struct lp_build_tgsi_context * bld_base,
62 LLVMValueRef value,
63 unsigned swizzle_x,
64 unsigned swizzle_y,
65 unsigned swizzle_z,
66 unsigned swizzle_w)
67 {
68 LLVMValueRef swizzles[4];
69 LLVMTypeRef i32t =
70 LLVMInt32TypeInContext(bld_base->base.gallivm->context);
71
72 swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0);
73 swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0);
74 swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0);
75 swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0);
76
77 return LLVMBuildShuffleVector(bld_base->base.gallivm->builder,
78 value,
79 LLVMGetUndef(LLVMTypeOf(value)),
80 LLVMConstVector(swizzles, 4), "");
81 }
82
83 static struct tgsi_declaration_range
84 get_array_range(struct lp_build_tgsi_context *bld_base,
85 unsigned File, const struct tgsi_ind_register *reg)
86 {
87 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
88 if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 ||
89 reg->ArrayID > RADEON_LLVM_MAX_ARRAYS) {
90 struct tgsi_declaration_range range;
91 range.First = 0;
92 range.Last = bld_base->info->file_max[File];
93 return range;
94 }
95
96 return ctx->arrays[reg->ArrayID - 1];
97 }
98
99 static LLVMValueRef
100 emit_array_index(
101 struct lp_build_tgsi_soa_context *bld,
102 const struct tgsi_ind_register *reg,
103 unsigned offset)
104 {
105 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
106
107 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, bld->addr[reg->Index][reg->Swizzle], "");
108 return LLVMBuildAdd(gallivm->builder, addr, lp_build_const_int32(gallivm, offset), "");
109 }
110
111 static LLVMValueRef
112 emit_fetch(
113 struct lp_build_tgsi_context *bld_base,
114 const struct tgsi_full_src_register *reg,
115 enum tgsi_opcode_type type,
116 unsigned swizzle);
117
118 static LLVMValueRef
119 emit_array_fetch(
120 struct lp_build_tgsi_context *bld_base,
121 unsigned File, enum tgsi_opcode_type type,
122 struct tgsi_declaration_range range,
123 unsigned swizzle)
124 {
125 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
126 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
127 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
128
129 unsigned i, size = range.Last - range.First + 1;
130 LLVMTypeRef vec = LLVMVectorType(tgsi2llvmtype(bld_base, type), size);
131 LLVMValueRef result = LLVMGetUndef(vec);
132
133 struct tgsi_full_src_register tmp_reg = {};
134 tmp_reg.Register.File = File;
135
136 for (i = 0; i < size; ++i) {
137 tmp_reg.Register.Index = i + range.First;
138 LLVMValueRef temp = emit_fetch(bld_base, &tmp_reg, type, swizzle);
139 result = LLVMBuildInsertElement(builder, result, temp,
140 lp_build_const_int32(gallivm, i), "");
141 }
142 return result;
143 }
144
145 static LLVMValueRef
146 emit_fetch(
147 struct lp_build_tgsi_context *bld_base,
148 const struct tgsi_full_src_register *reg,
149 enum tgsi_opcode_type type,
150 unsigned swizzle)
151 {
152 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
153 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
154 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
155 LLVMValueRef result, ptr;
156
157 if (swizzle == ~0) {
158 LLVMValueRef values[TGSI_NUM_CHANNELS];
159 unsigned chan;
160 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
161 values[chan] = emit_fetch(bld_base, reg, type, chan);
162 }
163 return lp_build_gather_values(bld_base->base.gallivm, values,
164 TGSI_NUM_CHANNELS);
165 }
166
167 if (reg->Register.Indirect) {
168 struct tgsi_declaration_range range = get_array_range(bld_base,
169 reg->Register.File, &reg->Indirect);
170 return LLVMBuildExtractElement(builder,
171 emit_array_fetch(bld_base, reg->Register.File, type, range, swizzle),
172 emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First),
173 "");
174 }
175
176 switch(reg->Register.File) {
177 case TGSI_FILE_IMMEDIATE: {
178 LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type);
179 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
180 }
181
182 case TGSI_FILE_INPUT:
183 result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)];
184 break;
185
186 case TGSI_FILE_TEMPORARY:
187 ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
188 result = LLVMBuildLoad(builder, ptr, "");
189 break;
190
191 case TGSI_FILE_OUTPUT:
192 ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
193 result = LLVMBuildLoad(builder, ptr, "");
194 break;
195
196 default:
197 return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
198 }
199
200 return bitcast(bld_base, type, result);
201 }
202
203 static void emit_declaration(
204 struct lp_build_tgsi_context * bld_base,
205 const struct tgsi_full_declaration *decl)
206 {
207 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
208 switch(decl->Declaration.File) {
209 case TGSI_FILE_ADDRESS:
210 {
211 unsigned idx;
212 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
213 unsigned chan;
214 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
215 ctx->soa.addr[idx][chan] = lp_build_alloca(
216 &ctx->gallivm,
217 ctx->soa.bld_base.uint_bld.elem_type, "");
218 }
219 }
220 break;
221 }
222
223 case TGSI_FILE_TEMPORARY:
224 if (decl->Declaration.Array && decl->Array.ArrayID <= RADEON_LLVM_MAX_ARRAYS)
225 ctx->arrays[decl->Array.ArrayID - 1] = decl->Range;
226 lp_emit_declaration_soa(bld_base, decl);
227 break;
228
229 case TGSI_FILE_INPUT:
230 {
231 unsigned idx;
232 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
233 ctx->load_input(ctx, idx, decl);
234 }
235 }
236 break;
237
238 case TGSI_FILE_SYSTEM_VALUE:
239 {
240 unsigned idx;
241 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
242 ctx->load_system_value(ctx, idx, decl);
243 }
244 }
245 break;
246
247 case TGSI_FILE_OUTPUT:
248 {
249 unsigned idx;
250 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
251 unsigned chan;
252 assert(idx < RADEON_LLVM_MAX_OUTPUTS);
253 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
254 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm,
255 ctx->soa.bld_base.base.elem_type, "");
256 }
257 }
258
259 ctx->output_reg_count = MAX2(ctx->output_reg_count,
260 decl->Range.Last + 1);
261 break;
262 }
263
264 default:
265 break;
266 }
267 }
268
269 static void
270 emit_store(
271 struct lp_build_tgsi_context * bld_base,
272 const struct tgsi_full_instruction * inst,
273 const struct tgsi_opcode_info * info,
274 LLVMValueRef dst[4])
275 {
276 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
277 struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
278 struct lp_build_context base = bld->bld_base.base;
279 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
280 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
281 LLVMValueRef temp_ptr;
282 unsigned chan, chan_index;
283 boolean is_vec_store = FALSE;
284
285 if (dst[0]) {
286 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
287 is_vec_store = (k == LLVMVectorTypeKind);
288 }
289
290 if (is_vec_store) {
291 LLVMValueRef values[4] = {};
292 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
293 LLVMValueRef index = lp_build_const_int32(gallivm, chan);
294 values[chan] = LLVMBuildExtractElement(gallivm->builder,
295 dst[0], index, "");
296 }
297 bld_base->emit_store(bld_base, inst, info, values);
298 return;
299 }
300
301 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
302 LLVMValueRef value = dst[chan_index];
303
304 if (inst->Instruction.Saturate != TGSI_SAT_NONE) {
305 struct lp_build_emit_data clamp_emit_data;
306
307 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
308 clamp_emit_data.arg_count = 3;
309 clamp_emit_data.args[0] = value;
310 clamp_emit_data.args[2] = base.one;
311
312 switch(inst->Instruction.Saturate) {
313 case TGSI_SAT_ZERO_ONE:
314 clamp_emit_data.args[1] = base.zero;
315 break;
316 case TGSI_SAT_MINUS_PLUS_ONE:
317 clamp_emit_data.args[1] = LLVMConstReal(
318 base.elem_type, -1.0f);
319 break;
320 default:
321 assert(0);
322 }
323 value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
324 &clamp_emit_data);
325 }
326
327 if (reg->Register.File == TGSI_FILE_ADDRESS) {
328 temp_ptr = bld->addr[reg->Register.Index][chan_index];
329 LLVMBuildStore(builder, value, temp_ptr);
330 continue;
331 }
332
333 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
334
335 if (reg->Register.Indirect) {
336 struct tgsi_declaration_range range = get_array_range(bld_base,
337 reg->Register.File, &reg->Indirect);
338
339 unsigned i, size = range.Last - range.First + 1;
340 LLVMValueRef array = LLVMBuildInsertElement(builder,
341 emit_array_fetch(bld_base, reg->Register.File, TGSI_TYPE_FLOAT, range, chan_index),
342 value, emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First), "");
343
344 for (i = 0; i < size; ++i) {
345 switch(reg->Register.File) {
346 case TGSI_FILE_OUTPUT:
347 temp_ptr = bld->outputs[i + range.First][chan_index];
348 break;
349
350 case TGSI_FILE_TEMPORARY:
351 temp_ptr = lp_get_temp_ptr_soa(bld, i + range.First, chan_index);
352 break;
353
354 default:
355 return;
356 }
357 value = LLVMBuildExtractElement(builder, array,
358 lp_build_const_int32(gallivm, i), "");
359 LLVMBuildStore(builder, value, temp_ptr);
360 }
361
362 } else {
363 switch(reg->Register.File) {
364 case TGSI_FILE_OUTPUT:
365 temp_ptr = bld->outputs[reg->Register.Index][chan_index];
366 break;
367
368 case TGSI_FILE_TEMPORARY:
369 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, chan_index);
370 break;
371
372 default:
373 return;
374 }
375 LLVMBuildStore(builder, value, temp_ptr);
376 }
377 }
378 }
379
380 static void bgnloop_emit(
381 const struct lp_build_tgsi_action * action,
382 struct lp_build_tgsi_context * bld_base,
383 struct lp_build_emit_data * emit_data)
384 {
385 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
386 struct gallivm_state * gallivm = bld_base->base.gallivm;
387 LLVMBasicBlockRef loop_block;
388 LLVMBasicBlockRef endloop_block;
389 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
390 ctx->main_fn, "ENDLOOP");
391 loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
392 endloop_block, "LOOP");
393 LLVMBuildBr(gallivm->builder, loop_block);
394 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
395 ctx->loop_depth++;
396 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
397 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
398 }
399
400 static void brk_emit(
401 const struct lp_build_tgsi_action * action,
402 struct lp_build_tgsi_context * bld_base,
403 struct lp_build_emit_data * emit_data)
404 {
405 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
406 struct gallivm_state * gallivm = bld_base->base.gallivm;
407 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
408
409 LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
410 }
411
412 static void cont_emit(
413 const struct lp_build_tgsi_action * action,
414 struct lp_build_tgsi_context * bld_base,
415 struct lp_build_emit_data * emit_data)
416 {
417 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
418 struct gallivm_state * gallivm = bld_base->base.gallivm;
419 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
420
421 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
422 }
423
424 static void else_emit(
425 const struct lp_build_tgsi_action * action,
426 struct lp_build_tgsi_context * bld_base,
427 struct lp_build_emit_data * emit_data)
428 {
429 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
430 struct gallivm_state * gallivm = bld_base->base.gallivm;
431 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
432 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
433
434 /* We need to add a terminator to the current block if the previous
435 * instruction was an ENDIF.Example:
436 * IF
437 * [code]
438 * IF
439 * [code]
440 * ELSE
441 * [code]
442 * ENDIF <--
443 * ELSE<--
444 * [code]
445 * ENDIF
446 */
447
448 if (current_block != current_branch->if_block) {
449 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
450 }
451 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
452 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
453 }
454 current_branch->has_else = 1;
455 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
456 }
457
458 static void endif_emit(
459 const struct lp_build_tgsi_action * action,
460 struct lp_build_tgsi_context * bld_base,
461 struct lp_build_emit_data * emit_data)
462 {
463 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
464 struct gallivm_state * gallivm = bld_base->base.gallivm;
465 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
466 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
467
468 /* If we have consecutive ENDIF instructions, then the first ENDIF
469 * will not have a terminator, so we need to add one. */
470 if (current_block != current_branch->if_block
471 && current_block != current_branch->else_block
472 && !LLVMGetBasicBlockTerminator(current_block)) {
473
474 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
475 }
476 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
477 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
478 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
479 }
480
481 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
482 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
483 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
484 }
485
486 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
487 ctx->branch_depth--;
488 }
489
490 static void endloop_emit(
491 const struct lp_build_tgsi_action * action,
492 struct lp_build_tgsi_context * bld_base,
493 struct lp_build_emit_data * emit_data)
494 {
495 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
496 struct gallivm_state * gallivm = bld_base->base.gallivm;
497 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
498
499 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
500 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
501 }
502
503 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
504 ctx->loop_depth--;
505 }
506
507 static void if_emit(
508 const struct lp_build_tgsi_action * action,
509 struct lp_build_tgsi_context * bld_base,
510 struct lp_build_emit_data * emit_data)
511 {
512 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
513 struct gallivm_state * gallivm = bld_base->base.gallivm;
514 LLVMValueRef cond;
515 LLVMBasicBlockRef if_block, else_block, endif_block;
516
517 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
518 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
519 bld_base->int_bld.zero, "");
520
521 endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
522 ctx->main_fn, "ENDIF");
523 if_block = LLVMInsertBasicBlockInContext(gallivm->context,
524 endif_block, "IF");
525 else_block = LLVMInsertBasicBlockInContext(gallivm->context,
526 endif_block, "ELSE");
527 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
528 LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
529
530 ctx->branch_depth++;
531 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
532 ctx->branch[ctx->branch_depth - 1].if_block = if_block;
533 ctx->branch[ctx->branch_depth - 1].else_block = else_block;
534 ctx->branch[ctx->branch_depth - 1].has_else = 0;
535 }
536
537 static void kil_emit(
538 const struct lp_build_tgsi_action * action,
539 struct lp_build_tgsi_context * bld_base,
540 struct lp_build_emit_data * emit_data)
541 {
542 unsigned i;
543 for (i = 0; i < emit_data->arg_count; i++) {
544 emit_data->output[i] = lp_build_intrinsic_unary(
545 bld_base->base.gallivm->builder,
546 action->intr_name,
547 emit_data->dst_type, emit_data->args[i]);
548 }
549 }
550
551 void radeon_llvm_emit_prepare_cube_coords(
552 struct lp_build_tgsi_context * bld_base,
553 struct lp_build_emit_data * emit_data,
554 LLVMValueRef *coords_arg)
555 {
556
557 unsigned target = emit_data->inst->Texture.Texture;
558 unsigned opcode = emit_data->inst->Instruction.Opcode;
559 struct gallivm_state * gallivm = bld_base->base.gallivm;
560 LLVMBuilderRef builder = gallivm->builder;
561 LLVMTypeRef type = bld_base->base.elem_type;
562 LLVMValueRef coords[4];
563 LLVMValueRef mad_args[3];
564 LLVMValueRef idx;
565 struct LLVMOpaqueValue *cube_vec;
566 LLVMValueRef v;
567 unsigned i;
568
569 cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
570 v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
571 &cube_vec, 1, LLVMReadNoneAttribute);
572
573 for (i = 0; i < 4; ++i) {
574 idx = lp_build_const_int32(gallivm, i);
575 coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
576 }
577
578 coords[2] = build_intrinsic(builder, "fabs",
579 type, &coords[2], 1, LLVMReadNoneAttribute);
580 coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]);
581
582 mad_args[1] = coords[2];
583 mad_args[2] = LLVMConstReal(type, 1.5);
584
585 mad_args[0] = coords[0];
586 coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
587 mad_args[0], mad_args[1], mad_args[2]);
588
589 mad_args[0] = coords[1];
590 coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
591 mad_args[0], mad_args[1], mad_args[2]);
592
593 /* apply xyz = yxw swizzle to cooords */
594 coords[2] = coords[3];
595 coords[3] = coords[1];
596 coords[1] = coords[0];
597 coords[0] = coords[3];
598
599 /* all cases except simple cube map sampling require special handling
600 * for coord vector */
601 if (target != TGSI_TEXTURE_CUBE ||
602 opcode != TGSI_OPCODE_TEX) {
603
604 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
605 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
606 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
607
608 /* coords_arg.w component - array_index for cube arrays or
609 * compare value for SHADOWCUBE */
610 coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
611 coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
612 }
613
614 /* for instructions that need additional src (compare/lod/bias),
615 * put it in coord.w */
616 if (opcode == TGSI_OPCODE_TEX2 ||
617 opcode == TGSI_OPCODE_TXB2 ||
618 opcode == TGSI_OPCODE_TXL2) {
619 coords[3] = coords_arg[4];
620 }
621 }
622
623 memcpy(coords_arg, coords, sizeof(coords));
624 }
625
626 static void txd_fetch_args(
627 struct lp_build_tgsi_context * bld_base,
628 struct lp_build_emit_data * emit_data)
629 {
630 const struct tgsi_full_instruction * inst = emit_data->inst;
631
632 LLVMValueRef coords[4];
633 unsigned chan, src;
634 for (src = 0; src < 3; src++) {
635 for (chan = 0; chan < 4; chan++)
636 coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan);
637
638 emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm,
639 coords, 4);
640 }
641 emit_data->arg_count = 3;
642 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
643 }
644
645
646 static void txp_fetch_args(
647 struct lp_build_tgsi_context * bld_base,
648 struct lp_build_emit_data * emit_data)
649 {
650 const struct tgsi_full_instruction * inst = emit_data->inst;
651 LLVMValueRef src_w;
652 unsigned chan;
653 LLVMValueRef coords[4];
654
655 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
656 src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
657
658 for (chan = 0; chan < 3; chan++ ) {
659 LLVMValueRef arg = lp_build_emit_fetch(bld_base,
660 emit_data->inst, 0, chan);
661 coords[chan] = lp_build_emit_llvm_binary(bld_base,
662 TGSI_OPCODE_DIV, arg, src_w);
663 }
664 coords[3] = bld_base->base.one;
665
666 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
667 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
668 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
669 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
670 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
671 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
672 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
673 }
674
675 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
676 coords, 4);
677 emit_data->arg_count = 1;
678 }
679
680 static void tex_fetch_args(
681 struct lp_build_tgsi_context * bld_base,
682 struct lp_build_emit_data * emit_data)
683 {
684 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
685 * when we used CHAN_ALL. We should be able to get this to work,
686 * but for now we will swizzle it ourselves
687 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
688 0, CHAN_ALL);
689
690 */
691
692 const struct tgsi_full_instruction * inst = emit_data->inst;
693
694 LLVMValueRef coords[5];
695 unsigned chan;
696 for (chan = 0; chan < 4; chan++) {
697 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
698 }
699
700 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
701 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
702 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
703 /* These instructions have additional operand that should be packed
704 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
705 * That operand should be passed as a float value in the args array
706 * right after the coord vector. After packing it's not used anymore,
707 * that's why arg_count is not increased */
708 coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
709 }
710
711 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
712 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
713 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
714 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
715 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
716 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
717 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
718 }
719
720 emit_data->arg_count = 1;
721 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
722 coords, 4);
723 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
724 }
725
726 static void txf_fetch_args(
727 struct lp_build_tgsi_context * bld_base,
728 struct lp_build_emit_data * emit_data)
729 {
730 const struct tgsi_full_instruction * inst = emit_data->inst;
731 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
732 const struct tgsi_texture_offset * off = inst->TexOffsets;
733 LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
734
735 /* fetch tex coords */
736 tex_fetch_args(bld_base, emit_data);
737
738 /* fetch tex offsets */
739 if (inst->Texture.NumOffsets) {
740 assert(inst->Texture.NumOffsets == 1);
741
742 emit_data->args[1] = LLVMConstBitCast(
743 bld->immediates[off->Index][off->SwizzleX],
744 offset_type);
745 emit_data->args[2] = LLVMConstBitCast(
746 bld->immediates[off->Index][off->SwizzleY],
747 offset_type);
748 emit_data->args[3] = LLVMConstBitCast(
749 bld->immediates[off->Index][off->SwizzleZ],
750 offset_type);
751 } else {
752 emit_data->args[1] = bld_base->int_bld.zero;
753 emit_data->args[2] = bld_base->int_bld.zero;
754 emit_data->args[3] = bld_base->int_bld.zero;
755 }
756
757 emit_data->arg_count = 4;
758 }
759
760 static void emit_icmp(
761 const struct lp_build_tgsi_action * action,
762 struct lp_build_tgsi_context * bld_base,
763 struct lp_build_emit_data * emit_data)
764 {
765 unsigned pred;
766 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
767 LLVMContextRef context = bld_base->base.gallivm->context;
768
769 switch (emit_data->inst->Instruction.Opcode) {
770 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
771 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
772 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
773 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
774 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
775 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
776 default:
777 assert(!"unknown instruction");
778 pred = 0;
779 break;
780 }
781
782 LLVMValueRef v = LLVMBuildICmp(builder, pred,
783 emit_data->args[0], emit_data->args[1],"");
784
785 v = LLVMBuildSExtOrBitCast(builder, v,
786 LLVMInt32TypeInContext(context), "");
787
788 emit_data->output[emit_data->chan] = v;
789 }
790
791 static void emit_ucmp(
792 const struct lp_build_tgsi_action * action,
793 struct lp_build_tgsi_context * bld_base,
794 struct lp_build_emit_data * emit_data)
795 {
796 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
797
798 LLVMValueRef v = LLVMBuildFCmp(builder, LLVMRealUGE,
799 emit_data->args[0], lp_build_const_float(bld_base->base.gallivm, 0.), "");
800
801 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, v, emit_data->args[2], emit_data->args[1], "");
802 }
803
804 static void emit_cmp(
805 const struct lp_build_tgsi_action *action,
806 struct lp_build_tgsi_context * bld_base,
807 struct lp_build_emit_data * emit_data)
808 {
809 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
810 LLVMRealPredicate pred;
811 LLVMValueRef cond;
812
813 /* XXX I'm not sure whether to do unordered or ordered comparisons,
814 * but llvmpipe uses unordered comparisons, so for consistency we use
815 * unordered. (The authors of llvmpipe aren't sure about using
816 * unordered vs ordered comparisons either.
817 */
818 switch (emit_data->inst->Instruction.Opcode) {
819 case TGSI_OPCODE_SGE: pred = LLVMRealUGE; break;
820 case TGSI_OPCODE_SEQ: pred = LLVMRealUEQ; break;
821 case TGSI_OPCODE_SLE: pred = LLVMRealULE; break;
822 case TGSI_OPCODE_SLT: pred = LLVMRealULT; break;
823 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
824 case TGSI_OPCODE_SGT: pred = LLVMRealUGT; break;
825 default: assert(!"unknown instruction"); pred = 0; break;
826 }
827
828 cond = LLVMBuildFCmp(builder,
829 pred, emit_data->args[0], emit_data->args[1], "");
830
831 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
832 cond, bld_base->base.one, bld_base->base.zero, "");
833 }
834
835 static void emit_not(
836 const struct lp_build_tgsi_action * action,
837 struct lp_build_tgsi_context * bld_base,
838 struct lp_build_emit_data * emit_data)
839 {
840 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
841 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
842 emit_data->args[0]);
843 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
844 }
845
846 static void emit_arl(
847 const struct lp_build_tgsi_action * action,
848 struct lp_build_tgsi_context * bld_base,
849 struct lp_build_emit_data * emit_data)
850 {
851 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
852 LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
853 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
854 floor_index, bld_base->base.int_elem_type , "");
855 }
856
857 static void emit_and(
858 const struct lp_build_tgsi_action * action,
859 struct lp_build_tgsi_context * bld_base,
860 struct lp_build_emit_data * emit_data)
861 {
862 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
863 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
864 emit_data->args[0], emit_data->args[1], "");
865 }
866
867 static void emit_or(
868 const struct lp_build_tgsi_action * action,
869 struct lp_build_tgsi_context * bld_base,
870 struct lp_build_emit_data * emit_data)
871 {
872 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
873 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
874 emit_data->args[0], emit_data->args[1], "");
875 }
876
877 static void emit_uadd(
878 const struct lp_build_tgsi_action * action,
879 struct lp_build_tgsi_context * bld_base,
880 struct lp_build_emit_data * emit_data)
881 {
882 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
883 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
884 emit_data->args[0], emit_data->args[1], "");
885 }
886
887 static void emit_udiv(
888 const struct lp_build_tgsi_action * action,
889 struct lp_build_tgsi_context * bld_base,
890 struct lp_build_emit_data * emit_data)
891 {
892 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
893 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
894 emit_data->args[0], emit_data->args[1], "");
895 }
896
897 static void emit_idiv(
898 const struct lp_build_tgsi_action * action,
899 struct lp_build_tgsi_context * bld_base,
900 struct lp_build_emit_data * emit_data)
901 {
902 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
903 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
904 emit_data->args[0], emit_data->args[1], "");
905 }
906
907 static void emit_mod(
908 const struct lp_build_tgsi_action * action,
909 struct lp_build_tgsi_context * bld_base,
910 struct lp_build_emit_data * emit_data)
911 {
912 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
913 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
914 emit_data->args[0], emit_data->args[1], "");
915 }
916
917 static void emit_umod(
918 const struct lp_build_tgsi_action * action,
919 struct lp_build_tgsi_context * bld_base,
920 struct lp_build_emit_data * emit_data)
921 {
922 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
923 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
924 emit_data->args[0], emit_data->args[1], "");
925 }
926
927 static void emit_shl(
928 const struct lp_build_tgsi_action * action,
929 struct lp_build_tgsi_context * bld_base,
930 struct lp_build_emit_data * emit_data)
931 {
932 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
933 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
934 emit_data->args[0], emit_data->args[1], "");
935 }
936
937 static void emit_ushr(
938 const struct lp_build_tgsi_action * action,
939 struct lp_build_tgsi_context * bld_base,
940 struct lp_build_emit_data * emit_data)
941 {
942 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
943 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
944 emit_data->args[0], emit_data->args[1], "");
945 }
946 static void emit_ishr(
947 const struct lp_build_tgsi_action * action,
948 struct lp_build_tgsi_context * bld_base,
949 struct lp_build_emit_data * emit_data)
950 {
951 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
952 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
953 emit_data->args[0], emit_data->args[1], "");
954 }
955
956 static void emit_xor(
957 const struct lp_build_tgsi_action * action,
958 struct lp_build_tgsi_context * bld_base,
959 struct lp_build_emit_data * emit_data)
960 {
961 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
962 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
963 emit_data->args[0], emit_data->args[1], "");
964 }
965
966 static void emit_ssg(
967 const struct lp_build_tgsi_action * action,
968 struct lp_build_tgsi_context * bld_base,
969 struct lp_build_emit_data * emit_data)
970 {
971 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
972
973 LLVMValueRef cmp, val;
974
975 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
976 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
977 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
978 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
979 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
980 } else { // float SSG
981 cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->base.zero, "");
982 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
983 cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, "");
984 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
985 }
986
987 emit_data->output[emit_data->chan] = val;
988 }
989
990 static void emit_ineg(
991 const struct lp_build_tgsi_action * action,
992 struct lp_build_tgsi_context * bld_base,
993 struct lp_build_emit_data * emit_data)
994 {
995 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
996 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
997 emit_data->args[0], "");
998 }
999
1000 static void emit_f2i(
1001 const struct lp_build_tgsi_action * action,
1002 struct lp_build_tgsi_context * bld_base,
1003 struct lp_build_emit_data * emit_data)
1004 {
1005 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1006 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
1007 emit_data->args[0], bld_base->int_bld.elem_type, "");
1008 }
1009
1010 static void emit_f2u(
1011 const struct lp_build_tgsi_action * action,
1012 struct lp_build_tgsi_context * bld_base,
1013 struct lp_build_emit_data * emit_data)
1014 {
1015 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1016 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
1017 emit_data->args[0], bld_base->uint_bld.elem_type, "");
1018 }
1019
1020 static void emit_i2f(
1021 const struct lp_build_tgsi_action * action,
1022 struct lp_build_tgsi_context * bld_base,
1023 struct lp_build_emit_data * emit_data)
1024 {
1025 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1026 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
1027 emit_data->args[0], bld_base->base.elem_type, "");
1028 }
1029
1030 static void emit_u2f(
1031 const struct lp_build_tgsi_action * action,
1032 struct lp_build_tgsi_context * bld_base,
1033 struct lp_build_emit_data * emit_data)
1034 {
1035 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1036 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
1037 emit_data->args[0], bld_base->base.elem_type, "");
1038 }
1039
1040 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
1041 const struct tgsi_full_immediate *imm)
1042 {
1043 unsigned i;
1044 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
1045
1046 for (i = 0; i < 4; ++i) {
1047 ctx->soa.immediates[ctx->soa.num_immediates][i] =
1048 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false );
1049 }
1050
1051 ctx->soa.num_immediates++;
1052 }
1053
1054 LLVMValueRef
1055 build_intrinsic(LLVMBuilderRef builder,
1056 const char *name,
1057 LLVMTypeRef ret_type,
1058 LLVMValueRef *args,
1059 unsigned num_args,
1060 LLVMAttribute attr)
1061 {
1062 LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
1063 LLVMValueRef function;
1064
1065 function = LLVMGetNamedFunction(module, name);
1066 if(!function) {
1067 LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
1068 unsigned i;
1069
1070 assert(num_args <= LP_MAX_FUNC_ARGS);
1071
1072 for(i = 0; i < num_args; ++i) {
1073 assert(args[i]);
1074 arg_types[i] = LLVMTypeOf(args[i]);
1075 }
1076
1077 function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
1078
1079 if (attr)
1080 LLVMAddFunctionAttr(function, attr);
1081 }
1082
1083 return LLVMBuildCall(builder, function, args, num_args, "");
1084 }
1085
1086 static void build_tgsi_intrinsic(
1087 const struct lp_build_tgsi_action * action,
1088 struct lp_build_tgsi_context * bld_base,
1089 struct lp_build_emit_data * emit_data,
1090 LLVMAttribute attr)
1091 {
1092 struct lp_build_context * base = &bld_base->base;
1093 emit_data->output[emit_data->chan] = build_intrinsic(
1094 base->gallivm->builder, action->intr_name,
1095 emit_data->dst_type, emit_data->args,
1096 emit_data->arg_count, attr);
1097 }
1098 void
1099 build_tgsi_intrinsic_nomem(
1100 const struct lp_build_tgsi_action * action,
1101 struct lp_build_tgsi_context * bld_base,
1102 struct lp_build_emit_data * emit_data)
1103 {
1104 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadNoneAttribute);
1105 }
1106
1107 static void build_tgsi_intrinsic_readonly(
1108 const struct lp_build_tgsi_action * action,
1109 struct lp_build_tgsi_context * bld_base,
1110 struct lp_build_emit_data * emit_data)
1111 {
1112 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadOnlyAttribute);
1113 }
1114
1115 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
1116 {
1117 struct lp_type type;
1118
1119 /* Initialize the gallivm object:
1120 * We are only using the module, context, and builder fields of this struct.
1121 * This should be enough for us to be able to pass our gallivm struct to the
1122 * helper functions in the gallivm module.
1123 */
1124 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
1125 memset(&ctx->soa, 0, sizeof(ctx->soa));
1126 ctx->gallivm.context = LLVMContextCreate();
1127 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
1128 ctx->gallivm.context);
1129 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
1130
1131 ctx->store_output_intr = "llvm.AMDGPU.store.output.";
1132 ctx->swizzle_intr = "llvm.AMDGPU.swizzle";
1133 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1134
1135 /* XXX: We need to revisit this.I think the correct way to do this is
1136 * to use length = 4 here and use the elem_bld for everything. */
1137 type.floating = TRUE;
1138 type.sign = TRUE;
1139 type.width = 32;
1140 type.length = 1;
1141
1142 lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1143 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1144 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1145
1146 bld_base->soa = 1;
1147 bld_base->emit_store = emit_store;
1148 bld_base->emit_swizzle = emit_swizzle;
1149 bld_base->emit_declaration = emit_declaration;
1150 bld_base->emit_immediate = emit_immediate;
1151
1152 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch;
1153 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch;
1154 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch;
1155 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch;
1156
1157 /* Allocate outputs */
1158 ctx->soa.outputs = ctx->outputs;
1159
1160 ctx->num_arrays = 0;
1161
1162 /* XXX: Is there a better way to initialize all this ? */
1163
1164 lp_set_default_actions(bld_base);
1165
1166 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
1167 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
1168 bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
1169 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1170 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1171 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1172 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
1173 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
1174 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1175 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
1176 bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
1177 bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
1178 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1179 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly;
1180 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
1181 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
1182 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
1183 bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
1184 bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
1185 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1186 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1187 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1188 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1189 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
1190 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_readonly;
1191 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
1192 bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
1193 bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
1194 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1195 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1196 bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
1197 bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
1198 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1199 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1200 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1201 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
1202 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
1203 bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
1204 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1205 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1206 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1207 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1208 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1209 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1210 bld_base->op_actions[TGSI_OPCODE_KIL].emit = kil_emit;
1211 bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill";
1212 bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic;
1213 bld_base->op_actions[TGSI_OPCODE_KILP].intr_name = "llvm.AMDGPU.kilp";
1214 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_readonly;
1215 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
1216 bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
1217 bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
1218 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1219 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1220 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1221 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly;
1222 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
1223 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1224 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
1225 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
1226 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
1227 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1228 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
1229 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
1230 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
1231 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
1232 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly;
1233 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
1234 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1235 bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
1236 bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
1237 bld_base->op_actions[TGSI_OPCODE_TEX2].fetch_args = tex_fetch_args;
1238 bld_base->op_actions[TGSI_OPCODE_TEX2].intr_name = "llvm.AMDGPU.tex";
1239 bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
1240 bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
1241 bld_base->op_actions[TGSI_OPCODE_TXB2].fetch_args = tex_fetch_args;
1242 bld_base->op_actions[TGSI_OPCODE_TXB2].intr_name = "llvm.AMDGPU.txb";
1243 bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
1244 bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
1245 bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
1246 bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
1247 bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
1248 bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
1249 bld_base->op_actions[TGSI_OPCODE_TXL2].fetch_args = tex_fetch_args;
1250 bld_base->op_actions[TGSI_OPCODE_TXL2].intr_name = "llvm.AMDGPU.txl";
1251 bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
1252 bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
1253 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
1254 bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
1255 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1256 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
1257 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1258 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1259 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
1260 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
1261 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
1262 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
1263 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1264 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1265 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1266 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1267 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1268 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1269 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1270 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1271 bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
1272
1273 bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
1274 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
1275 }
1276
1277 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
1278 LLVMTypeRef *ParamTypes, unsigned ParamCount)
1279 {
1280 LLVMTypeRef main_fn_type;
1281 LLVMBasicBlockRef main_fn_body;
1282
1283 /* Setup the function */
1284 main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context),
1285 ParamTypes, ParamCount, 0);
1286 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1287 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1288 ctx->main_fn, "main_body");
1289 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1290 }
1291
1292 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1293 {
1294 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1295 /* End the main function with Return*/
1296 LLVMBuildRetVoid(gallivm->builder);
1297
1298 /* Create the pass manager */
1299 ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule(
1300 gallivm->module);
1301
1302 /* This pass should eliminate all the load and store instructions */
1303 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1304
1305 /* Add some optimization passes */
1306 LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1307 LLVMAddLICMPass(gallivm->passmgr);
1308 LLVMAddAggressiveDCEPass(gallivm->passmgr);
1309 LLVMAddCFGSimplificationPass(gallivm->passmgr);
1310
1311 /* Run the passs */
1312 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1313
1314 LLVMDisposeBuilder(gallivm->builder);
1315 LLVMDisposePassManager(gallivm->passmgr);
1316
1317 }
1318
1319 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1320 {
1321 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1322 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1323 }