projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeon/llvm: fix shadow cube texturing for GL3.0
[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26 #include "radeon_llvm.h"
27
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
42
43 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
44 {
45 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
46 }
47
48 static struct radeon_llvm_branch * get_current_branch(
49 struct radeon_llvm_context * ctx)
50 {
51 return ctx->branch_depth > 0 ?
52 ctx->branch + (ctx->branch_depth - 1) : NULL;
53 }
54
55 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
56 {
57 return (index * 4) + chan;
58 }
59
60 static LLVMValueRef emit_swizzle(
61 struct lp_build_tgsi_context * bld_base,
62 LLVMValueRef value,
63 unsigned swizzle_x,
64 unsigned swizzle_y,
65 unsigned swizzle_z,
66 unsigned swizzle_w)
67 {
68 LLVMValueRef swizzles[4];
69 LLVMTypeRef i32t =
70 LLVMInt32TypeInContext(bld_base->base.gallivm->context);
71
72 swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0);
73 swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0);
74 swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0);
75 swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0);
76
77 return LLVMBuildShuffleVector(bld_base->base.gallivm->builder,
78 value,
79 LLVMGetUndef(LLVMTypeOf(value)),
80 LLVMConstVector(swizzles, 4), "");
81 }
82
83 static struct tgsi_declaration_range
84 get_array_range(struct lp_build_tgsi_context *bld_base,
85 unsigned File, const struct tgsi_ind_register *reg)
86 {
87 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
88 if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 ||
89 reg->ArrayID > RADEON_LLVM_MAX_ARRAYS) {
90 struct tgsi_declaration_range range;
91 range.First = 0;
92 range.Last = bld_base->info->file_max[File];
93 return range;
94 }
95
96 return ctx->arrays[reg->ArrayID - 1];
97 }
98
99 static LLVMValueRef
100 emit_array_index(
101 struct lp_build_tgsi_soa_context *bld,
102 const struct tgsi_ind_register *reg,
103 unsigned offset)
104 {
105 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
106
107 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, bld->addr[reg->Index][reg->Swizzle], "");
108 return LLVMBuildAdd(gallivm->builder, addr, lp_build_const_int32(gallivm, offset), "");
109 }
110
111 static LLVMValueRef
112 emit_fetch(
113 struct lp_build_tgsi_context *bld_base,
114 const struct tgsi_full_src_register *reg,
115 enum tgsi_opcode_type type,
116 unsigned swizzle);
117
118 static LLVMValueRef
119 emit_array_fetch(
120 struct lp_build_tgsi_context *bld_base,
121 unsigned File, enum tgsi_opcode_type type,
122 struct tgsi_declaration_range range,
123 unsigned swizzle)
124 {
125 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
126 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
127 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
128
129 unsigned i, size = range.Last - range.First + 1;
130 LLVMTypeRef vec = LLVMVectorType(tgsi2llvmtype(bld_base, type), size);
131 LLVMValueRef result = LLVMGetUndef(vec);
132
133 struct tgsi_full_src_register tmp_reg = {};
134 tmp_reg.Register.File = File;
135
136 for (i = 0; i < size; ++i) {
137 tmp_reg.Register.Index = i + range.First;
138 LLVMValueRef temp = emit_fetch(bld_base, &tmp_reg, type, swizzle);
139 result = LLVMBuildInsertElement(builder, result, temp,
140 lp_build_const_int32(gallivm, i), "");
141 }
142 return result;
143 }
144
145 static LLVMValueRef
146 emit_fetch(
147 struct lp_build_tgsi_context *bld_base,
148 const struct tgsi_full_src_register *reg,
149 enum tgsi_opcode_type type,
150 unsigned swizzle)
151 {
152 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
153 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
154 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
155 LLVMValueRef result, ptr;
156
157 if (swizzle == ~0) {
158 LLVMValueRef values[TGSI_NUM_CHANNELS];
159 unsigned chan;
160 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
161 values[chan] = emit_fetch(bld_base, reg, type, chan);
162 }
163 return lp_build_gather_values(bld_base->base.gallivm, values,
164 TGSI_NUM_CHANNELS);
165 }
166
167 if (reg->Register.Indirect) {
168 struct tgsi_declaration_range range = get_array_range(bld_base,
169 reg->Register.File, &reg->Indirect);
170 return LLVMBuildExtractElement(builder,
171 emit_array_fetch(bld_base, reg->Register.File, type, range, swizzle),
172 emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First),
173 "");
174 }
175
176 switch(reg->Register.File) {
177 case TGSI_FILE_IMMEDIATE: {
178 LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type);
179 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
180 }
181
182 case TGSI_FILE_INPUT:
183 result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)];
184 break;
185
186 case TGSI_FILE_TEMPORARY:
187 ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
188 result = LLVMBuildLoad(builder, ptr, "");
189 break;
190
191 case TGSI_FILE_OUTPUT:
192 ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
193 result = LLVMBuildLoad(builder, ptr, "");
194 break;
195
196 default:
197 return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
198 }
199
200 return bitcast(bld_base, type, result);
201 }
202
203 static LLVMValueRef fetch_system_value(
204 struct lp_build_tgsi_context * bld_base,
205 const struct tgsi_full_src_register *reg,
206 enum tgsi_opcode_type type,
207 unsigned swizzle)
208 {
209 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
210 LLVMValueRef cval = ctx->system_values[reg->Register.Index];
211 return bitcast(bld_base, type, cval);
212 }
213
214 static void emit_declaration(
215 struct lp_build_tgsi_context * bld_base,
216 const struct tgsi_full_declaration *decl)
217 {
218 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
219 switch(decl->Declaration.File) {
220 case TGSI_FILE_ADDRESS:
221 {
222 unsigned idx;
223 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
224 unsigned chan;
225 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
226 ctx->soa.addr[idx][chan] = lp_build_alloca(
227 &ctx->gallivm,
228 ctx->soa.bld_base.uint_bld.elem_type, "");
229 }
230 }
231 break;
232 }
233
234 case TGSI_FILE_TEMPORARY:
235 if (decl->Declaration.Array && decl->Array.ArrayID <= RADEON_LLVM_MAX_ARRAYS)
236 ctx->arrays[decl->Array.ArrayID - 1] = decl->Range;
237 lp_emit_declaration_soa(bld_base, decl);
238 break;
239
240 case TGSI_FILE_INPUT:
241 {
242 unsigned idx;
243 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
244 ctx->load_input(ctx, idx, decl);
245 }
246 }
247 break;
248
249 case TGSI_FILE_SYSTEM_VALUE:
250 {
251 unsigned idx;
252 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
253 ctx->load_system_value(ctx, idx, decl);
254 }
255 }
256 break;
257
258 case TGSI_FILE_OUTPUT:
259 {
260 unsigned idx;
261 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
262 unsigned chan;
263 assert(idx < RADEON_LLVM_MAX_OUTPUTS);
264 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
265 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm,
266 ctx->soa.bld_base.base.elem_type, "");
267 }
268 }
269
270 ctx->output_reg_count = MAX2(ctx->output_reg_count,
271 decl->Range.Last + 1);
272 break;
273 }
274
275 default:
276 break;
277 }
278 }
279
280 static void
281 emit_store(
282 struct lp_build_tgsi_context * bld_base,
283 const struct tgsi_full_instruction * inst,
284 const struct tgsi_opcode_info * info,
285 LLVMValueRef dst[4])
286 {
287 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
288 struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
289 struct lp_build_context base = bld->bld_base.base;
290 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
291 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
292 LLVMValueRef temp_ptr;
293 unsigned chan, chan_index;
294 boolean is_vec_store = FALSE;
295
296 if (dst[0]) {
297 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
298 is_vec_store = (k == LLVMVectorTypeKind);
299 }
300
301 if (is_vec_store) {
302 LLVMValueRef values[4] = {};
303 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
304 LLVMValueRef index = lp_build_const_int32(gallivm, chan);
305 values[chan] = LLVMBuildExtractElement(gallivm->builder,
306 dst[0], index, "");
307 }
308 bld_base->emit_store(bld_base, inst, info, values);
309 return;
310 }
311
312 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
313 LLVMValueRef value = dst[chan_index];
314
315 if (inst->Instruction.Saturate != TGSI_SAT_NONE) {
316 struct lp_build_emit_data clamp_emit_data;
317
318 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
319 clamp_emit_data.arg_count = 3;
320 clamp_emit_data.args[0] = value;
321 clamp_emit_data.args[2] = base.one;
322
323 switch(inst->Instruction.Saturate) {
324 case TGSI_SAT_ZERO_ONE:
325 clamp_emit_data.args[1] = base.zero;
326 break;
327 case TGSI_SAT_MINUS_PLUS_ONE:
328 clamp_emit_data.args[1] = LLVMConstReal(
329 base.elem_type, -1.0f);
330 break;
331 default:
332 assert(0);
333 }
334 value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
335 &clamp_emit_data);
336 }
337
338 if (reg->Register.File == TGSI_FILE_ADDRESS) {
339 temp_ptr = bld->addr[reg->Register.Index][chan_index];
340 LLVMBuildStore(builder, value, temp_ptr);
341 continue;
342 }
343
344 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
345
346 if (reg->Register.Indirect) {
347 struct tgsi_declaration_range range = get_array_range(bld_base,
348 reg->Register.File, &reg->Indirect);
349
350 unsigned i, size = range.Last - range.First + 1;
351 LLVMValueRef array = LLVMBuildInsertElement(builder,
352 emit_array_fetch(bld_base, reg->Register.File, TGSI_TYPE_FLOAT, range, chan_index),
353 value, emit_array_index(bld, &reg->Indirect, reg->Register.Index - range.First), "");
354
355 for (i = 0; i < size; ++i) {
356 switch(reg->Register.File) {
357 case TGSI_FILE_OUTPUT:
358 temp_ptr = bld->outputs[i + range.First][chan_index];
359 break;
360
361 case TGSI_FILE_TEMPORARY:
362 temp_ptr = lp_get_temp_ptr_soa(bld, i + range.First, chan_index);
363 break;
364
365 default:
366 return;
367 }
368 value = LLVMBuildExtractElement(builder, array,
369 lp_build_const_int32(gallivm, i), "");
370 LLVMBuildStore(builder, value, temp_ptr);
371 }
372
373 } else {
374 switch(reg->Register.File) {
375 case TGSI_FILE_OUTPUT:
376 temp_ptr = bld->outputs[reg->Register.Index][chan_index];
377 break;
378
379 case TGSI_FILE_TEMPORARY:
380 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, chan_index);
381 break;
382
383 default:
384 return;
385 }
386 LLVMBuildStore(builder, value, temp_ptr);
387 }
388 }
389 }
390
391 static void bgnloop_emit(
392 const struct lp_build_tgsi_action * action,
393 struct lp_build_tgsi_context * bld_base,
394 struct lp_build_emit_data * emit_data)
395 {
396 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
397 struct gallivm_state * gallivm = bld_base->base.gallivm;
398 LLVMBasicBlockRef loop_block;
399 LLVMBasicBlockRef endloop_block;
400 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
401 ctx->main_fn, "ENDLOOP");
402 loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
403 endloop_block, "LOOP");
404 LLVMBuildBr(gallivm->builder, loop_block);
405 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
406 ctx->loop_depth++;
407 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
408 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
409 }
410
411 static void brk_emit(
412 const struct lp_build_tgsi_action * action,
413 struct lp_build_tgsi_context * bld_base,
414 struct lp_build_emit_data * emit_data)
415 {
416 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
417 struct gallivm_state * gallivm = bld_base->base.gallivm;
418 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
419
420 LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
421 }
422
423 static void cont_emit(
424 const struct lp_build_tgsi_action * action,
425 struct lp_build_tgsi_context * bld_base,
426 struct lp_build_emit_data * emit_data)
427 {
428 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
429 struct gallivm_state * gallivm = bld_base->base.gallivm;
430 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
431
432 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
433 }
434
435 static void else_emit(
436 const struct lp_build_tgsi_action * action,
437 struct lp_build_tgsi_context * bld_base,
438 struct lp_build_emit_data * emit_data)
439 {
440 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
441 struct gallivm_state * gallivm = bld_base->base.gallivm;
442 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
443 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
444
445 /* We need to add a terminator to the current block if the previous
446 * instruction was an ENDIF.Example:
447 * IF
448 * [code]
449 * IF
450 * [code]
451 * ELSE
452 * [code]
453 * ENDIF <--
454 * ELSE<--
455 * [code]
456 * ENDIF
457 */
458
459 if (current_block != current_branch->if_block) {
460 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
461 }
462 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
463 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
464 }
465 current_branch->has_else = 1;
466 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
467 }
468
469 static void endif_emit(
470 const struct lp_build_tgsi_action * action,
471 struct lp_build_tgsi_context * bld_base,
472 struct lp_build_emit_data * emit_data)
473 {
474 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
475 struct gallivm_state * gallivm = bld_base->base.gallivm;
476 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
477 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
478
479 /* If we have consecutive ENDIF instructions, then the first ENDIF
480 * will not have a terminator, so we need to add one. */
481 if (current_block != current_branch->if_block
482 && current_block != current_branch->else_block
483 && !LLVMGetBasicBlockTerminator(current_block)) {
484
485 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
486 }
487 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
488 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
489 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
490 }
491
492 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
493 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
494 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
495 }
496
497 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
498 ctx->branch_depth--;
499 }
500
501 static void endloop_emit(
502 const struct lp_build_tgsi_action * action,
503 struct lp_build_tgsi_context * bld_base,
504 struct lp_build_emit_data * emit_data)
505 {
506 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
507 struct gallivm_state * gallivm = bld_base->base.gallivm;
508 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
509
510 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
511 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
512 }
513
514 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
515 ctx->loop_depth--;
516 }
517
518 static void if_cond_emit(
519 const struct lp_build_tgsi_action * action,
520 struct lp_build_tgsi_context * bld_base,
521 struct lp_build_emit_data * emit_data,
522 LLVMValueRef cond)
523 {
524 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
525 struct gallivm_state * gallivm = bld_base->base.gallivm;
526 LLVMBasicBlockRef if_block, else_block, endif_block;
527
528 endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
529 ctx->main_fn, "ENDIF");
530 if_block = LLVMInsertBasicBlockInContext(gallivm->context,
531 endif_block, "IF");
532 else_block = LLVMInsertBasicBlockInContext(gallivm->context,
533 endif_block, "ELSE");
534 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
535 LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
536
537 ctx->branch_depth++;
538 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
539 ctx->branch[ctx->branch_depth - 1].if_block = if_block;
540 ctx->branch[ctx->branch_depth - 1].else_block = else_block;
541 ctx->branch[ctx->branch_depth - 1].has_else = 0;
542 }
543
544 static void if_emit(
545 const struct lp_build_tgsi_action * action,
546 struct lp_build_tgsi_context * bld_base,
547 struct lp_build_emit_data * emit_data)
548 {
549 struct gallivm_state * gallivm = bld_base->base.gallivm;
550 LLVMValueRef cond;
551
552 cond = LLVMBuildFCmp(gallivm->builder, LLVMRealUNE,
553 emit_data->args[0],
554 bld_base->base.zero, "");
555
556 if_cond_emit(action, bld_base, emit_data, cond);
557 }
558
559 static void uif_emit(
560 const struct lp_build_tgsi_action * action,
561 struct lp_build_tgsi_context * bld_base,
562 struct lp_build_emit_data * emit_data)
563 {
564 struct gallivm_state * gallivm = bld_base->base.gallivm;
565 LLVMValueRef cond;
566
567 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
568 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
569 bld_base->int_bld.zero, "");
570
571 if_cond_emit(action, bld_base, emit_data, cond);
572 }
573
574 static void kil_emit(
575 const struct lp_build_tgsi_action * action,
576 struct lp_build_tgsi_context * bld_base,
577 struct lp_build_emit_data * emit_data)
578 {
579 unsigned i;
580 for (i = 0; i < emit_data->arg_count; i++) {
581 emit_data->output[i] = lp_build_intrinsic_unary(
582 bld_base->base.gallivm->builder,
583 action->intr_name,
584 emit_data->dst_type, emit_data->args[i]);
585 }
586 }
587
588 void radeon_llvm_emit_prepare_cube_coords(
589 struct lp_build_tgsi_context * bld_base,
590 struct lp_build_emit_data * emit_data,
591 LLVMValueRef *coords_arg)
592 {
593
594 unsigned target = emit_data->inst->Texture.Texture;
595 unsigned opcode = emit_data->inst->Instruction.Opcode;
596 struct gallivm_state * gallivm = bld_base->base.gallivm;
597 LLVMBuilderRef builder = gallivm->builder;
598 LLVMTypeRef type = bld_base->base.elem_type;
599 LLVMValueRef coords[4];
600 LLVMValueRef mad_args[3];
601 LLVMValueRef idx;
602 struct LLVMOpaqueValue *cube_vec;
603 LLVMValueRef v;
604 unsigned i;
605
606 cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
607 v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
608 &cube_vec, 1, LLVMReadNoneAttribute);
609
610 for (i = 0; i < 4; ++i) {
611 idx = lp_build_const_int32(gallivm, i);
612 coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
613 }
614
615 coords[2] = build_intrinsic(builder, "fabs",
616 type, &coords[2], 1, LLVMReadNoneAttribute);
617 coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]);
618
619 mad_args[1] = coords[2];
620 mad_args[2] = LLVMConstReal(type, 1.5);
621
622 mad_args[0] = coords[0];
623 coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
624 mad_args[0], mad_args[1], mad_args[2]);
625
626 mad_args[0] = coords[1];
627 coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
628 mad_args[0], mad_args[1], mad_args[2]);
629
630 /* apply xyz = yxw swizzle to cooords */
631 coords[2] = coords[3];
632 coords[3] = coords[1];
633 coords[1] = coords[0];
634 coords[0] = coords[3];
635
636 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
637 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
638 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
639 /* coords_arg.w component - array_index for cube arrays */
640 coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
641 coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
642 }
643
644 /* Preserve compare/lod/bias. Put it in coords.w. */
645 if (opcode == TGSI_OPCODE_TEX2 ||
646 opcode == TGSI_OPCODE_TXB2 ||
647 opcode == TGSI_OPCODE_TXL2) {
648 coords[3] = coords_arg[4];
649 } else if (opcode == TGSI_OPCODE_TXB ||
650 opcode == TGSI_OPCODE_TXL ||
651 target == TGSI_TEXTURE_SHADOWCUBE) {
652 coords[3] = coords_arg[3];
653 }
654
655 memcpy(coords_arg, coords, sizeof(coords));
656 }
657
658 static void txd_fetch_args(
659 struct lp_build_tgsi_context * bld_base,
660 struct lp_build_emit_data * emit_data)
661 {
662 const struct tgsi_full_instruction * inst = emit_data->inst;
663
664 LLVMValueRef coords[4];
665 unsigned chan, src;
666 for (src = 0; src < 3; src++) {
667 for (chan = 0; chan < 4; chan++)
668 coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan);
669
670 emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm,
671 coords, 4);
672 }
673 emit_data->arg_count = 3;
674 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
675 }
676
677
678 static void txp_fetch_args(
679 struct lp_build_tgsi_context * bld_base,
680 struct lp_build_emit_data * emit_data)
681 {
682 const struct tgsi_full_instruction * inst = emit_data->inst;
683 LLVMValueRef src_w;
684 unsigned chan;
685 LLVMValueRef coords[4];
686
687 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
688 src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
689
690 for (chan = 0; chan < 3; chan++ ) {
691 LLVMValueRef arg = lp_build_emit_fetch(bld_base,
692 emit_data->inst, 0, chan);
693 coords[chan] = lp_build_emit_llvm_binary(bld_base,
694 TGSI_OPCODE_DIV, arg, src_w);
695 }
696 coords[3] = bld_base->base.one;
697
698 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
699 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
700 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
701 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
702 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
703 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
704 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
705 }
706
707 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
708 coords, 4);
709 emit_data->arg_count = 1;
710 }
711
712 static void tex_fetch_args(
713 struct lp_build_tgsi_context * bld_base,
714 struct lp_build_emit_data * emit_data)
715 {
716 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
717 * when we used CHAN_ALL. We should be able to get this to work,
718 * but for now we will swizzle it ourselves
719 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
720 0, CHAN_ALL);
721
722 */
723
724 const struct tgsi_full_instruction * inst = emit_data->inst;
725
726 LLVMValueRef coords[5];
727 unsigned chan;
728 for (chan = 0; chan < 4; chan++) {
729 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
730 }
731
732 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
733 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
734 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
735 /* These instructions have additional operand that should be packed
736 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
737 * That operand should be passed as a float value in the args array
738 * right after the coord vector. After packing it's not used anymore,
739 * that's why arg_count is not increased */
740 coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
741 }
742
743 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
744 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
745 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
746 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
747 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
748 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
749 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
750 }
751
752 emit_data->arg_count = 1;
753 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
754 coords, 4);
755 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
756 }
757
758 static void txf_fetch_args(
759 struct lp_build_tgsi_context * bld_base,
760 struct lp_build_emit_data * emit_data)
761 {
762 const struct tgsi_full_instruction * inst = emit_data->inst;
763 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
764 const struct tgsi_texture_offset * off = inst->TexOffsets;
765 LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
766
767 /* fetch tex coords */
768 tex_fetch_args(bld_base, emit_data);
769
770 /* fetch tex offsets */
771 if (inst->Texture.NumOffsets) {
772 assert(inst->Texture.NumOffsets == 1);
773
774 emit_data->args[1] = LLVMConstBitCast(
775 bld->immediates[off->Index][off->SwizzleX],
776 offset_type);
777 emit_data->args[2] = LLVMConstBitCast(
778 bld->immediates[off->Index][off->SwizzleY],
779 offset_type);
780 emit_data->args[3] = LLVMConstBitCast(
781 bld->immediates[off->Index][off->SwizzleZ],
782 offset_type);
783 } else {
784 emit_data->args[1] = bld_base->int_bld.zero;
785 emit_data->args[2] = bld_base->int_bld.zero;
786 emit_data->args[3] = bld_base->int_bld.zero;
787 }
788
789 emit_data->arg_count = 4;
790 }
791
792 static void emit_icmp(
793 const struct lp_build_tgsi_action * action,
794 struct lp_build_tgsi_context * bld_base,
795 struct lp_build_emit_data * emit_data)
796 {
797 unsigned pred;
798 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
799 LLVMContextRef context = bld_base->base.gallivm->context;
800
801 switch (emit_data->inst->Instruction.Opcode) {
802 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
803 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
804 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
805 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
806 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
807 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
808 default:
809 assert(!"unknown instruction");
810 pred = 0;
811 break;
812 }
813
814 LLVMValueRef v = LLVMBuildICmp(builder, pred,
815 emit_data->args[0], emit_data->args[1],"");
816
817 v = LLVMBuildSExtOrBitCast(builder, v,
818 LLVMInt32TypeInContext(context), "");
819
820 emit_data->output[emit_data->chan] = v;
821 }
822
823 static void emit_ucmp(
824 const struct lp_build_tgsi_action * action,
825 struct lp_build_tgsi_context * bld_base,
826 struct lp_build_emit_data * emit_data)
827 {
828 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
829
830 LLVMValueRef v = LLVMBuildFCmp(builder, LLVMRealUGE,
831 emit_data->args[0], lp_build_const_float(bld_base->base.gallivm, 0.), "");
832
833 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, v, emit_data->args[2], emit_data->args[1], "");
834 }
835
836 static void emit_cmp(
837 const struct lp_build_tgsi_action *action,
838 struct lp_build_tgsi_context * bld_base,
839 struct lp_build_emit_data * emit_data)
840 {
841 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
842 LLVMRealPredicate pred;
843 LLVMValueRef cond;
844
845 /* Use ordered for everything but NE (which is usual for
846 * float comparisons)
847 */
848 switch (emit_data->inst->Instruction.Opcode) {
849 case TGSI_OPCODE_SGE: pred = LLVMRealOGE; break;
850 case TGSI_OPCODE_SEQ: pred = LLVMRealOEQ; break;
851 case TGSI_OPCODE_SLE: pred = LLVMRealOLE; break;
852 case TGSI_OPCODE_SLT: pred = LLVMRealOLT; break;
853 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
854 case TGSI_OPCODE_SGT: pred = LLVMRealOGT; break;
855 default: assert(!"unknown instruction"); pred = 0; break;
856 }
857
858 cond = LLVMBuildFCmp(builder,
859 pred, emit_data->args[0], emit_data->args[1], "");
860
861 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
862 cond, bld_base->base.one, bld_base->base.zero, "");
863 }
864
865 static void emit_fcmp(
866 const struct lp_build_tgsi_action *action,
867 struct lp_build_tgsi_context * bld_base,
868 struct lp_build_emit_data * emit_data)
869 {
870 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
871 LLVMContextRef context = bld_base->base.gallivm->context;
872 LLVMRealPredicate pred;
873
874 /* Use ordered for everything but NE (which is usual for
875 * float comparisons)
876 */
877 switch (emit_data->inst->Instruction.Opcode) {
878 case TGSI_OPCODE_FSEQ: pred = LLVMRealOEQ; break;
879 case TGSI_OPCODE_FSGE: pred = LLVMRealOGE; break;
880 case TGSI_OPCODE_FSLT: pred = LLVMRealOLT; break;
881 case TGSI_OPCODE_FSNE: pred = LLVMRealUNE; break;
882 default: assert(!"unknown instruction"); pred = 0; break;
883 }
884
885 LLVMValueRef v = LLVMBuildFCmp(builder, pred,
886 emit_data->args[0], emit_data->args[1],"");
887
888 v = LLVMBuildSExtOrBitCast(builder, v,
889 LLVMInt32TypeInContext(context), "");
890
891 emit_data->output[emit_data->chan] = v;
892 }
893
894 static void emit_not(
895 const struct lp_build_tgsi_action * action,
896 struct lp_build_tgsi_context * bld_base,
897 struct lp_build_emit_data * emit_data)
898 {
899 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
900 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
901 emit_data->args[0]);
902 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
903 }
904
905 static void emit_arl(
906 const struct lp_build_tgsi_action * action,
907 struct lp_build_tgsi_context * bld_base,
908 struct lp_build_emit_data * emit_data)
909 {
910 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
911 LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
912 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
913 floor_index, bld_base->base.int_elem_type , "");
914 }
915
916 static void emit_and(
917 const struct lp_build_tgsi_action * action,
918 struct lp_build_tgsi_context * bld_base,
919 struct lp_build_emit_data * emit_data)
920 {
921 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
922 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
923 emit_data->args[0], emit_data->args[1], "");
924 }
925
926 static void emit_or(
927 const struct lp_build_tgsi_action * action,
928 struct lp_build_tgsi_context * bld_base,
929 struct lp_build_emit_data * emit_data)
930 {
931 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
932 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
933 emit_data->args[0], emit_data->args[1], "");
934 }
935
936 static void emit_uadd(
937 const struct lp_build_tgsi_action * action,
938 struct lp_build_tgsi_context * bld_base,
939 struct lp_build_emit_data * emit_data)
940 {
941 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
942 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
943 emit_data->args[0], emit_data->args[1], "");
944 }
945
946 static void emit_udiv(
947 const struct lp_build_tgsi_action * action,
948 struct lp_build_tgsi_context * bld_base,
949 struct lp_build_emit_data * emit_data)
950 {
951 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
952 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
953 emit_data->args[0], emit_data->args[1], "");
954 }
955
956 static void emit_idiv(
957 const struct lp_build_tgsi_action * action,
958 struct lp_build_tgsi_context * bld_base,
959 struct lp_build_emit_data * emit_data)
960 {
961 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
962 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
963 emit_data->args[0], emit_data->args[1], "");
964 }
965
966 static void emit_mod(
967 const struct lp_build_tgsi_action * action,
968 struct lp_build_tgsi_context * bld_base,
969 struct lp_build_emit_data * emit_data)
970 {
971 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
972 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
973 emit_data->args[0], emit_data->args[1], "");
974 }
975
976 static void emit_umod(
977 const struct lp_build_tgsi_action * action,
978 struct lp_build_tgsi_context * bld_base,
979 struct lp_build_emit_data * emit_data)
980 {
981 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
982 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
983 emit_data->args[0], emit_data->args[1], "");
984 }
985
986 static void emit_shl(
987 const struct lp_build_tgsi_action * action,
988 struct lp_build_tgsi_context * bld_base,
989 struct lp_build_emit_data * emit_data)
990 {
991 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
992 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
993 emit_data->args[0], emit_data->args[1], "");
994 }
995
996 static void emit_ushr(
997 const struct lp_build_tgsi_action * action,
998 struct lp_build_tgsi_context * bld_base,
999 struct lp_build_emit_data * emit_data)
1000 {
1001 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1002 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
1003 emit_data->args[0], emit_data->args[1], "");
1004 }
1005 static void emit_ishr(
1006 const struct lp_build_tgsi_action * action,
1007 struct lp_build_tgsi_context * bld_base,
1008 struct lp_build_emit_data * emit_data)
1009 {
1010 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1011 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
1012 emit_data->args[0], emit_data->args[1], "");
1013 }
1014
1015 static void emit_xor(
1016 const struct lp_build_tgsi_action * action,
1017 struct lp_build_tgsi_context * bld_base,
1018 struct lp_build_emit_data * emit_data)
1019 {
1020 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1021 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
1022 emit_data->args[0], emit_data->args[1], "");
1023 }
1024
1025 static void emit_ssg(
1026 const struct lp_build_tgsi_action * action,
1027 struct lp_build_tgsi_context * bld_base,
1028 struct lp_build_emit_data * emit_data)
1029 {
1030 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1031
1032 LLVMValueRef cmp, val;
1033
1034 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
1035 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
1036 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
1037 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
1038 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
1039 } else { // float SSG
1040 cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->base.zero, "");
1041 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
1042 cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, "");
1043 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
1044 }
1045
1046 emit_data->output[emit_data->chan] = val;
1047 }
1048
1049 static void emit_ineg(
1050 const struct lp_build_tgsi_action * action,
1051 struct lp_build_tgsi_context * bld_base,
1052 struct lp_build_emit_data * emit_data)
1053 {
1054 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1055 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
1056 emit_data->args[0], "");
1057 }
1058
1059 static void emit_f2i(
1060 const struct lp_build_tgsi_action * action,
1061 struct lp_build_tgsi_context * bld_base,
1062 struct lp_build_emit_data * emit_data)
1063 {
1064 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1065 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
1066 emit_data->args[0], bld_base->int_bld.elem_type, "");
1067 }
1068
1069 static void emit_f2u(
1070 const struct lp_build_tgsi_action * action,
1071 struct lp_build_tgsi_context * bld_base,
1072 struct lp_build_emit_data * emit_data)
1073 {
1074 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1075 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
1076 emit_data->args[0], bld_base->uint_bld.elem_type, "");
1077 }
1078
1079 static void emit_i2f(
1080 const struct lp_build_tgsi_action * action,
1081 struct lp_build_tgsi_context * bld_base,
1082 struct lp_build_emit_data * emit_data)
1083 {
1084 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1085 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
1086 emit_data->args[0], bld_base->base.elem_type, "");
1087 }
1088
1089 static void emit_u2f(
1090 const struct lp_build_tgsi_action * action,
1091 struct lp_build_tgsi_context * bld_base,
1092 struct lp_build_emit_data * emit_data)
1093 {
1094 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1095 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
1096 emit_data->args[0], bld_base->base.elem_type, "");
1097 }
1098
1099 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
1100 const struct tgsi_full_immediate *imm)
1101 {
1102 unsigned i;
1103 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
1104
1105 for (i = 0; i < 4; ++i) {
1106 ctx->soa.immediates[ctx->soa.num_immediates][i] =
1107 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false );
1108 }
1109
1110 ctx->soa.num_immediates++;
1111 }
1112
1113 LLVMValueRef
1114 build_intrinsic(LLVMBuilderRef builder,
1115 const char *name,
1116 LLVMTypeRef ret_type,
1117 LLVMValueRef *args,
1118 unsigned num_args,
1119 LLVMAttribute attr)
1120 {
1121 LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
1122 LLVMValueRef function;
1123
1124 function = LLVMGetNamedFunction(module, name);
1125 if(!function) {
1126 LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
1127 unsigned i;
1128
1129 assert(num_args <= LP_MAX_FUNC_ARGS);
1130
1131 for(i = 0; i < num_args; ++i) {
1132 assert(args[i]);
1133 arg_types[i] = LLVMTypeOf(args[i]);
1134 }
1135
1136 function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
1137
1138 if (attr)
1139 LLVMAddFunctionAttr(function, attr);
1140 }
1141
1142 return LLVMBuildCall(builder, function, args, num_args, "");
1143 }
1144
1145 static void build_tgsi_intrinsic(
1146 const struct lp_build_tgsi_action * action,
1147 struct lp_build_tgsi_context * bld_base,
1148 struct lp_build_emit_data * emit_data,
1149 LLVMAttribute attr)
1150 {
1151 struct lp_build_context * base = &bld_base->base;
1152 emit_data->output[emit_data->chan] = build_intrinsic(
1153 base->gallivm->builder, action->intr_name,
1154 emit_data->dst_type, emit_data->args,
1155 emit_data->arg_count, attr);
1156 }
1157 void
1158 build_tgsi_intrinsic_nomem(
1159 const struct lp_build_tgsi_action * action,
1160 struct lp_build_tgsi_context * bld_base,
1161 struct lp_build_emit_data * emit_data)
1162 {
1163 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadNoneAttribute);
1164 }
1165
1166 static void build_tgsi_intrinsic_readonly(
1167 const struct lp_build_tgsi_action * action,
1168 struct lp_build_tgsi_context * bld_base,
1169 struct lp_build_emit_data * emit_data)
1170 {
1171 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadOnlyAttribute);
1172 }
1173
1174 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
1175 {
1176 struct lp_type type;
1177
1178 /* Initialize the gallivm object:
1179 * We are only using the module, context, and builder fields of this struct.
1180 * This should be enough for us to be able to pass our gallivm struct to the
1181 * helper functions in the gallivm module.
1182 */
1183 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
1184 memset(&ctx->soa, 0, sizeof(ctx->soa));
1185 ctx->gallivm.context = LLVMContextCreate();
1186 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
1187 ctx->gallivm.context);
1188 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
1189
1190 ctx->store_output_intr = "llvm.AMDGPU.store.output.";
1191 ctx->swizzle_intr = "llvm.AMDGPU.swizzle";
1192 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1193
1194 /* XXX: We need to revisit this.I think the correct way to do this is
1195 * to use length = 4 here and use the elem_bld for everything. */
1196 type.floating = TRUE;
1197 type.fixed = FALSE;
1198 type.sign = TRUE;
1199 type.norm = FALSE;
1200 type.width = 32;
1201 type.length = 1;
1202
1203 lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1204 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1205 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1206
1207 bld_base->soa = 1;
1208 bld_base->emit_store = emit_store;
1209 bld_base->emit_swizzle = emit_swizzle;
1210 bld_base->emit_declaration = emit_declaration;
1211 bld_base->emit_immediate = emit_immediate;
1212
1213 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch;
1214 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch;
1215 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch;
1216 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch;
1217 bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = fetch_system_value;
1218
1219 /* Allocate outputs */
1220 ctx->soa.outputs = ctx->outputs;
1221
1222 ctx->num_arrays = 0;
1223
1224 /* XXX: Is there a better way to initialize all this ? */
1225
1226 lp_set_default_actions(bld_base);
1227
1228 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
1229 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
1230 bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
1231 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1232 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1233 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1234 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
1235 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
1236 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1237 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
1238 bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
1239 bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
1240 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1241 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly;
1242 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
1243 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
1244 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
1245 bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
1246 bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
1247 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1248 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1249 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1250 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1251 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
1252 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_readonly;
1253 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
1254 bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
1255 bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
1256 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1257 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1258 bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
1259 bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp;
1260 bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp;
1261 bld_base->op_actions[TGSI_OPCODE_FSNE].emit = emit_fcmp;
1262 bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
1263 bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
1264 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1265 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1266 bld_base->op_actions[TGSI_OPCODE_UIF].emit = uif_emit;
1267 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1268 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
1269 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
1270 bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
1271 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1272 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1273 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1274 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1275 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1276 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1277 bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit;
1278 bld_base->op_actions[TGSI_OPCODE_KILL_IF].intr_name = "llvm.AMDGPU.kill";
1279 bld_base->op_actions[TGSI_OPCODE_KILL].emit = lp_build_tgsi_intrinsic;
1280 bld_base->op_actions[TGSI_OPCODE_KILL].intr_name = "llvm.AMDGPU.kilp";
1281 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_readonly;
1282 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
1283 bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
1284 bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
1285 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1286 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1287 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1288 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly;
1289 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
1290 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1291 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
1292 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
1293 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
1294 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1295 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
1296 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
1297 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
1298 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
1299 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly;
1300 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
1301 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1302 bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
1303 bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
1304 bld_base->op_actions[TGSI_OPCODE_TEX2].fetch_args = tex_fetch_args;
1305 bld_base->op_actions[TGSI_OPCODE_TEX2].intr_name = "llvm.AMDGPU.tex";
1306 bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
1307 bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
1308 bld_base->op_actions[TGSI_OPCODE_TXB2].fetch_args = tex_fetch_args;
1309 bld_base->op_actions[TGSI_OPCODE_TXB2].intr_name = "llvm.AMDGPU.txb";
1310 bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
1311 bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
1312 bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
1313 bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
1314 bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
1315 bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
1316 bld_base->op_actions[TGSI_OPCODE_TXL2].fetch_args = tex_fetch_args;
1317 bld_base->op_actions[TGSI_OPCODE_TXL2].intr_name = "llvm.AMDGPU.txl";
1318 bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
1319 bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
1320 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
1321 bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
1322 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1323 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
1324 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1325 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1326 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
1327 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
1328 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
1329 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
1330 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1331 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1332 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1333 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1334 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1335 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1336 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1337 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1338 bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
1339
1340 bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
1341 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
1342 }
1343
1344 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
1345 LLVMTypeRef *ParamTypes, unsigned ParamCount)
1346 {
1347 LLVMTypeRef main_fn_type;
1348 LLVMBasicBlockRef main_fn_body;
1349
1350 /* Setup the function */
1351 main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context),
1352 ParamTypes, ParamCount, 0);
1353 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1354 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1355 ctx->main_fn, "main_body");
1356 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1357 }
1358
1359 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1360 {
1361 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1362 /* End the main function with Return*/
1363 LLVMBuildRetVoid(gallivm->builder);
1364
1365 /* Create the pass manager */
1366 ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule(
1367 gallivm->module);
1368
1369 /* This pass should eliminate all the load and store instructions */
1370 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1371
1372 /* Add some optimization passes */
1373 LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1374 LLVMAddLICMPass(gallivm->passmgr);
1375 LLVMAddAggressiveDCEPass(gallivm->passmgr);
1376 LLVMAddCFGSimplificationPass(gallivm->passmgr);
1377
1378 /* Run the passs */
1379 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1380
1381 LLVMDisposeBuilder(gallivm->builder);
1382 LLVMDisposePassManager(gallivm->passmgr);
1383
1384 }
1385
1386 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1387 {
1388 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1389 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1390 }