2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
26 #include "radeon_llvm.h"
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
43 static struct radeon_llvm_loop
* get_current_loop(struct radeon_llvm_context
* ctx
)
45 return ctx
->loop_depth
> 0 ? ctx
->loop
+ (ctx
->loop_depth
- 1) : NULL
;
48 static struct radeon_llvm_branch
* get_current_branch(
49 struct radeon_llvm_context
* ctx
)
51 return ctx
->branch_depth
> 0 ?
52 ctx
->branch
+ (ctx
->branch_depth
- 1) : NULL
;
55 unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
57 return (index
* 4) + chan
;
60 static LLVMValueRef
emit_swizzle(
61 struct lp_build_tgsi_context
* bld_base
,
68 LLVMValueRef swizzles
[4];
70 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
);
72 swizzles
[0] = LLVMConstInt(i32t
, swizzle_x
, 0);
73 swizzles
[1] = LLVMConstInt(i32t
, swizzle_y
, 0);
74 swizzles
[2] = LLVMConstInt(i32t
, swizzle_z
, 0);
75 swizzles
[3] = LLVMConstInt(i32t
, swizzle_w
, 0);
77 return LLVMBuildShuffleVector(bld_base
->base
.gallivm
->builder
,
79 LLVMGetUndef(LLVMTypeOf(value
)),
80 LLVMConstVector(swizzles
, 4), "");
85 struct lp_build_tgsi_soa_context
*bld
,
86 const struct tgsi_full_src_register
*reg
,
89 struct gallivm_state
* gallivm
= bld
->bld_base
.base
.gallivm
;
91 LLVMValueRef addr
= LLVMBuildLoad(gallivm
->builder
,
92 bld
->addr
[reg
->Indirect
.Index
][swizzle
], "");
93 LLVMValueRef offset
= lp_build_const_int32(gallivm
, reg
->Register
.Index
);
94 LLVMValueRef hw_index
= LLVMBuildAdd(gallivm
->builder
, addr
, offset
, "");
95 LLVMValueRef soa_index
= LLVMBuildMul(gallivm
->builder
, hw_index
,
96 lp_build_const_int32(gallivm
, 4), "");
97 LLVMValueRef array_index
= LLVMBuildAdd(gallivm
->builder
, soa_index
,
98 lp_build_const_int32(gallivm
, swizzle
), "");
104 emit_fetch_immediate(
105 struct lp_build_tgsi_context
*bld_base
,
106 const struct tgsi_full_src_register
*reg
,
107 enum tgsi_opcode_type type
,
111 LLVMContextRef ctx
= bld_base
->base
.gallivm
->context
;
114 case TGSI_TYPE_UNSIGNED
:
115 case TGSI_TYPE_SIGNED
:
116 ctype
= LLVMInt32TypeInContext(ctx
);
118 case TGSI_TYPE_UNTYPED
:
119 case TGSI_TYPE_FLOAT
:
120 ctype
= LLVMFloatTypeInContext(ctx
);
127 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
129 LLVMValueRef values
[TGSI_NUM_CHANNELS
] = {};
131 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
132 values
[chan
] = LLVMConstBitCast(bld
->immediates
[reg
->Register
.Index
][chan
], ctype
);
134 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
137 return LLVMConstBitCast(bld
->immediates
[reg
->Register
.Index
][swizzle
], ctype
);
143 struct lp_build_tgsi_context
*bld_base
,
144 const struct tgsi_full_src_register
*reg
,
145 enum tgsi_opcode_type type
,
148 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
150 LLVMValueRef values
[TGSI_NUM_CHANNELS
] = {};
152 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
153 values
[chan
] = ctx
->inputs
[radeon_llvm_reg_index_soa(
154 reg
->Register
.Index
, chan
)];
156 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
159 return bitcast(bld_base
, type
, ctx
->inputs
[radeon_llvm_reg_index_soa(reg
->Register
.Index
, swizzle
)]);
164 emit_fetch_temporary(
165 struct lp_build_tgsi_context
*bld_base
,
166 const struct tgsi_full_src_register
*reg
,
167 enum tgsi_opcode_type type
,
170 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
171 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
173 LLVMValueRef values
[TGSI_NUM_CHANNELS
] = {};
175 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
176 values
[chan
] = emit_fetch_temporary(bld_base
, reg
, type
, chan
);
178 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
182 if (reg
->Register
.Indirect
) {
183 LLVMValueRef array_index
= emit_array_index(bld
, reg
, swizzle
);
184 LLVMValueRef ptr
= LLVMBuildGEP(builder
, bld
->temps_array
, &array_index
,
186 return LLVMBuildLoad(builder
, ptr
, "");
188 LLVMValueRef temp_ptr
;
189 temp_ptr
= lp_get_temp_ptr_soa(bld
, reg
->Register
.Index
, swizzle
);
190 return bitcast(bld_base
,type
,LLVMBuildLoad(builder
, temp_ptr
, ""));
196 struct lp_build_tgsi_context
*bld_base
,
197 const struct tgsi_full_src_register
*reg
,
198 enum tgsi_opcode_type type
,
201 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
202 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
203 if (reg
->Register
.Indirect
) {
204 LLVMValueRef array_index
= emit_array_index(bld
, reg
, swizzle
);
205 LLVMValueRef ptr
= LLVMBuildGEP(builder
, bld
->outputs_array
, &array_index
,
207 return LLVMBuildLoad(builder
, ptr
, "");
209 LLVMValueRef temp_ptr
;
210 temp_ptr
= lp_get_output_ptr(bld
, reg
->Register
.Index
, swizzle
);
211 return LLVMBuildLoad(builder
, temp_ptr
, "");
215 static void emit_declaration(
216 struct lp_build_tgsi_context
* bld_base
,
217 const struct tgsi_full_declaration
*decl
)
219 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
220 switch(decl
->Declaration
.File
) {
221 case TGSI_FILE_ADDRESS
:
224 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
226 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
227 ctx
->soa
.addr
[idx
][chan
] = lp_build_alloca(
229 ctx
->soa
.bld_base
.uint_bld
.elem_type
, "");
235 case TGSI_FILE_TEMPORARY
:
236 lp_emit_declaration_soa(bld_base
, decl
);
239 case TGSI_FILE_INPUT
:
242 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
243 ctx
->load_input(ctx
, idx
, decl
);
248 case TGSI_FILE_SYSTEM_VALUE
:
251 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
252 ctx
->load_system_value(ctx
, idx
, decl
);
257 case TGSI_FILE_OUTPUT
:
260 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
262 assert(idx
< RADEON_LLVM_MAX_OUTPUTS
);
263 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
264 ctx
->soa
.outputs
[idx
][chan
] = lp_build_alloca(&ctx
->gallivm
,
265 ctx
->soa
.bld_base
.base
.elem_type
, "");
269 ctx
->output_reg_count
= MAX2(ctx
->output_reg_count
,
270 decl
->Range
.Last
+ 1);
281 struct lp_build_tgsi_context
* bld_base
,
282 const struct tgsi_full_instruction
* inst
,
283 const struct tgsi_opcode_info
* info
,
286 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
287 struct gallivm_state
*gallivm
= bld
->bld_base
.base
.gallivm
;
288 struct lp_build_context base
= bld
->bld_base
.base
;
289 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[0];
290 LLVMBuilderRef builder
= bld
->bld_base
.base
.gallivm
->builder
;
291 LLVMValueRef temp_ptr
;
292 unsigned chan
, chan_index
;
293 boolean is_vec_store
= FALSE
;
295 LLVMTypeKind k
= LLVMGetTypeKind(LLVMTypeOf(dst
[0]));
296 is_vec_store
= (k
== LLVMVectorTypeKind
);
300 LLVMValueRef values
[4] = {};
301 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst
, chan
) {
302 LLVMValueRef index
= lp_build_const_int32(gallivm
, chan
);
303 values
[chan
] = LLVMBuildExtractElement(gallivm
->builder
,
306 bld_base
->emit_store(bld_base
, inst
, info
, values
);
310 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst
, chan_index
) {
311 LLVMValueRef value
= dst
[chan_index
];
313 if (inst
->Instruction
.Saturate
!= TGSI_SAT_NONE
) {
314 struct lp_build_emit_data clamp_emit_data
;
316 memset(&clamp_emit_data
, 0, sizeof(clamp_emit_data
));
317 clamp_emit_data
.arg_count
= 3;
318 clamp_emit_data
.args
[0] = value
;
319 clamp_emit_data
.args
[2] = base
.one
;
321 switch(inst
->Instruction
.Saturate
) {
322 case TGSI_SAT_ZERO_ONE
:
323 clamp_emit_data
.args
[1] = base
.zero
;
325 case TGSI_SAT_MINUS_PLUS_ONE
:
326 clamp_emit_data
.args
[1] = LLVMConstReal(
327 base
.elem_type
, -1.0f
);
332 value
= lp_build_emit_llvm(bld_base
, TGSI_OPCODE_CLAMP
,
336 switch(reg
->Register
.File
) {
337 case TGSI_FILE_ADDRESS
:
338 temp_ptr
= bld
->addr
[reg
->Register
.Index
][chan_index
];
339 LLVMBuildStore(builder
, value
, temp_ptr
);
341 case TGSI_FILE_OUTPUT
:
342 temp_ptr
= bld
->outputs
[reg
->Register
.Index
][chan_index
];
345 case TGSI_FILE_TEMPORARY
:
346 temp_ptr
= lp_get_temp_ptr_soa(bld
, reg
->Register
.Index
, chan_index
);
353 value
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, value
);
355 LLVMBuildStore(builder
, value
, temp_ptr
);
359 static void bgnloop_emit(
360 const struct lp_build_tgsi_action
* action
,
361 struct lp_build_tgsi_context
* bld_base
,
362 struct lp_build_emit_data
* emit_data
)
364 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
365 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
366 LLVMBasicBlockRef loop_block
;
367 LLVMBasicBlockRef endloop_block
;
368 endloop_block
= LLVMAppendBasicBlockInContext(gallivm
->context
,
369 ctx
->main_fn
, "ENDLOOP");
370 loop_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
371 endloop_block
, "LOOP");
372 LLVMBuildBr(gallivm
->builder
, loop_block
);
373 LLVMPositionBuilderAtEnd(gallivm
->builder
, loop_block
);
375 ctx
->loop
[ctx
->loop_depth
- 1].loop_block
= loop_block
;
376 ctx
->loop
[ctx
->loop_depth
- 1].endloop_block
= endloop_block
;
379 static void brk_emit(
380 const struct lp_build_tgsi_action
* action
,
381 struct lp_build_tgsi_context
* bld_base
,
382 struct lp_build_emit_data
* emit_data
)
384 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
385 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
386 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
388 LLVMBuildBr(gallivm
->builder
, current_loop
->endloop_block
);
391 static void cont_emit(
392 const struct lp_build_tgsi_action
* action
,
393 struct lp_build_tgsi_context
* bld_base
,
394 struct lp_build_emit_data
* emit_data
)
396 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
397 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
398 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
400 LLVMBuildBr(gallivm
->builder
, current_loop
->loop_block
);
403 static void else_emit(
404 const struct lp_build_tgsi_action
* action
,
405 struct lp_build_tgsi_context
* bld_base
,
406 struct lp_build_emit_data
* emit_data
)
408 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
409 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
410 struct radeon_llvm_branch
* current_branch
= get_current_branch(ctx
);
411 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(gallivm
->builder
);
413 /* We need to add a terminator to the current block if the previous
414 * instruction was an ENDIF.Example:
427 if (current_block
!= current_branch
->if_block
) {
428 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
430 if (!LLVMGetBasicBlockTerminator(current_branch
->if_block
)) {
431 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
433 current_branch
->has_else
= 1;
434 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->else_block
);
437 static void endif_emit(
438 const struct lp_build_tgsi_action
* action
,
439 struct lp_build_tgsi_context
* bld_base
,
440 struct lp_build_emit_data
* emit_data
)
442 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
443 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
444 struct radeon_llvm_branch
* current_branch
= get_current_branch(ctx
);
445 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(gallivm
->builder
);
447 /* If we have consecutive ENDIF instructions, then the first ENDIF
448 * will not have a terminator, so we need to add one. */
449 if (current_block
!= current_branch
->if_block
450 && current_block
!= current_branch
->else_block
451 && !LLVMGetBasicBlockTerminator(current_block
)) {
453 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
455 if (!LLVMGetBasicBlockTerminator(current_branch
->else_block
)) {
456 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->else_block
);
457 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
460 if (!LLVMGetBasicBlockTerminator(current_branch
->if_block
)) {
461 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->if_block
);
462 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
465 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->endif_block
);
469 static void endloop_emit(
470 const struct lp_build_tgsi_action
* action
,
471 struct lp_build_tgsi_context
* bld_base
,
472 struct lp_build_emit_data
* emit_data
)
474 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
475 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
476 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
478 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm
->builder
))) {
479 LLVMBuildBr(gallivm
->builder
, current_loop
->loop_block
);
482 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_loop
->endloop_block
);
487 const struct lp_build_tgsi_action
* action
,
488 struct lp_build_tgsi_context
* bld_base
,
489 struct lp_build_emit_data
* emit_data
)
491 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
492 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
494 LLVMBasicBlockRef if_block
, else_block
, endif_block
;
496 cond
= LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
497 bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, emit_data
->args
[0]),
498 bld_base
->int_bld
.zero
, "");
500 endif_block
= LLVMAppendBasicBlockInContext(gallivm
->context
,
501 ctx
->main_fn
, "ENDIF");
502 if_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
504 else_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
505 endif_block
, "ELSE");
506 LLVMBuildCondBr(gallivm
->builder
, cond
, if_block
, else_block
);
507 LLVMPositionBuilderAtEnd(gallivm
->builder
, if_block
);
510 ctx
->branch
[ctx
->branch_depth
- 1].endif_block
= endif_block
;
511 ctx
->branch
[ctx
->branch_depth
- 1].if_block
= if_block
;
512 ctx
->branch
[ctx
->branch_depth
- 1].else_block
= else_block
;
513 ctx
->branch
[ctx
->branch_depth
- 1].has_else
= 0;
516 static void kil_emit(
517 const struct lp_build_tgsi_action
* action
,
518 struct lp_build_tgsi_context
* bld_base
,
519 struct lp_build_emit_data
* emit_data
)
522 for (i
= 0; i
< emit_data
->arg_count
; i
++) {
523 emit_data
->output
[i
] = lp_build_intrinsic_unary(
524 bld_base
->base
.gallivm
->builder
,
526 emit_data
->dst_type
, emit_data
->args
[i
]);
530 /* coord_arg - index of the source coord vector in the emit_data->args array */
531 void radeon_llvm_emit_prepare_cube_coords(
532 struct lp_build_tgsi_context
* bld_base
,
533 struct lp_build_emit_data
* emit_data
,
537 unsigned target
= emit_data
->inst
->Texture
.Texture
;
538 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
539 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
540 LLVMBuilderRef builder
= gallivm
->builder
;
541 LLVMTypeRef type
= bld_base
->base
.elem_type
;
542 LLVMValueRef coords
[4];
543 LLVMValueRef mad_args
[3];
547 LLVMValueRef v
= build_intrinsic(builder
, "llvm.AMDGPU.cube",
548 LLVMVectorType(type
, 4),
549 &emit_data
->args
[coord_arg
], 1, LLVMReadNoneAttribute
);
551 for (i
= 0; i
< 4; ++i
) {
552 idx
= lp_build_const_int32(gallivm
, i
);
553 coords
[i
] = LLVMBuildExtractElement(builder
, v
, idx
, "");
556 coords
[2] = build_intrinsic(builder
, "fabs",
557 type
, &coords
[2], 1, LLVMReadNoneAttribute
);
558 coords
[2] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_RCP
, coords
[2]);
560 mad_args
[1] = coords
[2];
561 mad_args
[2] = LLVMConstReal(type
, 1.5);
563 mad_args
[0] = coords
[0];
564 coords
[0] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
565 mad_args
[0], mad_args
[1], mad_args
[2]);
567 mad_args
[0] = coords
[1];
568 coords
[1] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
569 mad_args
[0], mad_args
[1], mad_args
[2]);
571 /* apply xyz = yxw swizzle to cooords */
572 coords
[2] = coords
[3];
573 coords
[3] = coords
[1];
574 coords
[1] = coords
[0];
575 coords
[0] = coords
[3];
577 /* all cases except simple cube map sampling require special handling
578 * for coord vector */
579 if (target
!= TGSI_TEXTURE_CUBE
||
580 opcode
!= TGSI_OPCODE_TEX
) {
582 /* load source coord.w component - array_index for cube arrays or
583 * compare value for SHADOWCUBE */
584 idx
= lp_build_const_int32(gallivm
, 3);
585 coords
[3] = LLVMBuildExtractElement(builder
,
586 emit_data
->args
[coord_arg
], idx
, "");
588 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
589 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
590 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
592 coords
[2] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
593 coords
[3], lp_build_const_float(gallivm
, 8.0), coords
[2]);
596 /* for instructions that need additional src (compare/lod/bias),
597 * put it in coord.w */
598 if (opcode
== TGSI_OPCODE_TEX2
||
599 opcode
== TGSI_OPCODE_TXB2
||
600 opcode
== TGSI_OPCODE_TXL2
) {
601 coords
[3] = emit_data
->args
[coord_arg
+ 1];
605 emit_data
->args
[coord_arg
] =
606 lp_build_gather_values(bld_base
->base
.gallivm
, coords
, 4);
609 static void txd_fetch_args(
610 struct lp_build_tgsi_context
* bld_base
,
611 struct lp_build_emit_data
* emit_data
)
613 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
615 LLVMValueRef coords
[4];
617 for (src
= 0; src
< 3; src
++) {
618 for (chan
= 0; chan
< 4; chan
++)
619 coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
621 emit_data
->args
[src
] = lp_build_gather_values(bld_base
->base
.gallivm
,
624 emit_data
->arg_count
= 3;
625 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
629 static void txp_fetch_args(
630 struct lp_build_tgsi_context
* bld_base
,
631 struct lp_build_emit_data
* emit_data
)
633 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
636 LLVMValueRef coords
[4];
638 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
639 src_w
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
641 for (chan
= 0; chan
< 3; chan
++ ) {
642 LLVMValueRef arg
= lp_build_emit_fetch(bld_base
,
643 emit_data
->inst
, 0, chan
);
644 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
645 TGSI_OPCODE_DIV
, arg
, src_w
);
647 coords
[3] = bld_base
->base
.one
;
648 emit_data
->args
[0] = lp_build_gather_values(bld_base
->base
.gallivm
,
650 emit_data
->arg_count
= 1;
652 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
653 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
654 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
655 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
656 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
657 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
658 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, 0);
662 static void tex_fetch_args(
663 struct lp_build_tgsi_context
* bld_base
,
664 struct lp_build_emit_data
* emit_data
)
666 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
667 * when we used CHAN_ALL. We should be able to get this to work,
668 * but for now we will swizzle it ourselves
669 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
674 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
676 LLVMValueRef coords
[4];
678 for (chan
= 0; chan
< 4; chan
++) {
679 coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 0, chan
);
682 emit_data
->arg_count
= 1;
683 emit_data
->args
[0] = lp_build_gather_values(bld_base
->base
.gallivm
,
685 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
687 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
688 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
689 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
690 /* These instructions have additional operand that should be packed
691 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
692 * That operand should be passed as a float value in the args array
693 * right after the coord vector. After packing it's not used anymore,
694 * that's why arg_count is not increased */
695 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
698 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
699 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
700 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
701 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
702 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
703 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
704 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, 0);
708 static void txf_fetch_args(
709 struct lp_build_tgsi_context
* bld_base
,
710 struct lp_build_emit_data
* emit_data
)
712 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
713 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
714 const struct tgsi_texture_offset
* off
= inst
->TexOffsets
;
715 LLVMTypeRef offset_type
= bld_base
->int_bld
.elem_type
;
717 /* fetch tex coords */
718 tex_fetch_args(bld_base
, emit_data
);
720 /* fetch tex offsets */
721 if (inst
->Texture
.NumOffsets
) {
722 assert(inst
->Texture
.NumOffsets
== 1);
724 emit_data
->args
[1] = LLVMConstBitCast(
725 bld
->immediates
[off
->Index
][off
->SwizzleX
],
727 emit_data
->args
[2] = LLVMConstBitCast(
728 bld
->immediates
[off
->Index
][off
->SwizzleY
],
730 emit_data
->args
[3] = LLVMConstBitCast(
731 bld
->immediates
[off
->Index
][off
->SwizzleZ
],
734 emit_data
->args
[1] = bld_base
->int_bld
.zero
;
735 emit_data
->args
[2] = bld_base
->int_bld
.zero
;
736 emit_data
->args
[3] = bld_base
->int_bld
.zero
;
739 emit_data
->arg_count
= 4;
742 static void emit_icmp(
743 const struct lp_build_tgsi_action
* action
,
744 struct lp_build_tgsi_context
* bld_base
,
745 struct lp_build_emit_data
* emit_data
)
748 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
749 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
751 switch (emit_data
->inst
->Instruction
.Opcode
) {
752 case TGSI_OPCODE_USEQ
: pred
= LLVMIntEQ
; break;
753 case TGSI_OPCODE_USNE
: pred
= LLVMIntNE
; break;
754 case TGSI_OPCODE_USGE
: pred
= LLVMIntUGE
; break;
755 case TGSI_OPCODE_USLT
: pred
= LLVMIntULT
; break;
756 case TGSI_OPCODE_ISGE
: pred
= LLVMIntSGE
; break;
757 case TGSI_OPCODE_ISLT
: pred
= LLVMIntSLT
; break;
759 assert(!"unknown instruction");
762 LLVMValueRef v
= LLVMBuildICmp(builder
, pred
,
763 emit_data
->args
[0], emit_data
->args
[1],"");
765 v
= LLVMBuildSExtOrBitCast(builder
, v
,
766 LLVMInt32TypeInContext(context
), "");
768 emit_data
->output
[emit_data
->chan
] = v
;
771 static void emit_cmp(
772 const struct lp_build_tgsi_action
*action
,
773 struct lp_build_tgsi_context
* bld_base
,
774 struct lp_build_emit_data
* emit_data
)
776 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
777 LLVMRealPredicate pred
;
780 /* XXX I'm not sure whether to do unordered or ordered comparisons,
781 * but llvmpipe uses unordered comparisons, so for consistency we use
782 * unordered. (The authors of llvmpipe aren't sure about using
783 * unordered vs ordered comparisons either.
785 switch (emit_data
->inst
->Instruction
.Opcode
) {
786 case TGSI_OPCODE_SGE
: pred
= LLVMRealUGE
; break;
787 case TGSI_OPCODE_SEQ
: pred
= LLVMRealUEQ
; break;
788 case TGSI_OPCODE_SLE
: pred
= LLVMRealULE
; break;
789 case TGSI_OPCODE_SLT
: pred
= LLVMRealULT
; break;
790 case TGSI_OPCODE_SNE
: pred
= LLVMRealUNE
; break;
791 case TGSI_OPCODE_SGT
: pred
= LLVMRealUGT
; break;
792 default: assert(!"unknown instruction");
795 cond
= LLVMBuildFCmp(builder
,
796 pred
, emit_data
->args
[0], emit_data
->args
[1], "");
798 emit_data
->output
[emit_data
->chan
] = LLVMBuildSelect(builder
,
799 cond
, bld_base
->base
.one
, bld_base
->base
.zero
, "");
802 static void emit_not(
803 const struct lp_build_tgsi_action
* action
,
804 struct lp_build_tgsi_context
* bld_base
,
805 struct lp_build_emit_data
* emit_data
)
807 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
808 LLVMValueRef v
= bitcast(bld_base
, TGSI_TYPE_UNSIGNED
,
810 emit_data
->output
[emit_data
->chan
] = LLVMBuildNot(builder
, v
, "");
813 static void emit_arl(
814 const struct lp_build_tgsi_action
* action
,
815 struct lp_build_tgsi_context
* bld_base
,
816 struct lp_build_emit_data
* emit_data
)
818 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
819 LLVMValueRef floor_index
= lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_FLR
, emit_data
->args
[0]);
820 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToSI(builder
,
821 floor_index
, bld_base
->base
.int_elem_type
, "");
824 static void emit_and(
825 const struct lp_build_tgsi_action
* action
,
826 struct lp_build_tgsi_context
* bld_base
,
827 struct lp_build_emit_data
* emit_data
)
829 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
830 emit_data
->output
[emit_data
->chan
] = LLVMBuildAnd(builder
,
831 emit_data
->args
[0], emit_data
->args
[1], "");
835 const struct lp_build_tgsi_action
* action
,
836 struct lp_build_tgsi_context
* bld_base
,
837 struct lp_build_emit_data
* emit_data
)
839 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
840 emit_data
->output
[emit_data
->chan
] = LLVMBuildOr(builder
,
841 emit_data
->args
[0], emit_data
->args
[1], "");
844 static void emit_uadd(
845 const struct lp_build_tgsi_action
* action
,
846 struct lp_build_tgsi_context
* bld_base
,
847 struct lp_build_emit_data
* emit_data
)
849 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
850 emit_data
->output
[emit_data
->chan
] = LLVMBuildAdd(builder
,
851 emit_data
->args
[0], emit_data
->args
[1], "");
854 static void emit_udiv(
855 const struct lp_build_tgsi_action
* action
,
856 struct lp_build_tgsi_context
* bld_base
,
857 struct lp_build_emit_data
* emit_data
)
859 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
860 emit_data
->output
[emit_data
->chan
] = LLVMBuildUDiv(builder
,
861 emit_data
->args
[0], emit_data
->args
[1], "");
864 static void emit_idiv(
865 const struct lp_build_tgsi_action
* action
,
866 struct lp_build_tgsi_context
* bld_base
,
867 struct lp_build_emit_data
* emit_data
)
869 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
870 emit_data
->output
[emit_data
->chan
] = LLVMBuildSDiv(builder
,
871 emit_data
->args
[0], emit_data
->args
[1], "");
874 static void emit_mod(
875 const struct lp_build_tgsi_action
* action
,
876 struct lp_build_tgsi_context
* bld_base
,
877 struct lp_build_emit_data
* emit_data
)
879 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
880 emit_data
->output
[emit_data
->chan
] = LLVMBuildSRem(builder
,
881 emit_data
->args
[0], emit_data
->args
[1], "");
884 static void emit_umod(
885 const struct lp_build_tgsi_action
* action
,
886 struct lp_build_tgsi_context
* bld_base
,
887 struct lp_build_emit_data
* emit_data
)
889 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
890 emit_data
->output
[emit_data
->chan
] = LLVMBuildURem(builder
,
891 emit_data
->args
[0], emit_data
->args
[1], "");
894 static void emit_shl(
895 const struct lp_build_tgsi_action
* action
,
896 struct lp_build_tgsi_context
* bld_base
,
897 struct lp_build_emit_data
* emit_data
)
899 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
900 emit_data
->output
[emit_data
->chan
] = LLVMBuildShl(builder
,
901 emit_data
->args
[0], emit_data
->args
[1], "");
904 static void emit_ushr(
905 const struct lp_build_tgsi_action
* action
,
906 struct lp_build_tgsi_context
* bld_base
,
907 struct lp_build_emit_data
* emit_data
)
909 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
910 emit_data
->output
[emit_data
->chan
] = LLVMBuildLShr(builder
,
911 emit_data
->args
[0], emit_data
->args
[1], "");
913 static void emit_ishr(
914 const struct lp_build_tgsi_action
* action
,
915 struct lp_build_tgsi_context
* bld_base
,
916 struct lp_build_emit_data
* emit_data
)
918 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
919 emit_data
->output
[emit_data
->chan
] = LLVMBuildAShr(builder
,
920 emit_data
->args
[0], emit_data
->args
[1], "");
923 static void emit_xor(
924 const struct lp_build_tgsi_action
* action
,
925 struct lp_build_tgsi_context
* bld_base
,
926 struct lp_build_emit_data
* emit_data
)
928 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
929 emit_data
->output
[emit_data
->chan
] = LLVMBuildXor(builder
,
930 emit_data
->args
[0], emit_data
->args
[1], "");
933 static void emit_ssg(
934 const struct lp_build_tgsi_action
* action
,
935 struct lp_build_tgsi_context
* bld_base
,
936 struct lp_build_emit_data
* emit_data
)
938 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
940 LLVMValueRef cmp
, val
;
942 if (emit_data
->inst
->Instruction
.Opcode
== TGSI_OPCODE_ISSG
) {
943 cmp
= LLVMBuildICmp(builder
, LLVMIntSGT
, emit_data
->args
[0], bld_base
->int_bld
.zero
, "");
944 val
= LLVMBuildSelect(builder
, cmp
, bld_base
->int_bld
.one
, emit_data
->args
[0], "");
945 cmp
= LLVMBuildICmp(builder
, LLVMIntSGE
, val
, bld_base
->int_bld
.zero
, "");
946 val
= LLVMBuildSelect(builder
, cmp
, val
, LLVMConstInt(bld_base
->int_bld
.elem_type
, -1, true), "");
947 } else { // float SSG
948 cmp
= LLVMBuildFCmp(builder
, LLVMRealUGT
, emit_data
->args
[0], bld_base
->base
.zero
, "");
949 val
= LLVMBuildSelect(builder
, cmp
, bld_base
->base
.one
, emit_data
->args
[0], "");
950 cmp
= LLVMBuildFCmp(builder
, LLVMRealUGE
, val
, bld_base
->base
.zero
, "");
951 val
= LLVMBuildSelect(builder
, cmp
, val
, LLVMConstReal(bld_base
->base
.elem_type
, -1), "");
954 emit_data
->output
[emit_data
->chan
] = val
;
957 static void emit_ineg(
958 const struct lp_build_tgsi_action
* action
,
959 struct lp_build_tgsi_context
* bld_base
,
960 struct lp_build_emit_data
* emit_data
)
962 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
963 emit_data
->output
[emit_data
->chan
] = LLVMBuildNeg(builder
,
964 emit_data
->args
[0], "");
967 static void emit_f2i(
968 const struct lp_build_tgsi_action
* action
,
969 struct lp_build_tgsi_context
* bld_base
,
970 struct lp_build_emit_data
* emit_data
)
972 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
973 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToSI(builder
,
974 emit_data
->args
[0], bld_base
->int_bld
.elem_type
, "");
977 static void emit_f2u(
978 const struct lp_build_tgsi_action
* action
,
979 struct lp_build_tgsi_context
* bld_base
,
980 struct lp_build_emit_data
* emit_data
)
982 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
983 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToUI(builder
,
984 emit_data
->args
[0], bld_base
->uint_bld
.elem_type
, "");
987 static void emit_i2f(
988 const struct lp_build_tgsi_action
* action
,
989 struct lp_build_tgsi_context
* bld_base
,
990 struct lp_build_emit_data
* emit_data
)
992 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
993 emit_data
->output
[emit_data
->chan
] = LLVMBuildSIToFP(builder
,
994 emit_data
->args
[0], bld_base
->base
.elem_type
, "");
997 static void emit_u2f(
998 const struct lp_build_tgsi_action
* action
,
999 struct lp_build_tgsi_context
* bld_base
,
1000 struct lp_build_emit_data
* emit_data
)
1002 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1003 emit_data
->output
[emit_data
->chan
] = LLVMBuildUIToFP(builder
,
1004 emit_data
->args
[0], bld_base
->base
.elem_type
, "");
1007 static void emit_immediate(struct lp_build_tgsi_context
* bld_base
,
1008 const struct tgsi_full_immediate
*imm
)
1011 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
1013 for (i
= 0; i
< 4; ++i
) {
1014 ctx
->soa
.immediates
[ctx
->soa
.num_immediates
][i
] =
1015 LLVMConstInt(bld_base
->uint_bld
.elem_type
, imm
->u
[i
].Uint
, false );
1018 ctx
->soa
.num_immediates
++;
1022 build_intrinsic(LLVMBuilderRef builder
,
1024 LLVMTypeRef ret_type
,
1029 LLVMModuleRef module
= LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder
)));
1030 LLVMValueRef function
;
1032 function
= LLVMGetNamedFunction(module
, name
);
1034 LLVMTypeRef arg_types
[LP_MAX_FUNC_ARGS
];
1037 assert(num_args
<= LP_MAX_FUNC_ARGS
);
1039 for(i
= 0; i
< num_args
; ++i
) {
1041 arg_types
[i
] = LLVMTypeOf(args
[i
]);
1044 function
= lp_declare_intrinsic(module
, name
, ret_type
, arg_types
, num_args
);
1047 LLVMAddFunctionAttr(function
, attr
);
1050 return LLVMBuildCall(builder
, function
, args
, num_args
, "");
1053 static void build_tgsi_intrinsic(
1054 const struct lp_build_tgsi_action
* action
,
1055 struct lp_build_tgsi_context
* bld_base
,
1056 struct lp_build_emit_data
* emit_data
,
1059 struct lp_build_context
* base
= &bld_base
->base
;
1060 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1061 base
->gallivm
->builder
, action
->intr_name
,
1062 emit_data
->dst_type
, emit_data
->args
,
1063 emit_data
->arg_count
, attr
);
1066 build_tgsi_intrinsic_nomem(
1067 const struct lp_build_tgsi_action
* action
,
1068 struct lp_build_tgsi_context
* bld_base
,
1069 struct lp_build_emit_data
* emit_data
)
1071 build_tgsi_intrinsic(action
, bld_base
, emit_data
, LLVMReadNoneAttribute
);
1074 static void build_tgsi_intrinsic_readonly(
1075 const struct lp_build_tgsi_action
* action
,
1076 struct lp_build_tgsi_context
* bld_base
,
1077 struct lp_build_emit_data
* emit_data
)
1079 build_tgsi_intrinsic(action
, bld_base
, emit_data
, LLVMReadOnlyAttribute
);
1082 void radeon_llvm_context_init(struct radeon_llvm_context
* ctx
)
1084 struct lp_type type
;
1085 LLVMTypeRef main_fn_type
;
1086 LLVMBasicBlockRef main_fn_body
;
1088 /* Initialize the gallivm object:
1089 * We are only using the module, context, and builder fields of this struct.
1090 * This should be enough for us to be able to pass our gallivm struct to the
1091 * helper functions in the gallivm module.
1093 memset(&ctx
->gallivm
, 0, sizeof (ctx
->gallivm
));
1094 memset(&ctx
->soa
, 0, sizeof(ctx
->soa
));
1095 ctx
->gallivm
.context
= LLVMContextCreate();
1096 ctx
->gallivm
.module
= LLVMModuleCreateWithNameInContext("tgsi",
1097 ctx
->gallivm
.context
);
1098 ctx
->gallivm
.builder
= LLVMCreateBuilderInContext(ctx
->gallivm
.context
);
1100 /* Setup the module */
1101 main_fn_type
= LLVMFunctionType(LLVMVoidTypeInContext(ctx
->gallivm
.context
),
1103 ctx
->main_fn
= LLVMAddFunction(ctx
->gallivm
.module
, "main", main_fn_type
);
1104 main_fn_body
= LLVMAppendBasicBlockInContext(ctx
->gallivm
.context
,
1105 ctx
->main_fn
, "main_body");
1106 LLVMPositionBuilderAtEnd(ctx
->gallivm
.builder
, main_fn_body
);
1108 ctx
->store_output_intr
= "llvm.AMDGPU.store.output.";
1109 ctx
->swizzle_intr
= "llvm.AMDGPU.swizzle";
1110 struct lp_build_tgsi_context
* bld_base
= &ctx
->soa
.bld_base
;
1112 /* XXX: We need to revisit this.I think the correct way to do this is
1113 * to use length = 4 here and use the elem_bld for everything. */
1114 type
.floating
= TRUE
;
1119 lp_build_context_init(&bld_base
->base
, &ctx
->gallivm
, type
);
1120 lp_build_context_init(&ctx
->soa
.bld_base
.uint_bld
, &ctx
->gallivm
, lp_uint_type(type
));
1121 lp_build_context_init(&ctx
->soa
.bld_base
.int_bld
, &ctx
->gallivm
, lp_int_type(type
));
1124 bld_base
->emit_store
= emit_store
;
1125 bld_base
->emit_swizzle
= emit_swizzle
;
1126 bld_base
->emit_declaration
= emit_declaration
;
1127 bld_base
->emit_immediate
= emit_immediate
;
1129 bld_base
->emit_fetch_funcs
[TGSI_FILE_IMMEDIATE
] = emit_fetch_immediate
;
1130 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = emit_fetch_input
;
1131 bld_base
->emit_fetch_funcs
[TGSI_FILE_TEMPORARY
] = emit_fetch_temporary
;
1132 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = emit_fetch_output
;
1134 /* Allocate outputs */
1135 ctx
->soa
.outputs
= ctx
->outputs
;
1137 /* XXX: Is there a better way to initialize all this ? */
1139 lp_set_default_actions(bld_base
);
1141 bld_base
->op_actions
[TGSI_OPCODE_ABS
].emit
= build_tgsi_intrinsic_readonly
;
1142 bld_base
->op_actions
[TGSI_OPCODE_ABS
].intr_name
= "fabs";
1143 bld_base
->op_actions
[TGSI_OPCODE_ARL
].emit
= emit_arl
;
1144 bld_base
->op_actions
[TGSI_OPCODE_AND
].emit
= emit_and
;
1145 bld_base
->op_actions
[TGSI_OPCODE_BGNLOOP
].emit
= bgnloop_emit
;
1146 bld_base
->op_actions
[TGSI_OPCODE_BRK
].emit
= brk_emit
;
1147 bld_base
->op_actions
[TGSI_OPCODE_CEIL
].emit
= build_tgsi_intrinsic_readonly
;
1148 bld_base
->op_actions
[TGSI_OPCODE_CEIL
].intr_name
= "ceil";
1149 bld_base
->op_actions
[TGSI_OPCODE_CLAMP
].emit
= build_tgsi_intrinsic_nomem
;
1150 bld_base
->op_actions
[TGSI_OPCODE_CLAMP
].intr_name
= "llvm.AMDIL.clamp.";
1151 bld_base
->op_actions
[TGSI_OPCODE_CMP
].emit
= build_tgsi_intrinsic_nomem
;
1152 bld_base
->op_actions
[TGSI_OPCODE_CMP
].intr_name
= "llvm.AMDGPU.cndlt";
1153 bld_base
->op_actions
[TGSI_OPCODE_CONT
].emit
= cont_emit
;
1154 bld_base
->op_actions
[TGSI_OPCODE_COS
].emit
= build_tgsi_intrinsic_readonly
;
1155 bld_base
->op_actions
[TGSI_OPCODE_COS
].intr_name
= "llvm.cos.f32";
1156 bld_base
->op_actions
[TGSI_OPCODE_DDX
].intr_name
= "llvm.AMDGPU.ddx";
1157 bld_base
->op_actions
[TGSI_OPCODE_DDX
].fetch_args
= tex_fetch_args
;
1158 bld_base
->op_actions
[TGSI_OPCODE_DDY
].intr_name
= "llvm.AMDGPU.ddy";
1159 bld_base
->op_actions
[TGSI_OPCODE_DDY
].fetch_args
= tex_fetch_args
;
1160 bld_base
->op_actions
[TGSI_OPCODE_ELSE
].emit
= else_emit
;
1161 bld_base
->op_actions
[TGSI_OPCODE_ENDIF
].emit
= endif_emit
;
1162 bld_base
->op_actions
[TGSI_OPCODE_ENDLOOP
].emit
= endloop_emit
;
1163 bld_base
->op_actions
[TGSI_OPCODE_EX2
].emit
= build_tgsi_intrinsic_nomem
;
1164 bld_base
->op_actions
[TGSI_OPCODE_EX2
].intr_name
= "llvm.AMDIL.exp.";
1165 bld_base
->op_actions
[TGSI_OPCODE_FLR
].emit
= build_tgsi_intrinsic_readonly
;
1166 bld_base
->op_actions
[TGSI_OPCODE_FLR
].intr_name
= "floor";
1167 bld_base
->op_actions
[TGSI_OPCODE_FRC
].emit
= build_tgsi_intrinsic_nomem
;
1168 bld_base
->op_actions
[TGSI_OPCODE_FRC
].intr_name
= "llvm.AMDIL.fraction.";
1169 bld_base
->op_actions
[TGSI_OPCODE_F2I
].emit
= emit_f2i
;
1170 bld_base
->op_actions
[TGSI_OPCODE_F2U
].emit
= emit_f2u
;
1171 bld_base
->op_actions
[TGSI_OPCODE_IABS
].emit
= build_tgsi_intrinsic_nomem
;
1172 bld_base
->op_actions
[TGSI_OPCODE_IABS
].intr_name
= "llvm.AMDIL.abs.";
1173 bld_base
->op_actions
[TGSI_OPCODE_IDIV
].emit
= emit_idiv
;
1174 bld_base
->op_actions
[TGSI_OPCODE_IF
].emit
= if_emit
;
1175 bld_base
->op_actions
[TGSI_OPCODE_IMAX
].emit
= build_tgsi_intrinsic_nomem
;
1176 bld_base
->op_actions
[TGSI_OPCODE_IMAX
].intr_name
= "llvm.AMDGPU.imax";
1177 bld_base
->op_actions
[TGSI_OPCODE_IMIN
].emit
= build_tgsi_intrinsic_nomem
;
1178 bld_base
->op_actions
[TGSI_OPCODE_IMIN
].intr_name
= "llvm.AMDGPU.imin";
1179 bld_base
->op_actions
[TGSI_OPCODE_INEG
].emit
= emit_ineg
;
1180 bld_base
->op_actions
[TGSI_OPCODE_ISHR
].emit
= emit_ishr
;
1181 bld_base
->op_actions
[TGSI_OPCODE_ISGE
].emit
= emit_icmp
;
1182 bld_base
->op_actions
[TGSI_OPCODE_ISLT
].emit
= emit_icmp
;
1183 bld_base
->op_actions
[TGSI_OPCODE_ISSG
].emit
= emit_ssg
;
1184 bld_base
->op_actions
[TGSI_OPCODE_I2F
].emit
= emit_i2f
;
1185 bld_base
->op_actions
[TGSI_OPCODE_KIL
].emit
= kil_emit
;
1186 bld_base
->op_actions
[TGSI_OPCODE_KIL
].intr_name
= "llvm.AMDGPU.kill";
1187 bld_base
->op_actions
[TGSI_OPCODE_KILP
].emit
= lp_build_tgsi_intrinsic
;
1188 bld_base
->op_actions
[TGSI_OPCODE_KILP
].intr_name
= "llvm.AMDGPU.kilp";
1189 bld_base
->op_actions
[TGSI_OPCODE_LG2
].emit
= build_tgsi_intrinsic_readonly
;
1190 bld_base
->op_actions
[TGSI_OPCODE_LG2
].intr_name
= "llvm.log2.f32";
1191 bld_base
->op_actions
[TGSI_OPCODE_LRP
].emit
= build_tgsi_intrinsic_nomem
;
1192 bld_base
->op_actions
[TGSI_OPCODE_LRP
].intr_name
= "llvm.AMDGPU.lrp";
1193 bld_base
->op_actions
[TGSI_OPCODE_MOD
].emit
= emit_mod
;
1194 bld_base
->op_actions
[TGSI_OPCODE_NOT
].emit
= emit_not
;
1195 bld_base
->op_actions
[TGSI_OPCODE_OR
].emit
= emit_or
;
1196 bld_base
->op_actions
[TGSI_OPCODE_POW
].emit
= build_tgsi_intrinsic_readonly
;
1197 bld_base
->op_actions
[TGSI_OPCODE_POW
].intr_name
= "llvm.pow.f32";
1198 bld_base
->op_actions
[TGSI_OPCODE_ROUND
].emit
= build_tgsi_intrinsic_nomem
;
1199 bld_base
->op_actions
[TGSI_OPCODE_ROUND
].intr_name
= "llvm.AMDIL.round.nearest.";
1200 bld_base
->op_actions
[TGSI_OPCODE_SGE
].emit
= emit_cmp
;
1201 bld_base
->op_actions
[TGSI_OPCODE_SEQ
].emit
= emit_cmp
;
1202 bld_base
->op_actions
[TGSI_OPCODE_SHL
].emit
= emit_shl
;
1203 bld_base
->op_actions
[TGSI_OPCODE_SLE
].emit
= emit_cmp
;
1204 bld_base
->op_actions
[TGSI_OPCODE_SLT
].emit
= emit_cmp
;
1205 bld_base
->op_actions
[TGSI_OPCODE_SNE
].emit
= emit_cmp
;
1206 bld_base
->op_actions
[TGSI_OPCODE_SGT
].emit
= emit_cmp
;
1207 bld_base
->op_actions
[TGSI_OPCODE_SIN
].emit
= build_tgsi_intrinsic_readonly
;
1208 bld_base
->op_actions
[TGSI_OPCODE_SIN
].intr_name
= "llvm.sin.f32";
1209 bld_base
->op_actions
[TGSI_OPCODE_SSG
].emit
= emit_ssg
;
1210 bld_base
->op_actions
[TGSI_OPCODE_TEX
].fetch_args
= tex_fetch_args
;
1211 bld_base
->op_actions
[TGSI_OPCODE_TEX
].intr_name
= "llvm.AMDGPU.tex";
1212 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].fetch_args
= tex_fetch_args
;
1213 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].intr_name
= "llvm.AMDGPU.tex";
1214 bld_base
->op_actions
[TGSI_OPCODE_TXB
].fetch_args
= tex_fetch_args
;
1215 bld_base
->op_actions
[TGSI_OPCODE_TXB
].intr_name
= "llvm.AMDGPU.txb";
1216 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].fetch_args
= tex_fetch_args
;
1217 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].intr_name
= "llvm.AMDGPU.txb";
1218 bld_base
->op_actions
[TGSI_OPCODE_TXD
].fetch_args
= txd_fetch_args
;
1219 bld_base
->op_actions
[TGSI_OPCODE_TXD
].intr_name
= "llvm.AMDGPU.txd";
1220 bld_base
->op_actions
[TGSI_OPCODE_TXF
].fetch_args
= txf_fetch_args
;
1221 bld_base
->op_actions
[TGSI_OPCODE_TXF
].intr_name
= "llvm.AMDGPU.txf";
1222 bld_base
->op_actions
[TGSI_OPCODE_TXL
].fetch_args
= tex_fetch_args
;
1223 bld_base
->op_actions
[TGSI_OPCODE_TXL
].intr_name
= "llvm.AMDGPU.txl";
1224 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].fetch_args
= tex_fetch_args
;
1225 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].intr_name
= "llvm.AMDGPU.txl";
1226 bld_base
->op_actions
[TGSI_OPCODE_TXP
].fetch_args
= txp_fetch_args
;
1227 bld_base
->op_actions
[TGSI_OPCODE_TXP
].intr_name
= "llvm.AMDGPU.tex";
1228 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= tex_fetch_args
;
1229 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].intr_name
= "llvm.AMDGPU.txq";
1230 bld_base
->op_actions
[TGSI_OPCODE_TRUNC
].emit
= build_tgsi_intrinsic_nomem
;
1231 bld_base
->op_actions
[TGSI_OPCODE_TRUNC
].intr_name
= "llvm.AMDGPU.trunc";
1232 bld_base
->op_actions
[TGSI_OPCODE_UADD
].emit
= emit_uadd
;
1233 bld_base
->op_actions
[TGSI_OPCODE_UDIV
].emit
= emit_udiv
;
1234 bld_base
->op_actions
[TGSI_OPCODE_UMAX
].emit
= build_tgsi_intrinsic_nomem
;
1235 bld_base
->op_actions
[TGSI_OPCODE_UMAX
].intr_name
= "llvm.AMDGPU.umax";
1236 bld_base
->op_actions
[TGSI_OPCODE_UMIN
].emit
= build_tgsi_intrinsic_nomem
;
1237 bld_base
->op_actions
[TGSI_OPCODE_UMIN
].intr_name
= "llvm.AMDGPU.umin";
1238 bld_base
->op_actions
[TGSI_OPCODE_UMOD
].emit
= emit_umod
;
1239 bld_base
->op_actions
[TGSI_OPCODE_USEQ
].emit
= emit_icmp
;
1240 bld_base
->op_actions
[TGSI_OPCODE_USGE
].emit
= emit_icmp
;
1241 bld_base
->op_actions
[TGSI_OPCODE_USHR
].emit
= emit_ushr
;
1242 bld_base
->op_actions
[TGSI_OPCODE_USLT
].emit
= emit_icmp
;
1243 bld_base
->op_actions
[TGSI_OPCODE_USNE
].emit
= emit_icmp
;
1244 bld_base
->op_actions
[TGSI_OPCODE_U2F
].emit
= emit_u2f
;
1245 bld_base
->op_actions
[TGSI_OPCODE_XOR
].emit
= emit_xor
;
1247 bld_base
->rsq_action
.emit
= build_tgsi_intrinsic_nomem
;
1248 bld_base
->rsq_action
.intr_name
= "llvm.AMDGPU.rsq";
1251 void radeon_llvm_finalize_module(struct radeon_llvm_context
* ctx
)
1253 struct gallivm_state
* gallivm
= ctx
->soa
.bld_base
.base
.gallivm
;
1254 /* End the main function with Return*/
1255 LLVMBuildRetVoid(gallivm
->builder
);
1257 /* Create the pass manager */
1258 ctx
->gallivm
.passmgr
= LLVMCreateFunctionPassManagerForModule(
1261 /* This pass should eliminate all the load and store instructions */
1262 LLVMAddPromoteMemoryToRegisterPass(gallivm
->passmgr
);
1264 /* Add some optimization passes */
1265 LLVMAddScalarReplAggregatesPass(gallivm
->passmgr
);
1266 LLVMAddCFGSimplificationPass(gallivm
->passmgr
);
1269 LLVMRunFunctionPassManager(gallivm
->passmgr
, ctx
->main_fn
);
1271 LLVMDisposeBuilder(gallivm
->builder
);
1272 LLVMDisposePassManager(gallivm
->passmgr
);
1276 void radeon_llvm_dispose(struct radeon_llvm_context
* ctx
)
1278 LLVMDisposeModule(ctx
->soa
.bld_base
.base
.gallivm
->module
);
1279 LLVMContextDispose(ctx
->soa
.bld_base
.base
.gallivm
->context
);