2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
26 #include "radeon_llvm.h"
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "gallivm/lp_bld_swizzle.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "util/u_math.h"
38 #include "util/u_memory.h"
39 #include "util/u_debug.h"
41 #include <llvm-c/Core.h>
42 #include <llvm-c/Transforms/Scalar.h>
44 static struct radeon_llvm_loop
* get_current_loop(struct radeon_llvm_context
* ctx
)
46 return ctx
->loop_depth
> 0 ? ctx
->loop
+ (ctx
->loop_depth
- 1) : NULL
;
49 static struct radeon_llvm_branch
* get_current_branch(
50 struct radeon_llvm_context
* ctx
)
52 return ctx
->branch_depth
> 0 ?
53 ctx
->branch
+ (ctx
->branch_depth
- 1) : NULL
;
56 unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
58 return (index
* 4) + chan
;
61 static LLVMValueRef
emit_swizzle(
62 struct lp_build_tgsi_context
* bld_base
,
69 LLVMValueRef swizzles
[4];
71 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
);
73 swizzles
[0] = LLVMConstInt(i32t
, swizzle_x
, 0);
74 swizzles
[1] = LLVMConstInt(i32t
, swizzle_y
, 0);
75 swizzles
[2] = LLVMConstInt(i32t
, swizzle_z
, 0);
76 swizzles
[3] = LLVMConstInt(i32t
, swizzle_w
, 0);
78 return LLVMBuildShuffleVector(bld_base
->base
.gallivm
->builder
,
80 LLVMGetUndef(LLVMTypeOf(value
)),
81 LLVMConstVector(swizzles
, 4), "");
84 static struct tgsi_declaration_range
85 get_array_range(struct lp_build_tgsi_context
*bld_base
,
86 unsigned File
, const struct tgsi_ind_register
*reg
)
88 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
90 if (File
!= TGSI_FILE_TEMPORARY
|| reg
->ArrayID
== 0 ||
91 reg
->ArrayID
> bld_base
->info
->array_max
[TGSI_FILE_TEMPORARY
]) {
92 struct tgsi_declaration_range range
;
94 range
.Last
= bld_base
->info
->file_max
[File
];
98 return ctx
->arrays
[reg
->ArrayID
- 1];
103 struct lp_build_tgsi_soa_context
*bld
,
104 const struct tgsi_ind_register
*reg
,
107 struct gallivm_state
* gallivm
= bld
->bld_base
.base
.gallivm
;
109 LLVMValueRef addr
= LLVMBuildLoad(gallivm
->builder
, bld
->addr
[reg
->Index
][reg
->Swizzle
], "");
110 return LLVMBuildAdd(gallivm
->builder
, addr
, lp_build_const_int32(gallivm
, offset
), "");
114 radeon_llvm_emit_fetch_double(
115 struct lp_build_tgsi_context
*bld_base
,
119 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
122 result
= LLVMGetUndef(LLVMVectorType(LLVMIntTypeInContext(bld_base
->base
.gallivm
->context
, 32), bld_base
->base
.type
.length
* 2));
124 result
= LLVMBuildInsertElement(builder
,
126 bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, ptr
),
127 bld_base
->int_bld
.zero
, "");
128 result
= LLVMBuildInsertElement(builder
,
130 bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, ptr2
),
131 bld_base
->int_bld
.one
, "");
132 return bitcast(bld_base
, TGSI_TYPE_DOUBLE
, result
);
137 struct lp_build_tgsi_context
*bld_base
,
138 unsigned File
, enum tgsi_opcode_type type
,
139 struct tgsi_declaration_range range
,
142 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
143 struct gallivm_state
* gallivm
= bld
->bld_base
.base
.gallivm
;
144 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
146 unsigned i
, size
= range
.Last
- range
.First
+ 1;
147 LLVMTypeRef vec
= LLVMVectorType(tgsi2llvmtype(bld_base
, type
), size
);
148 LLVMValueRef result
= LLVMGetUndef(vec
);
150 struct tgsi_full_src_register tmp_reg
= {};
151 tmp_reg
.Register
.File
= File
;
153 for (i
= 0; i
< size
; ++i
) {
154 tmp_reg
.Register
.Index
= i
+ range
.First
;
155 LLVMValueRef temp
= radeon_llvm_emit_fetch(bld_base
, &tmp_reg
, type
, swizzle
);
156 result
= LLVMBuildInsertElement(builder
, result
, temp
,
157 lp_build_const_int32(gallivm
, i
), "");
162 static bool uses_temp_indirect_addressing(
163 struct lp_build_tgsi_context
*bld_base
)
165 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
166 return (bld
->indirect_files
& (1 << TGSI_FILE_TEMPORARY
));
169 LLVMValueRef
radeon_llvm_emit_fetch(struct lp_build_tgsi_context
*bld_base
,
170 const struct tgsi_full_src_register
*reg
,
171 enum tgsi_opcode_type type
,
174 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
175 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
176 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
177 LLVMValueRef result
= NULL
, ptr
, ptr2
;
180 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
182 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
183 values
[chan
] = radeon_llvm_emit_fetch(bld_base
, reg
, type
, chan
);
185 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
189 if (reg
->Register
.Indirect
) {
190 struct tgsi_declaration_range range
= get_array_range(bld_base
,
191 reg
->Register
.File
, ®
->Indirect
);
192 return LLVMBuildExtractElement(builder
,
193 emit_array_fetch(bld_base
, reg
->Register
.File
, type
, range
, swizzle
),
194 emit_array_index(bld
, ®
->Indirect
, reg
->Register
.Index
- range
.First
),
198 switch(reg
->Register
.File
) {
199 case TGSI_FILE_IMMEDIATE
: {
200 LLVMTypeRef ctype
= tgsi2llvmtype(bld_base
, type
);
201 if (type
== TGSI_TYPE_DOUBLE
) {
202 result
= LLVMGetUndef(LLVMVectorType(LLVMIntTypeInContext(bld_base
->base
.gallivm
->context
, 32), bld_base
->base
.type
.length
* 2));
203 result
= LLVMConstInsertElement(result
,
204 bld
->immediates
[reg
->Register
.Index
][swizzle
],
205 bld_base
->int_bld
.zero
);
206 result
= LLVMConstInsertElement(result
,
207 bld
->immediates
[reg
->Register
.Index
][swizzle
+ 1],
208 bld_base
->int_bld
.one
);
209 return LLVMConstBitCast(result
, ctype
);
211 return LLVMConstBitCast(bld
->immediates
[reg
->Register
.Index
][swizzle
], ctype
);
215 case TGSI_FILE_INPUT
:
216 result
= ctx
->inputs
[radeon_llvm_reg_index_soa(reg
->Register
.Index
, swizzle
)];
217 if (type
== TGSI_TYPE_DOUBLE
) {
219 ptr2
= ctx
->inputs
[radeon_llvm_reg_index_soa(reg
->Register
.Index
, swizzle
+ 1)];
220 return radeon_llvm_emit_fetch_double(bld_base
, ptr
, ptr2
);
224 case TGSI_FILE_TEMPORARY
:
225 if (reg
->Register
.Index
>= ctx
->temps_count
)
226 return LLVMGetUndef(tgsi2llvmtype(bld_base
, type
));
227 if (uses_temp_indirect_addressing(bld_base
)) {
228 ptr
= lp_get_temp_ptr_soa(bld
, reg
->Register
.Index
, swizzle
);
231 ptr
= ctx
->temps
[reg
->Register
.Index
* TGSI_NUM_CHANNELS
+ swizzle
];
232 if (type
== TGSI_TYPE_DOUBLE
) {
233 ptr2
= ctx
->temps
[reg
->Register
.Index
* TGSI_NUM_CHANNELS
+ swizzle
+ 1];
234 return radeon_llvm_emit_fetch_double(bld_base
,
235 LLVMBuildLoad(builder
, ptr
, ""),
236 LLVMBuildLoad(builder
, ptr2
, ""));
238 result
= LLVMBuildLoad(builder
, ptr
, "");
241 case TGSI_FILE_OUTPUT
:
242 ptr
= lp_get_output_ptr(bld
, reg
->Register
.Index
, swizzle
);
243 if (type
== TGSI_TYPE_DOUBLE
) {
244 ptr2
= lp_get_output_ptr(bld
, reg
->Register
.Index
, swizzle
+ 1);
245 return radeon_llvm_emit_fetch_double(bld_base
,
246 LLVMBuildLoad(builder
, ptr
, ""),
247 LLVMBuildLoad(builder
, ptr2
, ""));
249 result
= LLVMBuildLoad(builder
, ptr
, "");
253 return LLVMGetUndef(tgsi2llvmtype(bld_base
, type
));
256 return bitcast(bld_base
, type
, result
);
259 static LLVMValueRef
fetch_system_value(
260 struct lp_build_tgsi_context
* bld_base
,
261 const struct tgsi_full_src_register
*reg
,
262 enum tgsi_opcode_type type
,
265 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
266 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
268 LLVMValueRef cval
= ctx
->system_values
[reg
->Register
.Index
];
269 if (LLVMGetTypeKind(LLVMTypeOf(cval
)) == LLVMVectorTypeKind
) {
270 cval
= LLVMBuildExtractElement(gallivm
->builder
, cval
,
271 lp_build_const_int32(gallivm
, swizzle
), "");
273 return bitcast(bld_base
, type
, cval
);
276 static LLVMValueRef
si_build_alloca_undef(struct gallivm_state
*gallivm
,
280 LLVMValueRef ptr
= lp_build_alloca(gallivm
, type
, name
);
281 LLVMBuildStore(gallivm
->builder
, LLVMGetUndef(type
), ptr
);
285 static void emit_declaration(
286 struct lp_build_tgsi_context
* bld_base
,
287 const struct tgsi_full_declaration
*decl
)
289 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
290 unsigned first
, last
, i
, idx
;
291 switch(decl
->Declaration
.File
) {
292 case TGSI_FILE_ADDRESS
:
295 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
297 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
298 ctx
->soa
.addr
[idx
][chan
] = si_build_alloca_undef(
300 ctx
->soa
.bld_base
.uint_bld
.elem_type
, "");
306 case TGSI_FILE_TEMPORARY
:
307 if (decl
->Declaration
.Array
) {
309 int size
= bld_base
->info
->array_max
[TGSI_FILE_TEMPORARY
];
310 ctx
->arrays
= MALLOC(sizeof(ctx
->arrays
[0]) * size
);
313 ctx
->arrays
[decl
->Array
.ArrayID
- 1] = decl
->Range
;
315 if (uses_temp_indirect_addressing(bld_base
)) {
316 lp_emit_declaration_soa(bld_base
, decl
);
319 first
= decl
->Range
.First
;
320 last
= decl
->Range
.Last
;
321 if (!ctx
->temps_count
) {
322 ctx
->temps_count
= bld_base
->info
->file_max
[TGSI_FILE_TEMPORARY
] + 1;
323 ctx
->temps
= MALLOC(TGSI_NUM_CHANNELS
* ctx
->temps_count
* sizeof(LLVMValueRef
));
325 for (idx
= first
; idx
<= last
; idx
++) {
326 for (i
= 0; i
< TGSI_NUM_CHANNELS
; i
++) {
327 ctx
->temps
[idx
* TGSI_NUM_CHANNELS
+ i
] =
328 si_build_alloca_undef(bld_base
->base
.gallivm
,
329 bld_base
->base
.vec_type
,
335 case TGSI_FILE_INPUT
:
338 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
340 ctx
->load_input(ctx
, idx
, decl
);
345 case TGSI_FILE_SYSTEM_VALUE
:
348 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
349 ctx
->load_system_value(ctx
, idx
, decl
);
354 case TGSI_FILE_OUTPUT
:
357 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
359 assert(idx
< RADEON_LLVM_MAX_OUTPUTS
);
360 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
361 ctx
->soa
.outputs
[idx
][chan
] = si_build_alloca_undef(
363 ctx
->soa
.bld_base
.base
.elem_type
, "");
374 LLVMValueRef
radeon_llvm_saturate(struct lp_build_tgsi_context
*bld_base
,
377 struct lp_build_emit_data clamp_emit_data
;
379 memset(&clamp_emit_data
, 0, sizeof(clamp_emit_data
));
380 clamp_emit_data
.arg_count
= 3;
381 clamp_emit_data
.args
[0] = value
;
382 clamp_emit_data
.args
[2] = bld_base
->base
.one
;
383 clamp_emit_data
.args
[1] = bld_base
->base
.zero
;
385 return lp_build_emit_llvm(bld_base
, TGSI_OPCODE_CLAMP
,
389 void radeon_llvm_emit_store(
390 struct lp_build_tgsi_context
* bld_base
,
391 const struct tgsi_full_instruction
* inst
,
392 const struct tgsi_opcode_info
* info
,
395 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
396 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
397 struct gallivm_state
*gallivm
= bld
->bld_base
.base
.gallivm
;
398 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[0];
399 LLVMBuilderRef builder
= bld
->bld_base
.base
.gallivm
->builder
;
400 LLVMValueRef temp_ptr
, temp_ptr2
= NULL
;
401 unsigned chan
, chan_index
;
402 boolean is_vec_store
= FALSE
;
403 enum tgsi_opcode_type dtype
= tgsi_opcode_infer_dst_type(inst
->Instruction
.Opcode
);
406 LLVMTypeKind k
= LLVMGetTypeKind(LLVMTypeOf(dst
[0]));
407 is_vec_store
= (k
== LLVMVectorTypeKind
);
411 LLVMValueRef values
[4] = {};
412 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst
, chan
) {
413 LLVMValueRef index
= lp_build_const_int32(gallivm
, chan
);
414 values
[chan
] = LLVMBuildExtractElement(gallivm
->builder
,
417 bld_base
->emit_store(bld_base
, inst
, info
, values
);
421 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst
, chan_index
) {
422 LLVMValueRef value
= dst
[chan_index
];
424 if (dtype
== TGSI_TYPE_DOUBLE
&& (chan_index
== 1 || chan_index
== 3))
426 if (inst
->Instruction
.Saturate
)
427 value
= radeon_llvm_saturate(bld_base
, value
);
429 if (reg
->Register
.File
== TGSI_FILE_ADDRESS
) {
430 temp_ptr
= bld
->addr
[reg
->Register
.Index
][chan_index
];
431 LLVMBuildStore(builder
, value
, temp_ptr
);
435 if (dtype
!= TGSI_TYPE_DOUBLE
)
436 value
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, value
);
438 if (reg
->Register
.Indirect
) {
439 struct tgsi_declaration_range range
= get_array_range(bld_base
,
440 reg
->Register
.File
, ®
->Indirect
);
442 unsigned i
, size
= range
.Last
- range
.First
+ 1;
443 LLVMValueRef array
= LLVMBuildInsertElement(builder
,
444 emit_array_fetch(bld_base
, reg
->Register
.File
, TGSI_TYPE_FLOAT
, range
, chan_index
),
445 value
, emit_array_index(bld
, ®
->Indirect
, reg
->Register
.Index
- range
.First
), "");
447 for (i
= 0; i
< size
; ++i
) {
448 switch(reg
->Register
.File
) {
449 case TGSI_FILE_OUTPUT
:
450 temp_ptr
= bld
->outputs
[i
+ range
.First
][chan_index
];
453 case TGSI_FILE_TEMPORARY
:
454 if (range
.First
+ i
>= ctx
->temps_count
)
456 if (uses_temp_indirect_addressing(bld_base
))
457 temp_ptr
= lp_get_temp_ptr_soa(bld
, i
+ range
.First
, chan_index
);
459 temp_ptr
= ctx
->temps
[(i
+ range
.First
) * TGSI_NUM_CHANNELS
+ chan_index
];
465 value
= LLVMBuildExtractElement(builder
, array
,
466 lp_build_const_int32(gallivm
, i
), "");
467 LLVMBuildStore(builder
, value
, temp_ptr
);
471 switch(reg
->Register
.File
) {
472 case TGSI_FILE_OUTPUT
:
473 temp_ptr
= bld
->outputs
[reg
->Register
.Index
][chan_index
];
474 if (dtype
== TGSI_TYPE_DOUBLE
)
475 temp_ptr2
= bld
->outputs
[reg
->Register
.Index
][chan_index
+ 1];
478 case TGSI_FILE_TEMPORARY
:
479 if (reg
->Register
.Index
>= ctx
->temps_count
)
481 if (uses_temp_indirect_addressing(bld_base
)) {
485 temp_ptr
= ctx
->temps
[ TGSI_NUM_CHANNELS
* reg
->Register
.Index
+ chan_index
];
486 if (dtype
== TGSI_TYPE_DOUBLE
)
487 temp_ptr2
= ctx
->temps
[ TGSI_NUM_CHANNELS
* reg
->Register
.Index
+ chan_index
+ 1];
494 if (dtype
!= TGSI_TYPE_DOUBLE
)
495 LLVMBuildStore(builder
, value
, temp_ptr
);
497 LLVMValueRef ptr
= LLVMBuildBitCast(builder
, value
,
498 LLVMVectorType(LLVMIntTypeInContext(bld_base
->base
.gallivm
->context
, 32), 2), "");
500 value
= LLVMBuildExtractElement(builder
, ptr
,
501 bld_base
->uint_bld
.zero
, "");
502 val2
= LLVMBuildExtractElement(builder
, ptr
,
503 bld_base
->uint_bld
.one
, "");
505 LLVMBuildStore(builder
, bitcast(bld_base
, TGSI_TYPE_FLOAT
, value
), temp_ptr
);
506 LLVMBuildStore(builder
, bitcast(bld_base
, TGSI_TYPE_FLOAT
, val2
), temp_ptr2
);
512 static void bgnloop_emit(
513 const struct lp_build_tgsi_action
* action
,
514 struct lp_build_tgsi_context
* bld_base
,
515 struct lp_build_emit_data
* emit_data
)
517 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
518 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
519 LLVMBasicBlockRef loop_block
;
520 LLVMBasicBlockRef endloop_block
;
521 endloop_block
= LLVMAppendBasicBlockInContext(gallivm
->context
,
522 ctx
->main_fn
, "ENDLOOP");
523 loop_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
524 endloop_block
, "LOOP");
525 LLVMBuildBr(gallivm
->builder
, loop_block
);
526 LLVMPositionBuilderAtEnd(gallivm
->builder
, loop_block
);
528 if (++ctx
->loop_depth
> ctx
->loop_depth_max
) {
529 unsigned new_max
= ctx
->loop_depth_max
<< 1;
532 new_max
= RADEON_LLVM_INITIAL_CF_DEPTH
;
534 ctx
->loop
= REALLOC(ctx
->loop
, ctx
->loop_depth_max
*
535 sizeof(ctx
->loop
[0]),
536 new_max
* sizeof(ctx
->loop
[0]));
537 ctx
->loop_depth_max
= new_max
;
540 ctx
->loop
[ctx
->loop_depth
- 1].loop_block
= loop_block
;
541 ctx
->loop
[ctx
->loop_depth
- 1].endloop_block
= endloop_block
;
544 static void brk_emit(
545 const struct lp_build_tgsi_action
* action
,
546 struct lp_build_tgsi_context
* bld_base
,
547 struct lp_build_emit_data
* emit_data
)
549 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
550 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
551 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
553 LLVMBuildBr(gallivm
->builder
, current_loop
->endloop_block
);
556 static void cont_emit(
557 const struct lp_build_tgsi_action
* action
,
558 struct lp_build_tgsi_context
* bld_base
,
559 struct lp_build_emit_data
* emit_data
)
561 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
562 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
563 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
565 LLVMBuildBr(gallivm
->builder
, current_loop
->loop_block
);
568 static void else_emit(
569 const struct lp_build_tgsi_action
* action
,
570 struct lp_build_tgsi_context
* bld_base
,
571 struct lp_build_emit_data
* emit_data
)
573 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
574 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
575 struct radeon_llvm_branch
* current_branch
= get_current_branch(ctx
);
576 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(gallivm
->builder
);
578 /* We need to add a terminator to the current block if the previous
579 * instruction was an ENDIF.Example:
592 if (current_block
!= current_branch
->if_block
) {
593 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
595 if (!LLVMGetBasicBlockTerminator(current_branch
->if_block
)) {
596 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
598 current_branch
->has_else
= 1;
599 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->else_block
);
602 static void endif_emit(
603 const struct lp_build_tgsi_action
* action
,
604 struct lp_build_tgsi_context
* bld_base
,
605 struct lp_build_emit_data
* emit_data
)
607 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
608 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
609 struct radeon_llvm_branch
* current_branch
= get_current_branch(ctx
);
610 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(gallivm
->builder
);
612 /* If we have consecutive ENDIF instructions, then the first ENDIF
613 * will not have a terminator, so we need to add one. */
614 if (current_block
!= current_branch
->if_block
615 && current_block
!= current_branch
->else_block
616 && !LLVMGetBasicBlockTerminator(current_block
)) {
618 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
620 if (!LLVMGetBasicBlockTerminator(current_branch
->else_block
)) {
621 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->else_block
);
622 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
625 if (!LLVMGetBasicBlockTerminator(current_branch
->if_block
)) {
626 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->if_block
);
627 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
630 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->endif_block
);
634 static void endloop_emit(
635 const struct lp_build_tgsi_action
* action
,
636 struct lp_build_tgsi_context
* bld_base
,
637 struct lp_build_emit_data
* emit_data
)
639 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
640 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
641 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
643 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm
->builder
))) {
644 LLVMBuildBr(gallivm
->builder
, current_loop
->loop_block
);
647 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_loop
->endloop_block
);
651 static void if_cond_emit(
652 const struct lp_build_tgsi_action
* action
,
653 struct lp_build_tgsi_context
* bld_base
,
654 struct lp_build_emit_data
* emit_data
,
657 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
658 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
659 LLVMBasicBlockRef if_block
, else_block
, endif_block
;
661 endif_block
= LLVMAppendBasicBlockInContext(gallivm
->context
,
662 ctx
->main_fn
, "ENDIF");
663 if_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
665 else_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
666 endif_block
, "ELSE");
667 LLVMBuildCondBr(gallivm
->builder
, cond
, if_block
, else_block
);
668 LLVMPositionBuilderAtEnd(gallivm
->builder
, if_block
);
670 if (++ctx
->branch_depth
> ctx
->branch_depth_max
) {
671 unsigned new_max
= ctx
->branch_depth_max
<< 1;
674 new_max
= RADEON_LLVM_INITIAL_CF_DEPTH
;
676 ctx
->branch
= REALLOC(ctx
->branch
, ctx
->branch_depth_max
*
677 sizeof(ctx
->branch
[0]),
678 new_max
* sizeof(ctx
->branch
[0]));
679 ctx
->branch_depth_max
= new_max
;
682 ctx
->branch
[ctx
->branch_depth
- 1].endif_block
= endif_block
;
683 ctx
->branch
[ctx
->branch_depth
- 1].if_block
= if_block
;
684 ctx
->branch
[ctx
->branch_depth
- 1].else_block
= else_block
;
685 ctx
->branch
[ctx
->branch_depth
- 1].has_else
= 0;
689 const struct lp_build_tgsi_action
* action
,
690 struct lp_build_tgsi_context
* bld_base
,
691 struct lp_build_emit_data
* emit_data
)
693 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
696 cond
= LLVMBuildFCmp(gallivm
->builder
, LLVMRealUNE
,
698 bld_base
->base
.zero
, "");
700 if_cond_emit(action
, bld_base
, emit_data
, cond
);
703 static void uif_emit(
704 const struct lp_build_tgsi_action
* action
,
705 struct lp_build_tgsi_context
* bld_base
,
706 struct lp_build_emit_data
* emit_data
)
708 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
711 cond
= LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
712 bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, emit_data
->args
[0]),
713 bld_base
->int_bld
.zero
, "");
715 if_cond_emit(action
, bld_base
, emit_data
, cond
);
718 static void kill_if_fetch_args(
719 struct lp_build_tgsi_context
* bld_base
,
720 struct lp_build_emit_data
* emit_data
)
722 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
723 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
724 LLVMBuilderRef builder
= gallivm
->builder
;
726 LLVMValueRef conds
[TGSI_NUM_CHANNELS
];
728 for (i
= 0; i
< TGSI_NUM_CHANNELS
; i
++) {
729 LLVMValueRef value
= lp_build_emit_fetch(bld_base
, inst
, 0, i
);
730 conds
[i
] = LLVMBuildFCmp(builder
, LLVMRealOLT
, value
,
731 bld_base
->base
.zero
, "");
734 /* Or the conditions together */
735 for (i
= TGSI_NUM_CHANNELS
- 1; i
> 0; i
--) {
736 conds
[i
- 1] = LLVMBuildOr(builder
, conds
[i
], conds
[i
- 1], "");
739 emit_data
->dst_type
= LLVMVoidTypeInContext(gallivm
->context
);
740 emit_data
->arg_count
= 1;
741 emit_data
->args
[0] = LLVMBuildSelect(builder
, conds
[0],
742 lp_build_const_float(gallivm
, -1.0f
),
743 bld_base
->base
.zero
, "");
746 static void kil_emit(
747 const struct lp_build_tgsi_action
* action
,
748 struct lp_build_tgsi_context
* bld_base
,
749 struct lp_build_emit_data
* emit_data
)
752 for (i
= 0; i
< emit_data
->arg_count
; i
++) {
753 emit_data
->output
[i
] = lp_build_intrinsic_unary(
754 bld_base
->base
.gallivm
->builder
,
756 emit_data
->dst_type
, emit_data
->args
[i
]);
760 static void radeon_llvm_cube_to_2d_coords(struct lp_build_tgsi_context
*bld_base
,
761 LLVMValueRef
*in
, LLVMValueRef
*out
)
763 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
764 LLVMBuilderRef builder
= gallivm
->builder
;
765 LLVMTypeRef type
= bld_base
->base
.elem_type
;
766 LLVMValueRef coords
[4];
767 LLVMValueRef mad_args
[3];
768 LLVMValueRef v
, cube_vec
;
771 cube_vec
= lp_build_gather_values(bld_base
->base
.gallivm
, in
, 4);
772 v
= lp_build_intrinsic(builder
, "llvm.AMDGPU.cube", LLVMVectorType(type
, 4),
773 &cube_vec
, 1, LLVMReadNoneAttribute
);
775 for (i
= 0; i
< 4; ++i
)
776 coords
[i
] = LLVMBuildExtractElement(builder
, v
,
777 lp_build_const_int32(gallivm
, i
), "");
779 coords
[2] = lp_build_intrinsic(builder
, "llvm.fabs.f32",
780 type
, &coords
[2], 1, LLVMReadNoneAttribute
);
781 coords
[2] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_RCP
, coords
[2]);
783 mad_args
[1] = coords
[2];
784 mad_args
[2] = LLVMConstReal(type
, 1.5);
786 mad_args
[0] = coords
[0];
787 coords
[0] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
788 mad_args
[0], mad_args
[1], mad_args
[2]);
790 mad_args
[0] = coords
[1];
791 coords
[1] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
792 mad_args
[0], mad_args
[1], mad_args
[2]);
794 /* apply xyz = yxw swizzle to cooords */
800 void radeon_llvm_emit_prepare_cube_coords(
801 struct lp_build_tgsi_context
* bld_base
,
802 struct lp_build_emit_data
* emit_data
,
803 LLVMValueRef
*coords_arg
,
804 LLVMValueRef
*derivs_arg
)
807 unsigned target
= emit_data
->inst
->Texture
.Texture
;
808 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
809 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
810 LLVMBuilderRef builder
= gallivm
->builder
;
811 LLVMValueRef coords
[4];
814 radeon_llvm_cube_to_2d_coords(bld_base
, coords_arg
, coords
);
816 if (opcode
== TGSI_OPCODE_TXD
&& derivs_arg
) {
817 LLVMValueRef derivs
[4];
820 /* Convert cube derivatives to 2D derivatives. */
821 for (axis
= 0; axis
< 2; axis
++) {
822 LLVMValueRef shifted_cube_coords
[4], shifted_coords
[4];
824 /* Shift the cube coordinates by the derivatives to get
825 * the cube coordinates of the "neighboring pixel".
827 for (i
= 0; i
< 3; i
++)
828 shifted_cube_coords
[i
] =
829 LLVMBuildFAdd(builder
, coords_arg
[i
],
830 derivs_arg
[axis
*3+i
], "");
831 shifted_cube_coords
[3] = LLVMGetUndef(bld_base
->base
.elem_type
);
833 /* Project the shifted cube coordinates onto the face. */
834 radeon_llvm_cube_to_2d_coords(bld_base
, shifted_cube_coords
,
837 /* Subtract both sets of 2D coordinates to get 2D derivatives.
838 * This won't work if the shifted coordinates ended up
839 * in a different face.
841 for (i
= 0; i
< 2; i
++)
842 derivs
[axis
* 2 + i
] =
843 LLVMBuildFSub(builder
, shifted_coords
[i
],
847 memcpy(derivs_arg
, derivs
, sizeof(derivs
));
850 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
851 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
852 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
853 /* coords_arg.w component - array_index for cube arrays */
854 coords
[2] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
855 coords_arg
[3], lp_build_const_float(gallivm
, 8.0), coords
[2]);
858 /* Preserve compare/lod/bias. Put it in coords.w. */
859 if (opcode
== TGSI_OPCODE_TEX2
||
860 opcode
== TGSI_OPCODE_TXB2
||
861 opcode
== TGSI_OPCODE_TXL2
) {
862 coords
[3] = coords_arg
[4];
863 } else if (opcode
== TGSI_OPCODE_TXB
||
864 opcode
== TGSI_OPCODE_TXL
||
865 target
== TGSI_TEXTURE_SHADOWCUBE
) {
866 coords
[3] = coords_arg
[3];
869 memcpy(coords_arg
, coords
, sizeof(coords
));
872 static void emit_icmp(
873 const struct lp_build_tgsi_action
* action
,
874 struct lp_build_tgsi_context
* bld_base
,
875 struct lp_build_emit_data
* emit_data
)
878 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
879 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
881 switch (emit_data
->inst
->Instruction
.Opcode
) {
882 case TGSI_OPCODE_USEQ
: pred
= LLVMIntEQ
; break;
883 case TGSI_OPCODE_USNE
: pred
= LLVMIntNE
; break;
884 case TGSI_OPCODE_USGE
: pred
= LLVMIntUGE
; break;
885 case TGSI_OPCODE_USLT
: pred
= LLVMIntULT
; break;
886 case TGSI_OPCODE_ISGE
: pred
= LLVMIntSGE
; break;
887 case TGSI_OPCODE_ISLT
: pred
= LLVMIntSLT
; break;
889 assert(!"unknown instruction");
894 LLVMValueRef v
= LLVMBuildICmp(builder
, pred
,
895 emit_data
->args
[0], emit_data
->args
[1],"");
897 v
= LLVMBuildSExtOrBitCast(builder
, v
,
898 LLVMInt32TypeInContext(context
), "");
900 emit_data
->output
[emit_data
->chan
] = v
;
903 static void emit_ucmp(
904 const struct lp_build_tgsi_action
* action
,
905 struct lp_build_tgsi_context
* bld_base
,
906 struct lp_build_emit_data
* emit_data
)
908 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
910 LLVMValueRef arg0
= LLVMBuildBitCast(builder
, emit_data
->args
[0],
911 bld_base
->uint_bld
.elem_type
, "");
913 LLVMValueRef v
= LLVMBuildICmp(builder
, LLVMIntNE
, arg0
,
914 bld_base
->uint_bld
.zero
, "");
916 emit_data
->output
[emit_data
->chan
] =
917 LLVMBuildSelect(builder
, v
, emit_data
->args
[1], emit_data
->args
[2], "");
920 static void emit_cmp(const struct lp_build_tgsi_action
*action
,
921 struct lp_build_tgsi_context
*bld_base
,
922 struct lp_build_emit_data
*emit_data
)
924 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
925 LLVMValueRef cond
, *args
= emit_data
->args
;
927 cond
= LLVMBuildFCmp(builder
, LLVMRealOLT
, args
[0],
928 bld_base
->base
.zero
, "");
930 emit_data
->output
[emit_data
->chan
] =
931 LLVMBuildSelect(builder
, cond
, args
[1], args
[2], "");
934 static void emit_set_cond(
935 const struct lp_build_tgsi_action
*action
,
936 struct lp_build_tgsi_context
* bld_base
,
937 struct lp_build_emit_data
* emit_data
)
939 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
940 LLVMRealPredicate pred
;
943 /* Use ordered for everything but NE (which is usual for
946 switch (emit_data
->inst
->Instruction
.Opcode
) {
947 case TGSI_OPCODE_SGE
: pred
= LLVMRealOGE
; break;
948 case TGSI_OPCODE_SEQ
: pred
= LLVMRealOEQ
; break;
949 case TGSI_OPCODE_SLE
: pred
= LLVMRealOLE
; break;
950 case TGSI_OPCODE_SLT
: pred
= LLVMRealOLT
; break;
951 case TGSI_OPCODE_SNE
: pred
= LLVMRealUNE
; break;
952 case TGSI_OPCODE_SGT
: pred
= LLVMRealOGT
; break;
953 default: assert(!"unknown instruction"); pred
= 0; break;
956 cond
= LLVMBuildFCmp(builder
,
957 pred
, emit_data
->args
[0], emit_data
->args
[1], "");
959 emit_data
->output
[emit_data
->chan
] = LLVMBuildSelect(builder
,
960 cond
, bld_base
->base
.one
, bld_base
->base
.zero
, "");
963 static void emit_fcmp(
964 const struct lp_build_tgsi_action
*action
,
965 struct lp_build_tgsi_context
* bld_base
,
966 struct lp_build_emit_data
* emit_data
)
968 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
969 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
970 LLVMRealPredicate pred
;
972 /* Use ordered for everything but NE (which is usual for
975 switch (emit_data
->inst
->Instruction
.Opcode
) {
976 case TGSI_OPCODE_FSEQ
: pred
= LLVMRealOEQ
; break;
977 case TGSI_OPCODE_FSGE
: pred
= LLVMRealOGE
; break;
978 case TGSI_OPCODE_FSLT
: pred
= LLVMRealOLT
; break;
979 case TGSI_OPCODE_FSNE
: pred
= LLVMRealUNE
; break;
980 default: assert(!"unknown instruction"); pred
= 0; break;
983 LLVMValueRef v
= LLVMBuildFCmp(builder
, pred
,
984 emit_data
->args
[0], emit_data
->args
[1],"");
986 v
= LLVMBuildSExtOrBitCast(builder
, v
,
987 LLVMInt32TypeInContext(context
), "");
989 emit_data
->output
[emit_data
->chan
] = v
;
992 static void emit_dcmp(
993 const struct lp_build_tgsi_action
*action
,
994 struct lp_build_tgsi_context
* bld_base
,
995 struct lp_build_emit_data
* emit_data
)
997 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
998 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
999 LLVMRealPredicate pred
;
1001 /* Use ordered for everything but NE (which is usual for
1002 * float comparisons)
1004 switch (emit_data
->inst
->Instruction
.Opcode
) {
1005 case TGSI_OPCODE_DSEQ
: pred
= LLVMRealOEQ
; break;
1006 case TGSI_OPCODE_DSGE
: pred
= LLVMRealOGE
; break;
1007 case TGSI_OPCODE_DSLT
: pred
= LLVMRealOLT
; break;
1008 case TGSI_OPCODE_DSNE
: pred
= LLVMRealUNE
; break;
1009 default: assert(!"unknown instruction"); pred
= 0; break;
1012 LLVMValueRef v
= LLVMBuildFCmp(builder
, pred
,
1013 emit_data
->args
[0], emit_data
->args
[1],"");
1015 v
= LLVMBuildSExtOrBitCast(builder
, v
,
1016 LLVMInt32TypeInContext(context
), "");
1018 emit_data
->output
[emit_data
->chan
] = v
;
1021 static void emit_not(
1022 const struct lp_build_tgsi_action
* action
,
1023 struct lp_build_tgsi_context
* bld_base
,
1024 struct lp_build_emit_data
* emit_data
)
1026 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1027 LLVMValueRef v
= bitcast(bld_base
, TGSI_TYPE_UNSIGNED
,
1028 emit_data
->args
[0]);
1029 emit_data
->output
[emit_data
->chan
] = LLVMBuildNot(builder
, v
, "");
1032 static void emit_arl(
1033 const struct lp_build_tgsi_action
* action
,
1034 struct lp_build_tgsi_context
* bld_base
,
1035 struct lp_build_emit_data
* emit_data
)
1037 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1038 LLVMValueRef floor_index
= lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_FLR
, emit_data
->args
[0]);
1039 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToSI(builder
,
1040 floor_index
, bld_base
->base
.int_elem_type
, "");
1043 static void emit_and(
1044 const struct lp_build_tgsi_action
* action
,
1045 struct lp_build_tgsi_context
* bld_base
,
1046 struct lp_build_emit_data
* emit_data
)
1048 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1049 emit_data
->output
[emit_data
->chan
] = LLVMBuildAnd(builder
,
1050 emit_data
->args
[0], emit_data
->args
[1], "");
1053 static void emit_or(
1054 const struct lp_build_tgsi_action
* action
,
1055 struct lp_build_tgsi_context
* bld_base
,
1056 struct lp_build_emit_data
* emit_data
)
1058 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1059 emit_data
->output
[emit_data
->chan
] = LLVMBuildOr(builder
,
1060 emit_data
->args
[0], emit_data
->args
[1], "");
1063 static void emit_uadd(
1064 const struct lp_build_tgsi_action
* action
,
1065 struct lp_build_tgsi_context
* bld_base
,
1066 struct lp_build_emit_data
* emit_data
)
1068 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1069 emit_data
->output
[emit_data
->chan
] = LLVMBuildAdd(builder
,
1070 emit_data
->args
[0], emit_data
->args
[1], "");
1073 static void emit_udiv(
1074 const struct lp_build_tgsi_action
* action
,
1075 struct lp_build_tgsi_context
* bld_base
,
1076 struct lp_build_emit_data
* emit_data
)
1078 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1079 emit_data
->output
[emit_data
->chan
] = LLVMBuildUDiv(builder
,
1080 emit_data
->args
[0], emit_data
->args
[1], "");
1083 static void emit_idiv(
1084 const struct lp_build_tgsi_action
* action
,
1085 struct lp_build_tgsi_context
* bld_base
,
1086 struct lp_build_emit_data
* emit_data
)
1088 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1089 emit_data
->output
[emit_data
->chan
] = LLVMBuildSDiv(builder
,
1090 emit_data
->args
[0], emit_data
->args
[1], "");
1093 static void emit_mod(
1094 const struct lp_build_tgsi_action
* action
,
1095 struct lp_build_tgsi_context
* bld_base
,
1096 struct lp_build_emit_data
* emit_data
)
1098 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1099 emit_data
->output
[emit_data
->chan
] = LLVMBuildSRem(builder
,
1100 emit_data
->args
[0], emit_data
->args
[1], "");
1103 static void emit_umod(
1104 const struct lp_build_tgsi_action
* action
,
1105 struct lp_build_tgsi_context
* bld_base
,
1106 struct lp_build_emit_data
* emit_data
)
1108 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1109 emit_data
->output
[emit_data
->chan
] = LLVMBuildURem(builder
,
1110 emit_data
->args
[0], emit_data
->args
[1], "");
1113 static void emit_shl(
1114 const struct lp_build_tgsi_action
* action
,
1115 struct lp_build_tgsi_context
* bld_base
,
1116 struct lp_build_emit_data
* emit_data
)
1118 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1119 emit_data
->output
[emit_data
->chan
] = LLVMBuildShl(builder
,
1120 emit_data
->args
[0], emit_data
->args
[1], "");
1123 static void emit_ushr(
1124 const struct lp_build_tgsi_action
* action
,
1125 struct lp_build_tgsi_context
* bld_base
,
1126 struct lp_build_emit_data
* emit_data
)
1128 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1129 emit_data
->output
[emit_data
->chan
] = LLVMBuildLShr(builder
,
1130 emit_data
->args
[0], emit_data
->args
[1], "");
1132 static void emit_ishr(
1133 const struct lp_build_tgsi_action
* action
,
1134 struct lp_build_tgsi_context
* bld_base
,
1135 struct lp_build_emit_data
* emit_data
)
1137 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1138 emit_data
->output
[emit_data
->chan
] = LLVMBuildAShr(builder
,
1139 emit_data
->args
[0], emit_data
->args
[1], "");
1142 static void emit_xor(
1143 const struct lp_build_tgsi_action
* action
,
1144 struct lp_build_tgsi_context
* bld_base
,
1145 struct lp_build_emit_data
* emit_data
)
1147 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1148 emit_data
->output
[emit_data
->chan
] = LLVMBuildXor(builder
,
1149 emit_data
->args
[0], emit_data
->args
[1], "");
1152 static void emit_ssg(
1153 const struct lp_build_tgsi_action
* action
,
1154 struct lp_build_tgsi_context
* bld_base
,
1155 struct lp_build_emit_data
* emit_data
)
1157 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1159 LLVMValueRef cmp
, val
;
1161 if (emit_data
->inst
->Instruction
.Opcode
== TGSI_OPCODE_ISSG
) {
1162 cmp
= LLVMBuildICmp(builder
, LLVMIntSGT
, emit_data
->args
[0], bld_base
->int_bld
.zero
, "");
1163 val
= LLVMBuildSelect(builder
, cmp
, bld_base
->int_bld
.one
, emit_data
->args
[0], "");
1164 cmp
= LLVMBuildICmp(builder
, LLVMIntSGE
, val
, bld_base
->int_bld
.zero
, "");
1165 val
= LLVMBuildSelect(builder
, cmp
, val
, LLVMConstInt(bld_base
->int_bld
.elem_type
, -1, true), "");
1166 } else { // float SSG
1167 cmp
= LLVMBuildFCmp(builder
, LLVMRealOGT
, emit_data
->args
[0], bld_base
->base
.zero
, "");
1168 val
= LLVMBuildSelect(builder
, cmp
, bld_base
->base
.one
, emit_data
->args
[0], "");
1169 cmp
= LLVMBuildFCmp(builder
, LLVMRealOGE
, val
, bld_base
->base
.zero
, "");
1170 val
= LLVMBuildSelect(builder
, cmp
, val
, LLVMConstReal(bld_base
->base
.elem_type
, -1), "");
1173 emit_data
->output
[emit_data
->chan
] = val
;
1176 static void emit_ineg(
1177 const struct lp_build_tgsi_action
* action
,
1178 struct lp_build_tgsi_context
* bld_base
,
1179 struct lp_build_emit_data
* emit_data
)
1181 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1182 emit_data
->output
[emit_data
->chan
] = LLVMBuildNeg(builder
,
1183 emit_data
->args
[0], "");
1186 static void emit_dneg(
1187 const struct lp_build_tgsi_action
* action
,
1188 struct lp_build_tgsi_context
* bld_base
,
1189 struct lp_build_emit_data
* emit_data
)
1191 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1192 emit_data
->output
[emit_data
->chan
] = LLVMBuildFNeg(builder
,
1193 emit_data
->args
[0], "");
1196 static void emit_frac(
1197 const struct lp_build_tgsi_action
* action
,
1198 struct lp_build_tgsi_context
* bld_base
,
1199 struct lp_build_emit_data
* emit_data
)
1201 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1204 if (emit_data
->info
->opcode
== TGSI_OPCODE_FRC
)
1205 intr
= "llvm.floor.f32";
1206 else if (emit_data
->info
->opcode
== TGSI_OPCODE_DFRAC
)
1207 intr
= "llvm.floor.f64";
1213 LLVMValueRef floor
= lp_build_intrinsic(builder
, intr
, emit_data
->dst_type
,
1214 &emit_data
->args
[0], 1,
1215 LLVMReadNoneAttribute
);
1216 emit_data
->output
[emit_data
->chan
] = LLVMBuildFSub(builder
,
1217 emit_data
->args
[0], floor
, "");
1220 static void emit_f2i(
1221 const struct lp_build_tgsi_action
* action
,
1222 struct lp_build_tgsi_context
* bld_base
,
1223 struct lp_build_emit_data
* emit_data
)
1225 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1226 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToSI(builder
,
1227 emit_data
->args
[0], bld_base
->int_bld
.elem_type
, "");
1230 static void emit_f2u(
1231 const struct lp_build_tgsi_action
* action
,
1232 struct lp_build_tgsi_context
* bld_base
,
1233 struct lp_build_emit_data
* emit_data
)
1235 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1236 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToUI(builder
,
1237 emit_data
->args
[0], bld_base
->uint_bld
.elem_type
, "");
1240 static void emit_i2f(
1241 const struct lp_build_tgsi_action
* action
,
1242 struct lp_build_tgsi_context
* bld_base
,
1243 struct lp_build_emit_data
* emit_data
)
1245 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1246 emit_data
->output
[emit_data
->chan
] = LLVMBuildSIToFP(builder
,
1247 emit_data
->args
[0], bld_base
->base
.elem_type
, "");
1250 static void emit_u2f(
1251 const struct lp_build_tgsi_action
* action
,
1252 struct lp_build_tgsi_context
* bld_base
,
1253 struct lp_build_emit_data
* emit_data
)
1255 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1256 emit_data
->output
[emit_data
->chan
] = LLVMBuildUIToFP(builder
,
1257 emit_data
->args
[0], bld_base
->base
.elem_type
, "");
1260 static void emit_immediate(struct lp_build_tgsi_context
* bld_base
,
1261 const struct tgsi_full_immediate
*imm
)
1264 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
1266 for (i
= 0; i
< 4; ++i
) {
1267 ctx
->soa
.immediates
[ctx
->soa
.num_immediates
][i
] =
1268 LLVMConstInt(bld_base
->uint_bld
.elem_type
, imm
->u
[i
].Uint
, false );
1271 ctx
->soa
.num_immediates
++;
1275 build_tgsi_intrinsic_nomem(const struct lp_build_tgsi_action
*action
,
1276 struct lp_build_tgsi_context
*bld_base
,
1277 struct lp_build_emit_data
*emit_data
)
1279 struct lp_build_context
* base
= &bld_base
->base
;
1280 emit_data
->output
[emit_data
->chan
] =
1281 lp_build_intrinsic(base
->gallivm
->builder
, action
->intr_name
,
1282 emit_data
->dst_type
, emit_data
->args
,
1283 emit_data
->arg_count
, LLVMReadNoneAttribute
);
1286 static void emit_bfi(const struct lp_build_tgsi_action
* action
,
1287 struct lp_build_tgsi_context
* bld_base
,
1288 struct lp_build_emit_data
* emit_data
)
1290 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1291 LLVMBuilderRef builder
= gallivm
->builder
;
1292 LLVMValueRef bfi_args
[3];
1294 // Calculate the bitmask: (((1 << src3) - 1) << src2
1295 bfi_args
[0] = LLVMBuildShl(builder
,
1296 LLVMBuildSub(builder
,
1297 LLVMBuildShl(builder
,
1298 bld_base
->int_bld
.one
,
1299 emit_data
->args
[3], ""),
1300 bld_base
->int_bld
.one
, ""),
1301 emit_data
->args
[2], "");
1303 bfi_args
[1] = LLVMBuildShl(builder
, emit_data
->args
[1],
1304 emit_data
->args
[2], "");
1306 bfi_args
[2] = emit_data
->args
[0];
1309 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1310 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1312 emit_data
->output
[emit_data
->chan
] =
1313 LLVMBuildXor(builder
, bfi_args
[2],
1314 LLVMBuildAnd(builder
, bfi_args
[0],
1315 LLVMBuildXor(builder
, bfi_args
[1], bfi_args
[2],
1319 /* this is ffs in C */
1320 static void emit_lsb(const struct lp_build_tgsi_action
* action
,
1321 struct lp_build_tgsi_context
* bld_base
,
1322 struct lp_build_emit_data
* emit_data
)
1324 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1325 LLVMValueRef args
[2] = {
1328 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1329 * add special code to check for x=0. The reason is that
1330 * the LLVM behavior for x=0 is different from what we
1333 * The hardware already implements the correct behavior.
1335 lp_build_const_int32(gallivm
, 1)
1338 emit_data
->output
[emit_data
->chan
] =
1339 lp_build_intrinsic(gallivm
->builder
, "llvm.cttz.i32",
1340 emit_data
->dst_type
, args
, Elements(args
),
1341 LLVMReadNoneAttribute
);
1344 /* Find the last bit set. */
1345 static void emit_umsb(const struct lp_build_tgsi_action
* action
,
1346 struct lp_build_tgsi_context
* bld_base
,
1347 struct lp_build_emit_data
* emit_data
)
1349 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1350 LLVMBuilderRef builder
= gallivm
->builder
;
1351 LLVMValueRef args
[2] = {
1353 /* Don't generate code for handling zero: */
1354 lp_build_const_int32(gallivm
, 1)
1358 lp_build_intrinsic(builder
, "llvm.ctlz.i32",
1359 emit_data
->dst_type
, args
, Elements(args
),
1360 LLVMReadNoneAttribute
);
1362 /* The HW returns the last bit index from MSB, but TGSI wants
1363 * the index from LSB. Invert it by doing "31 - msb". */
1364 msb
= LLVMBuildSub(builder
, lp_build_const_int32(gallivm
, 31),
1367 /* Check for zero: */
1368 emit_data
->output
[emit_data
->chan
] =
1369 LLVMBuildSelect(builder
,
1370 LLVMBuildICmp(builder
, LLVMIntEQ
, args
[0],
1371 bld_base
->uint_bld
.zero
, ""),
1372 lp_build_const_int32(gallivm
, -1), msb
, "");
1375 /* Find the last bit opposite of the sign bit. */
1376 static void emit_imsb(const struct lp_build_tgsi_action
* action
,
1377 struct lp_build_tgsi_context
* bld_base
,
1378 struct lp_build_emit_data
* emit_data
)
1380 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1381 LLVMBuilderRef builder
= gallivm
->builder
;
1382 LLVMValueRef arg
= emit_data
->args
[0];
1385 lp_build_intrinsic(builder
, "llvm.AMDGPU.flbit.i32",
1386 emit_data
->dst_type
, &arg
, 1,
1387 LLVMReadNoneAttribute
);
1389 /* The HW returns the last bit index from MSB, but TGSI wants
1390 * the index from LSB. Invert it by doing "31 - msb". */
1391 msb
= LLVMBuildSub(builder
, lp_build_const_int32(gallivm
, 31),
1394 /* If arg == 0 || arg == -1 (0xffffffff), return -1. */
1395 LLVMValueRef all_ones
= lp_build_const_int32(gallivm
, -1);
1398 LLVMBuildOr(builder
,
1399 LLVMBuildICmp(builder
, LLVMIntEQ
, arg
,
1400 bld_base
->uint_bld
.zero
, ""),
1401 LLVMBuildICmp(builder
, LLVMIntEQ
, arg
,
1404 emit_data
->output
[emit_data
->chan
] =
1405 LLVMBuildSelect(builder
, cond
, all_ones
, msb
, "");
1408 static void emit_iabs(const struct lp_build_tgsi_action
*action
,
1409 struct lp_build_tgsi_context
*bld_base
,
1410 struct lp_build_emit_data
*emit_data
)
1412 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1414 emit_data
->output
[emit_data
->chan
] =
1415 lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_IMAX
,
1417 LLVMBuildNeg(builder
,
1418 emit_data
->args
[0], ""));
1421 static void emit_minmax_int(const struct lp_build_tgsi_action
*action
,
1422 struct lp_build_tgsi_context
*bld_base
,
1423 struct lp_build_emit_data
*emit_data
)
1425 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1426 LLVMIntPredicate op
;
1428 switch (emit_data
->info
->opcode
) {
1431 case TGSI_OPCODE_IMAX
:
1434 case TGSI_OPCODE_IMIN
:
1437 case TGSI_OPCODE_UMAX
:
1440 case TGSI_OPCODE_UMIN
:
1445 emit_data
->output
[emit_data
->chan
] =
1446 LLVMBuildSelect(builder
,
1447 LLVMBuildICmp(builder
, op
, emit_data
->args
[0],
1448 emit_data
->args
[1], ""),
1450 emit_data
->args
[1], "");
1453 static void pk2h_fetch_args(struct lp_build_tgsi_context
* bld_base
,
1454 struct lp_build_emit_data
* emit_data
)
1456 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
1458 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
1462 static void emit_pk2h(const struct lp_build_tgsi_action
*action
,
1463 struct lp_build_tgsi_context
*bld_base
,
1464 struct lp_build_emit_data
*emit_data
)
1466 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1467 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
1468 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1469 LLVMTypeRef fp16
, i16
;
1470 LLVMValueRef const16
, comp
[2];
1473 fp16
= LLVMHalfTypeInContext(context
);
1474 i16
= LLVMInt16TypeInContext(context
);
1475 const16
= lp_build_const_int32(uint_bld
->gallivm
, 16);
1477 for (i
= 0; i
< 2; i
++) {
1478 comp
[i
] = LLVMBuildFPTrunc(builder
, emit_data
->args
[i
], fp16
, "");
1479 comp
[i
] = LLVMBuildBitCast(builder
, comp
[i
], i16
, "");
1480 comp
[i
] = LLVMBuildZExt(builder
, comp
[i
], uint_bld
->elem_type
, "");
1483 comp
[1] = LLVMBuildShl(builder
, comp
[1], const16
, "");
1484 comp
[0] = LLVMBuildOr(builder
, comp
[0], comp
[1], "");
1486 emit_data
->output
[emit_data
->chan
] = comp
[0];
1489 static void up2h_fetch_args(struct lp_build_tgsi_context
* bld_base
,
1490 struct lp_build_emit_data
* emit_data
)
1492 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
1496 static void emit_up2h(const struct lp_build_tgsi_action
*action
,
1497 struct lp_build_tgsi_context
*bld_base
,
1498 struct lp_build_emit_data
*emit_data
)
1500 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1501 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
1502 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1503 LLVMTypeRef fp16
, i16
;
1504 LLVMValueRef const16
, input
, val
;
1507 fp16
= LLVMHalfTypeInContext(context
);
1508 i16
= LLVMInt16TypeInContext(context
);
1509 const16
= lp_build_const_int32(uint_bld
->gallivm
, 16);
1510 input
= emit_data
->args
[0];
1512 for (i
= 0; i
< 2; i
++) {
1513 val
= i
== 1 ? LLVMBuildLShr(builder
, input
, const16
, "") : input
;
1514 val
= LLVMBuildTrunc(builder
, val
, i16
, "");
1515 val
= LLVMBuildBitCast(builder
, val
, fp16
, "");
1516 emit_data
->output
[i
] =
1517 LLVMBuildFPExt(builder
, val
, bld_base
->base
.elem_type
, "");
1521 void radeon_llvm_context_init(struct radeon_llvm_context
* ctx
, const char *triple
)
1523 struct lp_type type
;
1525 /* Initialize the gallivm object:
1526 * We are only using the module, context, and builder fields of this struct.
1527 * This should be enough for us to be able to pass our gallivm struct to the
1528 * helper functions in the gallivm module.
1530 memset(&ctx
->gallivm
, 0, sizeof (ctx
->gallivm
));
1531 memset(&ctx
->soa
, 0, sizeof(ctx
->soa
));
1532 ctx
->gallivm
.context
= LLVMContextCreate();
1533 ctx
->gallivm
.module
= LLVMModuleCreateWithNameInContext("tgsi",
1534 ctx
->gallivm
.context
);
1535 LLVMSetTarget(ctx
->gallivm
.module
,
1537 #if HAVE_LLVM < 0x0306
1542 ctx
->gallivm
.builder
= LLVMCreateBuilderInContext(ctx
->gallivm
.context
);
1544 struct lp_build_tgsi_context
* bld_base
= &ctx
->soa
.bld_base
;
1546 type
.floating
= TRUE
;
1553 lp_build_context_init(&bld_base
->base
, &ctx
->gallivm
, type
);
1554 lp_build_context_init(&ctx
->soa
.bld_base
.uint_bld
, &ctx
->gallivm
, lp_uint_type(type
));
1555 lp_build_context_init(&ctx
->soa
.bld_base
.int_bld
, &ctx
->gallivm
, lp_int_type(type
));
1557 struct lp_type dbl_type
;
1559 dbl_type
.width
*= 2;
1560 lp_build_context_init(&ctx
->soa
.bld_base
.dbl_bld
, &ctx
->gallivm
, dbl_type
);
1564 bld_base
->emit_store
= radeon_llvm_emit_store
;
1565 bld_base
->emit_swizzle
= emit_swizzle
;
1566 bld_base
->emit_declaration
= emit_declaration
;
1567 bld_base
->emit_immediate
= emit_immediate
;
1569 bld_base
->emit_fetch_funcs
[TGSI_FILE_IMMEDIATE
] = radeon_llvm_emit_fetch
;
1570 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = radeon_llvm_emit_fetch
;
1571 bld_base
->emit_fetch_funcs
[TGSI_FILE_TEMPORARY
] = radeon_llvm_emit_fetch
;
1572 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = radeon_llvm_emit_fetch
;
1573 bld_base
->emit_fetch_funcs
[TGSI_FILE_SYSTEM_VALUE
] = fetch_system_value
;
1575 /* Allocate outputs */
1576 ctx
->soa
.outputs
= ctx
->outputs
;
1578 lp_set_default_actions(bld_base
);
1580 bld_base
->op_actions
[TGSI_OPCODE_ABS
].emit
= build_tgsi_intrinsic_nomem
;
1581 bld_base
->op_actions
[TGSI_OPCODE_ABS
].intr_name
= "llvm.fabs.f32";
1582 bld_base
->op_actions
[TGSI_OPCODE_AND
].emit
= emit_and
;
1583 bld_base
->op_actions
[TGSI_OPCODE_ARL
].emit
= emit_arl
;
1584 bld_base
->op_actions
[TGSI_OPCODE_BFI
].emit
= emit_bfi
;
1585 bld_base
->op_actions
[TGSI_OPCODE_BGNLOOP
].emit
= bgnloop_emit
;
1586 bld_base
->op_actions
[TGSI_OPCODE_BREV
].emit
= build_tgsi_intrinsic_nomem
;
1587 bld_base
->op_actions
[TGSI_OPCODE_BREV
].intr_name
=
1588 HAVE_LLVM
>= 0x0308 ? "llvm.bitreverse.i32" : "llvm.AMDGPU.brev";
1589 bld_base
->op_actions
[TGSI_OPCODE_BRK
].emit
= brk_emit
;
1590 bld_base
->op_actions
[TGSI_OPCODE_CEIL
].emit
= build_tgsi_intrinsic_nomem
;
1591 bld_base
->op_actions
[TGSI_OPCODE_CEIL
].intr_name
= "llvm.ceil.f32";
1592 bld_base
->op_actions
[TGSI_OPCODE_CLAMP
].emit
= build_tgsi_intrinsic_nomem
;
1593 bld_base
->op_actions
[TGSI_OPCODE_CLAMP
].intr_name
=
1594 HAVE_LLVM
>= 0x0308 ? "llvm.AMDGPU.clamp." : "llvm.AMDIL.clamp.";
1595 bld_base
->op_actions
[TGSI_OPCODE_CMP
].emit
= emit_cmp
;
1596 bld_base
->op_actions
[TGSI_OPCODE_CONT
].emit
= cont_emit
;
1597 bld_base
->op_actions
[TGSI_OPCODE_COS
].emit
= build_tgsi_intrinsic_nomem
;
1598 bld_base
->op_actions
[TGSI_OPCODE_COS
].intr_name
= "llvm.cos.f32";
1599 bld_base
->op_actions
[TGSI_OPCODE_DABS
].emit
= build_tgsi_intrinsic_nomem
;
1600 bld_base
->op_actions
[TGSI_OPCODE_DABS
].intr_name
= "llvm.fabs.f64";
1601 bld_base
->op_actions
[TGSI_OPCODE_DFMA
].emit
= build_tgsi_intrinsic_nomem
;
1602 bld_base
->op_actions
[TGSI_OPCODE_DFMA
].intr_name
= "llvm.fma.f64";
1603 bld_base
->op_actions
[TGSI_OPCODE_DFRAC
].emit
= emit_frac
;
1604 bld_base
->op_actions
[TGSI_OPCODE_DNEG
].emit
= emit_dneg
;
1605 bld_base
->op_actions
[TGSI_OPCODE_DSEQ
].emit
= emit_dcmp
;
1606 bld_base
->op_actions
[TGSI_OPCODE_DSGE
].emit
= emit_dcmp
;
1607 bld_base
->op_actions
[TGSI_OPCODE_DSLT
].emit
= emit_dcmp
;
1608 bld_base
->op_actions
[TGSI_OPCODE_DSNE
].emit
= emit_dcmp
;
1609 bld_base
->op_actions
[TGSI_OPCODE_DRSQ
].emit
= build_tgsi_intrinsic_nomem
;
1610 bld_base
->op_actions
[TGSI_OPCODE_DRSQ
].intr_name
= "llvm.AMDGPU.rsq.f64";
1611 bld_base
->op_actions
[TGSI_OPCODE_DSQRT
].emit
= build_tgsi_intrinsic_nomem
;
1612 bld_base
->op_actions
[TGSI_OPCODE_DSQRT
].intr_name
= "llvm.sqrt.f64";
1613 bld_base
->op_actions
[TGSI_OPCODE_ELSE
].emit
= else_emit
;
1614 bld_base
->op_actions
[TGSI_OPCODE_ENDIF
].emit
= endif_emit
;
1615 bld_base
->op_actions
[TGSI_OPCODE_ENDLOOP
].emit
= endloop_emit
;
1616 bld_base
->op_actions
[TGSI_OPCODE_EX2
].emit
= build_tgsi_intrinsic_nomem
;
1617 bld_base
->op_actions
[TGSI_OPCODE_EX2
].intr_name
=
1618 HAVE_LLVM
>= 0x0308 ? "llvm.exp2.f32" : "llvm.AMDIL.exp.";
1619 bld_base
->op_actions
[TGSI_OPCODE_FLR
].emit
= build_tgsi_intrinsic_nomem
;
1620 bld_base
->op_actions
[TGSI_OPCODE_FLR
].intr_name
= "llvm.floor.f32";
1621 bld_base
->op_actions
[TGSI_OPCODE_FMA
].emit
= build_tgsi_intrinsic_nomem
;
1622 bld_base
->op_actions
[TGSI_OPCODE_FMA
].intr_name
= "llvm.fma.f32";
1623 bld_base
->op_actions
[TGSI_OPCODE_FRC
].emit
= emit_frac
;
1624 bld_base
->op_actions
[TGSI_OPCODE_F2I
].emit
= emit_f2i
;
1625 bld_base
->op_actions
[TGSI_OPCODE_F2U
].emit
= emit_f2u
;
1626 bld_base
->op_actions
[TGSI_OPCODE_FSEQ
].emit
= emit_fcmp
;
1627 bld_base
->op_actions
[TGSI_OPCODE_FSGE
].emit
= emit_fcmp
;
1628 bld_base
->op_actions
[TGSI_OPCODE_FSLT
].emit
= emit_fcmp
;
1629 bld_base
->op_actions
[TGSI_OPCODE_FSNE
].emit
= emit_fcmp
;
1630 bld_base
->op_actions
[TGSI_OPCODE_IABS
].emit
= emit_iabs
;
1631 bld_base
->op_actions
[TGSI_OPCODE_IBFE
].emit
= build_tgsi_intrinsic_nomem
;
1632 bld_base
->op_actions
[TGSI_OPCODE_IBFE
].intr_name
= "llvm.AMDGPU.bfe.i32";
1633 bld_base
->op_actions
[TGSI_OPCODE_IDIV
].emit
= emit_idiv
;
1634 bld_base
->op_actions
[TGSI_OPCODE_IF
].emit
= if_emit
;
1635 bld_base
->op_actions
[TGSI_OPCODE_UIF
].emit
= uif_emit
;
1636 bld_base
->op_actions
[TGSI_OPCODE_IMAX
].emit
= emit_minmax_int
;
1637 bld_base
->op_actions
[TGSI_OPCODE_IMIN
].emit
= emit_minmax_int
;
1638 bld_base
->op_actions
[TGSI_OPCODE_IMSB
].emit
= emit_imsb
;
1639 bld_base
->op_actions
[TGSI_OPCODE_INEG
].emit
= emit_ineg
;
1640 bld_base
->op_actions
[TGSI_OPCODE_ISHR
].emit
= emit_ishr
;
1641 bld_base
->op_actions
[TGSI_OPCODE_ISGE
].emit
= emit_icmp
;
1642 bld_base
->op_actions
[TGSI_OPCODE_ISLT
].emit
= emit_icmp
;
1643 bld_base
->op_actions
[TGSI_OPCODE_ISSG
].emit
= emit_ssg
;
1644 bld_base
->op_actions
[TGSI_OPCODE_I2F
].emit
= emit_i2f
;
1645 bld_base
->op_actions
[TGSI_OPCODE_KILL_IF
].fetch_args
= kill_if_fetch_args
;
1646 bld_base
->op_actions
[TGSI_OPCODE_KILL_IF
].emit
= kil_emit
;
1647 bld_base
->op_actions
[TGSI_OPCODE_KILL_IF
].intr_name
= "llvm.AMDGPU.kill";
1648 bld_base
->op_actions
[TGSI_OPCODE_KILL
].emit
= lp_build_tgsi_intrinsic
;
1649 bld_base
->op_actions
[TGSI_OPCODE_KILL
].intr_name
= "llvm.AMDGPU.kilp";
1650 bld_base
->op_actions
[TGSI_OPCODE_LSB
].emit
= emit_lsb
;
1651 bld_base
->op_actions
[TGSI_OPCODE_LG2
].emit
= build_tgsi_intrinsic_nomem
;
1652 bld_base
->op_actions
[TGSI_OPCODE_LG2
].intr_name
= "llvm.log2.f32";
1653 bld_base
->op_actions
[TGSI_OPCODE_MOD
].emit
= emit_mod
;
1654 bld_base
->op_actions
[TGSI_OPCODE_UMSB
].emit
= emit_umsb
;
1655 bld_base
->op_actions
[TGSI_OPCODE_NOT
].emit
= emit_not
;
1656 bld_base
->op_actions
[TGSI_OPCODE_OR
].emit
= emit_or
;
1657 bld_base
->op_actions
[TGSI_OPCODE_PK2H
].fetch_args
= pk2h_fetch_args
;
1658 bld_base
->op_actions
[TGSI_OPCODE_PK2H
].emit
= emit_pk2h
;
1659 bld_base
->op_actions
[TGSI_OPCODE_POPC
].emit
= build_tgsi_intrinsic_nomem
;
1660 bld_base
->op_actions
[TGSI_OPCODE_POPC
].intr_name
= "llvm.ctpop.i32";
1661 bld_base
->op_actions
[TGSI_OPCODE_POW
].emit
= build_tgsi_intrinsic_nomem
;
1662 bld_base
->op_actions
[TGSI_OPCODE_POW
].intr_name
= "llvm.pow.f32";
1663 bld_base
->op_actions
[TGSI_OPCODE_ROUND
].emit
= build_tgsi_intrinsic_nomem
;
1664 bld_base
->op_actions
[TGSI_OPCODE_ROUND
].intr_name
= "llvm.rint.f32";
1665 bld_base
->op_actions
[TGSI_OPCODE_RSQ
].intr_name
= "llvm.AMDGPU.rsq.clamped.f32";
1666 bld_base
->op_actions
[TGSI_OPCODE_RSQ
].emit
= build_tgsi_intrinsic_nomem
;
1667 bld_base
->op_actions
[TGSI_OPCODE_SGE
].emit
= emit_set_cond
;
1668 bld_base
->op_actions
[TGSI_OPCODE_SEQ
].emit
= emit_set_cond
;
1669 bld_base
->op_actions
[TGSI_OPCODE_SHL
].emit
= emit_shl
;
1670 bld_base
->op_actions
[TGSI_OPCODE_SLE
].emit
= emit_set_cond
;
1671 bld_base
->op_actions
[TGSI_OPCODE_SLT
].emit
= emit_set_cond
;
1672 bld_base
->op_actions
[TGSI_OPCODE_SNE
].emit
= emit_set_cond
;
1673 bld_base
->op_actions
[TGSI_OPCODE_SGT
].emit
= emit_set_cond
;
1674 bld_base
->op_actions
[TGSI_OPCODE_SIN
].emit
= build_tgsi_intrinsic_nomem
;
1675 bld_base
->op_actions
[TGSI_OPCODE_SIN
].intr_name
= "llvm.sin.f32";
1676 bld_base
->op_actions
[TGSI_OPCODE_SQRT
].emit
= build_tgsi_intrinsic_nomem
;
1677 bld_base
->op_actions
[TGSI_OPCODE_SQRT
].intr_name
= "llvm.sqrt.f32";
1678 bld_base
->op_actions
[TGSI_OPCODE_SSG
].emit
= emit_ssg
;
1679 bld_base
->op_actions
[TGSI_OPCODE_TRUNC
].emit
= build_tgsi_intrinsic_nomem
;
1680 bld_base
->op_actions
[TGSI_OPCODE_TRUNC
].intr_name
= "llvm.trunc.f32";
1681 bld_base
->op_actions
[TGSI_OPCODE_UADD
].emit
= emit_uadd
;
1682 bld_base
->op_actions
[TGSI_OPCODE_UBFE
].emit
= build_tgsi_intrinsic_nomem
;
1683 bld_base
->op_actions
[TGSI_OPCODE_UBFE
].intr_name
= "llvm.AMDGPU.bfe.u32";
1684 bld_base
->op_actions
[TGSI_OPCODE_UDIV
].emit
= emit_udiv
;
1685 bld_base
->op_actions
[TGSI_OPCODE_UMAX
].emit
= emit_minmax_int
;
1686 bld_base
->op_actions
[TGSI_OPCODE_UMIN
].emit
= emit_minmax_int
;
1687 bld_base
->op_actions
[TGSI_OPCODE_UMOD
].emit
= emit_umod
;
1688 bld_base
->op_actions
[TGSI_OPCODE_USEQ
].emit
= emit_icmp
;
1689 bld_base
->op_actions
[TGSI_OPCODE_USGE
].emit
= emit_icmp
;
1690 bld_base
->op_actions
[TGSI_OPCODE_USHR
].emit
= emit_ushr
;
1691 bld_base
->op_actions
[TGSI_OPCODE_USLT
].emit
= emit_icmp
;
1692 bld_base
->op_actions
[TGSI_OPCODE_USNE
].emit
= emit_icmp
;
1693 bld_base
->op_actions
[TGSI_OPCODE_U2F
].emit
= emit_u2f
;
1694 bld_base
->op_actions
[TGSI_OPCODE_XOR
].emit
= emit_xor
;
1695 bld_base
->op_actions
[TGSI_OPCODE_UCMP
].emit
= emit_ucmp
;
1696 bld_base
->op_actions
[TGSI_OPCODE_UP2H
].fetch_args
= up2h_fetch_args
;
1697 bld_base
->op_actions
[TGSI_OPCODE_UP2H
].emit
= emit_up2h
;
1700 void radeon_llvm_create_func(struct radeon_llvm_context
* ctx
,
1701 LLVMTypeRef
*return_types
, unsigned num_return_elems
,
1702 LLVMTypeRef
*ParamTypes
, unsigned ParamCount
)
1704 LLVMTypeRef main_fn_type
, ret_type
;
1705 LLVMBasicBlockRef main_fn_body
;
1707 if (num_return_elems
)
1708 ret_type
= LLVMStructTypeInContext(ctx
->gallivm
.context
,
1710 num_return_elems
, true);
1712 ret_type
= LLVMVoidTypeInContext(ctx
->gallivm
.context
);
1714 /* Setup the function */
1715 ctx
->return_type
= ret_type
;
1716 main_fn_type
= LLVMFunctionType(ret_type
, ParamTypes
, ParamCount
, 0);
1717 ctx
->main_fn
= LLVMAddFunction(ctx
->gallivm
.module
, "main", main_fn_type
);
1718 main_fn_body
= LLVMAppendBasicBlockInContext(ctx
->gallivm
.context
,
1719 ctx
->main_fn
, "main_body");
1720 LLVMPositionBuilderAtEnd(ctx
->gallivm
.builder
, main_fn_body
);
1723 void radeon_llvm_finalize_module(struct radeon_llvm_context
* ctx
)
1725 struct gallivm_state
* gallivm
= ctx
->soa
.bld_base
.base
.gallivm
;
1726 const char *triple
= LLVMGetTarget(gallivm
->module
);
1727 LLVMTargetLibraryInfoRef target_library_info
;
1729 /* Create the pass manager */
1730 gallivm
->passmgr
= LLVMCreateFunctionPassManagerForModule(
1733 target_library_info
= gallivm_create_target_library_info(triple
);
1734 LLVMAddTargetLibraryInfo(target_library_info
, gallivm
->passmgr
);
1736 /* This pass should eliminate all the load and store instructions */
1737 LLVMAddPromoteMemoryToRegisterPass(gallivm
->passmgr
);
1739 /* Add some optimization passes */
1740 LLVMAddScalarReplAggregatesPass(gallivm
->passmgr
);
1741 LLVMAddLICMPass(gallivm
->passmgr
);
1742 LLVMAddAggressiveDCEPass(gallivm
->passmgr
);
1743 LLVMAddCFGSimplificationPass(gallivm
->passmgr
);
1744 LLVMAddInstructionCombiningPass(gallivm
->passmgr
);
1747 LLVMRunFunctionPassManager(gallivm
->passmgr
, ctx
->main_fn
);
1749 LLVMDisposeBuilder(gallivm
->builder
);
1750 LLVMDisposePassManager(gallivm
->passmgr
);
1751 gallivm_dispose_target_library_info(target_library_info
);
1754 void radeon_llvm_dispose(struct radeon_llvm_context
* ctx
)
1756 LLVMDisposeModule(ctx
->soa
.bld_base
.base
.gallivm
->module
);
1757 LLVMContextDispose(ctx
->soa
.bld_base
.base
.gallivm
->context
);
1762 ctx
->temps_count
= 0;
1765 ctx
->loop_depth_max
= 0;
1768 ctx
->branch_depth_max
= 0;