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r600g/llvm: Add support for UBO
[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26 #include "radeon_llvm.h"
27
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
42
43 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
44 {
45 return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
46 }
47
48 static struct radeon_llvm_branch * get_current_branch(
49 struct radeon_llvm_context * ctx)
50 {
51 return ctx->branch_depth > 0 ?
52 ctx->branch + (ctx->branch_depth - 1) : NULL;
53 }
54
55 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
56 {
57 return (index * 4) + chan;
58 }
59
60 static LLVMValueRef emit_swizzle(
61 struct lp_build_tgsi_context * bld_base,
62 LLVMValueRef value,
63 unsigned swizzle_x,
64 unsigned swizzle_y,
65 unsigned swizzle_z,
66 unsigned swizzle_w)
67 {
68 LLVMValueRef swizzles[4];
69 LLVMTypeRef i32t =
70 LLVMInt32TypeInContext(bld_base->base.gallivm->context);
71
72 swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0);
73 swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0);
74 swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0);
75 swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0);
76
77 return LLVMBuildShuffleVector(bld_base->base.gallivm->builder,
78 value,
79 LLVMGetUndef(LLVMTypeOf(value)),
80 LLVMConstVector(swizzles, 4), "");
81 }
82
83 static LLVMValueRef
84 emit_array_index(
85 struct lp_build_tgsi_soa_context *bld,
86 const struct tgsi_full_src_register *reg,
87 unsigned swizzle)
88 {
89 struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
90
91 LLVMValueRef addr = LLVMBuildLoad(gallivm->builder,
92 bld->addr[reg->Indirect.Index][swizzle], "");
93 LLVMValueRef offset = lp_build_const_int32(gallivm, reg->Register.Index);
94 LLVMValueRef hw_index = LLVMBuildAdd(gallivm->builder, addr, offset, "");
95 LLVMValueRef soa_index = LLVMBuildMul(gallivm->builder, hw_index,
96 lp_build_const_int32(gallivm, 4), "");
97 LLVMValueRef array_index = LLVMBuildAdd(gallivm->builder, soa_index,
98 lp_build_const_int32(gallivm, swizzle), "");
99
100 return array_index;
101 }
102
103 static LLVMValueRef
104 emit_fetch_immediate(
105 struct lp_build_tgsi_context *bld_base,
106 const struct tgsi_full_src_register *reg,
107 enum tgsi_opcode_type type,
108 unsigned swizzle)
109 {
110 LLVMTypeRef ctype;
111 LLVMContextRef ctx = bld_base->base.gallivm->context;
112
113 switch (type) {
114 case TGSI_TYPE_UNSIGNED:
115 case TGSI_TYPE_SIGNED:
116 ctype = LLVMInt32TypeInContext(ctx);
117 break;
118 case TGSI_TYPE_UNTYPED:
119 case TGSI_TYPE_FLOAT:
120 ctype = LLVMFloatTypeInContext(ctx);
121 break;
122 default:
123 ctype = 0;
124 break;
125 }
126
127 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
128 if (swizzle == ~0) {
129 LLVMValueRef values[TGSI_NUM_CHANNELS] = {};
130 unsigned chan;
131 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
132 values[chan] = LLVMConstBitCast(bld->immediates[reg->Register.Index][chan], ctype);
133 }
134 return lp_build_gather_values(bld_base->base.gallivm, values,
135 TGSI_NUM_CHANNELS);
136 } else {
137 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
138 }
139 }
140
141 static LLVMValueRef
142 emit_fetch_input(
143 struct lp_build_tgsi_context *bld_base,
144 const struct tgsi_full_src_register *reg,
145 enum tgsi_opcode_type type,
146 unsigned swizzle)
147 {
148 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
149 if (swizzle == ~0) {
150 LLVMValueRef values[TGSI_NUM_CHANNELS] = {};
151 unsigned chan;
152 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
153 values[chan] = ctx->inputs[radeon_llvm_reg_index_soa(
154 reg->Register.Index, chan)];
155 }
156 return lp_build_gather_values(bld_base->base.gallivm, values,
157 TGSI_NUM_CHANNELS);
158 } else {
159 return bitcast(bld_base, type, ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)]);
160 }
161 }
162
163 static LLVMValueRef
164 emit_fetch_temporary(
165 struct lp_build_tgsi_context *bld_base,
166 const struct tgsi_full_src_register *reg,
167 enum tgsi_opcode_type type,
168 unsigned swizzle)
169 {
170 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
171 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
172 if (swizzle == ~0) {
173 LLVMValueRef values[TGSI_NUM_CHANNELS] = {};
174 unsigned chan;
175 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
176 values[chan] = emit_fetch_temporary(bld_base, reg, type, chan);
177 }
178 return lp_build_gather_values(bld_base->base.gallivm, values,
179 TGSI_NUM_CHANNELS);
180 }
181
182 if (reg->Register.Indirect) {
183 LLVMValueRef array_index = emit_array_index(bld, reg, swizzle);
184 LLVMValueRef ptr = LLVMBuildGEP(builder, bld->temps_array, &array_index,
185 1, "");
186 return LLVMBuildLoad(builder, ptr, "");
187 } else {
188 LLVMValueRef temp_ptr;
189 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
190 return bitcast(bld_base,type,LLVMBuildLoad(builder, temp_ptr, ""));
191 }
192 }
193
194 static LLVMValueRef
195 emit_fetch_output(
196 struct lp_build_tgsi_context *bld_base,
197 const struct tgsi_full_src_register *reg,
198 enum tgsi_opcode_type type,
199 unsigned swizzle)
200 {
201 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
202 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
203 if (reg->Register.Indirect) {
204 LLVMValueRef array_index = emit_array_index(bld, reg, swizzle);
205 LLVMValueRef ptr = LLVMBuildGEP(builder, bld->outputs_array, &array_index,
206 1, "");
207 return LLVMBuildLoad(builder, ptr, "");
208 } else {
209 LLVMValueRef temp_ptr;
210 temp_ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
211 return LLVMBuildLoad(builder, temp_ptr, "");
212 }
213 }
214
215 static void emit_declaration(
216 struct lp_build_tgsi_context * bld_base,
217 const struct tgsi_full_declaration *decl)
218 {
219 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
220 switch(decl->Declaration.File) {
221 case TGSI_FILE_ADDRESS:
222 {
223 unsigned idx;
224 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
225 unsigned chan;
226 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
227 ctx->soa.addr[idx][chan] = lp_build_alloca(
228 &ctx->gallivm,
229 ctx->soa.bld_base.uint_bld.elem_type, "");
230 }
231 }
232 break;
233 }
234
235 case TGSI_FILE_TEMPORARY:
236 lp_emit_declaration_soa(bld_base, decl);
237 break;
238
239 case TGSI_FILE_INPUT:
240 {
241 unsigned idx;
242 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
243 ctx->load_input(ctx, idx, decl);
244 }
245 }
246 break;
247
248 case TGSI_FILE_SYSTEM_VALUE:
249 {
250 unsigned idx;
251 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
252 ctx->load_system_value(ctx, idx, decl);
253 }
254 }
255 break;
256
257 case TGSI_FILE_OUTPUT:
258 {
259 unsigned idx;
260 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
261 unsigned chan;
262 assert(idx < RADEON_LLVM_MAX_OUTPUTS);
263 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
264 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm,
265 ctx->soa.bld_base.base.elem_type, "");
266 }
267 }
268
269 ctx->output_reg_count = MAX2(ctx->output_reg_count,
270 decl->Range.Last + 1);
271 break;
272 }
273
274 default:
275 break;
276 }
277 }
278
279 static void
280 emit_store(
281 struct lp_build_tgsi_context * bld_base,
282 const struct tgsi_full_instruction * inst,
283 const struct tgsi_opcode_info * info,
284 LLVMValueRef dst[4])
285 {
286 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
287 struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
288 struct lp_build_context base = bld->bld_base.base;
289 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
290 LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
291 LLVMValueRef temp_ptr;
292 unsigned chan, chan_index;
293 boolean is_vec_store = FALSE;
294 if (dst[0]) {
295 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
296 is_vec_store = (k == LLVMVectorTypeKind);
297 }
298
299 if (is_vec_store) {
300 LLVMValueRef values[4] = {};
301 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
302 LLVMValueRef index = lp_build_const_int32(gallivm, chan);
303 values[chan] = LLVMBuildExtractElement(gallivm->builder,
304 dst[0], index, "");
305 }
306 bld_base->emit_store(bld_base, inst, info, values);
307 return;
308 }
309
310 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
311 LLVMValueRef value = dst[chan_index];
312
313 if (inst->Instruction.Saturate != TGSI_SAT_NONE) {
314 struct lp_build_emit_data clamp_emit_data;
315
316 memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
317 clamp_emit_data.arg_count = 3;
318 clamp_emit_data.args[0] = value;
319 clamp_emit_data.args[2] = base.one;
320
321 switch(inst->Instruction.Saturate) {
322 case TGSI_SAT_ZERO_ONE:
323 clamp_emit_data.args[1] = base.zero;
324 break;
325 case TGSI_SAT_MINUS_PLUS_ONE:
326 clamp_emit_data.args[1] = LLVMConstReal(
327 base.elem_type, -1.0f);
328 break;
329 default:
330 assert(0);
331 }
332 value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
333 &clamp_emit_data);
334 }
335
336 switch(reg->Register.File) {
337 case TGSI_FILE_ADDRESS:
338 temp_ptr = bld->addr[reg->Register.Index][chan_index];
339 LLVMBuildStore(builder, value, temp_ptr);
340 continue;
341 case TGSI_FILE_OUTPUT:
342 temp_ptr = bld->outputs[reg->Register.Index][chan_index];
343 break;
344
345 case TGSI_FILE_TEMPORARY:
346 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, chan_index);
347 break;
348
349 default:
350 return;
351 }
352
353 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
354
355 LLVMBuildStore(builder, value, temp_ptr);
356 }
357 }
358
359 static void bgnloop_emit(
360 const struct lp_build_tgsi_action * action,
361 struct lp_build_tgsi_context * bld_base,
362 struct lp_build_emit_data * emit_data)
363 {
364 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
365 struct gallivm_state * gallivm = bld_base->base.gallivm;
366 LLVMBasicBlockRef loop_block;
367 LLVMBasicBlockRef endloop_block;
368 endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
369 ctx->main_fn, "ENDLOOP");
370 loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
371 endloop_block, "LOOP");
372 LLVMBuildBr(gallivm->builder, loop_block);
373 LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
374 ctx->loop_depth++;
375 ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
376 ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
377 }
378
379 static void brk_emit(
380 const struct lp_build_tgsi_action * action,
381 struct lp_build_tgsi_context * bld_base,
382 struct lp_build_emit_data * emit_data)
383 {
384 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
385 struct gallivm_state * gallivm = bld_base->base.gallivm;
386 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
387
388 LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
389 }
390
391 static void cont_emit(
392 const struct lp_build_tgsi_action * action,
393 struct lp_build_tgsi_context * bld_base,
394 struct lp_build_emit_data * emit_data)
395 {
396 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
397 struct gallivm_state * gallivm = bld_base->base.gallivm;
398 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
399
400 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
401 }
402
403 static void else_emit(
404 const struct lp_build_tgsi_action * action,
405 struct lp_build_tgsi_context * bld_base,
406 struct lp_build_emit_data * emit_data)
407 {
408 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
409 struct gallivm_state * gallivm = bld_base->base.gallivm;
410 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
411 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
412
413 /* We need to add a terminator to the current block if the previous
414 * instruction was an ENDIF.Example:
415 * IF
416 * [code]
417 * IF
418 * [code]
419 * ELSE
420 * [code]
421 * ENDIF <--
422 * ELSE<--
423 * [code]
424 * ENDIF
425 */
426
427 if (current_block != current_branch->if_block) {
428 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
429 }
430 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
431 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
432 }
433 current_branch->has_else = 1;
434 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
435 }
436
437 static void endif_emit(
438 const struct lp_build_tgsi_action * action,
439 struct lp_build_tgsi_context * bld_base,
440 struct lp_build_emit_data * emit_data)
441 {
442 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
443 struct gallivm_state * gallivm = bld_base->base.gallivm;
444 struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
445 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
446
447 /* If we have consecutive ENDIF instructions, then the first ENDIF
448 * will not have a terminator, so we need to add one. */
449 if (current_block != current_branch->if_block
450 && current_block != current_branch->else_block
451 && !LLVMGetBasicBlockTerminator(current_block)) {
452
453 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
454 }
455 if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
456 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
457 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
458 }
459
460 if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
461 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
462 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
463 }
464
465 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
466 ctx->branch_depth--;
467 }
468
469 static void endloop_emit(
470 const struct lp_build_tgsi_action * action,
471 struct lp_build_tgsi_context * bld_base,
472 struct lp_build_emit_data * emit_data)
473 {
474 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
475 struct gallivm_state * gallivm = bld_base->base.gallivm;
476 struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
477
478 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
479 LLVMBuildBr(gallivm->builder, current_loop->loop_block);
480 }
481
482 LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
483 ctx->loop_depth--;
484 }
485
486 static void if_emit(
487 const struct lp_build_tgsi_action * action,
488 struct lp_build_tgsi_context * bld_base,
489 struct lp_build_emit_data * emit_data)
490 {
491 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
492 struct gallivm_state * gallivm = bld_base->base.gallivm;
493 LLVMValueRef cond;
494 LLVMBasicBlockRef if_block, else_block, endif_block;
495
496 cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
497 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
498 bld_base->int_bld.zero, "");
499
500 endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
501 ctx->main_fn, "ENDIF");
502 if_block = LLVMInsertBasicBlockInContext(gallivm->context,
503 endif_block, "IF");
504 else_block = LLVMInsertBasicBlockInContext(gallivm->context,
505 endif_block, "ELSE");
506 LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
507 LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
508
509 ctx->branch_depth++;
510 ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
511 ctx->branch[ctx->branch_depth - 1].if_block = if_block;
512 ctx->branch[ctx->branch_depth - 1].else_block = else_block;
513 ctx->branch[ctx->branch_depth - 1].has_else = 0;
514 }
515
516 static void kil_emit(
517 const struct lp_build_tgsi_action * action,
518 struct lp_build_tgsi_context * bld_base,
519 struct lp_build_emit_data * emit_data)
520 {
521 unsigned i;
522 for (i = 0; i < emit_data->arg_count; i++) {
523 emit_data->output[i] = lp_build_intrinsic_unary(
524 bld_base->base.gallivm->builder,
525 action->intr_name,
526 emit_data->dst_type, emit_data->args[i]);
527 }
528 }
529
530 /* coord_arg - index of the source coord vector in the emit_data->args array */
531 void radeon_llvm_emit_prepare_cube_coords(
532 struct lp_build_tgsi_context * bld_base,
533 struct lp_build_emit_data * emit_data,
534 LLVMValueRef *coords_arg)
535 {
536
537 unsigned target = emit_data->inst->Texture.Texture;
538 unsigned opcode = emit_data->inst->Instruction.Opcode;
539 struct gallivm_state * gallivm = bld_base->base.gallivm;
540 LLVMBuilderRef builder = gallivm->builder;
541 LLVMTypeRef type = bld_base->base.elem_type;
542 LLVMValueRef coords[4];
543 LLVMValueRef mad_args[3];
544 LLVMValueRef idx;
545 struct LLVMOpaqueValue *cube_vec;
546 LLVMValueRef v;
547 unsigned i;
548
549 cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
550 v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
551 &cube_vec, 1, LLVMReadNoneAttribute);
552
553 for (i = 0; i < 4; ++i) {
554 idx = lp_build_const_int32(gallivm, i);
555 coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
556 }
557
558 coords[2] = build_intrinsic(builder, "fabs",
559 type, &coords[2], 1, LLVMReadNoneAttribute);
560 coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]);
561
562 mad_args[1] = coords[2];
563 mad_args[2] = LLVMConstReal(type, 1.5);
564
565 mad_args[0] = coords[0];
566 coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
567 mad_args[0], mad_args[1], mad_args[2]);
568
569 mad_args[0] = coords[1];
570 coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
571 mad_args[0], mad_args[1], mad_args[2]);
572
573 /* apply xyz = yxw swizzle to cooords */
574 coords[2] = coords[3];
575 coords[3] = coords[1];
576 coords[1] = coords[0];
577 coords[0] = coords[3];
578
579 /* all cases except simple cube map sampling require special handling
580 * for coord vector */
581 if (target != TGSI_TEXTURE_CUBE ||
582 opcode != TGSI_OPCODE_TEX) {
583
584 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
585 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
586 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
587
588 /* coords_arg.w component - array_index for cube arrays or
589 * compare value for SHADOWCUBE */
590 coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
591 coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
592 }
593
594 /* for instructions that need additional src (compare/lod/bias),
595 * put it in coord.w */
596 if (opcode == TGSI_OPCODE_TEX2 ||
597 opcode == TGSI_OPCODE_TXB2 ||
598 opcode == TGSI_OPCODE_TXL2) {
599 coords[3] = coords_arg[4];
600 }
601 }
602
603 memcpy(coords_arg, coords, sizeof(coords));
604 }
605
606 static void txd_fetch_args(
607 struct lp_build_tgsi_context * bld_base,
608 struct lp_build_emit_data * emit_data)
609 {
610 const struct tgsi_full_instruction * inst = emit_data->inst;
611
612 LLVMValueRef coords[4];
613 unsigned chan, src;
614 for (src = 0; src < 3; src++) {
615 for (chan = 0; chan < 4; chan++)
616 coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan);
617
618 emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm,
619 coords, 4);
620 }
621 emit_data->arg_count = 3;
622 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
623 }
624
625
626 static void txp_fetch_args(
627 struct lp_build_tgsi_context * bld_base,
628 struct lp_build_emit_data * emit_data)
629 {
630 const struct tgsi_full_instruction * inst = emit_data->inst;
631 LLVMValueRef src_w;
632 unsigned chan;
633 LLVMValueRef coords[4];
634
635 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
636 src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
637
638 for (chan = 0; chan < 3; chan++ ) {
639 LLVMValueRef arg = lp_build_emit_fetch(bld_base,
640 emit_data->inst, 0, chan);
641 coords[chan] = lp_build_emit_llvm_binary(bld_base,
642 TGSI_OPCODE_DIV, arg, src_w);
643 }
644 coords[3] = bld_base->base.one;
645
646 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
647 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
648 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
649 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
650 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
651 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
652 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
653 }
654
655 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
656 coords, 4);
657 emit_data->arg_count = 1;
658 }
659
660 static void tex_fetch_args(
661 struct lp_build_tgsi_context * bld_base,
662 struct lp_build_emit_data * emit_data)
663 {
664 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
665 * when we used CHAN_ALL. We should be able to get this to work,
666 * but for now we will swizzle it ourselves
667 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
668 0, CHAN_ALL);
669
670 */
671
672 const struct tgsi_full_instruction * inst = emit_data->inst;
673
674 LLVMValueRef coords[5];
675 unsigned chan;
676 for (chan = 0; chan < 4; chan++) {
677 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
678 }
679
680 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
681 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
682 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
683 /* These instructions have additional operand that should be packed
684 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
685 * That operand should be passed as a float value in the args array
686 * right after the coord vector. After packing it's not used anymore,
687 * that's why arg_count is not increased */
688 coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
689 }
690
691 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
692 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
693 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
694 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
695 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
696 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
697 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
698 }
699
700 emit_data->arg_count = 1;
701 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
702 coords, 4);
703 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
704 }
705
706 static void txf_fetch_args(
707 struct lp_build_tgsi_context * bld_base,
708 struct lp_build_emit_data * emit_data)
709 {
710 const struct tgsi_full_instruction * inst = emit_data->inst;
711 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
712 const struct tgsi_texture_offset * off = inst->TexOffsets;
713 LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
714
715 /* fetch tex coords */
716 tex_fetch_args(bld_base, emit_data);
717
718 /* fetch tex offsets */
719 if (inst->Texture.NumOffsets) {
720 assert(inst->Texture.NumOffsets == 1);
721
722 emit_data->args[1] = LLVMConstBitCast(
723 bld->immediates[off->Index][off->SwizzleX],
724 offset_type);
725 emit_data->args[2] = LLVMConstBitCast(
726 bld->immediates[off->Index][off->SwizzleY],
727 offset_type);
728 emit_data->args[3] = LLVMConstBitCast(
729 bld->immediates[off->Index][off->SwizzleZ],
730 offset_type);
731 } else {
732 emit_data->args[1] = bld_base->int_bld.zero;
733 emit_data->args[2] = bld_base->int_bld.zero;
734 emit_data->args[3] = bld_base->int_bld.zero;
735 }
736
737 emit_data->arg_count = 4;
738 }
739
740 static void emit_icmp(
741 const struct lp_build_tgsi_action * action,
742 struct lp_build_tgsi_context * bld_base,
743 struct lp_build_emit_data * emit_data)
744 {
745 unsigned pred;
746 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
747 LLVMContextRef context = bld_base->base.gallivm->context;
748
749 switch (emit_data->inst->Instruction.Opcode) {
750 case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
751 case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
752 case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
753 case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
754 case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
755 case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
756 default:
757 assert(!"unknown instruction");
758 }
759
760 LLVMValueRef v = LLVMBuildICmp(builder, pred,
761 emit_data->args[0], emit_data->args[1],"");
762
763 v = LLVMBuildSExtOrBitCast(builder, v,
764 LLVMInt32TypeInContext(context), "");
765
766 emit_data->output[emit_data->chan] = v;
767 }
768
769 static void emit_ucmp(
770 const struct lp_build_tgsi_action * action,
771 struct lp_build_tgsi_context * bld_base,
772 struct lp_build_emit_data * emit_data)
773 {
774 unsigned pred;
775 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
776 LLVMContextRef context = bld_base->base.gallivm->context;
777
778
779 LLVMValueRef v = LLVMBuildFCmp(builder, LLVMRealUGE,
780 emit_data->args[0], lp_build_const_float(bld_base->base.gallivm, 0.), "");
781
782 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, v, emit_data->args[2], emit_data->args[1], "");
783 }
784
785 static void emit_cmp(
786 const struct lp_build_tgsi_action *action,
787 struct lp_build_tgsi_context * bld_base,
788 struct lp_build_emit_data * emit_data)
789 {
790 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
791 LLVMRealPredicate pred;
792 LLVMValueRef cond;
793
794 /* XXX I'm not sure whether to do unordered or ordered comparisons,
795 * but llvmpipe uses unordered comparisons, so for consistency we use
796 * unordered. (The authors of llvmpipe aren't sure about using
797 * unordered vs ordered comparisons either.
798 */
799 switch (emit_data->inst->Instruction.Opcode) {
800 case TGSI_OPCODE_SGE: pred = LLVMRealUGE; break;
801 case TGSI_OPCODE_SEQ: pred = LLVMRealUEQ; break;
802 case TGSI_OPCODE_SLE: pred = LLVMRealULE; break;
803 case TGSI_OPCODE_SLT: pred = LLVMRealULT; break;
804 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
805 case TGSI_OPCODE_SGT: pred = LLVMRealUGT; break;
806 default: assert(!"unknown instruction");
807 }
808
809 cond = LLVMBuildFCmp(builder,
810 pred, emit_data->args[0], emit_data->args[1], "");
811
812 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
813 cond, bld_base->base.one, bld_base->base.zero, "");
814 }
815
816 static void emit_not(
817 const struct lp_build_tgsi_action * action,
818 struct lp_build_tgsi_context * bld_base,
819 struct lp_build_emit_data * emit_data)
820 {
821 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
822 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
823 emit_data->args[0]);
824 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
825 }
826
827 static void emit_arl(
828 const struct lp_build_tgsi_action * action,
829 struct lp_build_tgsi_context * bld_base,
830 struct lp_build_emit_data * emit_data)
831 {
832 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
833 LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
834 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
835 floor_index, bld_base->base.int_elem_type , "");
836 }
837
838 static void emit_and(
839 const struct lp_build_tgsi_action * action,
840 struct lp_build_tgsi_context * bld_base,
841 struct lp_build_emit_data * emit_data)
842 {
843 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
844 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
845 emit_data->args[0], emit_data->args[1], "");
846 }
847
848 static void emit_or(
849 const struct lp_build_tgsi_action * action,
850 struct lp_build_tgsi_context * bld_base,
851 struct lp_build_emit_data * emit_data)
852 {
853 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
854 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
855 emit_data->args[0], emit_data->args[1], "");
856 }
857
858 static void emit_uadd(
859 const struct lp_build_tgsi_action * action,
860 struct lp_build_tgsi_context * bld_base,
861 struct lp_build_emit_data * emit_data)
862 {
863 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
864 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
865 emit_data->args[0], emit_data->args[1], "");
866 }
867
868 static void emit_udiv(
869 const struct lp_build_tgsi_action * action,
870 struct lp_build_tgsi_context * bld_base,
871 struct lp_build_emit_data * emit_data)
872 {
873 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
874 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
875 emit_data->args[0], emit_data->args[1], "");
876 }
877
878 static void emit_idiv(
879 const struct lp_build_tgsi_action * action,
880 struct lp_build_tgsi_context * bld_base,
881 struct lp_build_emit_data * emit_data)
882 {
883 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
884 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
885 emit_data->args[0], emit_data->args[1], "");
886 }
887
888 static void emit_mod(
889 const struct lp_build_tgsi_action * action,
890 struct lp_build_tgsi_context * bld_base,
891 struct lp_build_emit_data * emit_data)
892 {
893 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
894 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
895 emit_data->args[0], emit_data->args[1], "");
896 }
897
898 static void emit_umod(
899 const struct lp_build_tgsi_action * action,
900 struct lp_build_tgsi_context * bld_base,
901 struct lp_build_emit_data * emit_data)
902 {
903 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
904 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
905 emit_data->args[0], emit_data->args[1], "");
906 }
907
908 static void emit_shl(
909 const struct lp_build_tgsi_action * action,
910 struct lp_build_tgsi_context * bld_base,
911 struct lp_build_emit_data * emit_data)
912 {
913 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
914 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
915 emit_data->args[0], emit_data->args[1], "");
916 }
917
918 static void emit_ushr(
919 const struct lp_build_tgsi_action * action,
920 struct lp_build_tgsi_context * bld_base,
921 struct lp_build_emit_data * emit_data)
922 {
923 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
924 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
925 emit_data->args[0], emit_data->args[1], "");
926 }
927 static void emit_ishr(
928 const struct lp_build_tgsi_action * action,
929 struct lp_build_tgsi_context * bld_base,
930 struct lp_build_emit_data * emit_data)
931 {
932 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
933 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
934 emit_data->args[0], emit_data->args[1], "");
935 }
936
937 static void emit_xor(
938 const struct lp_build_tgsi_action * action,
939 struct lp_build_tgsi_context * bld_base,
940 struct lp_build_emit_data * emit_data)
941 {
942 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
943 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
944 emit_data->args[0], emit_data->args[1], "");
945 }
946
947 static void emit_ssg(
948 const struct lp_build_tgsi_action * action,
949 struct lp_build_tgsi_context * bld_base,
950 struct lp_build_emit_data * emit_data)
951 {
952 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
953
954 LLVMValueRef cmp, val;
955
956 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
957 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
958 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
959 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
960 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
961 } else { // float SSG
962 cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->base.zero, "");
963 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
964 cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, "");
965 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
966 }
967
968 emit_data->output[emit_data->chan] = val;
969 }
970
971 static void emit_ineg(
972 const struct lp_build_tgsi_action * action,
973 struct lp_build_tgsi_context * bld_base,
974 struct lp_build_emit_data * emit_data)
975 {
976 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
977 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
978 emit_data->args[0], "");
979 }
980
981 static void emit_f2i(
982 const struct lp_build_tgsi_action * action,
983 struct lp_build_tgsi_context * bld_base,
984 struct lp_build_emit_data * emit_data)
985 {
986 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
987 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
988 emit_data->args[0], bld_base->int_bld.elem_type, "");
989 }
990
991 static void emit_f2u(
992 const struct lp_build_tgsi_action * action,
993 struct lp_build_tgsi_context * bld_base,
994 struct lp_build_emit_data * emit_data)
995 {
996 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
997 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
998 emit_data->args[0], bld_base->uint_bld.elem_type, "");
999 }
1000
1001 static void emit_i2f(
1002 const struct lp_build_tgsi_action * action,
1003 struct lp_build_tgsi_context * bld_base,
1004 struct lp_build_emit_data * emit_data)
1005 {
1006 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1007 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
1008 emit_data->args[0], bld_base->base.elem_type, "");
1009 }
1010
1011 static void emit_u2f(
1012 const struct lp_build_tgsi_action * action,
1013 struct lp_build_tgsi_context * bld_base,
1014 struct lp_build_emit_data * emit_data)
1015 {
1016 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
1017 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
1018 emit_data->args[0], bld_base->base.elem_type, "");
1019 }
1020
1021 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
1022 const struct tgsi_full_immediate *imm)
1023 {
1024 unsigned i;
1025 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
1026
1027 for (i = 0; i < 4; ++i) {
1028 ctx->soa.immediates[ctx->soa.num_immediates][i] =
1029 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false );
1030 }
1031
1032 ctx->soa.num_immediates++;
1033 }
1034
1035 LLVMValueRef
1036 build_intrinsic(LLVMBuilderRef builder,
1037 const char *name,
1038 LLVMTypeRef ret_type,
1039 LLVMValueRef *args,
1040 unsigned num_args,
1041 LLVMAttribute attr)
1042 {
1043 LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
1044 LLVMValueRef function;
1045
1046 function = LLVMGetNamedFunction(module, name);
1047 if(!function) {
1048 LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
1049 unsigned i;
1050
1051 assert(num_args <= LP_MAX_FUNC_ARGS);
1052
1053 for(i = 0; i < num_args; ++i) {
1054 assert(args[i]);
1055 arg_types[i] = LLVMTypeOf(args[i]);
1056 }
1057
1058 function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
1059
1060 if (attr)
1061 LLVMAddFunctionAttr(function, attr);
1062 }
1063
1064 return LLVMBuildCall(builder, function, args, num_args, "");
1065 }
1066
1067 static void build_tgsi_intrinsic(
1068 const struct lp_build_tgsi_action * action,
1069 struct lp_build_tgsi_context * bld_base,
1070 struct lp_build_emit_data * emit_data,
1071 LLVMAttribute attr)
1072 {
1073 struct lp_build_context * base = &bld_base->base;
1074 emit_data->output[emit_data->chan] = build_intrinsic(
1075 base->gallivm->builder, action->intr_name,
1076 emit_data->dst_type, emit_data->args,
1077 emit_data->arg_count, attr);
1078 }
1079 void
1080 build_tgsi_intrinsic_nomem(
1081 const struct lp_build_tgsi_action * action,
1082 struct lp_build_tgsi_context * bld_base,
1083 struct lp_build_emit_data * emit_data)
1084 {
1085 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadNoneAttribute);
1086 }
1087
1088 static void build_tgsi_intrinsic_readonly(
1089 const struct lp_build_tgsi_action * action,
1090 struct lp_build_tgsi_context * bld_base,
1091 struct lp_build_emit_data * emit_data)
1092 {
1093 build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadOnlyAttribute);
1094 }
1095
1096 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
1097 {
1098 struct lp_type type;
1099 LLVMTypeRef main_fn_type;
1100 LLVMBasicBlockRef main_fn_body;
1101
1102 /* Initialize the gallivm object:
1103 * We are only using the module, context, and builder fields of this struct.
1104 * This should be enough for us to be able to pass our gallivm struct to the
1105 * helper functions in the gallivm module.
1106 */
1107 memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
1108 memset(&ctx->soa, 0, sizeof(ctx->soa));
1109 ctx->gallivm.context = LLVMContextCreate();
1110 ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
1111 ctx->gallivm.context);
1112 ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
1113
1114 /* Setup the module */
1115 main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context),
1116 NULL, 0, 0);
1117 ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1118 main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1119 ctx->main_fn, "main_body");
1120 LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1121
1122 ctx->store_output_intr = "llvm.AMDGPU.store.output.";
1123 ctx->swizzle_intr = "llvm.AMDGPU.swizzle";
1124 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1125
1126 /* XXX: We need to revisit this.I think the correct way to do this is
1127 * to use length = 4 here and use the elem_bld for everything. */
1128 type.floating = TRUE;
1129 type.sign = TRUE;
1130 type.width = 32;
1131 type.length = 1;
1132
1133 lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1134 lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1135 lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1136
1137 bld_base->soa = 1;
1138 bld_base->emit_store = emit_store;
1139 bld_base->emit_swizzle = emit_swizzle;
1140 bld_base->emit_declaration = emit_declaration;
1141 bld_base->emit_immediate = emit_immediate;
1142
1143 bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch_immediate;
1144 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch_input;
1145 bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch_temporary;
1146 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch_output;
1147
1148 /* Allocate outputs */
1149 ctx->soa.outputs = ctx->outputs;
1150
1151 /* XXX: Is there a better way to initialize all this ? */
1152
1153 lp_set_default_actions(bld_base);
1154
1155 bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
1156 bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
1157 bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
1158 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1159 bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1160 bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1161 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
1162 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
1163 bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1164 bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
1165 bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
1166 bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
1167 bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1168 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly;
1169 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
1170 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
1171 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
1172 bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
1173 bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
1174 bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1175 bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1176 bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1177 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1178 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
1179 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_readonly;
1180 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
1181 bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
1182 bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
1183 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1184 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1185 bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
1186 bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
1187 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1188 bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1189 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1190 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
1191 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
1192 bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
1193 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1194 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1195 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1196 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1197 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1198 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1199 bld_base->op_actions[TGSI_OPCODE_KIL].emit = kil_emit;
1200 bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill";
1201 bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic;
1202 bld_base->op_actions[TGSI_OPCODE_KILP].intr_name = "llvm.AMDGPU.kilp";
1203 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_readonly;
1204 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
1205 bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
1206 bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
1207 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1208 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1209 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1210 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly;
1211 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
1212 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1213 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
1214 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
1215 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
1216 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1217 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
1218 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
1219 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
1220 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
1221 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly;
1222 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
1223 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1224 bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
1225 bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
1226 bld_base->op_actions[TGSI_OPCODE_TEX2].fetch_args = tex_fetch_args;
1227 bld_base->op_actions[TGSI_OPCODE_TEX2].intr_name = "llvm.AMDGPU.tex";
1228 bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
1229 bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
1230 bld_base->op_actions[TGSI_OPCODE_TXB2].fetch_args = tex_fetch_args;
1231 bld_base->op_actions[TGSI_OPCODE_TXB2].intr_name = "llvm.AMDGPU.txb";
1232 bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
1233 bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
1234 bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
1235 bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
1236 bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
1237 bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
1238 bld_base->op_actions[TGSI_OPCODE_TXL2].fetch_args = tex_fetch_args;
1239 bld_base->op_actions[TGSI_OPCODE_TXL2].intr_name = "llvm.AMDGPU.txl";
1240 bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
1241 bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
1242 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
1243 bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
1244 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1245 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
1246 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1247 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1248 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
1249 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
1250 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
1251 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
1252 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1253 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1254 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1255 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1256 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1257 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1258 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1259 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1260 bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
1261
1262 bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
1263 bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
1264 }
1265
1266 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1267 {
1268 struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1269 /* End the main function with Return*/
1270 LLVMBuildRetVoid(gallivm->builder);
1271
1272 /* Create the pass manager */
1273 ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule(
1274 gallivm->module);
1275
1276 /* This pass should eliminate all the load and store instructions */
1277 LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1278
1279 /* Add some optimization passes */
1280 LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1281 LLVMAddCFGSimplificationPass(gallivm->passmgr);
1282
1283 /* Run the passs */
1284 LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1285
1286 LLVMDisposeBuilder(gallivm->builder);
1287 LLVMDisposePassManager(gallivm->passmgr);
1288
1289 }
1290
1291 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1292 {
1293 LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1294 LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1295 }