2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
26 #include "radeon_llvm.h"
28 #include "gallivm/lp_bld_const.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_init.h"
32 #include "gallivm/lp_bld_intr.h"
33 #include "gallivm/lp_bld_swizzle.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_debug.h"
40 #include <llvm-c/Core.h>
41 #include <llvm-c/Transforms/Scalar.h>
43 static struct radeon_llvm_loop
* get_current_loop(struct radeon_llvm_context
* ctx
)
45 return ctx
->loop_depth
> 0 ? ctx
->loop
+ (ctx
->loop_depth
- 1) : NULL
;
48 static struct radeon_llvm_branch
* get_current_branch(
49 struct radeon_llvm_context
* ctx
)
51 return ctx
->branch_depth
> 0 ?
52 ctx
->branch
+ (ctx
->branch_depth
- 1) : NULL
;
55 unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
57 return (index
* 4) + chan
;
60 static LLVMValueRef
emit_swizzle(
61 struct lp_build_tgsi_context
* bld_base
,
68 LLVMValueRef swizzles
[4];
70 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
);
72 swizzles
[0] = LLVMConstInt(i32t
, swizzle_x
, 0);
73 swizzles
[1] = LLVMConstInt(i32t
, swizzle_y
, 0);
74 swizzles
[2] = LLVMConstInt(i32t
, swizzle_z
, 0);
75 swizzles
[3] = LLVMConstInt(i32t
, swizzle_w
, 0);
77 return LLVMBuildShuffleVector(bld_base
->base
.gallivm
->builder
,
79 LLVMGetUndef(LLVMTypeOf(value
)),
80 LLVMConstVector(swizzles
, 4), "");
85 struct lp_build_tgsi_soa_context
*bld
,
86 const struct tgsi_full_src_register
*reg
,
89 struct gallivm_state
* gallivm
= bld
->bld_base
.base
.gallivm
;
91 LLVMValueRef addr
= LLVMBuildLoad(gallivm
->builder
,
92 bld
->addr
[reg
->Indirect
.Index
][swizzle
], "");
93 LLVMValueRef offset
= lp_build_const_int32(gallivm
, reg
->Register
.Index
);
94 LLVMValueRef hw_index
= LLVMBuildAdd(gallivm
->builder
, addr
, offset
, "");
95 LLVMValueRef soa_index
= LLVMBuildMul(gallivm
->builder
, hw_index
,
96 lp_build_const_int32(gallivm
, 4), "");
97 LLVMValueRef array_index
= LLVMBuildAdd(gallivm
->builder
, soa_index
,
98 lp_build_const_int32(gallivm
, swizzle
), "");
104 emit_fetch_immediate(
105 struct lp_build_tgsi_context
*bld_base
,
106 const struct tgsi_full_src_register
*reg
,
107 enum tgsi_opcode_type type
,
111 LLVMContextRef ctx
= bld_base
->base
.gallivm
->context
;
114 case TGSI_TYPE_UNSIGNED
:
115 case TGSI_TYPE_SIGNED
:
116 ctype
= LLVMInt32TypeInContext(ctx
);
118 case TGSI_TYPE_UNTYPED
:
119 case TGSI_TYPE_FLOAT
:
120 ctype
= LLVMFloatTypeInContext(ctx
);
127 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
129 LLVMValueRef values
[TGSI_NUM_CHANNELS
] = {};
131 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
132 values
[chan
] = LLVMConstBitCast(bld
->immediates
[reg
->Register
.Index
][chan
], ctype
);
134 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
137 return LLVMConstBitCast(bld
->immediates
[reg
->Register
.Index
][swizzle
], ctype
);
143 struct lp_build_tgsi_context
*bld_base
,
144 const struct tgsi_full_src_register
*reg
,
145 enum tgsi_opcode_type type
,
148 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
150 LLVMValueRef values
[TGSI_NUM_CHANNELS
] = {};
152 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
153 values
[chan
] = ctx
->inputs
[radeon_llvm_reg_index_soa(
154 reg
->Register
.Index
, chan
)];
156 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
159 return bitcast(bld_base
, type
, ctx
->inputs
[radeon_llvm_reg_index_soa(reg
->Register
.Index
, swizzle
)]);
164 emit_fetch_temporary(
165 struct lp_build_tgsi_context
*bld_base
,
166 const struct tgsi_full_src_register
*reg
,
167 enum tgsi_opcode_type type
,
170 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
171 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
173 LLVMValueRef values
[TGSI_NUM_CHANNELS
] = {};
175 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
176 values
[chan
] = emit_fetch_temporary(bld_base
, reg
, type
, chan
);
178 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
182 if (reg
->Register
.Indirect
) {
183 LLVMValueRef array_index
= emit_array_index(bld
, reg
, swizzle
);
184 LLVMValueRef ptr
= LLVMBuildGEP(builder
, bld
->temps_array
, &array_index
,
186 return LLVMBuildLoad(builder
, ptr
, "");
188 LLVMValueRef temp_ptr
;
189 temp_ptr
= lp_get_temp_ptr_soa(bld
, reg
->Register
.Index
, swizzle
);
190 return bitcast(bld_base
,type
,LLVMBuildLoad(builder
, temp_ptr
, ""));
196 struct lp_build_tgsi_context
*bld_base
,
197 const struct tgsi_full_src_register
*reg
,
198 enum tgsi_opcode_type type
,
201 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
202 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
203 if (reg
->Register
.Indirect
) {
204 LLVMValueRef array_index
= emit_array_index(bld
, reg
, swizzle
);
205 LLVMValueRef ptr
= LLVMBuildGEP(builder
, bld
->outputs_array
, &array_index
,
207 return LLVMBuildLoad(builder
, ptr
, "");
209 LLVMValueRef temp_ptr
;
210 temp_ptr
= lp_get_output_ptr(bld
, reg
->Register
.Index
, swizzle
);
211 return LLVMBuildLoad(builder
, temp_ptr
, "");
215 static void emit_declaration(
216 struct lp_build_tgsi_context
* bld_base
,
217 const struct tgsi_full_declaration
*decl
)
219 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
220 switch(decl
->Declaration
.File
) {
221 case TGSI_FILE_ADDRESS
:
224 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
226 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
227 ctx
->soa
.addr
[idx
][chan
] = lp_build_alloca(
229 ctx
->soa
.bld_base
.uint_bld
.elem_type
, "");
235 case TGSI_FILE_TEMPORARY
:
236 lp_emit_declaration_soa(bld_base
, decl
);
239 case TGSI_FILE_INPUT
:
242 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
243 ctx
->load_input(ctx
, idx
, decl
);
248 case TGSI_FILE_SYSTEM_VALUE
:
251 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
252 ctx
->load_system_value(ctx
, idx
, decl
);
257 case TGSI_FILE_OUTPUT
:
260 for (idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; idx
++) {
262 assert(idx
< RADEON_LLVM_MAX_OUTPUTS
);
263 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
264 ctx
->soa
.outputs
[idx
][chan
] = lp_build_alloca(&ctx
->gallivm
,
265 ctx
->soa
.bld_base
.base
.elem_type
, "");
269 ctx
->output_reg_count
= MAX2(ctx
->output_reg_count
,
270 decl
->Range
.Last
+ 1);
281 struct lp_build_tgsi_context
* bld_base
,
282 const struct tgsi_full_instruction
* inst
,
283 const struct tgsi_opcode_info
* info
,
286 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
287 struct gallivm_state
*gallivm
= bld
->bld_base
.base
.gallivm
;
288 struct lp_build_context base
= bld
->bld_base
.base
;
289 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[0];
290 LLVMBuilderRef builder
= bld
->bld_base
.base
.gallivm
->builder
;
291 LLVMValueRef temp_ptr
;
292 unsigned chan
, chan_index
;
293 boolean is_vec_store
= FALSE
;
295 LLVMTypeKind k
= LLVMGetTypeKind(LLVMTypeOf(dst
[0]));
296 is_vec_store
= (k
== LLVMVectorTypeKind
);
300 LLVMValueRef values
[4] = {};
301 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst
, chan
) {
302 LLVMValueRef index
= lp_build_const_int32(gallivm
, chan
);
303 values
[chan
] = LLVMBuildExtractElement(gallivm
->builder
,
306 bld_base
->emit_store(bld_base
, inst
, info
, values
);
310 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst
, chan_index
) {
311 LLVMValueRef value
= dst
[chan_index
];
313 if (inst
->Instruction
.Saturate
!= TGSI_SAT_NONE
) {
314 struct lp_build_emit_data clamp_emit_data
;
316 memset(&clamp_emit_data
, 0, sizeof(clamp_emit_data
));
317 clamp_emit_data
.arg_count
= 3;
318 clamp_emit_data
.args
[0] = value
;
319 clamp_emit_data
.args
[2] = base
.one
;
321 switch(inst
->Instruction
.Saturate
) {
322 case TGSI_SAT_ZERO_ONE
:
323 clamp_emit_data
.args
[1] = base
.zero
;
325 case TGSI_SAT_MINUS_PLUS_ONE
:
326 clamp_emit_data
.args
[1] = LLVMConstReal(
327 base
.elem_type
, -1.0f
);
332 value
= lp_build_emit_llvm(bld_base
, TGSI_OPCODE_CLAMP
,
336 switch(reg
->Register
.File
) {
337 case TGSI_FILE_ADDRESS
:
338 temp_ptr
= bld
->addr
[reg
->Register
.Index
][chan_index
];
339 LLVMBuildStore(builder
, value
, temp_ptr
);
341 case TGSI_FILE_OUTPUT
:
342 temp_ptr
= bld
->outputs
[reg
->Register
.Index
][chan_index
];
345 case TGSI_FILE_TEMPORARY
:
346 temp_ptr
= lp_get_temp_ptr_soa(bld
, reg
->Register
.Index
, chan_index
);
353 value
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, value
);
355 LLVMBuildStore(builder
, value
, temp_ptr
);
359 static void bgnloop_emit(
360 const struct lp_build_tgsi_action
* action
,
361 struct lp_build_tgsi_context
* bld_base
,
362 struct lp_build_emit_data
* emit_data
)
364 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
365 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
366 LLVMBasicBlockRef loop_block
;
367 LLVMBasicBlockRef endloop_block
;
368 endloop_block
= LLVMAppendBasicBlockInContext(gallivm
->context
,
369 ctx
->main_fn
, "ENDLOOP");
370 loop_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
371 endloop_block
, "LOOP");
372 LLVMBuildBr(gallivm
->builder
, loop_block
);
373 LLVMPositionBuilderAtEnd(gallivm
->builder
, loop_block
);
375 ctx
->loop
[ctx
->loop_depth
- 1].loop_block
= loop_block
;
376 ctx
->loop
[ctx
->loop_depth
- 1].endloop_block
= endloop_block
;
379 static void brk_emit(
380 const struct lp_build_tgsi_action
* action
,
381 struct lp_build_tgsi_context
* bld_base
,
382 struct lp_build_emit_data
* emit_data
)
384 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
385 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
386 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
388 LLVMBuildBr(gallivm
->builder
, current_loop
->endloop_block
);
391 static void cont_emit(
392 const struct lp_build_tgsi_action
* action
,
393 struct lp_build_tgsi_context
* bld_base
,
394 struct lp_build_emit_data
* emit_data
)
396 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
397 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
398 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
400 LLVMBuildBr(gallivm
->builder
, current_loop
->loop_block
);
403 static void else_emit(
404 const struct lp_build_tgsi_action
* action
,
405 struct lp_build_tgsi_context
* bld_base
,
406 struct lp_build_emit_data
* emit_data
)
408 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
409 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
410 struct radeon_llvm_branch
* current_branch
= get_current_branch(ctx
);
411 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(gallivm
->builder
);
413 /* We need to add a terminator to the current block if the previous
414 * instruction was an ENDIF.Example:
427 if (current_block
!= current_branch
->if_block
) {
428 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
430 if (!LLVMGetBasicBlockTerminator(current_branch
->if_block
)) {
431 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
433 current_branch
->has_else
= 1;
434 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->else_block
);
437 static void endif_emit(
438 const struct lp_build_tgsi_action
* action
,
439 struct lp_build_tgsi_context
* bld_base
,
440 struct lp_build_emit_data
* emit_data
)
442 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
443 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
444 struct radeon_llvm_branch
* current_branch
= get_current_branch(ctx
);
445 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(gallivm
->builder
);
447 /* If we have consecutive ENDIF instructions, then the first ENDIF
448 * will not have a terminator, so we need to add one. */
449 if (current_block
!= current_branch
->if_block
450 && current_block
!= current_branch
->else_block
451 && !LLVMGetBasicBlockTerminator(current_block
)) {
453 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
455 if (!LLVMGetBasicBlockTerminator(current_branch
->else_block
)) {
456 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->else_block
);
457 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
460 if (!LLVMGetBasicBlockTerminator(current_branch
->if_block
)) {
461 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->if_block
);
462 LLVMBuildBr(gallivm
->builder
, current_branch
->endif_block
);
465 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_branch
->endif_block
);
469 static void endloop_emit(
470 const struct lp_build_tgsi_action
* action
,
471 struct lp_build_tgsi_context
* bld_base
,
472 struct lp_build_emit_data
* emit_data
)
474 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
475 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
476 struct radeon_llvm_loop
* current_loop
= get_current_loop(ctx
);
478 if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm
->builder
))) {
479 LLVMBuildBr(gallivm
->builder
, current_loop
->loop_block
);
482 LLVMPositionBuilderAtEnd(gallivm
->builder
, current_loop
->endloop_block
);
487 const struct lp_build_tgsi_action
* action
,
488 struct lp_build_tgsi_context
* bld_base
,
489 struct lp_build_emit_data
* emit_data
)
491 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
492 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
494 LLVMBasicBlockRef if_block
, else_block
, endif_block
;
496 cond
= LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
497 bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, emit_data
->args
[0]),
498 bld_base
->int_bld
.zero
, "");
500 endif_block
= LLVMAppendBasicBlockInContext(gallivm
->context
,
501 ctx
->main_fn
, "ENDIF");
502 if_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
504 else_block
= LLVMInsertBasicBlockInContext(gallivm
->context
,
505 endif_block
, "ELSE");
506 LLVMBuildCondBr(gallivm
->builder
, cond
, if_block
, else_block
);
507 LLVMPositionBuilderAtEnd(gallivm
->builder
, if_block
);
510 ctx
->branch
[ctx
->branch_depth
- 1].endif_block
= endif_block
;
511 ctx
->branch
[ctx
->branch_depth
- 1].if_block
= if_block
;
512 ctx
->branch
[ctx
->branch_depth
- 1].else_block
= else_block
;
513 ctx
->branch
[ctx
->branch_depth
- 1].has_else
= 0;
516 static void kil_emit(
517 const struct lp_build_tgsi_action
* action
,
518 struct lp_build_tgsi_context
* bld_base
,
519 struct lp_build_emit_data
* emit_data
)
522 for (i
= 0; i
< emit_data
->arg_count
; i
++) {
523 emit_data
->output
[i
] = lp_build_intrinsic_unary(
524 bld_base
->base
.gallivm
->builder
,
526 emit_data
->dst_type
, emit_data
->args
[i
]);
530 void radeon_llvm_emit_prepare_cube_coords(
531 struct lp_build_tgsi_context
* bld_base
,
532 struct lp_build_emit_data
* emit_data
,
533 LLVMValueRef
*coords_arg
)
536 unsigned target
= emit_data
->inst
->Texture
.Texture
;
537 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
538 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
539 LLVMBuilderRef builder
= gallivm
->builder
;
540 LLVMTypeRef type
= bld_base
->base
.elem_type
;
541 LLVMValueRef coords
[4];
542 LLVMValueRef mad_args
[3];
544 struct LLVMOpaqueValue
*cube_vec
;
548 cube_vec
= lp_build_gather_values(bld_base
->base
.gallivm
, coords_arg
, 4);
549 v
= build_intrinsic(builder
, "llvm.AMDGPU.cube", LLVMVectorType(type
, 4),
550 &cube_vec
, 1, LLVMReadNoneAttribute
);
552 for (i
= 0; i
< 4; ++i
) {
553 idx
= lp_build_const_int32(gallivm
, i
);
554 coords
[i
] = LLVMBuildExtractElement(builder
, v
, idx
, "");
557 coords
[2] = build_intrinsic(builder
, "fabs",
558 type
, &coords
[2], 1, LLVMReadNoneAttribute
);
559 coords
[2] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_RCP
, coords
[2]);
561 mad_args
[1] = coords
[2];
562 mad_args
[2] = LLVMConstReal(type
, 1.5);
564 mad_args
[0] = coords
[0];
565 coords
[0] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
566 mad_args
[0], mad_args
[1], mad_args
[2]);
568 mad_args
[0] = coords
[1];
569 coords
[1] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
570 mad_args
[0], mad_args
[1], mad_args
[2]);
572 /* apply xyz = yxw swizzle to cooords */
573 coords
[2] = coords
[3];
574 coords
[3] = coords
[1];
575 coords
[1] = coords
[0];
576 coords
[0] = coords
[3];
578 /* all cases except simple cube map sampling require special handling
579 * for coord vector */
580 if (target
!= TGSI_TEXTURE_CUBE
||
581 opcode
!= TGSI_OPCODE_TEX
) {
583 /* for cube arrays coord.z = coord.w(array_index) * 8 + face */
584 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
585 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
587 /* coords_arg.w component - array_index for cube arrays or
588 * compare value for SHADOWCUBE */
589 coords
[2] = lp_build_emit_llvm_ternary(bld_base
, TGSI_OPCODE_MAD
,
590 coords_arg
[3], lp_build_const_float(gallivm
, 8.0), coords
[2]);
593 /* for instructions that need additional src (compare/lod/bias),
594 * put it in coord.w */
595 if (opcode
== TGSI_OPCODE_TEX2
||
596 opcode
== TGSI_OPCODE_TXB2
||
597 opcode
== TGSI_OPCODE_TXL2
) {
598 coords
[3] = coords_arg
[4];
602 memcpy(coords_arg
, coords
, sizeof(coords
));
605 static void txd_fetch_args(
606 struct lp_build_tgsi_context
* bld_base
,
607 struct lp_build_emit_data
* emit_data
)
609 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
611 LLVMValueRef coords
[4];
613 for (src
= 0; src
< 3; src
++) {
614 for (chan
= 0; chan
< 4; chan
++)
615 coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
617 emit_data
->args
[src
] = lp_build_gather_values(bld_base
->base
.gallivm
,
620 emit_data
->arg_count
= 3;
621 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
625 static void txp_fetch_args(
626 struct lp_build_tgsi_context
* bld_base
,
627 struct lp_build_emit_data
* emit_data
)
629 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
632 LLVMValueRef coords
[4];
634 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
635 src_w
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
637 for (chan
= 0; chan
< 3; chan
++ ) {
638 LLVMValueRef arg
= lp_build_emit_fetch(bld_base
,
639 emit_data
->inst
, 0, chan
);
640 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
641 TGSI_OPCODE_DIV
, arg
, src_w
);
643 coords
[3] = bld_base
->base
.one
;
645 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
646 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
647 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
648 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
649 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
650 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
651 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
);
654 emit_data
->args
[0] = lp_build_gather_values(bld_base
->base
.gallivm
,
656 emit_data
->arg_count
= 1;
659 static void tex_fetch_args(
660 struct lp_build_tgsi_context
* bld_base
,
661 struct lp_build_emit_data
* emit_data
)
663 /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
664 * when we used CHAN_ALL. We should be able to get this to work,
665 * but for now we will swizzle it ourselves
666 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
671 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
673 LLVMValueRef coords
[5];
675 for (chan
= 0; chan
< 4; chan
++) {
676 coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 0, chan
);
679 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
680 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
681 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
682 /* These instructions have additional operand that should be packed
683 * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
684 * That operand should be passed as a float value in the args array
685 * right after the coord vector. After packing it's not used anymore,
686 * that's why arg_count is not increased */
687 coords
[4] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
690 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
691 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
692 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
693 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
694 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
695 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
696 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
);
699 emit_data
->arg_count
= 1;
700 emit_data
->args
[0] = lp_build_gather_values(bld_base
->base
.gallivm
,
702 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
705 static void txf_fetch_args(
706 struct lp_build_tgsi_context
* bld_base
,
707 struct lp_build_emit_data
* emit_data
)
709 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
710 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
711 const struct tgsi_texture_offset
* off
= inst
->TexOffsets
;
712 LLVMTypeRef offset_type
= bld_base
->int_bld
.elem_type
;
714 /* fetch tex coords */
715 tex_fetch_args(bld_base
, emit_data
);
717 /* fetch tex offsets */
718 if (inst
->Texture
.NumOffsets
) {
719 assert(inst
->Texture
.NumOffsets
== 1);
721 emit_data
->args
[1] = LLVMConstBitCast(
722 bld
->immediates
[off
->Index
][off
->SwizzleX
],
724 emit_data
->args
[2] = LLVMConstBitCast(
725 bld
->immediates
[off
->Index
][off
->SwizzleY
],
727 emit_data
->args
[3] = LLVMConstBitCast(
728 bld
->immediates
[off
->Index
][off
->SwizzleZ
],
731 emit_data
->args
[1] = bld_base
->int_bld
.zero
;
732 emit_data
->args
[2] = bld_base
->int_bld
.zero
;
733 emit_data
->args
[3] = bld_base
->int_bld
.zero
;
736 emit_data
->arg_count
= 4;
739 static void emit_icmp(
740 const struct lp_build_tgsi_action
* action
,
741 struct lp_build_tgsi_context
* bld_base
,
742 struct lp_build_emit_data
* emit_data
)
745 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
746 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
748 switch (emit_data
->inst
->Instruction
.Opcode
) {
749 case TGSI_OPCODE_USEQ
: pred
= LLVMIntEQ
; break;
750 case TGSI_OPCODE_USNE
: pred
= LLVMIntNE
; break;
751 case TGSI_OPCODE_USGE
: pred
= LLVMIntUGE
; break;
752 case TGSI_OPCODE_USLT
: pred
= LLVMIntULT
; break;
753 case TGSI_OPCODE_ISGE
: pred
= LLVMIntSGE
; break;
754 case TGSI_OPCODE_ISLT
: pred
= LLVMIntSLT
; break;
756 assert(!"unknown instruction");
759 LLVMValueRef v
= LLVMBuildICmp(builder
, pred
,
760 emit_data
->args
[0], emit_data
->args
[1],"");
762 v
= LLVMBuildSExtOrBitCast(builder
, v
,
763 LLVMInt32TypeInContext(context
), "");
765 emit_data
->output
[emit_data
->chan
] = v
;
768 static void emit_ucmp(
769 const struct lp_build_tgsi_action
* action
,
770 struct lp_build_tgsi_context
* bld_base
,
771 struct lp_build_emit_data
* emit_data
)
774 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
775 LLVMContextRef context
= bld_base
->base
.gallivm
->context
;
778 LLVMValueRef v
= LLVMBuildFCmp(builder
, LLVMRealUGE
,
779 emit_data
->args
[0], lp_build_const_float(bld_base
->base
.gallivm
, 0.), "");
781 emit_data
->output
[emit_data
->chan
] = LLVMBuildSelect(builder
, v
, emit_data
->args
[2], emit_data
->args
[1], "");
784 static void emit_cmp(
785 const struct lp_build_tgsi_action
*action
,
786 struct lp_build_tgsi_context
* bld_base
,
787 struct lp_build_emit_data
* emit_data
)
789 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
790 LLVMRealPredicate pred
;
793 /* XXX I'm not sure whether to do unordered or ordered comparisons,
794 * but llvmpipe uses unordered comparisons, so for consistency we use
795 * unordered. (The authors of llvmpipe aren't sure about using
796 * unordered vs ordered comparisons either.
798 switch (emit_data
->inst
->Instruction
.Opcode
) {
799 case TGSI_OPCODE_SGE
: pred
= LLVMRealUGE
; break;
800 case TGSI_OPCODE_SEQ
: pred
= LLVMRealUEQ
; break;
801 case TGSI_OPCODE_SLE
: pred
= LLVMRealULE
; break;
802 case TGSI_OPCODE_SLT
: pred
= LLVMRealULT
; break;
803 case TGSI_OPCODE_SNE
: pred
= LLVMRealUNE
; break;
804 case TGSI_OPCODE_SGT
: pred
= LLVMRealUGT
; break;
805 default: assert(!"unknown instruction");
808 cond
= LLVMBuildFCmp(builder
,
809 pred
, emit_data
->args
[0], emit_data
->args
[1], "");
811 emit_data
->output
[emit_data
->chan
] = LLVMBuildSelect(builder
,
812 cond
, bld_base
->base
.one
, bld_base
->base
.zero
, "");
815 static void emit_not(
816 const struct lp_build_tgsi_action
* action
,
817 struct lp_build_tgsi_context
* bld_base
,
818 struct lp_build_emit_data
* emit_data
)
820 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
821 LLVMValueRef v
= bitcast(bld_base
, TGSI_TYPE_UNSIGNED
,
823 emit_data
->output
[emit_data
->chan
] = LLVMBuildNot(builder
, v
, "");
826 static void emit_arl(
827 const struct lp_build_tgsi_action
* action
,
828 struct lp_build_tgsi_context
* bld_base
,
829 struct lp_build_emit_data
* emit_data
)
831 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
832 LLVMValueRef floor_index
= lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_FLR
, emit_data
->args
[0]);
833 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToSI(builder
,
834 floor_index
, bld_base
->base
.int_elem_type
, "");
837 static void emit_and(
838 const struct lp_build_tgsi_action
* action
,
839 struct lp_build_tgsi_context
* bld_base
,
840 struct lp_build_emit_data
* emit_data
)
842 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
843 emit_data
->output
[emit_data
->chan
] = LLVMBuildAnd(builder
,
844 emit_data
->args
[0], emit_data
->args
[1], "");
848 const struct lp_build_tgsi_action
* action
,
849 struct lp_build_tgsi_context
* bld_base
,
850 struct lp_build_emit_data
* emit_data
)
852 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
853 emit_data
->output
[emit_data
->chan
] = LLVMBuildOr(builder
,
854 emit_data
->args
[0], emit_data
->args
[1], "");
857 static void emit_uadd(
858 const struct lp_build_tgsi_action
* action
,
859 struct lp_build_tgsi_context
* bld_base
,
860 struct lp_build_emit_data
* emit_data
)
862 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
863 emit_data
->output
[emit_data
->chan
] = LLVMBuildAdd(builder
,
864 emit_data
->args
[0], emit_data
->args
[1], "");
867 static void emit_udiv(
868 const struct lp_build_tgsi_action
* action
,
869 struct lp_build_tgsi_context
* bld_base
,
870 struct lp_build_emit_data
* emit_data
)
872 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
873 emit_data
->output
[emit_data
->chan
] = LLVMBuildUDiv(builder
,
874 emit_data
->args
[0], emit_data
->args
[1], "");
877 static void emit_idiv(
878 const struct lp_build_tgsi_action
* action
,
879 struct lp_build_tgsi_context
* bld_base
,
880 struct lp_build_emit_data
* emit_data
)
882 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
883 emit_data
->output
[emit_data
->chan
] = LLVMBuildSDiv(builder
,
884 emit_data
->args
[0], emit_data
->args
[1], "");
887 static void emit_mod(
888 const struct lp_build_tgsi_action
* action
,
889 struct lp_build_tgsi_context
* bld_base
,
890 struct lp_build_emit_data
* emit_data
)
892 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
893 emit_data
->output
[emit_data
->chan
] = LLVMBuildSRem(builder
,
894 emit_data
->args
[0], emit_data
->args
[1], "");
897 static void emit_umod(
898 const struct lp_build_tgsi_action
* action
,
899 struct lp_build_tgsi_context
* bld_base
,
900 struct lp_build_emit_data
* emit_data
)
902 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
903 emit_data
->output
[emit_data
->chan
] = LLVMBuildURem(builder
,
904 emit_data
->args
[0], emit_data
->args
[1], "");
907 static void emit_shl(
908 const struct lp_build_tgsi_action
* action
,
909 struct lp_build_tgsi_context
* bld_base
,
910 struct lp_build_emit_data
* emit_data
)
912 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
913 emit_data
->output
[emit_data
->chan
] = LLVMBuildShl(builder
,
914 emit_data
->args
[0], emit_data
->args
[1], "");
917 static void emit_ushr(
918 const struct lp_build_tgsi_action
* action
,
919 struct lp_build_tgsi_context
* bld_base
,
920 struct lp_build_emit_data
* emit_data
)
922 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
923 emit_data
->output
[emit_data
->chan
] = LLVMBuildLShr(builder
,
924 emit_data
->args
[0], emit_data
->args
[1], "");
926 static void emit_ishr(
927 const struct lp_build_tgsi_action
* action
,
928 struct lp_build_tgsi_context
* bld_base
,
929 struct lp_build_emit_data
* emit_data
)
931 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
932 emit_data
->output
[emit_data
->chan
] = LLVMBuildAShr(builder
,
933 emit_data
->args
[0], emit_data
->args
[1], "");
936 static void emit_xor(
937 const struct lp_build_tgsi_action
* action
,
938 struct lp_build_tgsi_context
* bld_base
,
939 struct lp_build_emit_data
* emit_data
)
941 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
942 emit_data
->output
[emit_data
->chan
] = LLVMBuildXor(builder
,
943 emit_data
->args
[0], emit_data
->args
[1], "");
946 static void emit_ssg(
947 const struct lp_build_tgsi_action
* action
,
948 struct lp_build_tgsi_context
* bld_base
,
949 struct lp_build_emit_data
* emit_data
)
951 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
953 LLVMValueRef cmp
, val
;
955 if (emit_data
->inst
->Instruction
.Opcode
== TGSI_OPCODE_ISSG
) {
956 cmp
= LLVMBuildICmp(builder
, LLVMIntSGT
, emit_data
->args
[0], bld_base
->int_bld
.zero
, "");
957 val
= LLVMBuildSelect(builder
, cmp
, bld_base
->int_bld
.one
, emit_data
->args
[0], "");
958 cmp
= LLVMBuildICmp(builder
, LLVMIntSGE
, val
, bld_base
->int_bld
.zero
, "");
959 val
= LLVMBuildSelect(builder
, cmp
, val
, LLVMConstInt(bld_base
->int_bld
.elem_type
, -1, true), "");
960 } else { // float SSG
961 cmp
= LLVMBuildFCmp(builder
, LLVMRealUGT
, emit_data
->args
[0], bld_base
->base
.zero
, "");
962 val
= LLVMBuildSelect(builder
, cmp
, bld_base
->base
.one
, emit_data
->args
[0], "");
963 cmp
= LLVMBuildFCmp(builder
, LLVMRealUGE
, val
, bld_base
->base
.zero
, "");
964 val
= LLVMBuildSelect(builder
, cmp
, val
, LLVMConstReal(bld_base
->base
.elem_type
, -1), "");
967 emit_data
->output
[emit_data
->chan
] = val
;
970 static void emit_ineg(
971 const struct lp_build_tgsi_action
* action
,
972 struct lp_build_tgsi_context
* bld_base
,
973 struct lp_build_emit_data
* emit_data
)
975 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
976 emit_data
->output
[emit_data
->chan
] = LLVMBuildNeg(builder
,
977 emit_data
->args
[0], "");
980 static void emit_f2i(
981 const struct lp_build_tgsi_action
* action
,
982 struct lp_build_tgsi_context
* bld_base
,
983 struct lp_build_emit_data
* emit_data
)
985 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
986 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToSI(builder
,
987 emit_data
->args
[0], bld_base
->int_bld
.elem_type
, "");
990 static void emit_f2u(
991 const struct lp_build_tgsi_action
* action
,
992 struct lp_build_tgsi_context
* bld_base
,
993 struct lp_build_emit_data
* emit_data
)
995 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
996 emit_data
->output
[emit_data
->chan
] = LLVMBuildFPToUI(builder
,
997 emit_data
->args
[0], bld_base
->uint_bld
.elem_type
, "");
1000 static void emit_i2f(
1001 const struct lp_build_tgsi_action
* action
,
1002 struct lp_build_tgsi_context
* bld_base
,
1003 struct lp_build_emit_data
* emit_data
)
1005 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1006 emit_data
->output
[emit_data
->chan
] = LLVMBuildSIToFP(builder
,
1007 emit_data
->args
[0], bld_base
->base
.elem_type
, "");
1010 static void emit_u2f(
1011 const struct lp_build_tgsi_action
* action
,
1012 struct lp_build_tgsi_context
* bld_base
,
1013 struct lp_build_emit_data
* emit_data
)
1015 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
1016 emit_data
->output
[emit_data
->chan
] = LLVMBuildUIToFP(builder
,
1017 emit_data
->args
[0], bld_base
->base
.elem_type
, "");
1020 static void emit_immediate(struct lp_build_tgsi_context
* bld_base
,
1021 const struct tgsi_full_immediate
*imm
)
1024 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
1026 for (i
= 0; i
< 4; ++i
) {
1027 ctx
->soa
.immediates
[ctx
->soa
.num_immediates
][i
] =
1028 LLVMConstInt(bld_base
->uint_bld
.elem_type
, imm
->u
[i
].Uint
, false );
1031 ctx
->soa
.num_immediates
++;
1035 build_intrinsic(LLVMBuilderRef builder
,
1037 LLVMTypeRef ret_type
,
1042 LLVMModuleRef module
= LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder
)));
1043 LLVMValueRef function
;
1045 function
= LLVMGetNamedFunction(module
, name
);
1047 LLVMTypeRef arg_types
[LP_MAX_FUNC_ARGS
];
1050 assert(num_args
<= LP_MAX_FUNC_ARGS
);
1052 for(i
= 0; i
< num_args
; ++i
) {
1054 arg_types
[i
] = LLVMTypeOf(args
[i
]);
1057 function
= lp_declare_intrinsic(module
, name
, ret_type
, arg_types
, num_args
);
1060 LLVMAddFunctionAttr(function
, attr
);
1063 return LLVMBuildCall(builder
, function
, args
, num_args
, "");
1066 static void build_tgsi_intrinsic(
1067 const struct lp_build_tgsi_action
* action
,
1068 struct lp_build_tgsi_context
* bld_base
,
1069 struct lp_build_emit_data
* emit_data
,
1072 struct lp_build_context
* base
= &bld_base
->base
;
1073 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1074 base
->gallivm
->builder
, action
->intr_name
,
1075 emit_data
->dst_type
, emit_data
->args
,
1076 emit_data
->arg_count
, attr
);
1079 build_tgsi_intrinsic_nomem(
1080 const struct lp_build_tgsi_action
* action
,
1081 struct lp_build_tgsi_context
* bld_base
,
1082 struct lp_build_emit_data
* emit_data
)
1084 build_tgsi_intrinsic(action
, bld_base
, emit_data
, LLVMReadNoneAttribute
);
1087 static void build_tgsi_intrinsic_readonly(
1088 const struct lp_build_tgsi_action
* action
,
1089 struct lp_build_tgsi_context
* bld_base
,
1090 struct lp_build_emit_data
* emit_data
)
1092 build_tgsi_intrinsic(action
, bld_base
, emit_data
, LLVMReadOnlyAttribute
);
1095 void radeon_llvm_context_init(struct radeon_llvm_context
* ctx
)
1097 struct lp_type type
;
1098 LLVMTypeRef main_fn_type
;
1099 LLVMBasicBlockRef main_fn_body
;
1101 /* Initialize the gallivm object:
1102 * We are only using the module, context, and builder fields of this struct.
1103 * This should be enough for us to be able to pass our gallivm struct to the
1104 * helper functions in the gallivm module.
1106 memset(&ctx
->gallivm
, 0, sizeof (ctx
->gallivm
));
1107 memset(&ctx
->soa
, 0, sizeof(ctx
->soa
));
1108 ctx
->gallivm
.context
= LLVMContextCreate();
1109 ctx
->gallivm
.module
= LLVMModuleCreateWithNameInContext("tgsi",
1110 ctx
->gallivm
.context
);
1111 ctx
->gallivm
.builder
= LLVMCreateBuilderInContext(ctx
->gallivm
.context
);
1113 /* Setup the module */
1114 main_fn_type
= LLVMFunctionType(LLVMVoidTypeInContext(ctx
->gallivm
.context
),
1116 ctx
->main_fn
= LLVMAddFunction(ctx
->gallivm
.module
, "main", main_fn_type
);
1117 main_fn_body
= LLVMAppendBasicBlockInContext(ctx
->gallivm
.context
,
1118 ctx
->main_fn
, "main_body");
1119 LLVMPositionBuilderAtEnd(ctx
->gallivm
.builder
, main_fn_body
);
1121 ctx
->store_output_intr
= "llvm.AMDGPU.store.output.";
1122 ctx
->swizzle_intr
= "llvm.AMDGPU.swizzle";
1123 struct lp_build_tgsi_context
* bld_base
= &ctx
->soa
.bld_base
;
1125 /* XXX: We need to revisit this.I think the correct way to do this is
1126 * to use length = 4 here and use the elem_bld for everything. */
1127 type
.floating
= TRUE
;
1132 lp_build_context_init(&bld_base
->base
, &ctx
->gallivm
, type
);
1133 lp_build_context_init(&ctx
->soa
.bld_base
.uint_bld
, &ctx
->gallivm
, lp_uint_type(type
));
1134 lp_build_context_init(&ctx
->soa
.bld_base
.int_bld
, &ctx
->gallivm
, lp_int_type(type
));
1137 bld_base
->emit_store
= emit_store
;
1138 bld_base
->emit_swizzle
= emit_swizzle
;
1139 bld_base
->emit_declaration
= emit_declaration
;
1140 bld_base
->emit_immediate
= emit_immediate
;
1142 bld_base
->emit_fetch_funcs
[TGSI_FILE_IMMEDIATE
] = emit_fetch_immediate
;
1143 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = emit_fetch_input
;
1144 bld_base
->emit_fetch_funcs
[TGSI_FILE_TEMPORARY
] = emit_fetch_temporary
;
1145 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = emit_fetch_output
;
1147 /* Allocate outputs */
1148 ctx
->soa
.outputs
= ctx
->outputs
;
1150 /* XXX: Is there a better way to initialize all this ? */
1152 lp_set_default_actions(bld_base
);
1154 bld_base
->op_actions
[TGSI_OPCODE_ABS
].emit
= build_tgsi_intrinsic_readonly
;
1155 bld_base
->op_actions
[TGSI_OPCODE_ABS
].intr_name
= "fabs";
1156 bld_base
->op_actions
[TGSI_OPCODE_ARL
].emit
= emit_arl
;
1157 bld_base
->op_actions
[TGSI_OPCODE_AND
].emit
= emit_and
;
1158 bld_base
->op_actions
[TGSI_OPCODE_BGNLOOP
].emit
= bgnloop_emit
;
1159 bld_base
->op_actions
[TGSI_OPCODE_BRK
].emit
= brk_emit
;
1160 bld_base
->op_actions
[TGSI_OPCODE_CEIL
].emit
= build_tgsi_intrinsic_readonly
;
1161 bld_base
->op_actions
[TGSI_OPCODE_CEIL
].intr_name
= "ceil";
1162 bld_base
->op_actions
[TGSI_OPCODE_CLAMP
].emit
= build_tgsi_intrinsic_nomem
;
1163 bld_base
->op_actions
[TGSI_OPCODE_CLAMP
].intr_name
= "llvm.AMDIL.clamp.";
1164 bld_base
->op_actions
[TGSI_OPCODE_CMP
].emit
= build_tgsi_intrinsic_nomem
;
1165 bld_base
->op_actions
[TGSI_OPCODE_CMP
].intr_name
= "llvm.AMDGPU.cndlt";
1166 bld_base
->op_actions
[TGSI_OPCODE_CONT
].emit
= cont_emit
;
1167 bld_base
->op_actions
[TGSI_OPCODE_COS
].emit
= build_tgsi_intrinsic_readonly
;
1168 bld_base
->op_actions
[TGSI_OPCODE_COS
].intr_name
= "llvm.cos.f32";
1169 bld_base
->op_actions
[TGSI_OPCODE_DDX
].intr_name
= "llvm.AMDGPU.ddx";
1170 bld_base
->op_actions
[TGSI_OPCODE_DDX
].fetch_args
= tex_fetch_args
;
1171 bld_base
->op_actions
[TGSI_OPCODE_DDY
].intr_name
= "llvm.AMDGPU.ddy";
1172 bld_base
->op_actions
[TGSI_OPCODE_DDY
].fetch_args
= tex_fetch_args
;
1173 bld_base
->op_actions
[TGSI_OPCODE_ELSE
].emit
= else_emit
;
1174 bld_base
->op_actions
[TGSI_OPCODE_ENDIF
].emit
= endif_emit
;
1175 bld_base
->op_actions
[TGSI_OPCODE_ENDLOOP
].emit
= endloop_emit
;
1176 bld_base
->op_actions
[TGSI_OPCODE_EX2
].emit
= build_tgsi_intrinsic_nomem
;
1177 bld_base
->op_actions
[TGSI_OPCODE_EX2
].intr_name
= "llvm.AMDIL.exp.";
1178 bld_base
->op_actions
[TGSI_OPCODE_FLR
].emit
= build_tgsi_intrinsic_readonly
;
1179 bld_base
->op_actions
[TGSI_OPCODE_FLR
].intr_name
= "floor";
1180 bld_base
->op_actions
[TGSI_OPCODE_FRC
].emit
= build_tgsi_intrinsic_nomem
;
1181 bld_base
->op_actions
[TGSI_OPCODE_FRC
].intr_name
= "llvm.AMDIL.fraction.";
1182 bld_base
->op_actions
[TGSI_OPCODE_F2I
].emit
= emit_f2i
;
1183 bld_base
->op_actions
[TGSI_OPCODE_F2U
].emit
= emit_f2u
;
1184 bld_base
->op_actions
[TGSI_OPCODE_IABS
].emit
= build_tgsi_intrinsic_nomem
;
1185 bld_base
->op_actions
[TGSI_OPCODE_IABS
].intr_name
= "llvm.AMDIL.abs.";
1186 bld_base
->op_actions
[TGSI_OPCODE_IDIV
].emit
= emit_idiv
;
1187 bld_base
->op_actions
[TGSI_OPCODE_IF
].emit
= if_emit
;
1188 bld_base
->op_actions
[TGSI_OPCODE_IMAX
].emit
= build_tgsi_intrinsic_nomem
;
1189 bld_base
->op_actions
[TGSI_OPCODE_IMAX
].intr_name
= "llvm.AMDGPU.imax";
1190 bld_base
->op_actions
[TGSI_OPCODE_IMIN
].emit
= build_tgsi_intrinsic_nomem
;
1191 bld_base
->op_actions
[TGSI_OPCODE_IMIN
].intr_name
= "llvm.AMDGPU.imin";
1192 bld_base
->op_actions
[TGSI_OPCODE_INEG
].emit
= emit_ineg
;
1193 bld_base
->op_actions
[TGSI_OPCODE_ISHR
].emit
= emit_ishr
;
1194 bld_base
->op_actions
[TGSI_OPCODE_ISGE
].emit
= emit_icmp
;
1195 bld_base
->op_actions
[TGSI_OPCODE_ISLT
].emit
= emit_icmp
;
1196 bld_base
->op_actions
[TGSI_OPCODE_ISSG
].emit
= emit_ssg
;
1197 bld_base
->op_actions
[TGSI_OPCODE_I2F
].emit
= emit_i2f
;
1198 bld_base
->op_actions
[TGSI_OPCODE_KIL
].emit
= kil_emit
;
1199 bld_base
->op_actions
[TGSI_OPCODE_KIL
].intr_name
= "llvm.AMDGPU.kill";
1200 bld_base
->op_actions
[TGSI_OPCODE_KILP
].emit
= lp_build_tgsi_intrinsic
;
1201 bld_base
->op_actions
[TGSI_OPCODE_KILP
].intr_name
= "llvm.AMDGPU.kilp";
1202 bld_base
->op_actions
[TGSI_OPCODE_LG2
].emit
= build_tgsi_intrinsic_readonly
;
1203 bld_base
->op_actions
[TGSI_OPCODE_LG2
].intr_name
= "llvm.log2.f32";
1204 bld_base
->op_actions
[TGSI_OPCODE_LRP
].emit
= build_tgsi_intrinsic_nomem
;
1205 bld_base
->op_actions
[TGSI_OPCODE_LRP
].intr_name
= "llvm.AMDGPU.lrp";
1206 bld_base
->op_actions
[TGSI_OPCODE_MOD
].emit
= emit_mod
;
1207 bld_base
->op_actions
[TGSI_OPCODE_NOT
].emit
= emit_not
;
1208 bld_base
->op_actions
[TGSI_OPCODE_OR
].emit
= emit_or
;
1209 bld_base
->op_actions
[TGSI_OPCODE_POW
].emit
= build_tgsi_intrinsic_readonly
;
1210 bld_base
->op_actions
[TGSI_OPCODE_POW
].intr_name
= "llvm.pow.f32";
1211 bld_base
->op_actions
[TGSI_OPCODE_ROUND
].emit
= build_tgsi_intrinsic_nomem
;
1212 bld_base
->op_actions
[TGSI_OPCODE_ROUND
].intr_name
= "llvm.AMDIL.round.nearest.";
1213 bld_base
->op_actions
[TGSI_OPCODE_SGE
].emit
= emit_cmp
;
1214 bld_base
->op_actions
[TGSI_OPCODE_SEQ
].emit
= emit_cmp
;
1215 bld_base
->op_actions
[TGSI_OPCODE_SHL
].emit
= emit_shl
;
1216 bld_base
->op_actions
[TGSI_OPCODE_SLE
].emit
= emit_cmp
;
1217 bld_base
->op_actions
[TGSI_OPCODE_SLT
].emit
= emit_cmp
;
1218 bld_base
->op_actions
[TGSI_OPCODE_SNE
].emit
= emit_cmp
;
1219 bld_base
->op_actions
[TGSI_OPCODE_SGT
].emit
= emit_cmp
;
1220 bld_base
->op_actions
[TGSI_OPCODE_SIN
].emit
= build_tgsi_intrinsic_readonly
;
1221 bld_base
->op_actions
[TGSI_OPCODE_SIN
].intr_name
= "llvm.sin.f32";
1222 bld_base
->op_actions
[TGSI_OPCODE_SSG
].emit
= emit_ssg
;
1223 bld_base
->op_actions
[TGSI_OPCODE_TEX
].fetch_args
= tex_fetch_args
;
1224 bld_base
->op_actions
[TGSI_OPCODE_TEX
].intr_name
= "llvm.AMDGPU.tex";
1225 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].fetch_args
= tex_fetch_args
;
1226 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].intr_name
= "llvm.AMDGPU.tex";
1227 bld_base
->op_actions
[TGSI_OPCODE_TXB
].fetch_args
= tex_fetch_args
;
1228 bld_base
->op_actions
[TGSI_OPCODE_TXB
].intr_name
= "llvm.AMDGPU.txb";
1229 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].fetch_args
= tex_fetch_args
;
1230 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].intr_name
= "llvm.AMDGPU.txb";
1231 bld_base
->op_actions
[TGSI_OPCODE_TXD
].fetch_args
= txd_fetch_args
;
1232 bld_base
->op_actions
[TGSI_OPCODE_TXD
].intr_name
= "llvm.AMDGPU.txd";
1233 bld_base
->op_actions
[TGSI_OPCODE_TXF
].fetch_args
= txf_fetch_args
;
1234 bld_base
->op_actions
[TGSI_OPCODE_TXF
].intr_name
= "llvm.AMDGPU.txf";
1235 bld_base
->op_actions
[TGSI_OPCODE_TXL
].fetch_args
= tex_fetch_args
;
1236 bld_base
->op_actions
[TGSI_OPCODE_TXL
].intr_name
= "llvm.AMDGPU.txl";
1237 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].fetch_args
= tex_fetch_args
;
1238 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].intr_name
= "llvm.AMDGPU.txl";
1239 bld_base
->op_actions
[TGSI_OPCODE_TXP
].fetch_args
= txp_fetch_args
;
1240 bld_base
->op_actions
[TGSI_OPCODE_TXP
].intr_name
= "llvm.AMDGPU.tex";
1241 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= tex_fetch_args
;
1242 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].intr_name
= "llvm.AMDGPU.txq";
1243 bld_base
->op_actions
[TGSI_OPCODE_TRUNC
].emit
= build_tgsi_intrinsic_nomem
;
1244 bld_base
->op_actions
[TGSI_OPCODE_TRUNC
].intr_name
= "llvm.AMDGPU.trunc";
1245 bld_base
->op_actions
[TGSI_OPCODE_UADD
].emit
= emit_uadd
;
1246 bld_base
->op_actions
[TGSI_OPCODE_UDIV
].emit
= emit_udiv
;
1247 bld_base
->op_actions
[TGSI_OPCODE_UMAX
].emit
= build_tgsi_intrinsic_nomem
;
1248 bld_base
->op_actions
[TGSI_OPCODE_UMAX
].intr_name
= "llvm.AMDGPU.umax";
1249 bld_base
->op_actions
[TGSI_OPCODE_UMIN
].emit
= build_tgsi_intrinsic_nomem
;
1250 bld_base
->op_actions
[TGSI_OPCODE_UMIN
].intr_name
= "llvm.AMDGPU.umin";
1251 bld_base
->op_actions
[TGSI_OPCODE_UMOD
].emit
= emit_umod
;
1252 bld_base
->op_actions
[TGSI_OPCODE_USEQ
].emit
= emit_icmp
;
1253 bld_base
->op_actions
[TGSI_OPCODE_USGE
].emit
= emit_icmp
;
1254 bld_base
->op_actions
[TGSI_OPCODE_USHR
].emit
= emit_ushr
;
1255 bld_base
->op_actions
[TGSI_OPCODE_USLT
].emit
= emit_icmp
;
1256 bld_base
->op_actions
[TGSI_OPCODE_USNE
].emit
= emit_icmp
;
1257 bld_base
->op_actions
[TGSI_OPCODE_U2F
].emit
= emit_u2f
;
1258 bld_base
->op_actions
[TGSI_OPCODE_XOR
].emit
= emit_xor
;
1259 bld_base
->op_actions
[TGSI_OPCODE_UCMP
].emit
= emit_ucmp
;
1261 bld_base
->rsq_action
.emit
= build_tgsi_intrinsic_nomem
;
1262 bld_base
->rsq_action
.intr_name
= "llvm.AMDGPU.rsq";
1265 void radeon_llvm_finalize_module(struct radeon_llvm_context
* ctx
)
1267 struct gallivm_state
* gallivm
= ctx
->soa
.bld_base
.base
.gallivm
;
1268 /* End the main function with Return*/
1269 LLVMBuildRetVoid(gallivm
->builder
);
1271 /* Create the pass manager */
1272 ctx
->gallivm
.passmgr
= LLVMCreateFunctionPassManagerForModule(
1275 /* This pass should eliminate all the load and store instructions */
1276 LLVMAddPromoteMemoryToRegisterPass(gallivm
->passmgr
);
1278 /* Add some optimization passes */
1279 LLVMAddScalarReplAggregatesPass(gallivm
->passmgr
);
1280 LLVMAddCFGSimplificationPass(gallivm
->passmgr
);
1283 LLVMRunFunctionPassManager(gallivm
->passmgr
, ctx
->main_fn
);
1285 LLVMDisposeBuilder(gallivm
->builder
);
1286 LLVMDisposePassManager(gallivm
->passmgr
);
1290 void radeon_llvm_dispose(struct radeon_llvm_context
* ctx
)
1292 LLVMDisposeModule(ctx
->soa
.bld_base
.base
.gallivm
->module
);
1293 LLVMContextDispose(ctx
->soa
.bld_base
.base
.gallivm
->context
);